CYPRESS PALCE20V8 User Manual

20V8

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PALCE20V8

Flash Erasable,

Reprogrammab l e CMOS PAL Device

Features

• Active pull-up on data input pins

• Low power version (20V8L)
—55 mA max. commercial (15, 25 ns)
—65 mA max. military/industrial

(15, 25 ns)

• Standard version has low power
—90 mA max. commercial

(15, 25 ns)
—115 mA max. commercial (10 ns)
—130 mA max. military/industrial (15, 25 ns)

• CMOS Flash technology for electrical erasability and
reprogrammability

• User-programmable macrocell

—Output polarity control
—Individually selectable for registered or combinato-

rial operation

LogicBlock Diagram(PDIP/CDIP/QSOP)

GND11I

12

10

I

9

1098765 4321

I

8

I

7

I

6

• QSOP package availa ble
—10, 15, and 25 ns com’l version

—15, and 25 ns military/industrial versions

• High reliability
—Proven Flash technology

—100% programming and functional testing

Functional Description

The Cypress PALCE20V8 is a CMOS Flash Erasable sec­ond-generation programmable array logic device. It is imple­mented with the famili ar sum-of-product (AND-OR ) logic struc­ture and the programmable macroce ll .

The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil c erdip, a 28-lead square ceramic lea dless chip car­rier, a 28-lead square pl astic leaded ch ip carrier , and a 24-lea d
quarter size outline. The device provides up to 20 inputs and
8 outputs. The PALCE20V8 ca n be elec trical ly erase d and re­programmed. The programmable macrocell enables the de­vice to function as a superset to the familia r 24-pin PLDs such
as 20L8, 20R8, 20R6, 20R4.

I

5

I

4

I

3

I

2

I

CLK/I

1

0

PROGRAMMABLE

AND ARRAY

(64 x 40)

8888888 8

MUX

13 15 16 17 18 19 20 21 22 23

OE/I

11

Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell

14

I

12

I/O

0

I/O

1

I/O

2

I/O

3

I/O

4

I/O

5

I/O

MUX

24

6

I/O

I

7

V

13

CC

20V8–1

PAL is a registered trademark of Advanced Micro Devices, Inc.

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03026 Rev. ** Revised March 26, 1997

PALCE20V8

Pin Configuration

5

3

6

4

7

5

8
9

6

10

7

11

8

PLCC/LCC

Top View

0

CC

1

2

IICLK/I

4 3 2 2827 26

121314 1516 1718

9

I

VII/O

NC

1

10

11

I

GND

NC

I

OE/I

7

13

I/O

25

6

I/O

24

5

I/O

23

4

NC

22

I/O

21

3

I/O

20

2

I/O

19

1

0

12

I/O

20V8–3

DIP/QSOP

Top View

CLK/I

1

24

V

CC

I

23

13

22

I/O

7

I/O

21

6

20

I/O

5

I/O

19

4

I/O

18

3

I/O

17

2

I/O

1

16

I/O

15

0

I

12

OE/I

11

20V8–2

NC

I
I
I

I
I
I

GND

0

I

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

2
3
4
5
6
7
8
9
10
11 14
12 13

Selection Guide

tPD ns tS ns tCO ns ICC mA

Generic Part Number

PALCE20V8−5 5 3 4 115
PALCE20V8−7 7.5 7 5 115
PALCE20V8−10 10 10 10 10 7 10 115 130
PALCE20V8−15 15 15 12 12 10 12 90 130
PALCE20V8−25 25 25 15 20 12 20 90 130
PALCE20V8L−15 15 15 12 12 10 12 55 65
PALCE20V8L−25 25 25 15 20 12 20 55 65

Shaded area contains preliminary information.

Com’l/Ind Mil Com’l/Ind Mil Com’l/Ind Mil Com’l Mil/Ind

Functional Description (continued)

The PALCE20V8 features 8 product terms per output and 40
input terms into the AN D array . The fi rst product term in a mac­rocell can be used eit her as an inter nal out put en abl e con tr ol
or as a data product term.

There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether th e macrocell functions as a reg ister or
combinatorial wi th invert ing or no ninvertin g output. The outp ut
enable control c an come from an external pin o r internally fro m
a product term. The output can also be perma ne ntly ena ble d,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select­able from either the input/output pin associated with the mac­rocell, the input/outpu t pin as so ci ated wi th an adj ac ent pin, or
from the macrocell register itself.

Power-Up Reset

All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ­ated output pin will be HIGH due to active-LOW outputs.

Electronic Signature

An electronic signature word is provided in the PALCE20V8
that consists of 64 bi ts of programmabl e memory that can co n­tain user-defined data.

Security Bit

A security bit is provided that defeats the readback of the in­ternal programmed pattern when the bit is programmed.

Low Power

The Cypress PALCE20V8 provides low-power operation
through the use of CMO S technology , and in creased testabilit y
with Flash reprogrammability.

Product Term Disable

Product Term Disabl e (PT D) fuses are included for e ach prod­uct term. The P TD fuses a llow each pro duct term to be individ­ually disabled.

Input and I/O Pin Pull-Ups

The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active
HIGH state (logical 1). All unused inputs and three-stated I/O
pins should be connected to another active input, V
Ground to improve noise immunity and reduce I

CC

, or

CC

.

Document #: 38-03026 Rev. ** Page 2 of 14

Configuration Table

CG

0

0 1 0 Registered Output Registered Med PALs
0 1 1 Combinatorial I/O Registered Med PALs
1 0 0 Combinatorial Output Small P A L s
1 0 1 Input Small P A L s
1 1 1 Combinatorial I/O 20L8 only

Macrocell

CG

1

CL0

x

Cell Configuration Devices Emulated

PALCE20V8

1

1

01X

0

CL0

CG

V

CC

CL1

x

x

1

CLK

CG1for pin 16 to 21 (DIP)

CG0for pin 15 and 22 (DIP)

Maximum Ratings

(Above which the useful life may be impai red. For user guide­lines, not tested.)

Storage Temperature .....................................−65°C to +150°C

Ambient Temperature with

Power Applied..................................................−55°C to +125°C

Supply Voltage to Ground Potential

(Pin 24 to Pin 12).................................................−0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State.....................................................−0.5V to +7.0V

DC Input Voltage.................................................−0.5V to +7.0V

1

1

OE

V

CC

QD

Q

100
0

1
01X

1
1
0

0
1

1

0

0
1
X

CL0

x

To

Adjacent

Macrocell

From
Adjacent
Pin

I/O

x

20V8–4

Output Current into Outputs (LOW).............................24 mA

DC Programming Voltage.............................................12.5V

Latch-Up Current.....................................................>200 mA

Operating Range

Range

Commercial 0°C to +75°C 5V ±5%
Industrial −40°C to +85°C 5V ±10%

[1]

Military

Note:

is the “instant on” case temperature.

1. T

A

Ambient

Temperature V

CC

−55°C to +125°C 5V ±10%

Document #: 38-03026 Rev. ** Page 3 of 14

PALCE20V8

Electrical Characteristics Ov er the Op erat ing Range

[2]

Parameter Description Test Conditions Min. Max. Unit

V

V

V
V
I

I

I
I

IH

IL

SC
CC

OH

OL

IH
IL

[5]

[4]

Output HIGH Voltage VCC = Min.,

= VIH or V

V

IN

Output LOW Voltage VCC = Min.,

= VIH or V

V

IN

IOH = −3.2 mA Com’l 2.4 V

IL

IOH = −2 mA Mil/Ind
IOL = 24 mA Com’l 0.5 V

IL

IOL = 12 mA Mil/Ind
Input HIGH Level Guaranteed Input Logical HIG H Vo ltage for All Inputs
Input LOW Level Guaranteed Input Logical LOW Voltage f or All Inputs
Input or I/O HIGH Leakage

Current
Input or I/O LOW Leakage

3.5V < VIN < V

CC

0V < VIN < VIN (Max.) −100 µA

Current
Output Short Circuit Current VCC = Max., V
Operating Power Supply

Current

VCC = Max.,

= 0V, VIH = 3V,

V

IL

Output Open,
f = 15 MHz
(counter)

OUT

[6,7]

= 0.5V

5, 7, 10 ns Com’l 115 mA

15, 25 ns 90 mA

15L, 25L ns 55 mA

10, 15, 25 ns Mil/Ind 130 mA

[3]
[3]

2.0 V

−0.5 0.8 V

−30 −150 mA

10 µA

15L, 25L ns Mil/Ind 65 mA

Capacitance

[7]

Parameter Description Test Conditions Typ. Unit

C
C

IN
OUT

Input Capacitance VIN = 2.0V @ f = 1 MHz 5 pF
Output Capacitance V

= 2.0V @ f = 1 MHz 5 pF

OUT

Endurance Characteristics

[7]

Parameter Description Test Conditions Min. Max. Unit

N Minimum Reprogramm ing Cycle s Normal Programming Conditions 100 Cycles

Notes:

2. See the last page of this specification for Gro up A subgro up test in g infor ma ti on .

3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

4. V

(Min.) is equal to −3.0V for pulse durations less than 20 ns.

IL

5. The leakage current is due to the internal pull-up resistor on all pins.

6. Not more than one output should be tested at a time. Durati on of the sho rt circuit s hould not be more t han one secon d. V
caused by tester ground degrad ation.

7. Tested initially and after any design or process changes that may affect these parameters.

= 0.5V has been chosen to a void test problems

OUT

Document #: 38-03026 Rev. ** Page 4 of 14

AC Test Loads and Waveforms

PALCE20V8

Specification S

tPD, t
t

PZX

t

PXZ

CO

, t

EA

, t

ER

Closed 50 pF 200Ω 390Ω 390Ω 750Ω 1.5V
Z ➧ H: Open

Z ➧ L: Closed
H ➧ Z: Open

L ➧ Z: Closed

3.0V

GND

1

2ns

≤

OUTPUT

ALL INPUT PULSES

90%

10%

≤ 2ns

20V8–5

TEST POINT

20V8–6

10%

90%

5V

S1

R1

R2

C

L

Commercial Military

C

L

1

R

2

R

1

R

Measured Output ValueR

2

1.5V

5 pF H ➧ Z: VOH − 0.5V

L ➧ Z: V

+ 0.5V

OL

Document #: 38-03026 Rev. ** Page 5 of 14