CYPRESS ISD-300LP User Manual

ISD-300LP™
CY7C68310
Low-Power USB 2.0 to ATA/ATAPI Bridge IC
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600
Document #: 38-08030 Rev. *G Revised February 4, 2004
CY7C68310
TABLE OF CONTENTS
1.0 INTRODUCTION ..............................................................................................................................4
1.2 Applications .................................................................................................................................5
1.3 Additional Resources .................................................................................................................. 5
1.4 Functional Block Diagram ........................................................................................................... 5
2.0 PIN ASSIGNMENTS ........................................................................................................................6
2.1 Pin Diagram ................................................................................................................................6
2.2 Pin Overview ...............................................................................................................................7
2.3 Detailed Pin Descriptions ............................................................................................................9
2.3.1 DP, DM .............................................................................................................................................. 9
2.3.2 RSDP, RSDM .................................................................................................................................... 9
2.3.3 TEST[0:3] .......................................................................................................................................... 9
2.3.4 XI, XO ................................................................................................................................................ 9
2.3.5 nEJECT .............................................................................................................................................9
2.3.6 SYSIRQ .............................................................................................................................................9
2.3.7 DRVPWRVLD .................................................................................................................................10
2.3.8 ATAEN ............................................................................................................................................10
2.3.9 GPIO Pins .......................................................................................................................................11
2.3.10 LOWPWR ...................................................................................................................................... 11
2.3.11 nRESET ........................................................................................................................................11
2.3.12 ATAPUEN .....................................................................................................................................11
2.3.13 nPWR500 ......................................................................................................................................11
2.3.14 SCL, SDA_nIMODE ......................................................................................................................11
2.3.15 DISKRDY ......................................................................................................................................11
2.3.16 VBUSPWRD .................................................................................................................................11
2.3.17 VBUSPWRVLD ............................................................................................................................. 11
3.0 FUNCTIONAL OVERVIEW ............................................................................................................11
3.1 USB Signaling Speeds ..............................................................................................................11
3.2 ATA Interface ............................................................................................................................12
3.2.1 ATA Command Block (ATACB) ......................................................................................................12
3.2.2 ATA Command Block 2 (ATACB2) ................................................................................................. 14
3.2.3 Vendor-specific EVENT_NOTIFY Command .................................................................................. 16
4.0 CONFIGURATION .........................................................................................................................16
4.1 CY7C68310 Configuration and USB Descriptor Sources .........................................................16
4.1.1 I2C-compatible Device ....................................................................................................................17
4.1.2 IMODE ............................................................................................................................................17
4.1.3 Internal ROM Contents ...................................................................................................................17
4.2 EEPROM Organization ............................................................................................................. 17
4.3 Programming the EEPROM ......................................................................................................30
4.3.1 LOAD_CONFIG_DATA ...................................................................................................................30
4.3.2 READ_CONFIG_DATA ...................................................................................................................30
5.0 TIMING CHARACTERISTICS ........................................................................................................31
2
5.1 I
C-compatible Memory Device Interface Timing ......................................................................31
5.2 USB Interface Timing ................................................................................................................31
5.3 ATA/ATAPI Interface Timing .....................................................................................................31
5.4 External Clock Source Timing ...................................................................................................31
5.5 Reset Timing .............................................................................................................................31
Document #: 38-08030 Rev. *G Page 2 of 38
CY7C68310
TABLE OF CONTENTS (continued)
6.0 EXTERNAL CIRCUITRY REQUIREMENTS ..................................................................................32
6.1 ATA Interface Termination ........................................................................................................ 32
6.2 Power Supply Regulation .......................................................................................................... 32
6.3 Pull-ups/Pull-downs on High-Z Pins ..........................................................................................32
7.0 MANUFACTURING INTERCONNECT TEST SUPPORT ..............................................................32
7.1 LOAD_MFG_DATA ...................................................................................................................32
7.2 READ_MFG_DATA ..................................................................................................................33
8.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................34
9.0 OPERATING CONDITIONS ...........................................................................................................35
10.0 DC CHARACTERISTICS .............................................................................................................35
11.0 ORDERING INFORMATION ........................................................................................................35
12.0 PACKAGE DIAGRAM ..................................................................................................................36
13.0 PCB LAYOUT RECOMMENDATIONS ........................................................................................36
14.0 DISCLAIMERS, TRADEMARKS, AND COPYRIGHTS ...............................................................37
LIST OF FIGURES
Figure 1-1. Block Diagram .......................................................................................................................5
Figure 2-1. 80-pin TQFP.......................................................................................................................... 6
Figure 2-2. SYSIRQ Latching Algorithm ................................................................................................ 10
Figure 5-1. I
2
C Interface Timing............................................................................................................. 31
Figure 6-1. External Circuitry Requirements..........................................................................................32
Figure 12-1. 80-pin TQFP Package Diagram ........................................................................................36
LIST OF TABLES
Table 2-1. CY7C68310 Test Modes .......................................................................................................9
Table 2-2. USB Interrupt Pipe Data Bitmap ..........................................................................................10
Table 3-1. ATACB Field Descriptions ...................................................................................................12
Table 3-2. ATACB2 Field Descriptions .................................................................................................14
Table 3-3. Notification Register Read Values .......................................................................................16
Table 3-4. Notification Register Write Values .......................................................................................16
Table 4-1. CY7C68310 Configuration and USB Descriptor Sources ....................................................17
Table 4-2. EEPROM Organization ........................................................................................................18
Table 4-3. EEPROM-related Vendor-specific Commands .................................................................... 30
Table 7-1. LOAD_MFG_DATA Command Format ...............................................................................32
Table 7-2. Bit-wise Mapping of LOAD_MFG_DATA Test Data ............................................................33
Table 7-3. READ_MFG_DATA Command Format ...............................................................................33
Table 7-4. Bit-wise Mapping of READ_MFG_Data Test Data ..............................................................34
Document #: 38-08030 Rev. *G Page 3 of 38
CY7C68310
1.0 Introduction
The CY7C68310 implements a bridge between one USB port and one ATA/ATAPI-based mass storage device port. This bridge adheres to the Mass Storage Class Bulk-Only Transport specification, version 1.0.
The USB port of the CY7C68310 is connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the CY7C68310 and receives status and data from the CY7C68310 using standard USB protocol.
The ATA/ATAPI port of the CY7C68310 is connected to a mass storage device. A 2-Kbyte buffer maximizes ATA/ATAPI data transfer rates by minimizing losses due to device seek times. The ATA interface supports ATA PIO modes 0–4, and Ultra Mode DMA modes 0–4.
The device initialization process is configurable, enabling the CY7C68310 to initialize most ATA/ATAPI devices without software intervention. The CY7C68310 can also be configured to allow software initialization of a device if initialization requirements are not supported by CY7C68310 algorithms.
1.1 Features
• Fixed-function mass storage device–requires no firmware code
• USB Mass Storage Class Bulk-Only specification-compliant (version 1.0)
• USB 2.0-certified (TID# 40001426)
Integrated USB transceiver
High-speed (480-Mbit) and full-speed (12-Mbit) support
USB Suspend/Resume, Remote Wakeup support
• Two power modes of operation–self-powered and USB bus-powered
Low power consumption allows for bus-powered operation
VBUS-powered CF support
True USB portable HDD support
• Compact 80-pin TQFP package with a Lead-Free option
ATA/ATAPI-6 specification-compliant–provides support for mass storage devices larger than 137GB
• 5V tolerant inputs, 3.3V output drive
• Flexible USB descriptor and configuration retrieval sources
2
I
C-compatible serial ROM interface
ATA interface using vendor-specific ATA command (FBh) implemented on ATAPI or ATA device
Default on-chip ROM contents for manufacturing/development
• 2-Kbyte SRAM data buffer for ATA/ATAPI data transfers
• ATA interface supports ATA PIO modes 0–4, UDMA modes 0–4 (multiword DMA not supported). ATA interface operation mode is automatically selected during device initialization or manually programmed with I
• Automatic detection of either Master or Slave ATA/ATAPI devices
• Mode Page 5 Support–increased support for formatting removable media devices
• ATA Interrupt support for ATAPI devices–offers more robust ATA support across OS platforms
• System event notification via Vendor-specific ATA command
Input pin for media cartridge detection or ejection request
USB bus state indications (Reset, FS/HS mode of operation, Suspend/Resume, Bus/Self-powered)
• Three General Purpose I/O (GPIO) pins
• Multiple LUNs supported within a single ATAPI device
• ATA translation provides seamless ATA support with standard MSC drivers
• Additional ATA command support provided by vendor-specific ATACBs (ATA command blocks utilizing the MSC Command Block Wrapper)
• Provisions to share ATA bus with other hosts (e.g. USB/1394 dual device)
• Manufacturing interconnect test support provided with vendor-specific USB commands:
Read/Write access to relevant ASIC pins
Manufacturing Interconnect Test Tools
• Utilizes inexpensive 30-Mhz crystal for clock source.
2
C-compatible configuration data
Document #: 38-08030 Rev. *G Page 4 of 38
CY7C68310
A
V
V
A V
1.2 Applications
The CY7C68310 implements a USB 2.0 bridge for all ATA/ATAPI-6 compliant mass storage devices, such as:
• Hard drives, including small form factor drives (2.5”, 1.8”, and 1.0”) designed for portable consumer electronics applications
• CD-ROM, CD-R/W
• DVD-ROM, DVD-RAM, DVD-R/W
• MP3 players
• Compact flash
• Microdrives
• Tape drives
• Personal video recorders.
1.3 Additional Resources
• CY4617 – CY7C68310 Mass Storage Reference Design Kit
USB Specification version 2.0
• ATA Attachment-6 with Packet Interface revision 3b
• USB Mass Storage Class Bulk-Only Transport specification, Rev. 1.0
1.4 Functional Block Diagram
USB HS/FS
Control Logic
USB
2.0
Xcvr
BUS
D+
D-
USB
256 Byte
EEPROM
nEJECT
SYSIRQ
DRVPWRVLD
DISKRDY
GPIO Pins (3)
SCL
SD
ROM
EEPROM Interface
Control
CY7C68310
Control Logic
Control
64 Byte
RAM
ATA Interface Logic
Bulk
2kByte FIFO
OSC
LOWPWR
nPWR500
BUSPWRVLD
BUSPWRD
nRESET
TAEN
Xtal
30MHz
ATA Control
16-bit Data
Figure 1-1. Block Diagram
Document #: 38-08030 Rev. *G Page 5 of 38
2.0 Pin Assignments
2.1 Pin Diagram
CY7C68310
VDD33 VDD25
nDIOW
nDIOR IORDY
ATAPUEN
nDMACK
ATAIRQ
DA1
VDD33
DA0
DA2
nCS0
nCS1
nPWR500
SCL
SDA_nIMODE
DISKRDY
VBUSPWRD
VBUSPWRVLD
VDD25
61
62
63 64
65
66
67 68
69 70
71 72
73
74
75 76
77
78
79 80
60
VSS
VDD25
DMARQ
DD15
DD0
DD14
DD1
DD13
57
56
55
59
58
54
53
52
CY7C68310-80AC
VDD33
DD2
DD12
51
50
49
VSS
DD4
DD10
45
44
DD5
43
DD3
DD11
48
47
46
DD8
DD9
DD6
42
41
40
39
38 37
36
35
34 33
32 31
30 29
28 27
26 25
24
23
22 21
DD7
TMC2 TMC1
nATARST
nRESET
LOWPWR SCANEN
GPIO2_nHS GPIO1
GPIO0
ATAEN
DRVPWRVLD
SYSIRQ
nEJECT
TEST3
VDD33
XO
XI VSS
4
5
1
2
3
VSS
RPU
VDD25
6
7
DP
VSS
RSDP
VDD33
8
DM
9
RSDM
10
VSS
11
PVDD25
12
13
14
15
16
AVS S
RREF
AVS S
AVS S
AVD D25
17
18
VDD25
TEST0
19
TEST1
20
TEST2
Figure 2-1. 80-pin TQFP
Document #: 38-08030 Rev. *G Page 6 of 38
CY7C68310
2.2 Pin Overview
Pin
Number Pin Name
2 RPU O USB Output D+ pull-up source. Power source for 1.5k pull-up resistor attached
5 RSDP O USB I/O USB full-speed output buffer (D+). RSDP also functions as a
6 DP I/O USB I/O USB high-speed I/O buffer (D+).
8 DM I/O USB I/O USB high-speed I/O buffer (D-).
9 RSDM O USB I/O USB full-speed output buffer (D-). RSDM also functions as a
18–20, 25 TEST[0:3] I 5V-tolerant input
22 XI I OSC input
23 XO O OSC output 30-MHz crystal output.
26 nEJECT I 5V-tolerant
27 SYSIRQ I 5V-tolerant
28 DRVPWRVLD I 5V-tolerant
29 ATAEN I 5V-tolerant
30–32 GPIO[0:1],
GPIO2_nHS
33 SCANEN I 5V tolerant
34 LOWPWR O high-Z driver,
35 nRESET I 5V-tolerant
36 nATARST O 3.3V drive,
37, 38 TMC[1:2] I 3.3V input Active HIGH. ASIC test pins. These pins must be tied to GND during
56, 54, 52,
DD[0:15] I/O 3.3V drive,
49,46, 44, 42, 39, 41, 43, 45, 48, 51, 53, 55,
57
58 DMARQ I 5V tolerant
62 nDIOW O 3.3V drive,
Pin
Direction Pin Type Pin Description
to D+ during full-speed operation.
current sink for termination during high-speed operation.
current sink for termination during high-speed operation.
Active HIGH. ASIC fabrication and manufacturing test mode select.
buffer
These pins must be tied to GND during normal operation.
30-MHz crystal input.
(2.5V-tolerant)
Active LOW. Media eject or remote wakeup requested. Tie to +3.3V
Schmitt input
if functionality is not used.
Active HIGH. USB interrupt request. Tie to GND if functionality is not
Schmitt input
used.
Configurable polarity. Device Presence Detect. This pin must not
Schmitt input
be allowed to float if functionality is not utilized.
Active HIGH. ATA interface enable.
Schmitt input
‘1’ = normal ATA operation ‘0’ = High-Z ATA interface pins and ATA interface logic halted
I/O 3.3V drive,
5V-tolerant,
6-mA IOL,
Schmitt input
General purpose I/O pins. The GPIO pins must be tied to GND if functionality is not utilized. If the hs_indicator config bit is set, the GPIO2_nHS pin will reflect the operating speed of the device. ‘1’ = full-speed operation ‘0’ = high-speed operation
Active HIGH. ASIC test pin. This pin must be tied to GND during
input buffer
normal operation.
Active HIGH. USB suspend indicator.
5V-tolerant,
6-mA I
OL
‘0’ = Chip active. VBUS power up to 100 mA granted. ‘High-Z’ = Chip suspend. VBUS system current limited to USB suspend mode value.
Active LOW. Asynchronous chip reset.
Schmitt input
Active LOW. ATA reset signal.
5V-tolerant,
6-mA I
OL
normal operation.
ATA data signals.
5V-tolerant,
OL
,
6-mA I
Schmitt input
ATA control signal.
Schmitt input
ATA control signal.
5V-tolerant,
6-mA I
OL
Document #: 38-08030 Rev. *G Page 7 of 38
CY7C68310
2.2 Pin Overview (continued)
Pin
Number Pin Name
63 nDIOR O 3.3V drive,
64 IORDY I 5V-tolerant
65 ATAPUEN O 3.3V drive,
66 nDMACK O 3.3V drive,
67 ATA IRQ I 5V-tolerant
70, 68, 71 DA[0:2] O 3.3V drive,
72, 73 nCS[0:1] O 3.3V drive,
74 nPWR500 O high-Z driver,
75 SCL O high-Z driver,
76 SDA_nlMODE I/O high-Z driver,
77 DISKRDY I 5V-tolerant
78 VBUSPWRD I 5V-tolerant
79 VBUSPWRVLD I 5V-tolerant
1, 4, 10,
VSS Power Digital ground.
21, 47, 60
3, 17, 40,
VDD25 Power 2.5V digital supply.
59, 80
7, 24, 50,
VDD33 Power 3.3V digital supply.
61, 69
11 PVDD25 Power Analog 2.5V supply (PLL).
12,14,16 AVSS Power Analog ground.
13 RREF Power PLL voltage reference. Current source for 2.4k (1%) resistor
15 AVDD25 Power Analog 2.5V supply.
Pin
Direction Pin Type Pin Description
ATA control signal.
5V-tolerant,
6 mA I
OL
ATA control signal.
Schmitt input
ATA IORDY pull-up connection. For VBUS-powered systems.
5V-tolerant,
6 mA I
OL
ATA control signal.
5V-tolerant,
6 mA I
OL
ATA interrupt request.
Schmitt input
ATA address signals.
5V-tolerant,
6 mA I
OL
ATA chip select signals.
5V-tolerant,
6 mA I
OL
Active LOW. VBUS power granted indicator.
5V-tolerant,
6 mA I
OL
5V-tolerant,
6 mA I
OL
‘0’ = VBUS power up to bMaxPower value ‘high-Z’ = bMaxPower value not granted (if more than 100 mA)
I2C-compatible clock. This pin may be left as a no-connect pin if
2
C-compatible interface is not utilized.
the I
I2C-compatible address/data or nIMODE select.
5V-tolerant,
6 mA I
Schmitt input
OL
,
Configurable polarity. Device ready.
Schmitt input
Active HIGH. Bus-powered operation select pin.
Schmitt input
‘1’ = Bus powered ‘0’ = Self powered
Active HIGH. Indicates that VBUS power is present.
Schmitt input
connected to AVSS.
Document #: 38-08030 Rev. *G Page 8 of 38
CY7C68310
2.3 Detailed Pin Descriptions
2.3.1 DP, DM
DP and DM are the high-speed USB signaling pins, and they should be tied to the D+ and D– pins of the USB connector. Because they operate at high frequencies, the USB signals require special consideration when designing the layout of the PCB. See section
13.0 for PCB layout guidelines.
2.3.2 RSDP, RSDM
RSDP and RSDM are the full-speed USB signaling pins, and they should be tied to the DP and DM pins through 39 resistors. RSDP and RSDM also function as current sinks for termination during high-speed operation.
2.3.3 TEST[0:3]
The test pins control the various test modes of the CY7C68310. Most test modes are reserved for ASIC fabrication, but the following table outlines the test modes available for device manufacturing environments. The test pins must be tied to GND for normal operation.
Table 2-1. CY7C68310 Test Modes
Test Mode Description
0000 Normal Mode. This is the default mode of operation.
0001 Reserved.
0010 Limbo Mode. All output pins set to high-Z during Limbo mode operation with the exception of the XO pin. The XO
pin output cell does not have high-Z control (always enabled), and must be disabled or disconnected by other means. To enter Limbo Mode, nRESET must be toggled after the Test pins are set to ‘0010’.
0011 Input xnorTree Mode. This mode tests the connectivity of all dedicated inputs and outputs. While in the Input
0100 Bi-di xnorTree Mode. This mode test the connectivity of all bi-directional inputs. While in the Bi-di xnor Tree Mode
0101–1111 Reserved.
xnorTree Mode of operation, all bi-directional pins are wired as chain outputs. The results of the connectivity procedure will be seen on all bidirectional pins. Chain Inputs (in order): VBUSPWRVLD, VBUSPWRD, DISKRDY, ATAIRQ, IORDY, DMARQ, nRESET, ATAEN, DRVPWRVLD, SYSIRQ, nEJECT Chain Outputs (in order): GPIO[2:0], DD[15:0], SDA_nIMODE.
of operation, all bi-directional pins are wired as inputs and become part of the xnor Tree chain. The results of the connectivity procedure will be seen on all output only pins. Chain Inputs: GPIO[0], GPIO[1], GPIO[2], DD[7], DD[8], DD[6], DD[0], DD[5], DD[10], DD[4], DD[11], DD[3], DD[12], DD[2], DD[13], DD[1], DD[14], DD[0], DD[15], SDA_nIMODE. Chain Outputs: nPWR500, nATARST, nDIOW, nDIOR, nDMACK, ATAPUEN, nCS[1:0], DA[2:0], LOWPWR, SCL
2.3.4 XI, XO
The CY7C68310 requires a 30-MHz signal to derive internal timing. Typically a 30-MHz (2.5V tolerant, parallel-resonant funda­mental mode) crystal is used, but a 30-MHz (2.5V, 50% duty cycle) square wave from another source can also be used. If a crystal is used, connect the pins to XI and XO, and also through 20pF capacitors to GND as shown in Figure 6-1. If an alternate clock source is used, apply it to XI and leave XO open.
2.3.5 nEJECT
The nEJECT input pin provides a means to communicate an Eject button push to the ATA/ATAPI device via event notification as well as a way to cause a USB Remote-wakeup. During normal operation, asserting nEJECT for 10ms indicates that a media eject has been requested. If the CY7C68310 is in a suspend state, and if remote wakeup is enabled by the USB host, a state change on this pin will immediately cause the CY7C68310 to perform a USB remote wakeup event.
2.3.6 SYSIRQ
The SYSIRQ pin provides a way for systems to request service from host software by use of the USB Interrupt pipe. If the CY7C68310 has no pending interrupt data to return, USB interrupt pipe data requests are NAKed. If pending data is available, CY7C68310 returns 16 bits of data indicating the state of the DISKRDY pin, the HS_MODE signal (that indicates whether CY7C68310 is operating in high-speed or full-speed), the VBUSPWRD pin, the User-Defined values from bits [7:3] of address 0xE of the configuration space, and the GPIO Pins. Tab le 2-2 shows the bitmap for the data returned on the interrupt pipe, and the figure beneath it depicts the latching algorithm incorporated by CY7C68310.
Document #: 38-08030 Rev. *G Page 9 of 38
CY7C68310
Table 2-2. USB Interrupt Pipe Data Bitmap
USB Interrupt Data Byte 1 USB Interrupt Data Byte 0
7654321076543210
0
0
0
0
0
DISKRDY
USB High-Speed
VBUSPWRD
USER_DEF[4]
USER_DEF[3]
USER_DEF[2]
USER_DEF[1]
USER_DEF[0]
GPIO[2]
GPIO[1]
GPIO[0]
Yes
No
SYSIRQ=1?
Yes
Latch State of IO Pins
Set Int_Data = 1
No
Int_Data = 0
and
SYSIRQ=0?
No
NAK Request
Return Interrupt Data
No
USB Interrupt
Pipe Polled?
Yes
Int_Data = 1?
Yes
Set Int_Data = 0
Figure 2-2. SYSIRQ Latching Algorithm
2.3.7 DRVPWRVLD
DRVPWRVLD can be used with removable devices (such as compact flash) to indicate that the media device is present. Pin polarity and function enable are controlled by bits 4 and 2, respectively, of EEPROM address 0x0B. When DRVPWRVLD is deasserted, the CY7C68310 will remove the pull-up on D+ (causing the CY7C68310 to drop off the USB), suspend all ATA state machine activity, drive all ATA interface signals to ‘0’ (assuming ATAEN = ‘1’), and enter into a low-power state. The CY7C68310 will remain in this state until DRVPWRVLD is asserted, at which time it will enable the D+ pull-up, allow resume of ATA state machine activity, and begin to drive the ATA interface pins (assuming ATAEN = ‘1’).
2.3.8 ATAEN
The ATAEN pin allows ATA bus sharing with other host devices. Deasserting ATAEN causes the CY7C68310 to high-Z all ATA bus interface pins and suspend ATA state machine activity, otherwise leaving the CY7C68310 operational (USB operation continues). Asserting ATAEN causes the CY7C68310 to reset the drive and resume normal operation. To disable USB operation and the ATA interface, the DRVPWRVLD signal can be used in conjunction with ATAEN to force the CY7C68310 into a low-power state until normal operation is resumed. Note that disabling the ATA bus with the ATAEN pin during the middle of a data transfer will result in data loss and may cause the operating system on the host computer to crash.
Document #: 38-08030 Rev. *G Page 10 of 38
CY7C68310
2.3.9 GPIO Pins
The GPIO pins allow for a general purpose Input/Output interface. Configuration bytes 0x0E and 0x0F contain the settings for the GPIO pins. See section 4.3 for details of how to use the vendor-specific commands to utilize the GPIO functionality. The status of the GPIO pins is also returned by a USB interrupt event. See section 2.3.6 for SYSIRQ details. Alternatively, if the hs_indicator config bit is set (bit 4 of EEPROM address 0x0F), the GPIO2_nHS pin will reflect the operating speed of the device.
2.3.10 LOWPWR
LOWPWR is an output pin that, when in a high-Z state, indicates that the CY7C68310 is in a suspend state. When LOWPWR output is driven ‘0’, the CY7C68310 is active.
2.3.11 nRESET
Asserting nRESET for a minimum of 1 ms after power rails are stable will reset the entire chip. An RC reset circuit should be used that ensures that no spurious resets occur.
2.3.12 ATAPUEN
This output provides control for the required host pull-up resistors on the ATA interface. ATAPUEN is driven ‘0’ when the ATA bus is inactive. ATAPUEN is driven ‘1’ when ATA bus is active. ATAPUEN is set to a high-Z state along with all other ATA interface pins when ATAEN is deasserted.
2.3.13 nPWR500
nPWR500 is an external pin that, when asserted, indicates VBUS current may be drawn up to the limit specified by the bMaxPower field of the USB configuration descriptors. nPWR500 will only be asserted if VBUSPWRD is also asserted. If the CY7C68310 enters a low-power state, nPWR500 is deasserted. When normal operation is resumed, nPWR500 is restored accordingly. The nPWR500 pin should never be used to control power sources for the CY7C68310.
2.3.14 SCL, SDA_nIMODE
If an external EEPROM device is used to store configuration information, the clock and data pins for the I should be connected to the configuration EEPROM and to VCC through 2.2k resistors as shown in Figure 6-1. If configuration information is to be obtained from the attached ATA/ATAPI device (IMODE), SCL should be left as a no-connect and SDA_nIMODE should be tied to GND.
2
C-compatible port
2.3.15 DISKRDY
This input pin indicates the attached device is powered and ready to begin communication with the CY7C68310. DISKRDY polarity can be set using EEPROM address 0x05, bit 0. DISKRDY qualifies the start of the CY7C68310 initialization sequence. A state change from ‘0’ to ‘1’ on DISKRDY will cause the CY7C68310 to wait for 25 ms before asserting nATARESET and re­initializing the device. The ATA interface state machines remain inactive and all of the ATA interface signals are driven logic '0' if DISKRDY is not asserted (assuming ATAEN = '1'). DISKRDY is filtered for 25 ms on the asserting edge and cleared asynchro­nously on the deasserting edge.
2.3.16 VBUSPWRD
The VBUSPWRD input pin indicates whether the device will report itself as bus-powered or self-powered. VBUSPWRD also qualifies the use of nPWR500. Based upon the state of this pin at start-up, the CY7C68310 will request the amount of current specified in the bMaxPower field of the USB Configuration Descriptor. If VBUSPWRD is asserted, the CY7C68310 will report that the device is bus-powered. If VBUSPWRD is deasserted, the CY7C68310 will report that the device is self-powered.
2.3.17 VBUSPWRVLD
VBUSPWRVLD (USB VBUS Power Valid) indicates that VBUS power is present at the USB connector. VBUSPWRVLD qualifies driving the system’s 1.5K pull-up resistor on D+ (the USB specification only allows the device to source power to D+ when the host is powered). VBUSPWRVLD is conditioned so that it is only detected after valid chip configuration bits have been loaded.
3.0 Functional Overview
3.1 USB Signaling Speeds
The CY7C68310 operates at two of the three signal rates that are defined in the Universal Serial Bus Specification Revision 2.0:
• Full-speed, with a signaling bit rate of 12 Mbits/sec.
• High-speed, with a signaling bit rate of 480 Mbits/sec.
Document #: 38-08030 Rev. *G Page 11 of 38
CY7C68310
3.2 ATA Interface
The ATA/ATAPI port on the CY7C68310 is compliant with the Information Technology–AT Attachment with Packet Interface–6 (ATA/ATAPI-6) Specification, T13/1410D Rev 2a. The CY7C68310 supports both ATAPI packet commands as well as ATA commands (by use of ATA Command Blocks), as outlined in Sections 3.2.1 and 3.2.2. Refer to the USB Mass Storage Class (MSC) Bulk Only Transport Specification for information on Command Block formatting. Additionally, the CY7C68310 translates ATAPI SFF-8070i commands to ATA commands for seamless integration of ATA devices with generic Mass Storage Class BOT drivers. The CY7C68310 also provides a vendor-specific “event notify” ATA command to automatically communicate certain USB and system events to the attached device.
3.2.1 ATA Command Block (ATACB)
The ATA Command Block (ATACB) functionality provides a means of passing ATA commands and ATA register accesses for execution. ATACB commands are transferred in the Command Block Wrapper Command Block (CBWCB) portion of the Command Block Wrapper (CBW). The ATACB is distinguished from other command blocks by the first two bytes of the command block matching the wATACBSignature. Only command blocks that have a valid wATACBSignature are interpreted as ATA Command Blocks. All other fields of the CBW and restrictions on the CBWCB remain as defined in the USB Mass Storage Class Bulk-Only Transport Specification. The ATACB must be 16 bytes in length. The following table and text defines the fields of the ATACB.
Table 3-1. ATACB Field Descriptions
Byte Field Name Field Description
0 bVSCBSignature This field indicates to the CY7C68310 that the ATACB contains a vendor-
1 bVSCBSubCommand This field must be set to 0x024h for ATACB commands.
2 bmATACBActionSelect This field controls the execution of the ATACB according to the bitfield values:
specific command block. This value of this filed must match the value in EEPROM address 0x06h for this vendor-specific command to be recognized.
Bit 7 IdentifyPacketDevice - This bit indicates that the data phase of the command will contain ATAPI (0xA1h) or ATA (0xECh) IDENTIFY device data. Setting IdentifyPacketDevice when the data phase does not contain IDENTIFY device data will result in unspecified device behavior. 0 = Data phase does not contain IDENTIFY device data 1= Data phase contains ATAPI or ATA IDENTIFY device data
Bit 6 UDMACommand - This bit enables supported UDMA device transfers. Setting this bit when a non-UDMA capable device is attached will result in undetermined behavior. 0 = Do not use UDMA device transfers (only use PIO mode) 1= Use UDMA device transfers
Bit 5 DEVOverride - This bit determines whether the DEV bit value is taken from the CY7C68310 configuration data or from the ATACB. 0 = The DEV bit will be taken from EEPROM address 0x05h, bit 5 1= The DEV bit will be taken from the ATACB field 0x0B, bit 4
Bit 4:3 DPErrorOverride - These bits control the Device and Phase Error override feature. These bits shall not be set in conjunction with bmATACBTask­FileRead. 00 = Data accesses are halted if a device or phase error is detected 01 = Data accesses are halted if a device error is detected, but not a phase error 10 = Data accesses are halted if a phase error is detected, but not a device error 11 = Neither device or phase errors will result in halting of data accesses
Bit 2 PollAltStatOverride - This bit determines whether or not the Alternate Status register will be polled and the BSY bit will be used to qualify the start of ATACB operation. 0 = The AltStat register will be polled until BSY=0 before proceeding with the ATACB operation 1= The ATACB operation will be executed without polling the AltStat register
Bit 1 DeviceSelectionOverride - This bit determines when the device selection will be performed in relation to the command register write accesses. 0 = Device selection will be performed prior to command register write accesses 1 = Device selection will be performed following command register write accesses
Document #: 38-08030 Rev. *G Page 12 of 38
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