Page 1
FM24C04B
4-Kbit (512 × 8) Serial (I2C) F-RAM
256-Kbit (32 K × 8) Serial (I2C) nvSRAM
Address
Latch
512 x 8
F-RAM Array
Data Latch
8
SDA
Counter
Serial to Parallel
Converter
Control Logic
SCL
WP
A2-A1
9
8
Logic Block Diagram
Features
Functional Overview
■ 4-Kbit ferroelectric random access memory (F-RAM) logically
organized as 512 × 8
❐ High-endurance 100 trillion (10
❐ 151-year data retention (See the Data Retention and
14
) read/writes
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ Fast 2-wire Serial interface (I
❐ Up to 1-MHz frequency
❐ Direct hardware replacement for serial (I
❐ Supports legacy timings for 100 kHz and 400 kHz
■ Low power consumption
❐ 100 A active current at 100 kHz
❐ 4 A (typ) standby current
■ Voltage operation: V
■ Industrial temperature: –40 C to +85 C
■ 8-pin small outline integrated circuit (SOIC) package
■ Restriction of hazardous substances (RoHS) compliant
DD
2
C)
= 4.5 V to 5.5 V
2
C) EEPROM
The FM24C04B is a 4-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by EEPROM and other nonvolatile
memories.
Unlike EEPROM, the FM24C04B performs write operations at
bus speed. No write delays are incurred. Data is written to the
memory array immediately after each byte is successfully
transferred to the device. The next bus cycle can commence
without the need for data polling. In addition, the product offers
substantial write endurance compared with other nonvolatile
memories. Also, F-RAM exhibits much lower power during writes
than EEPROM since write operations do not require an internally
elevated power supply voltage for write circuits. The FM24C04B
is capable of supporting 10
14
read/write cycles, or 100 million
times more write cycles than EEPROM.
These capabilities make the FM24C04B ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of EEPROM can cause data loss. The
combination of features allows more frequent data writing with
less overhead for the system.
The FM24C04B provides substantial benefits to users of serial
2
C) EEPROM as a hardware drop-in replacement. The device
(I
specifications are guaranteed over an industrial temperature
range of –40 C to +85 C.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-84446 Rev. *D Revised February 19, 2014
Page 2
FM24C04B
Contents
Pinout ................................................................................3
Pin Definitions ..................................................................3
Overview ............................................................................4
Memory Architecture ....................................... ... .. ............4
I2C Interface ......................................................................4
STOP Condition (P) .....................................................4
START Condition (S) ...................................................4
Data/Address Transfer ................................................5
Acknowledge / No-acknowledge .................................5
Slave Device Address .................................................6
Addressing Overview (Word Address) ........................6
Data Transfer ..............................................................6
Memory Operation ....................... ... ..................................6
Write Operation ............................ ... .. ..........................6
Read Operation ...........................................................7
Endurance ......................................................................... 8
Maximum Ratings .............................................................9
Operating Range ...............................................................9
DC Electrical Characteristics ..........................................9
Data Retention and Endurance .....................................10
Capacitance ....................................................................10
Thermal Resistance ........................................................10
AC Test Loads and Waveforms .....................................10
AC Test Conditions ........................................................10
AC Switching Characteristics .......................................11
Power Cycle Timing .......................................................12
Ordering Information ......................................................13
Ordering Code Definitions .........................................13
Package Diagram ............................................................14
Acronyms ........................................................................ 15
Document Conventions .................................................15
Units of Measure ........................... ... .........................15
Document History Page .................................................16
Sales, Solutions, and Legal Information ......................17
Worldwide Sales and Design Support .......................17
Products ....................................................................17
PSoC® Solutions ......................................................17
Cypress Developer Community .................................17
Technical Support .....................................................17
Document Number: 001-84446 Rev. *D Page 2 of 17
Page 3
FM24C04B
Pinout
WP
SCL
1
2
3
4
5
NC
8
7
6
V
DD
SDA
A1
Top View
not to scale
V
SS
A2
Figure 1. 8-pin SOIC pinout
Pin Definitions
Pin Name I/O Type Description
A2-A1 Input Device Select Address 2-1. These pins are used to select one of up to 4 devices of the same type on
the same I
sponding bits contained in the slave address. The address pins are pulled down internally.
SDA Input/Output Serial Data/Address. This is a bi-directional pin for the I
to be wire-AND'd with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for
noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor
is required.
SCL Input Serial Clock. The serial clock pin for the I
edge, and into the device on the rising edge. The SCL inp ut also incorporates a Schmitt trigger in put
for noise immunity.
WP Input Write Protect. When tied to V
WP is connected to ground, all addresses are write enabled. This pin is pulled down internally.
V
SS
V
DD
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
2
C bus. To select the device, the address value on the three pins must match the corre-
2
C interface. It is open-drain and is intended
2
C interface. Data is clocked out of the device on the falling
, addresses in the entire memory map will be write-protected. When
DD
Document Number: 001-84446 Rev. *D Page 3 of 17
Page 4
FM24C04B
Overview
Microcontroller
Vcc
SDA
SCL
Vcc
Vcc
1A1A1A
A2
A2
A2
LCSLCSLCS
SDA
ADSADS
PWPWPW
#0
#1
#3
R
Pmin
= (VDD - VOLmax) / I
OL
R
Pmax
= tr / (0.8473 * Cb)
The FM24C04B is a serial F-RAM memory. The memory array
is logically organized as 512 × 8 bits and is accessed using an
industry-standard I
F-RAM is similar to serial (I
between the FM24C04B and a serial (I
2
C interface. The functional operation of the
2
C) EEPROM. The major difference
2
C) EEPROM with the
same pinout is the F-RAM's superior wri te performance, high
endurance, and low power consumption.
Memory Architecture
When accessing the FM24C04B, the user addresses 512
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the I
protocol, which includes a slave address (to distinguish other
non-memory devices), a page address bit, and a word address.
The word address consists of 8-bits that specify one of the 256
addresses. The page address is 1-bit and so there are 2 pages
of 256 locations. The complete address of 9-bits specifies each
byte address uniquely.
The access time for the memory operation is essentially ze ro,
beyond the time needed for the serial protocol. That is, the
memory is read or written at the speed of the I
2
serial (I
C) EEPROM, it is not necessary to poll the device for a
2
C bus. Unlike a
ready condition because writes occur at bus speed. By the time
2
a new bus transaction can be shifted into the device, a write
operation is complete. This is explained in more detail in the
interface section.
Note that the FM24C04B contains no power management
circuits other than a simple internal power-on reset. It is the
user’s responsibility to ensure that V
tolerances to prevent incorrect operation.
is within data sheet
DD
I2C Interface
The FM24C04B employs a bi-directional I2C bus protocol using
few pins or board space. Figure 2 illustrates a typical system
configuration using the FM24C04B in a microcontroller-based
system. The industry standard I
C
but is described in this section.
By convention, any device that is sending data onto the bus is
the transmitter while the target device for this data is the receiver.
The device that is controlling the bus is the master. The master
is responsible for generating the clock signal for all operations.
Any device on the bus that is being controlled i s a slave. The
FM24C04B is always a slave device.
The bus protocol is controlled by transition states in the SDA and
SCL signals. There are four conditions including START, STOP,
data bit, or acknowledge. Figure 3 and Figure 4 illustrates the
signal conditions that specify the four states. Detailed timing
diagrams are shown in the electrical specifications section.
2
C bus is familiar to many users
STOP Condition (P)
A STOP condition is indicated when th e bu s ma ste r dri v e s SDA
from LOW to HIGH while the SCL signal is HIGH. All operations
using the FM24C04B should end with a STOP condition. If an
operation is in progress when a STOP is asserted, the operation
will be aborted. The master must have control of SDA in order to
assert a STOP condition.
Document Number: 001-84446 Rev. *D Page 4 of 17
Figure 2. System Configuration using Serial (I
2
C) nvSRAM
START Condition (S)
A STAR T condition is indicated when the bus master drives SDA
from HIGH to LOW while the SCL signal is HIGH. All commands
should be preceded by a START condition. An operation in
progress can be aborted by asserting a START condition at any
time. Aborting an operation using the STAR T condition will ready
the FM24C04B for a new operation.
If during operation the power supply drops below the specified
V
DD
to performing another operation.
minimum, the system should issue a START condition prior
Page 5
FM24C04B
Figure 3. START and STOP Conditions
full pagewidth
SDA
SCL
P
STOP Condition
SDA
SCL
S
START Condition
handbook, full pagewidth
S
or
P
SDA
S
P
SCL
STOP or
START
condition
S
START
condition
2 3 4 - 8 9
ACK
9
ACK
78
12
MSB
Acknowledgement
signal from slave
Byte complete
Acknowledgement
signal from receiver
1
handbook, full pagewidth
S
START
Condition
9821
Clock pulse for
acknowledgement
No Acknowledge
Acknowledge
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
SCL FROM
MASTER
Figure 4. Data Transfer on the I2C Bus
Data/Address Transfer
All data transfers (including addresses) take place while the SCL
signal is HIGH. Except under the three conditions described
above, the SDA signal should not change while SCL is HIGH.
Acknowledge / No-acknowledge
The acknowledge takes place after the 8th data bit has been
transferred in any transaction. During this state the transmitter
should release the SDA bus to allow the receiver to drive it. The
receiver drives the SDA signal LOW to acknowledge receipt of
the byte. If the receiver does not drive SDA LOW, the condition
is a no-acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two distinct reasons.
First is that a byte transfer fails. In this case, the no-acknowledge
ceases the current operation so that the device can be
addressed again. This allows the last byte to be recovered in the
event of a communication error.
Second and most common, the receiver does not acknowledge
to deliberately end an operation. For example, during a read
operation, the FM24C04B will continue to place data onto the
bus as long as the receiver sends acknowledges (and clocks).
When a read operation is complete and no more data is needed,
the receiver must not acknowledge the last byte. If the receiver
acknowledges the last byte, this will cause the FM24C04B to
attempt to drive the bus on the next clock while the master is
sending a new command such as STOP.
Figure 5. Acknowledge on the I2C Bus
Document Number: 001-84446 Rev. *D Page 5 of 17
Page 6
FM24C04B
Slave Device Address
handbook, halfpage
R/W
LSBMSB
Slave ID
10
1
0
A2A0A1
Device
Select
Page
select
S ASlave Address 0
Word Address
A Data Byte A P
By Master
By F-RAM
Start Address & Data Stop
Acknowledge
The first byte that the FM24C04B expects after a START
condition is the slave address. As shown in Figure 6, the slave
address contains the device type or slave ID, the device select
address bits, a page select bit, and a bit that specifies if the
transaction is a read or a write.
Bits 7-4 are the device type (slave ID) and should be set to 1010b
for the FM24C04B. These bits allow other function types to
reside on the I
2
C bus within an identical address range. Bits 3-2
are the device select address bits. They must match the corresponding value on the external address pins to select the device.
Up to four FM24C04B devices can reside on the same I
2
C bus
by assigning a different address to each. Bit 1 is the page select
bit. It specifies the 256-byte block of memory that is targeted for
the current operation. Bit 0 is the read/write bit (R/W
indicates a read operation and R/W
= ‘0’ indicates a write
). R/W = ‘1’
operation.
Figure 6. Memory Slave Device Address
Addressing Overview (Word Address)
After the FM24C04B (as receiver) acknowledges the slave
address, the master can place the word address on the b us for
a write operation. The word address is the lower 8-bits of the
address to be combined with the 1-bit page select to specify
exactly the byte to be written. The complete 9-bit address is
latched internally. No word address occurs for a read operation.
Reads always use the lower 8-bits that are held internally in the
address latch and the 9th address bit is part of the slave address.
Reads always begin at the address following the previous
access. A random read address can be loaded by doing a write
operation as explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24C04B increments the internal address
latch. This allows the next sequential byte to be accessed with
no additional addressing. After the last address (1FFh) is
reached, the address latch will roll over to 000h. There is no limit
to the number of bytes that can be accessed with a single read
or write operation.
Data Transfer
After the address bytes have been transmitted, data transfer
between the bus master and the FM24C04B can begin. F or a
read operation the FM24C04B will place 8 data bits on the bus
then wait for an acknowledge from the master. If the
acknowledge occurs, the FM24C04B will transfer the next
sequential byte. If the acknowledge is not sent, the FM24C04B
will end the read operation. For a write operation, the FM24C04B
will accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most significant bit)
first.
Memory Operation
The FM24C04B is designed to operate in a manner very similar
to other I
result from the higher performance write capability of F-RAM
technology. These improvements result in some differences
between the FM24C04B and a similar configuration EEPROM
during writes. The complete operation for both writes and reads
is explained below.
Write Operation
All writes begin with a slave address, then a word address. The
bus master indicates a write operation by setting the LSB of the
slave address (R/W
sends each byte of data to the memory and the memory
generates an acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range is reached
internally, the address counter will wrap from 1FFh to 000h.
Unlike other nonvolatile memory technologies, there is no
effective write delay with F-RAM. Since the read and write
access times of the underlying memory are the same, the user
experiences no delay through the bus. The entire memory cycle
occurs in less time than a single bus clock. Therefore, any
operation including read or write can occur immediately following
a write. Acknowledge polling, a technique used with EEPROMs
to determine if a write is complete is unnecessary and will always
return a ready condition.
Internally, an actual memory write occurs after the 8th data bit is
transferred. It will be complete before the acknowledge is sent.
Therefore, if the user desires to abort a write without altering the
memory contents, this should be done using START or STOP
condition prior to the 8th data bit. The FM24C04B uses no page
buffering.
The memory array can be write-protected using the WP pin.
Setting the WP pin to a HIGH condition (V
all addresses. The FM24C04B will not acknowledge data bytes
that are written to protected addresses. In addition, the address
counter will not increment if writes are attempted to these
addresses. Setting WP to a LOW state (V
protect. WP is pulled down internally.
Figure 7 and Figure 8 below illustrate a single-byte and
multiple-byte write cycles.
2
C interface memory products. The major differences
bit) to a '0'. After addressing, the bus master
) will write-protect
DD
) will disable the write
SS
Document Number: 001-84446 Rev. *D Page 6 of 17
Figure 7. Single-Byte Write
Page 7
FM24C04B
Figure 8. Multi-Byte Write
S ASlave Address 0 Word Address A Data Byte A P
By Master
By F-RAM
Start Address & Data Stop
Acknowledge
Data ByteA
S ASlave Address 1 Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
Acknowledge
No
Acknowledge
Data
S ASlave Address 1 Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
Acknowledge
No
Acknowledge
Data
Data ByteA
Acknowledge
Read Operation
There are two basic types of read operations. They are current
address read and selective address read. In a current address
read, the FM24C04B uses the internal address latch to supply
the lower 8 address bits. In a selective read, the user performs
a procedure to set these lower address bits to a specific value.
Current Address & Sequential Read
As mentioned above the FM24C04B uses an internal latch to
supply the lower 8 address bits for a read operation. A current
address read uses the existing value in the address latch as a
starting place for the read operation. The system reads from the
address immediately following that of the last operation.
To perform a cu rrent address read, the bus master supplies a
slave address with the LSB set to a '1'. This indicates that a read
operation is requested. The page select bit in the slave address
specifies the block of memory that is used for the read operation.
After receiving the complete slave address, the FM24C04B will
begin shifting out data from the current address on the next
clock. The current address is the bit from the slave address
combined with the 8-bits that were in the internal address latch.
Beginning with the current address, the bus master can read any
number of bytes. Thus, a sequential read is simply a current
Figure 9. Current Address Read
address read with multiple byte transfers. After each byte the
internal address counter will be incremented.
Note Each time the bus master acknowledges a byte, this
indicates that the FM24C04B should read out the next sequential
byte.
There are four ways to properly terminate a read operation.
Failing to properly terminate the read will most likely create a bus
contention as the FM24C04B attempts to read out additional
data onto the bus. The four valid methods are:
1. The bus master issues a no-acknowledge in the 9th clock
cycle and a STOP in the 10th clock cycle. This is illustrated in
the diagrams below. This is preferred.
2. The bus master issues a no-acknowledge in the 9th clock
cycle and a START in the 10th.
3. The bus master issues a STOP in the 9th clock cycle.
4. The bus master issues a START in the 9th clock cycle.
If the internal address reaches 1FFh, it will wrap around to 000h
on the next read cycle. Figure 9 and Figure 10 below show the
proper operation for current address reads.
Figure 10. Sequential Read
Document Number: 001-84446 Rev. *D Page 7 of 17
Page 8
FM24C04B
Selective (Random) Read
S ASlave Address 1 Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
No
Acknowledge
Data
Data ByteA
Acknowledge
S ASlave Address 0 Word Address A
Start
Address
Acknowledge
There is a simple technique that allows a user to select a random
address location as the starting point for a read operation. This
involves using the first two bytes of a write operation to set the
internal address followed by subsequent read operations.
To perform a selective read, the bus master sends out the slave
address with the LSB (R/W) set to 0. This specifies a write
Figure 11. Selective (Random) Read
operation. According to the write protocol, the bus master then
sends the word address byte that is loaded into the internal
address latch. After the FM24C04B acknowledges the word
address, the bus master issues a START condition. This simultaneously aborts the write operation and allows the read
command to be issued with the slave address LSB set to a '1'.
The operation is now a current address read.
Endurance
The FM24C04B internally operates with a read and restore
mechanism. Therefore, endurance cycles are applied for each
read or write cycle. The memory architecture is based on an
array of rows and columns. Each read or write access causes an
endurance cycle for an entire row. In the FM24C04B, a row is 64
bits wide. Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring frequently
accessed data is located in different rows. Regardless, F-RAM
read and write endurance is effectively unlimited at the 1-MHz
2
I
C speed. Even at 3000 accesses per second to the same row,
10 years time will elapse before 1 trillion endurance cycles occur.
Document Number: 001-84446 Rev. *D Page 8 of 17
Page 9
FM24C04B
Maximum Ratings
Notes
1. Typical values are at 25 °C, V
DD
= V
DD
(typ). Not 100% tested.
2. The input pull-down circuit is strong (40 k) when the input voltage is below V
IL
and weak (1 M) when the input voltage is above VIH.
3. These parameters are guaranteed by design and are not tested.
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum junction temperature ...................................95 C
Supply voltage on V
Input voltage .......... –1.0 V to + 7.0 V and V
relative to VSS .........–1.0 V to +7.0 V
DD
< V
IN
DD
+ 1.0 V
DC voltage applied to outputs
in High-Z state ....................................–0.5 V to V
+ 0.5 V
DD
Transient voltage (< 20 ns) on
any pin to ground potential .................–2.0 V to V
+ 2.0 V
DD
Package power dissipation
capability (T
= 25 °C) .......................................... .. .....1.0 W
A
DC Electrical Characteristics
Surface mount lead soldering
temperature (10 seconds) .......................................+260 C
Electrostatic Discharge Voltage
Human Body Model
Charged Device Model
Machine Model
(AEC-Q100-002 Rev. E) ..................... 3 kV
(AEC-Q100-011 Rev. B) ............. 1.25 kV
(AEC-Q100-003 Rev. E) ............................250 V
Latch-up current .................................................... > 140 mA
* Exception: The "V
IN
< V
+ 1.0 V" restriction does not apply
DD
to the SCL and SDA inputs.
Operating Range
Range Ambient Temperature (TA) V
Industrial –40 C to +85 C 4.5 V to 5.5 V
DD
Over the Operating Range
Parameter Description Test Conditions Min Typ
V
I
I
I
DD
DD
SB
LI
Power supply 4.5 5.0 5.5 V
or
f
= 100 kHz – – 100 A
SCL
f
= 400 kHz – – 200 A
SCL
f
= 1 MHz – – 400 A
SCL
–410A
–1 – +1 A
Average VDD current SCL toggling
between
V
– 0.3 V and VSS,
DD
other inputs V
V
– 0.3 V.
DD
SS
Standby current SCL = SDA = VDD. All other inputs VSS
Input leakage current
or V
VSS < VIN < V
Stop command issued.
DD.
DD
(Except WP and A2-A1)
Input leakage current
VSS < VIN < V
DD
–1 – +100 A
(for WP and A2-A1)
I
V
V
V
R
V
LO
IH
IL
OL
[2]
in
HYS
[3]
Output leakage current VSS < VIN < V
DD
Input HIGH voltage 0.7 × V
–1 – +1 A
DD
Input LOW voltage – 0.3 – 0.3 × V
Output LOW voltage I
Input resistance (WP, A2-A1) For V
Input Hysteresis 0.05 × V
= 3 mA – – 0.4 C
OL
For V
IN
IN
= V
= V
IL (Max)
IH (Min)
40 – – k
1––M
DD
[1]
Max Unit
–VDD + 0.3 V
V
DD
––V
Document Number: 001-84446 Rev. *D Page 9 of 17
Page 10
FM24C04B
Data Retention and Endurance
5.5 V
OUTPUT
100 pF
1.7 k
Note
4. These parameters are guaranteed by design and are not tested.
Parameter Description Test condition Min Max Unit
T
NV
DR
C
Data retention TA = 85 C10–Years
T
= 75 C38–
A
TA = 65 C 151 –
Endurance Over operating temperature 10
14
– Cycles
Capacitance
Parameter
C
O
C
I
[4]
Output pin capacitance (SDA) TA = 25 C, f = 1 MHz, V
Input pin capacitance 6pF
Description Test Conditions Max Unit
= VDD(typ) 8 pF
DD
Thermal Resistance
Parameter
JA
JC
[4]
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Description Test Conditions 8-pin SOIC Unit
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.
147 C/W
47 C/W
AC Test Loads and Waveforms
Figure 12. AC Test Loads and Waveforms
AC Test Conditions
Input pulse levels .................................10% and 90% of V
Input rise and fall times .................................................10 ns
Input and output timing reference levels ................ 0.5 × V
Output load capacitance ............................................100 pF
DD
DD
Document Number: 001-84446 Rev. *D Page 10 of 17
Page 11
FM24C04B
AC Switching Characteristics
t
SU:SDA
Start
t
R
`
t
F
Stop Start
t
BUF
t
HIGH
1/fSCL
t
LOW
t
SP
t
SP
Acknowledge
t
HD:DAT
t
SU:DAT
t
AA
t
DH
SCL
SDA
t
SU:STO
Start
Stop Start Acknowledge
t
AA
t
HD:DAT
t
HD:STA
t
SU:DAT
SCL
SDA
Notes
5. Test condit ions assume signal transition t ime of 10 ns or l ess, timing reference level s of V
DD
/2, input pulse levels of 0 to VDD(typ), and output loading of the specified
IOL and load capacitance shown in Figure 12.
6. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to f
SCL
(max).
7. These parameters are guaranteed by design and are not tested.
Over the Operating Range
Alt.
Parameter
[6]
f
SCL
t
SU; STA
t
HD;STA
t
LOW
t
HIGH
t
SU;DAT
t
HD;DAT
t
DH
[7]
t
R
[7]
t
F
t
SU;STO
t
AA
t
BUF
t
SP
[5]
Parameter
t
SU;DATA
t
HD;DATA
t
r
t
f
t
VD;DATA
SCL clock frequency – 0.1 – 0.4 – 1.0 MHz
Start condition setup for repeated Start 4.7 – 0.6 – 0.25 – ns
Start condition hold time 4.0 – 0.6 – 0.25 – ns
Clock LOW period 4.7 – 1.3 – 0.6 – ns
Clock HIGH period 4.0 – 0.6 – 0.4 – ns
Data in setup 250 – 100 – 100 – ns
Data in hold 0 – 0 – 0 – ns
Data output hold (from SCL @ VIL)0–0–0–ns
Input rise time – 1000 – 300 – 300 ns
Input fall time – 300 – 300 – 100 ns
STOP condition setup 4.0 – 0.6 – 0.25 – ns
SCL LOW to SDA Data Out Valid – 3 – 0.9 – 0.55 ns
Bus free before new transmission 4.7 – 1.3 – 0.5 – ns
Noise suppression time constant on SCL, SDA – 50 – 50 – 50 ns
Description Min Max Min Max Min Max Unit
Figure 13. Read Bus Timing Diagram
Figure 14. Write Bus Timing Diagram
Document Number: 001-84446 Rev. *D Page 11 of 17
Page 12
FM24C04B
Power Cycle Timing
SDA
~
~
t
PU
t
VR t
VF
V
DD
V
DD(min)
t
PD
V
DD(min)
I C START
2
I C STOP
2
Notes
8. Slope measured at any point on the V
DD
waveform.
9. Guaranteed by design.
Over the Operating Range
Parameter Description Min Max Unit
t
PU
t
PD
t
VR
t
VF
[8, 9]
[8, 9]
Power-up VDD(min) to first access (START condition) 1 – ms
Last access (STOP condition) to power-down (VDD(min)) 0 – µs
VDD power-up ramp rate 30 – µs/V
VDD power-down ramp rate 30 – µs/V
Figure 15. Power Cycle Timing
~
~
Document Number: 001-84446 Rev. *D Page 12 of 17
Page 13
FM24C04B
Ordering Information
Option:
Blank = Standard; T = Tape and Reel
Package Type: G = 8-pin SOIC
Die Revision = B
Density: 04 = 4-kbit
Voltage: C = 4.5 V to 5.5 V
I
2
C F-RAM
Cypress
24FM C 04 B G TR-
Ordering Code
Package
Diagram
Package Type
Operating
Range
FM24C04B-G 001-85066 8-pin SOIC Industrial
FM24C04B-GTR
All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
Document Number: 001-84446 Rev. *D Page 13 of 17
Page 14
FM24C04B
Package Diagram
51-85066 *F
51-85066 *F
Figure 16. 8-pin SOIC (150 mils) Package Outline, 51-85066
Document Number: 001-84446 Rev. *D Page 14 of 17
Page 15
FM24C04B
Acronyms Document Conventions
Acronym Description
ACK Acknowledge
CMOS Complementary Metal Oxide Semiconductor
EIA Electronic Industries Alliance
2
C Inter-Integrated Circuit
I
I/O Input/Output
JEDEC Joint Electron Devices Engineering Council
LSB Least Significant Bit
MSB Most Significant Bit
NACK No Acknowledge
RoHS Restriction of Hazardous Substances
R/W
SCL Serial Clock Line
SDA Serial Data Access
SOIC Small Outline Integrated Circuit
WP Write Protect
Read/Write
Units of Measure
Symbol Unit of Measure
°C degree Celsius
Hz hertz
Kb 1024 bit
kHz kilohertz
k kilohm
MHz megahertz
M megaohm
A microampere
s microsecond
mA milliampere
ms millisecond
ns nanosecond
ohm
% percent
pF picofarad
V volt
W watt
Document Number: 001-84446 Rev. *D Page 15 of 17
Page 16
FM24C04B
Document History Page
Document Title: FM24C04B, 4-Kbit (512 × 8) Serial (I2C) F-RAM
Document Number: 001-84446
Rev. ECN No.
** 3902082 02/25/2013 GVCH New spec
*A 3924523 03/07/2013 GVCH Changed t
*B 3996669 05/13/2013 GVCH Added Appendix A - Errata for FM24C04B
*C 4045469 06/30/2013 GVCH All errata items are fixed and the errata is removed.
*D 4283418 02/19/2014 GVCH Converted to Cypress standard format
Submission
Date
Orig. of
Change
Description of Change
spec value from 10 ms to 1 ms
PU
Changed endurance value from 10
Updated Maximum Ratings tabl e
- Removed Moisture Sensitivity Level (MSL)
- Added junction temperature and latch up current
Added Input leakage current (I
Updated Data Retention and Endurance table
Added Thermal Resistance table
Removed Package Marking Scheme (top mark)
Completing sunset review
12
to 1014 cycles
) for WP and A2-A1
LI
Document Number: 001-84446 Rev. *D Page 16 of 17
Page 17
FM24C04B
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive cypress.com/go/automotive
Clocks & Buffers cypress.com/go/clocks
Interface cypress.com/go/interface
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wirelessFM24VN10
PSoC® Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
© Cypress Semiconductor Corporation, 2013-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical co ntr ol o r safe ty ap pl ic at io ns, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunct ion or failure may reasonably be expected to result in significa nt injury to th e user. The inclusion of Cypress products in life- support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Co de except as speci fied above is pro hibited with out
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypres s does not
assume any liability arising out of the applic ation or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot author ize its p roducts fo r use as critical compon ents in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-84446 Rev. *D Revised February 19, 2014 Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
Loading...