Cypress CY7C656xx, EZ-USB HX2LP User Manual
PRELIMINARY
™
ily
x
CY7C656x
EZ-USB HX2LP
Low-Power USB 2.0 Hub Controller Fam
1.0 Features
• USB 2.0 hub controller
• Compliant with the USB 2.0 specification
• Windows
• Up to four downstream ports supported
• Supports bus-power and self powered modes
• Single-TT and Multi-TT modes supported
—Single-TT option for low-cost
—Multi-TT option for high performance
•2-Port
—Single TT option for bus power
• Fit/form/function compatible option with CY7C65640
(TetraHub)
• Multiple package options
—Space -saving 56 QFN
• Single power supply requirement
—Internal regulat or for reduced cost
• Integrated up stream pull-up resist or
• Integrated pull -down resistors for a ll downstream port s
• Integrated up stream and downstream terminati on
resistors
• Integrated port status indicator controls
• 24-MHz external crystal (inte grated PLL)
• Configurable with external SPI EEPROM
—Ven dor ID, Product ID, Device ID (VID/PID/DID)
—N um ber of active ports
—N um ber of removable ports
—Maximum power setting for high-speed and full-
speed
—H ub controller power setting
—Power-on timer
—Overcurrent detection mode
—Overcurrent timer
—Enable/Disable overcurrent timer
—Overcurrent pin polarity
—indicator pin polar ity
—Compound device
—Enable full-speed only
—Disable port indicators
—Gang power switching
—Enable single-TT mode only
—Self/bus powered compatibility
—Fully configurable string descriptors for multiple
language support
• In-system EEPROM programming
Hardware-quality lab (WHQL)-compliant
2.0 Introduction
EZ-USB HX2LP is Cypress’s nex t- generat ion fami ly of highperformance, low-powe r USB 2.0 hub controllers. HX2LP is an
ultra low-power single-chip USB 2.0 hub controller with
integrated upstream and downstream transceivers, a USB
Serial Inter face Engine (SIE), USB Hub Con tr ol and Repeate r
logic, and T ransac tion T ranslat or (TT) l ogic. Cypress has also
integrated many of the external passive component s, such as
pull-up and pull-down resistors, reducing the overall bill-ofmaterials required to implement a hub design. The entire
HX2LP portfolio consi sts of:
1. CY7C65640B (TetraHub LP): 4-port/multiple transaction
translator
This device option is fit/form/function compatible with Cypress’s existing CY7C65640 device. Cypress’s “Tetra” architecture provi des four downstream USB ports, each with
a dedicated T ransact ion T ranslator (TT), maki ng it t he highest-performance hub available. The TetraHub LP also offers best-in-class power consumption. The CY7C65640B is
available in a 56 QF N (TetraHub pin-compatible) for space
saving designs.
2. CY7C65630: 4-port/single transaction translator
This device option is for ultra low-cost applications where
performance is secondary consideration. All four ports
must share a single transaction translator in this configuration. The CY7C65630 is available in a 56 QFN and is also
pin for pin-compatible with the CY7C65640.
3. CY7C65620:
This device option is for a 2-port bus powered application.
Both ports must share a single transaction translator in this
configuration. The CY7C65620 is available in a 56 QFN
and is also pin for pin compatible with the CY7C65640.
All device options are supported by Cypress’s world-class
reference design kits, which include board schematics, bill of
materials, Gerber files, Orcad files, and thorough design
documentation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-08037 Rev. *D Revised March 31, 2005
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3.0 Block Diagrams
D+ D -
PRELIMINARY
CY7C656x
24
MHz
Crystal
USB 2.0 PHY
PLL
USB Upstream Port
Hub Repeater
USB Downstream Port 1
USB 2.0
PHY
Port Power
Control
Port
Status
Interface
USB Downstream Port 2
USB 2.0
PHY
Port Power
Control
Serial
Engine
Transaction Translator (X4)
Routin g L o gi c
USB Downstream Port 3
Port
Status
USB 2.0
PHY
TT RAM
Port Power
Control
USB Control Logic
SPI Communication
Port
Status
USB 2.0
High-Speed
Block
USB Downstream Port 4
PHY
Port Power
Control
Port
Status
SPI_SCK
SPI_SD
SPI_CS
OVR #[ 1 ]
LED
OVR #[ 2 ]
LEDD+ D- P WR#[1]
OVR#[3]
LEDD+ D- PWR#[2]
D+ D- PWR#[4]
OVR #[ 4 ]
LEDD+ D- PWR#[3]
Figure 3-1. CY7C65640B Block Diagram
Document #: 38-08037 Rev. *D Page 2 of 23
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3.0 Block Diagrams (continued)
D+ D -
PRELIMINARY
CY7C656x
24 MHz
Crys ta l
USB 2.0 PHY
PLL
USB Upstream Port
Hub Repeater
USB Downstream Port 1
USB 2.0
Port Power
PHY
Control
OVR # [1]
Port
Status
LED
Interface
USB Downstream Port 2
USB 2.0
Port Power
PHY
Control
OVR # [2]
Serial
Engine
Transac t ion Translator (X1)
Routing Logic
USB Downstream Port 3
Port
USB 2.0
Status
PHY
LEDD+ D- P W R#[1]
TT RA M
Port Power
Control
OVR # [3]
USB C ontrol Logi c
SPI Communication
Port
USB 2 .0
Status
D+ D- PW R#[ 4 ]
LEDD+ D- PWR#[2]
High-Speed
Block
USB Downstream Port 4
PHY
Port Power
Control
OVR#[4]
Port
Status
SPI_SCK
SPI_SD
SPI_CS
LEDD+ D- PW R#[3]
This applies to CY7C65630 only.
Figure 3-2. CY7C65630/CY7C65620 Block Diagram
Document #: 38-08037 Rev. *D Page 3 of 23
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PRELIMINARY
CY7C656x
3.1 USB Serial Interface Engine (SIE)
The SIE allows the CY7C656x x to commu nicate wit h the USB
host through the USB repeater component of the HUB. The
SIE handles the following USB activity independently of the
HUB Control Block:
• Bit stuffing/unstuffing
• Checksum generation/checking
• ACK/NAK/STALL
• TOKEN type identification
• Address checking.
3.2 Hub Repeater
The HUB Repeater manages the connectivity between
upstream and downstream facing ports that are operating at
the same speed. It supports full-/low-speed connectivity and
high-speed connectivity. Per the USB 2.0 specification, the
HUB Repeater provides the following functions:
• Sets up a nd tears down connectivity on packet boun daries
• Ensures orderly entry into and out of the Suspend state,
including proper handling of remote wakeups.
3.3 Transaction T r anslator (TT)
The TT basically transl ates dat a from one sp eed to another. A
TT takes high-speed split transactions and translates them to
full-/low-speed transactions when the HUB is operating at
high-speed (the upstream port is connected to a high-speed
host controller) and has full-/low-speed devices at tached. The
operating spee d of a device at tached on a downstream fac ing
port determi nes whether the Routing Logi c connects a port to
the Transaction Translator or Hub Repeater section. If a low/full-speed device is connected to the hub operating at highspeed, the data transfer route includes the transaction translator. If a high-speed device is connected to this high-speed
hub the route only includes the repeater and no transaction
translator since the device and the hub are in conformation
with respect to their data transfer speed. When the hub is
operating at full speed (the upstream port is connected to a
full-speed host controller), a high-speed peripheral will not
operate at its f ull capabi lity . The se devices will onl y work at 1.1
speed. Full- and low-speed devices connected to this hub will
operate at their 1. 1 speed.
4.0 Applications
• Ty pical applications for the HX2LP device family are :
• St andalone hubs
• Motherboard hubs
• Monitor hubs
• Advanced port replicators
• Docking stations
• Split-PC designs
• External personal storage drives
• Keyboard hubs
5.0 Functional Overview
The Cypress CY7C656xx USB 2.0 Hubs are a high-performance, low-system-cost solution for USB. The CY7C656xx
USB 2.0 Hubs integrate 1.5k up stream pull-up resi stors for fullspeed operation and all downstream 15k pull-down resistors
as well as series termination resistors on all upstream and
downstream D+ and D– pins. This results in optimization of
system costs by providing built-in support for the USB 2.0
specification.
5.1 System Initialization
On power-up, the CY7C656xx will read an external SPI
EEPROM for configuration information. At the most basic
level, this EEPROM will have the Vendor ID ( VID) , Product ID
(PID), and Device ID (DID) for the customer 's application. For
more speciali zed appl icati ons, othe r conf igurat ion opt ions can
be specified. See secti on 9.0 for more detail s.
After reading the EEPROM, if BUSPOWER (connected t o upstream VBus) is HIGH, CY7C656xx will enable the pull-up
resistor on the D+ to indicate that it is connected to the
upstream hub, after which a USB Bus Reset is expected.
During this reset, CY7C656xx will initiate a chirp to indicate
that it is a high-speed peripheral. In a USB 2.0 system, the
upstream hub will respond with a chirp sequence, and
CY7C656xx will be in a high-speed mode, with the upstream
D+ pull-up resistor turned off. In USB 1.x systems, no such
chirp sequence from the upstream hub will be seen, and
CY7C656xx will op erat e as a normal 1. x hub (operating at full
speed).
5.2 Enume ration
After a USB Bus Reset, CY7C656xx is in an unaddressed,
unconfigured state (configuration value set to 0). During the
enumeration process, the host will set the hub's address and
configuration by sending a SetCongfiguration request.
For high-speed multi-TT support, the host must also set the
alternate inter face set ting t o 1 (the defau lt mode is singl e-TT) .
Once the hub is configured, the full hub functionality is
available.
5.3 Multiple Transaction Translator Support
After the CY7C65640B is configured in a high-speed system,
it will be in Singl e TT mode. The host may t hen set the hub into
Multiple TT mode by sending a SetInterface command. In
Multiple TT mode, each full speed port is handled independently and thus has a full 12-Mbps bandwidth available. In
Single TT mode, all traffic from the host destined for full- or
low-speed ports will be forwarded to all of those ports. This
means that the 12-Mbps bandwidth is shared by all full- and
low-speed ports.
5.4 Down stream P orts
The CY7C656xx supports a maximum of four downstream
ports, each of which may be marked as usable or removable
in the extended configuration (0xD2 EEPROM load, see
section 9.2 or 0xD4 EEPROM load, see section 9.3).
Downstream D+ and D– pull-down resistors are incorporated
in CY7C656xx for each port. Prior to the hubs being
configured, the ports are driven SE0 (Single Ended Zero,
where both D+ and D– are driven low) and are set to the
Document #: 38-08037 Rev. *D Page 4 of 23
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PRELIMINARY
CY7C656x
unpowered stat e. Once the hubs ar e configu red, the por ts ar e
not driven, and the host may power the ports by sending a
SetPortPower command to each port. After a port is powered,
any connect or disconnect event is detected by the hub. Any
change in the port state is reported by the hubs back to the
host through the Status Change Endpoint (endpoint 1). Upon
receipt of SetPort R eset command from the host, the hub will
• Drive SE0 on the corresponding port
• Put the port in an enabled state
• Enable the green por t indicator for that port (i f not previously
overridden by t he host)
• Enable babble detection once the port is enabl ed.
Babble consists of either unterminated traffic from a
downstream port (o r loss of activi ty), or a non-idle condi tion on
the port after EOF2. If babble is detected on an enabled port,
that port will be disabl ed. A Cle arPort Enable comm and from
the host will also disable the specifie d port.
Downstream ports can be individually suspended by the host
with the SetPortSuspend command. If the hubs are not
suspended, any res ume will be con fined t o that in divid ual port
and reflected to the host through a port change indication in
the Hub Status Change Endpoint. If the hubs are suspended,
a resume on this port will be forwarded to the host, but other
resume events will not be seen on that port. The host may
resume the port by sendi ng a ClearPortSuspend com m and.
5.5 Upstream Port
The upstream port includes the transmitter and the receiver
state machine. The Transmitter and Receiver operate in highspeed and full-speed depending on the current hub configuration.
The transmitter state machine monitors the upstream facing
port while the Hub Repeater has conn ectivity in the upstr eam
direction. This monitoring activity prevents propagation of
erroneous indications in the upstream direction. In particular,
this machine prevents babble and disconnect events on the
downstream facing ports of this hub from propagating and
causing the hub to be disabled or disconnected by the hub to
which it is att ached. This all ows the Hub to only disco nnect th e
offensi ve port on detecting a babble from it.
5.6 Power Switching
The CY7C656xx includes interface signals for external port
power switches. Both ganged and individu al (per-por t) confi gurations are supported, with individual switching being the
default. Initially all ports are unpowered. After enumerating,
the host may power each port by sending a SetPortPower
command for that port. The power switching and over-current
detection of downstream ports is managed by control pins
connected to an external power switch device. PWR [n]#
output pins of the CY7C656xx series are connected to the
respective external power switch's port power enable signals.
(Note that each port power output pin of the external power
switch must be bypassed with an electrolytic or tantalum
capacitor as required by the USB specification. These capacitors supply the inrush currents, which occur during
downstream device hot-attach events.) The polarity of t his pin
can be configured through the EEPROM, see section 9.3.
5.7 Over-current Detection
Over-current detection includes timed detection of 8 ms by
default. This parameter is configured from the external
EEPROM in a range of 0 ms to 15 m s for both an enabled por t
and a disabled port individually. Detection of over-current on
downstream ports is managed by control pins conn ected to an
external power switch device.
The OVR[n]# pins of the CY7C656xx serie s are connected to
the respective external power switch's port over-current
indication (output) signals. Upon detecting an over-current
condition, the hub device r eports the over-current condition to
the host and disables the PWR# output to the external power
device. The polarity of this pin can be configured through the
EEPROM, see section 9.3.
5.8 Port I ndicators
The USB 2.0 port indicators are also supported directly by the
CY7C656xx. As per the specification, each downstream port
of the hub support s an opti onal st atus i ndicat or. The presence
of indicators for downstream facing ports is specified by bit 7
of the wHubCharacteristics field of the hub class descriptor.
The default CY7C656xx descriptor specifies that port
indicators are supported (wHubCharacteristics, bit 7 is set). If
port indicators are not included in the hub, this should be
disabled by the EEPROM.
Each port indicator is strategically located directly on the
opposite edge of the port which it is associated with. The
indicator provides two colors: green an d am ber. This is implemented as two separate LEDs, one amber and the other
green. A combi nation of hardware and soft ware contr ol is u sed
to inform t he user of the cur rent stat us of the port or the d evice
attached to the port and to guide the user through problem
resolution. Colors and bl inking are use d to provide infor mation
to the user . The signific ance of the color of th e LED depend on
the operational mode of the CY7C656xx. There are tw o modes
of operation for the CY7C656xx port indicat ors: automatic and
manual.
On power-up the CY7C656xx defaults to Automatic Mode,
where the color of the Port Indicator (Green, Amber, Off)
indicates the functional status of the CY7C656xx port. In
Automatic Mode, the CY7C656xx will turn on the green LED
whenever the port is en abled and the amber LED when i t has
had an overcurrent condition detected. The color of the port
indicator is se t by the p ort st ate m achine . Bli nking of the LEDs
is not supported in Automat ic Mode. Table 5-1 below identifies
the mapping of color to port state in Automatic Mode.
T able 5-1. Automatic Port State to Port Indicator Color Mapping
Downstream Facing Hub Port State
Powered Off
Off or Amber if due to an
Overcurrent Condition
Document #: 38-08037 Rev. *D Page 5 of 23
Disconnected, Disabled, Not
Configured, Resetting, Testing
Off Green Off
Enable d , Transmit, or
TransmitR
Suspended, Resuming,
SendEOR, Restart _E /S
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PRELIMINARY
CY7C656x
The LED control lines can also be modulated with a square
wave for power conservat ion in s ystems u sing batteri es. Alon e
with this there is also a polarity control for these pins, see
section 9.3.
In manual mode, the indicators are under the control of the
host, which can turn on one of the LEDs, or leave them off.
This is done by a system software USB Hub class request.
Blinking of the LEDs is supported in Manual Mode. The port
indicators allow the user to intervene on any error detection.
For example, when babble is detected on plugging in a
defective device, o r on occur rence of a n overcu rrent con dition,
the port indicators corresponding to the downstream port will
blink green or only light the amber LED, respecti vely.
Note:
1. Information presented in Table 5-1 and Table 5-2 is from USB 2.0 specification Tables 11-6 and 11-7, respectively.
Table 5-2 displays the color definition of the indicators when
CY7C656xx is in Manual Mode.
T able 5-2. Por t Indica tor Color Definitions i n Manual Mode
Color Definition Port Stat e
Off Not operational
Amber Error condition
Green Fully Operational
Blinking Off/Green Software At tention
Blinking Off/ Am ber Hardware Attention
Blinking Green/Amber Reserved
[1]
Document #: 38-08037 Rev. *D Page 6 of 23
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6.0 Pin Configuration
PRELIMINARY
CY7C656x
DD–[4]/NC
DD+[4]/NC
VCC
GND
DD–[3]/NC
DD+[3]/NC
VCC
GND
DD–[2]
DD+[2]
VCC
GND
PWR#[3]/NC
VCC
545556
OVR#[3]/NC
53 52
PWR#[4]/NC
GND
OVR#[4]/NC
51 50 49 48 47 46 45 44 43
SPI_SD
GND
SPI_SCK
RESET
1
2
3
4
5
6
7
8
9
10
11
SELFPWR
AMBER#[4]/NC
GREEN#[4]/NC
AMBER#[3]/NC
42
41
GREEN#[3]/NC
GND
40
VCC
39
38
AMBER#[2]
GREEN#[2]
37
AMBER#[1]
36
GREEN#[1]
35
GND
34
33
VCC
OVR#[2]
32
GND
12
DD–[1]
13
DD+[1]
14
VCC
Note:
2. NC are for CY7C65620 ONLY.
D–
D+
GND
VCC
XIN
GND
VCC
XOUT
GND
SPI_CS
VBUSPOWER
Figure 6-1. 56-pin Quad Flat Pack No Leads (8 mm x 8 mm)
PWR#[2]
31
OVR#[1]
30
PWR#[1]
29
2827262524232221201918171615
VCC
GND
[2]
Document #: 38-08037 Rev. *D Page 7 of 23
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