EZ-USB® FX3™ Technical Reference Manual
Document Number: 001-76074 Rev. *F
May 9, 2019
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
www.cypress.com
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2 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F
Contents
1. Introduction to EZ-USB FX3 19
1.1 Overview of USB 3.0 ..............................................................................................................19
1.1.1 Physical Layer.............................................................................................................19
1.1.2 Link Layer....................................................................................................................20
1.1.3 Protocol Layer .............................................................................................................21
1.1.3.1 Unicast Transactions ...................................................................................21
1.1.3.2 Token/ Data/Handshake Sequences ...........................................................21
1.1.3.3 Data Bursting...............................................................................................23
1.1.3.4 End-to-End Flow Control .............................................................................24
1.1.3.5 Streams .......................................................................................................25
1.2 SuperSpeed Power Management...........................................................................................25
1.2.1 Function Power Management .....................................................................................26
1.3 FX3/FX3S Features ................................................................................................................26
1.3.1 FX3 Block Diagram .....................................................................................................28
1.3.2 FX3S Block Diagram...................................................................................................29
1.4 Functional Overview ...............................................................................................................29
1.4.1 CPU.............................................................................................................................29
1.4.2 DMA ............................................................................................................................30
1.4.3 USB Interface..............................................................................................................30
1.4.4 GPIF II.........................................................................................................................30
1.4.5 UART Interface ...........................................................................................................31
1.4.6 I2C Interface................................................................................................................31
1.4.7 I2S Interface................................................................................................................31
1.4.8 SPI Interface ...............................................................................................................31
1.4.9 JTAG Interface ............................................................................................................31
1.4.10 Storage Interface.........................................................................................................31
1.4.10.1 SD/MMC Clock Stop....................................................................................32
1.4.10.2 SD_CLK Output Clock Stop ........................................................................32
1.4.10.3 Card Insertion and Removal Detection........................................................32
1.4.10.4 Write Protection (WP)..................................................................................32
1.4.10.5 SDIO Interrupt .............................................................................................32
1.4.10.6 SDIO Read-Wait Feature ............................................................................32
1.4.10.7 Boot Options................................................................................................32
1.4.11 Clocking ......................................................................................................................33
2. FX3 CPU Subsystem 34
2.1 Features..................................................................................................................................34
2.2 Block Diagram ........................................................................................................................35
2.3 Functional Overview ...............................................................................................................35
2.3.1 ARM926EJ-S CPU......................................................................................................35
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Contents
2.3.1.1 Processor Modes.........................................................................................36
2.3.1.2 Processor Registers ....................................................................................37
2.3.1.3 Exception Vectors........................................................................................38
2.3.1.4 MMU ............................................................................................................38
2.3.1.5 Cache Memories .........................................................................................39
2.3.1.6 Tightly Coupled Memories...........................................................................39
2.3.1.7 JTAG Interface ............................................................................................40
2.3.1.8 Vectored Interrupt Controller .......................................................................40
2.3.1.9 CPU Operating Frequency ..........................................................................42
2.3.1.10 CPU Power Modes ......................................................................................42
2.3.1.11 Timers..........................................................................................................43
3. Memory and System Interconnect 44
3.1 Features..................................................................................................................................44
3.2 Block Diagram ........................................................................................................................44
3.3 Functional Overview ...............................................................................................................45
3.3.1 Memory Regions .........................................................................................................45
3.3.2 System Interconnect ...................................................................................................47
3.3.3 Low-Power Operations................................................................................................47
3.3.4 Cache Operations .......................................................................................................48
3.3.4.1 Cache Coherency........................................................................................48
3.3.5 Memory Usage............................................................................................................49
4. Global Controller (GCTL) 51
4.1 GPIO Pins...............................................................................................................................51
4.1.1 I/O Matrix Configuration ..............................................................................................51
4.1.2 I/O Drive Strength .......................................................................................................53
4.1.3 GPIO Pull-up and Pull-down .......................................................................................53
4.1.4 Simple GPIO Override ................................................................................................53
4.1.5 Complex GPIO Override .............................................................................................53
4.1.6 I/O Power Observability ..............................................................................................54
4.1.6.1 GCTL_IOPOWER........................................................................................54
4.1.6.2 GCTL_IOPWR_INTR ..................................................................................54
4.1.6.3 GCTL_IOPWR_INTR_MASK ......................................................................54
4.2 Clock Management.................................................................................................................54
4.3 Power Management................................................................................................................56
4.3.1 Power Domains...........................................................................................................56
4.3.2 Power Modes ..............................................................................................................57
4.3.3 Reset...........................................................................................................................57
4.3.4 Hard Reset ..................................................................................................................57
4.3.5 Soft Reset ...................................................................................................................57
5. FX3 DMA Subsystem 58
5.1 DMA Introduction ....................................................................................................................58
5.2 DMA Features.........................................................................................................................58
5.3 DMA Block Diagram ...............................................................................................................58
5.4 DMA Overview........................................................................................................................59
5.5 DMA Subsystem Components................................................................................................60
5.5.1 Clocking ......................................................................................................................60
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Contents
5.5.2 Descriptors Buffers, and Sockets................................................................................61
5.5.3 DMA Descriptors .........................................................................................................61
5.5.4 DMA Buffer ..................................................................................................................63
5.5.4.1 Implications of Data Cache Usage ..............................................................63
5.5.4.2 Memory Corruption Due to Cache Line Overlap .........................................64
5.5.4.3 Safe Usage of Data Cache..........................................................................64
5.5.4.4 ALIGNMENT REQUIREMENT - How Not To Share Cache Lines ..............65
5.5.5 Sockets .......................................................................................................................65
5.5.5.1 Software Manipulation of Sockets ...............................................................68
5.5.5.2 Initializing a Socket......................................................................................68
5.5.5.3 Terminating a Socket...................................................................................68
5.5.5.4 Modifying or Suspending a Socket ..............................................................68
5.5.5.5 Inspecting a Socket .....................................................................................69
5.5.5.6 Wrapping Up a Socket.................................................................................69
5.5.6 Illustration of Descriptor, Buffer and Socket Usage.....................................................69
5.5.7 Understanding DMA Operation: Peripheral to Peripheral ...........................................69
5.5.8 Interrupt Requests.......................................................................................................71
5.5.9 DMA Interrupts ............................................................................................................71
5.6 Programming Sequence .........................................................................................................72
5.6.1 Initialization .................................................................................................................72
5.6.1.1 Producer Half...............................................................................................72
5.6.1.2 Consumer Half.............................................................................................72
5.6.2 Peripheral to Peripheral Transfer ................................................................................73
5.7 CPU Intervention In Between Ingress and Egress .................................................................76
5.8 Concept of DMA Channels .....................................................................................................77
6. Universal Serial Bus (USB) 78
6.1 Introduction .............................................................................................................................78
6.2 Features..................................................................................................................................78
6.3 Block Diagram ........................................................................................................................78
6.4 Overview.................................................................................................................................79
6.4.1 USB Interface Block ....................................................................................................79
6.4.2 USB 3.0 Function Controller .......................................................................................79
6.4.3 USB 2.0 Function Controller .......................................................................................79
6.4.4 USB 2.0 Embedded Host ............................................................................................79
6.4.5 USB OTG Controller ...................................................................................................80
6.4.6 End-Point Memory ......................................................................................................80
6.4.7 DMA Adapters .............................................................................................................80
6.4.8 USB I/O System ..........................................................................................................80
6.4.8.1 USB 2.0 OTG PHY ......................................................................................80
6.4.8.2 USB 3.0 PHY...............................................................................................81
6.5 UIB Top-Level Register Interface ...........................................................................................81
6.6 USB Function Controllers .......................................................................................................83
6.6.1 USB 3.0 Function ........................................................................................................83
6.6.1.1 Clocking.......................................................................................................83
6.6.1.2 Interrupt Requests .......................................................................................83
6.6.1.3 USB 3.0 Functional Description...................................................................84
6.6.2 Physical Layer.............................................................................................................85
6.6.3 Link Layer....................................................................................................................86
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Contents
6.6.4 Protocol Layer .............................................................................................................87
6.7 USB 2.0 Function....................................................................................................................89
6.7.1 Clocking ......................................................................................................................89
6.7.2 Interrupt Requests.......................................................................................................89
6.7.3 USB 2.0 Functional Description ..................................................................................89
6.7.3.1 Serial Interface Engine ................................................................................89
6.7.3.2 Token Processor .........................................................................................89
6.7.4 USB 2.0 Function Registers........................................................................................90
6.7.5 USB Reset ..................................................................................................................90
6.7.6 USB Suspend..............................................................................................................90
6.7.7 USB Resume ..............................................................................................................90
6.7.8 Start of Frame .............................................................................................................90
6.7.9 SETUP Packet ............................................................................................................90
6.7.10 IN Packet.....................................................................................................................91
6.7.11 OUT Packet.................................................................................................................91
6.8 USB 3.0 and USB 2.0 Function Coordination .........................................................................91
6.9 USB Function Programming Model ........................................................................................92
6.9.1 USB 3.0 Initialization ...................................................................................................92
6.9.2 USB 3.0 Enable...........................................................................................................93
6.9.3 USB 3.0 Fallback to USB 2.0 ......................................................................................94
6.9.4 USB Reset ..................................................................................................................95
6.9.5 USB Connect ..............................................................................................................96
6.9.6 USB Disconnect ..........................................................................................................98
6.9.7 Control Request ..........................................................................................................99
6.9.8 USB Embedded Host ................................................................................................106
6.9.8.1 Clocking.....................................................................................................106
6.9.9 Interrupt Requests.....................................................................................................106
6.9.10 Functional Description...............................................................................................107
6.9.10.1 Embedded Host.........................................................................................107
6.9.10.2 Scheduler Memory ....................................................................................107
6.9.11 Embedded Host Programming Model .......................................................................109
6.9.11.1 Host Connect.............................................................................................109
6.9.11.2 Host Disconnect ........................................................................................109
6.9.11.3 Managing Transfers...................................................................................110
6.10 USB OTG Controller .............................................................................................................112
6.10.1 Interrupt Requests.....................................................................................................112
6.10.2 USB OTG Programming Model................................................................................. 112
6.10.2.1 USB OTG Start and Stop ..........................................................................112
6.10.2.2 Session Request Protocol ...............................
..........................................116
6.10.2.3 Host Negotiation Protocol..........................................................................118
7. General Programmable Interface II (GPIF II) 120
7.1 Features................................................................................................................................120
7.2 Block Diagram ......................................................................................................................121
7.3 Typical GPIF II interface .......................................................................................................121
7.4 Functional Overview .............................................................................................................122
7.4.1 Actions ......................................................................................................................122
7.4.1.1 Action - IN_DATA ......................................................................................124
7.4.1.2 Action - IN_ADDR......................................................................................125
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Contents
7.4.1.3 Action - DR_DATA.....................................................................................125
7.4.1.4 Action - DR_ADDR ....................................................................................126
7.4.1.5 Action - COMMIT.......................................................................................127
7.4.1.6 Action - DR_GPIO .....................................................................................127
7.4.1.7 Action - LD_ADDR_COUNT......................................................................128
7.4.1.8 Action - LD_DATA_COUNT ......................................................................128
7.4.1.9 Action - LD_CTRL_COUNT.......................................................................129
7.4.1.10 Action - COUNT_ADDR ............................................................................130
7.4.1.11 Action - COUNT_DATA .............................................................................130
7.4.1.12 Action - COUNT_CTRL .............................................................................130
7.4.1.13 Action - CMP_ADDR .................................................................................130
7.4.1.14 Action - CMP_DATA..................................................................................131
7.4.1.15 Action - CMP_CTRL ..................................................................................131
7.4.1.16 Action - INTR_CPU ...................................................................................132
7.4.1.17 Action - INTR_HOST .................................................................................132
7.4.1.18 Action - DR_DRQ ......................................................................................132
7.4.2 Triggers .....................................................................................................................133
7.4.3 Transition Conditions ................................................................................................133
7.4.4 GPIF II Designer Tool................................................................................................134
7.4.5 GPIF II Hardware Resources ....................................................................................134
7.4.5.1 Comparators..............................................................................................134
7.4.5.2 Counters ....................................................................................................135
7.4.5.3 GPIF II Interrupt.........................................................................................135
7.4.6 Threads and Sockets ................................................................................................135
7.4.6.1 Difference Between PP_MODE=0 and PP_MODE=1 ...............................135
7.4.7 Addressing ................................................................................................................137
7.4.7.1 Number of Address Lines ..........................................................................137
7.4.7.2 Assigning Sockets to Threads ...................................................................137
7.4.7.3 Addressing Methods..................................................................................137
7.4.8 Async/Sync ...............................................................................................................138
7.4.9 Configuration of Flags ...............................................................................................138
7.4.10 Developing the GPIF II State Machine......................................................................138
7.5 Designing a GPIF II Interface ...............................................................................................138
7.6 GPIF II State Machine Implementation.................................................................................141
7.6.1 Add a State ...............................................................................................................141
7.6.2 Add Actions to a State...............................................................................................142
7.6.3 Draw Transitions Between Actions............................................................................142
7.6.4 Add a Transition Equation.........................................................................................143
7.6.5 Set State Properties ..................................................................................................143
7.6.6 Analyzing the Signal Timing of the GPIF II Interface.................................................144
7.6.6.1 Selection of Time Frame ...........................................................................144
7.6.6.2 Automatic Timing Scale Selection .............................................................144
7.6.7 Scenario Entry...........................................................................................................144
7.6.8 Macro ........................................................................................................................146
7.7 GPIF II Constraints .........................................
......................................................................146
7.7.1 Mirror States..............................................................................................................146
7.7.2 Mirror State Rules .....................................................................................................147
7.7.3 Mirror State Example ................................................................................................148
7.7.4 Guidelines for Transition Equation Entry...................................................................149
7.7.5 Intermediate States ...................................................................................................150
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Contents
7.8 Initialization and Configuration of GPIF II Block ...................................................................151
7.8.1 GPIF II State Machine Control ..................................................................................151
7.9 Performing Read and Write Operations Using GPIF II .........................................................151
7.10 DMA Channel Creation in FX3 Firmware to Perform GPIF II to USB Data Transfers ..........153
7.11 GPIF II State Machine to Read Data into a Socket ..............................................................153
7.12 DMA Channel Creation in FX3 Firmware to Perform USB to GPIF II Data Transfers ..........154
7.13 GPIF II State Machine to Drive Data from Socket as Data Source ......................................155
7.13.1 Alpha Values .............................................................................................................156
7.14 GPIF II Read and Write over Registers ................................................................................156
7.15 Implementing Synchronous Slave FIFO Interface ................................................................158
7.16 Synchronous Slave FIFO Access Sequence and Interface Timing......................................161
7.16.1 Synchronous Slave FIFO Read Sequence Description ............................................162
7.16.2 Synchronous Slave FIFO Write Sequence Description ............................................164
7.16.3 Slave FIFO Interface Logical Diagram ......................................................................165
7.16.4 GPIF II State Machine of Slave FIFO Interface.........................................................165
8. Low Performance Peripherals (LPP) 167
8.1 I2C Interface .........................................................................................................................168
8.1.1 I2C Block Features....................................................................................................168
8.1.2 I2C Interface Overview..............................................................................................169
8.2 FX3 I2C Operations Overview ..............................................................................................170
8.2.1 Reset and Initialization ..............................................................................................170
8.2.2 Preamble...................................................................................................................170
8.2.3 Data Transfer ............................................................................................................170
8.2.3.1 Programming Model ..................................................................................170
8.2.3.2 Register-Based I2C Transfers ...................................................................171
8.2.3.3 DMA-Based I2C Transfers ........................................................................171
8.2.3.4 Starting a Transaction ...............................................................................171
8.2.3.5 Terminating Transactions: Software and Hardware Aborts .......................172
8.2.3.6 Multimaster Arbitration...............................................................................172
8.2.3.7 Error Conditions.........................................................................................172
8.2.4 Examples ..................................................................................................................172
8.2.4.1 Initialize I2C Block .....................................................................................172
8.2.4.2 Configure I2C Block...................................................................................173
8.2.4.3 Reads and Writes Using Register Transfers .............................................173
8.2.4.4 Reads and Writes Using DMA Transfers...................................................174
8.3 Serial Peripheral Interface ....................................................................................................175
8.3.1 SPI Block Features ...................................................................................................175
8.3.2 SPI Interface Overview .............................................................................................176
8.3.3 FX3 SPI Operations Overview ..................................................................................177
8.3.3.1 Reset and Initialization ..............................................................................177
8.3.3.2 Modes Governing Transfers ......................................................................177
8.3.4 SSN Control Configurations ......................................................................................177
8.3.5 Data Transfers...........................................................................................................178
8.4 Programming Model .............................................................................................................178
8.4.1 Register-Based Transfers .........................................................................................178
8.4.2 DMA-Based Transfers...............................................................................................178
8.5 Examples ..............................................................................................................................179
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8.5.1 Initialize SPI Block.....................................................................................................179
8.5.2 Configure SPI Block ..................................................................................................179
8.5.3 Reads and Writes Using Register Transfers.............................................................180
8.5.4 Reads and Writes Using DMA Transfers...................................................................181
8.6 Universal Asynchronous Receiver Transmitter.....................................................................183
8.6.1 UART block features .................................................................................................183
8.6.2 UART Overview ........................................................................................................183
8.7 FX3 UART Operations Overview ..........................................................................................184
8.7.1 Reset and Initialization ..............................................................................................184
8.7.2 Programming Model..................................................................................................184
8.7.3 Register-Based Transfers .........................................................................................184
8.7.3.1 DMA-Based Transfers ...............................................................................184
8.7.3.2 Error Conditions.........................................................................................185
8.7.4 Examples ..................................................................................................................185
8.7.4.1 Initialize UART Block .................................................................................185
8.7.4.2 Send UART Messages and Receive Fixed Bytes of Text .........................185
8.8 Integrated Interchip Sound Interface ....................................................................................187
8.8.1 I2S Block Features....................................................................................................187
8.8.2 I2S Overview.............................................................................................................187
8.8.3 FX3 I2S Operations Overview...................................................................................188
8.8.4 Programming Model..................................................................................................188
8.8.4.1 Start Transmission.....................................................................................188
8.8.4.2 Mute Condition ..........................................................................................188
8.8.4.3 Pause Condition ........................................................................................188
8.8.4.4 Buffer Underflow........................................................................................189
8.8.4.5 Stop Event .................................................................................................189
8.8.4.6 Fixed Clock Mode......................................................................................189
8.8.4.7 Data Shift Mode.........................................................................................189
8.8.4.8 Padding .....................................................................................................189
8.8.4.9 Error Conditions.........................................................................................189
8.8.4.10 Examples...................................................................................................189
8.8.4.11 Initialize I2S Block .....................................................................................190
8.8.4.12 Configure I2S Interface..............................................................................190
8.8.4.13 Transfer Data from USB to I2S Interface Using DMA Transfers ...............190
8.9 GPIO.....................................................................................................................................192
8.9.1 GPIO Features ..........................................................................................................192
8.9.2 GPIO Overview .........................................................................................................192
8.9.3 Programming Model..................................................................................................192
8.9.3.1 Reset and Initialization ..............................................................................192
8.9.4 Examples ..................................................................................................................193
8.9.4.1 Initialize GPIO Block..................................................................................193
8.9.4.2 Configure GPIO[45] as Input Pin and GPIO[21] as Output Pin .................194
8.9.4.3 Configure GPIO[50] to Generate PWM Output .........................................196
9. Storage Ports 197
9.1 Storage Interface Block Features .........................................................................................197
9.2 Block Diagram ......................................................................................................................197
9.3 Storage Interface (S-Port).....................................................................................................199
9.4 SD/ MMC/ SDIO Interface ....................................................................................................201
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Contents
9.4.1 SD/MMC Interface Overview.....................................................................................201
9.4.2 SDIO Interface Overview ..........................................................................................203
9.5 FX3S S-Port Operations Overview .......................................................................................203
9.5.1 S-port Initialization and Configuration .......................................................................204
9.5.1.1 Configuring the FX3S I/O Matrix................................................................204
9.5.1.2 Setting S-Port Interface Parameters..........................................................204
9.5.1.3 Starting the Storage Driver ........................................................................205
9.5.1.4 Setting the S-Port Clock ............................................................................206
9.5.1.5 Sending SD/MMC/SDIO Commands.........................................................206
9.5.1.6 Handling SIB Events..................................................................................208
9.5.2 Reads and Writes to SD/ MMC Using DMA Transfers ..............................................210
9.5.2.1 Sending Vendor Commands to SD/ MMC.................................................212
9.5.2.2 Setting the Granularity of Write Operations...............................................212
9.5.2.3 Checking Card Status................................................................................212
9.5.2.4 Aborting Ongoing Transaction to S-Port....................................................212
9.5.3 Working with SDIO Cards .........................................................................................213
9.5.3.1 Configuration and Initialization ..................................................................213
9.5.3.2 Reads and Writes from SDIO Card Registers ...........................................213
9.5.3.3 IO_RW_DIRECT Command (CMD52) ......................................................213
9.5.3.4 Setting Function Block Size.......................................................................218
9.5.3.5 Initialization and Operation of SDIO Functions..........................................218
9.5.3.6 SDIO Interrupts..........................................................................................218
9.5.3.7 Enabling and Disabling SDIO Interrupts....................................................219
9.5.3.8 Handling SDIO Interrupts ..........................................................................219
9.6 FX3S-Specific Features........................................................................................................220
9.6.1 Card Insertion and Removal Detection Mechanism..................................................220
9.6.2 Handling Card Detection in Software ........................................................................221
9.6.3 Write Protection.........................................................................................................222
9.6.4 SD/MMC CLOCK STOP ...........................................................................................222
9.6.5 SD_CLK Output Clock Stop ......................................................................................222
9.6.6 SDIO Read-Wait/ Suspend-Resume Feature ...........................................................222
9.6.6.1 Read-Wait..................................................................................................222
9.6.6.2 Suspend-Resume Feature ........................................................................223
9.6.6.3 SD3.0 Host Tuning Feature.......................................................................223
9.6.6.4 Normal and Alternate eMMC4.4 Boot........................................................224
10. Registers 228
10.1 Introduction ...........................................................................................................................228
10.2 Register Conventions ...........................................................................................................229
10.3 Vectored Interrupt Controller (VIC) Registers .......................................................................230
10.3.1 VIC_IRQ_STATUS ...............................................................................................230
10.3.2 VIC_FIQ_STATUS ...............................................................................................231
10.3.3 VIC_RAW_STATUS .............................................................................................232
10.3.4 VIC_INT_SELECT ...............................................................................................233
10.3.5 VIC_INT_ENABLE ...............................................................................................234
10.3.6 VIC_INT_CLEAR .................................................................................................235
10.3.7 VIC_PRIORITY_MASK ........................................................................................236
10.3.8 VIC_VEC_ADDRESS ..........................................................................................237
10.3.9 VIC_VECT_PRIORITY .........................................................................................238
10.3.10 VIC_ADDRESS ....................................................................................................239
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Contents
10.4 Global Controller Registers...................................................................................................240
10.4.1 GCTL_IOMATRIX ................................................................................................240
10.4.2 GCTL_GPIO_SIMPLE .........................................................................................241
10.4.3 GCTL_GPIO_COMPLEX .....................................................................................243
10.4.4 GCTL_DS .............................................................................................................245
10.4.5 GCTL_WPU_CFG ................................................................................................247
10.4.6 GCTL_WPD_CFG ................................................................................................249
10.4.7 GCTL_IOPOWER ................................................................................................251
10.4.8 GCTL_IOPOWER_INTR ......................................................................................253
10.4.9 GCTL_IOPOWER_INTR_MASK ..........................................................................255
10.4.10 GCTL_SW_INT ....................................................................................................257
10.4.11 GCTL_PLL_CFG ..................................................................................................258
10.4.12 GCTL_CPU_CLK_CFG .......................................................................................260
10.4.13 GCTL_UIB_CORE_CLK ......................................................................................261
10.4.14 GCTL_PIB_CORE_CLK ......................................................................................262
10.4.15 GCTL_GPIO_FAST_CLK ....................................................................................263
10.4.16 GCTL_GPIO_SLOW_CLK ...................................................................................265
10.4.17 GCTL_I2C_CORE_CLK .......................................................................................266
10.4.18 GCTL_UART_CORE_CLK ..................................................................................267
10.4.19 GCTL_SPI_CORE_CLK ......................................................................................268
10.4.20 GCTL_I2S_CORE_CLK .......................................................................................269
10.5 Global Controller Always On Registers ................................................................................270
10.5.1 GCTL_WAKEUP_EN ...........................................................................................270
10.5.2 GCTL_WAKEUP_POLARITY ..............................................................................272
10.5.3 GCTL_WAKEUP_EVENT ....................................................................................274
10.5.4 GCTL_FREEZE ...................................................................................................276
10.5.5 GCTL_WATCHDOG_CS .....................................................................................277
10.5.6 GCTL_WATCHDOG_TIMER0 .............................................................................279
10.5.7 GCTL_WATCHDOG_TIMER1 .............................................................................280
10.6 PIB Registers........................................................................................................................281
10.6.1 PIB_CONFIG .......................................................................................................281
10.6.2 PIB_INTR .............................................................................................................283
10.6.3 PIB_INTR_MASK .................................................................................................285
10.6.4 PIB_CLOCK_DETECT .........................................................................................287
10.6.5 PIB_RD_MAILBOX ..............................................................................................288
10.6.6 PIB_WR_MAILBOX .............................................................................................290
10.6.7 PIB_ERROR ........................................................................................................292
10.6.8 PIB_EOP_EOT ....................................................................................................294
10.6.9 PIB_DLL_CTRL ...................................................................................................295
10.6.10 PIB_WR_THRESHOLD .......................................................................................297
10.6.11 PIB_RD_THRESHOLD ........................................................................................298
10.6.12 PIB_ID ..................................................................................................................299
10.6.13 PIB_POWER ........................................................................................................300
10.7 GPIF Registers .....................................................................................................................301
10.7.1 GPIF_CONFIG .....................................................................................................301
10.7.2 GPIF_BUS_CONFIG ...........................................................................................303
10.7.3 GPIF_BUS_CONFIG2 .........................................................................................305
10.7.4 GPIF_AD_CONFIG ..............................................................................................306
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Contents
10.7.5 GPIF_STATUS .....................................................................................................308
10.7.6 GPIF_INTR ..........................................................................................................310
10.7.7 GPIF_INTR_MASK ..............................................................................................312
10.7.8 GPIF_CTRL_BUS_DIRECTION ..........................................................................314
10.7.9 GPIF_CTRL_BUS_DEFAULT ..............................................................................315
10.7.10 GPIF_CTRL_BUS_POLARITY ............................................................................316
10.7.11 GPIF_CTRL_BUS_TOGGLE ...............................................................................317
10.7.12 GPIF_CTRL_BUS_SELECT ................................................................................318
10.7.13 GPIF_CTRL_COUNT_CONFIG ...........................................................................319
10.7.14 GPIF_CTRL_COUNT_RESET .............................................................................320
10.7.15 GPIF_CTRL_COUNT_LIMIT ...............................................................................321
10.7.16 GPIF_ADDR_COUNT_CONFIG ..........................................................................322
10.7.17 GPIF_ADDR_COUNT_RESET ............................................................................323
10.7.18 GPIF_ADDR_COUNT_LIMIT ...............................................................................324
10.7.19 GPIF_STATE_COUNT_CONFIG ........................................................................325
10.7.20 GPIF_STATE_COUNT_LIMIT .............................................................................326
10.7.21 GPIF_DATA_COUNT_CONFIG ..........................................................................327
10.7.22 GPIF_DATA_COUNT_RESET ............................................................................328
10.7.23 GPIF_DATA_COUNT_LIMIT ...............................................................................329
10.7.24 GPIF_CTRL_COMP_VALUE ...............................................................................330
10.7.25 GPIF_CTRL_COMP_MASK ................................................................................331
10.7.26 GPIF_DATA_COMP_VALUE ...............................................................................332
10.7.27 GPIF_DATA_COMP_MASK ................................................................................333
10.7.28 GPIF_ADDR_COMP_VALUE ..............................................................................334
10.7.29 GPIF_ADDR_COMP_MASK ................................................................................335
10.7.30 GPIF_DATA_CTRL ..............................................................................................336
10.7.31 GPIF_INGRESS_DATA .......................................................................................337
10.7.32 GPIF_EGRESS_DATA ........................................................................................338
10.7.33 GPIF_INGRESS_ADDRESS ...............................................................................339
10.7.34 GPIF_EGRESS_ADDRESS ................................................................................340
10.7.35 GPIF_THREAD_CONFIG ....................................................................................341
10.7.36 GPIF_LAMBDA_STAT .........................................................................................343
10.7.37 GPIF_ALPHA_STAT ............................................................................................344
10.7.38 GPIF_BETA_STAT ..............................................................................................345
10.7.39 GPIF_WAVEFORM_CTRL_STAT ................................
.......................................346
10.7.40 GPIF_WAVEFORM_SWITCH .............................................................................348
10.7.41 GPIF_WAVEFORM_SWITCH_TIMEOUT ...........................................................350
10.7.42 GPIF_BETA_DEASSERT ....................................................................................351
10.7.43 GPIF_FUNCTION ................................................................................................352
10.7.44 GPIF_LEFT_WAVEFORM ...................................................................................353
10.7.45 GPIF_RIGHT_WAVEFORM ................................................................................356
10.8 P-Port Registers ...................................................................................................................359
10.8.1 PP_ID ...................................................................................................................359
10.8.2 PP_INIT ................................................................................................................360
10.8.3 PP_CONFIG ........................................................................................................361
10.8.4 PP_INTR_MASK ..................................................................................................363
10.8.5 PP_DRQR5_MASK ..............................................................................................364
10.8.6 PP_SOCK_MASK ................................................................................................365
10.8.7 PP_ERROR .........................................................................................................366
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Contents
10.8.8 PP_DMA_XFER ...................................................................................................367
10.8.9 PP_DMA_SIZE ....................................................................................................368
10.8.10 PP_WR_MAILBOX ..............................................................................................369
10.8.11 PP_MMIO_ADDR ................................................................................................371
10.8.12 PP_MMIO_DATA .................................................................................................372
10.8.13 PP_MMIO .............................................................................................................373
10.8.14 PP_EVENT ..........................................................................................................374
10.8.15 PP_RD_MAILBOX ...............................................................................................376
10.8.16 PP_SOCK_STAT .................................................................................................378
10.8.17 PP_BUF_SIZE_CNT ............................................................................................379
10.9 USB Port Registers...............................................................................................................380
10.9.1 UIB_INTR .............................................................................................................380
10.9.2 UIB_INTR_MASK .................................................................................................382
10.9.3 UIB_ID ..................................................................................................................384
10.9.4 UIB_POWER ........................................................................................................385
10.10 USB2 HS/FS/LS PHY Registers ...........................................................................................386
10.10.1 PHY_CLK_AND_TEST ........................................................................................386
10.10.2 PHY_CONF ..........................................................................................................388
10.10.3 PHY_CHIRP .........................................................................................................390
10.11 USB2 Device Controller Registers........................................................................................391
10.11.1 DEV_CS ...............................................................................................................391
10.11.2 DEV_FRAMECNT ................................................................................................393
10.11.3 DEV_PWR_CS ....................................................................................................394
10.11.4 DEV_SETUPDAT .................................................................................................395
10.11.5 DEV_TOGGLE .....................................................................................................397
10.11.6 DEV_EPI_CS .......................................................................................................399
10.11.7 DEV_EPI_XFER_CNT .........................................................................................401
10.11.8 DEV_EPO_CS .....................................................................................................402
10.11.9 DEV_EPO_XFER_CNT .......................................................................................404
10.11.10 DEV_CTRL_INTR_MASK ....................................................................................405
10.11.11 DEV_CTRL_INTR ................................................................................................406
10.11.12 DEV_EP_INTR_MASK ........................................................................................407
10.11.13 DEV_EP_INTR .....................................................................................................408
10.12 USB Controller Miscellaneous Registers ..............................................................................409
10.12.1 CHGDET_CTRL ...................................................................................................409
10.12.2 CHGDET_INTR ....................................................................................................411
10.12.3 CHGDET_INTR_MASK .......................................................................................412
10.12.4 OTG_CTRL ...............................................
...........................................................413
10.12.5 OTG_INTR ...........................................................................................................415
10.12.6 OTG_INTR_MASK ...............................................................................................416
10.12.7 OTG_TIMER ........................................................................................................417
10.13 USB End Point Manager Registers ......................................................................................418
10.13.1 EEPM_CS ............................................................................................................418
10.13.2 IEPM_CS .............................................................................................................420
10.13.3 IEPM_MULT .........................................................................................................421
10.13.4 EEPM_ENDPOINT ..............................................................................................422
10.13.5 IEPM_ENDPOINT ................................................................................................423
10.13.6 IEPM_FIFO ..........................................................................................................424
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Contents
10.14 USB2 Host Controller Registers ...........................................................................................425
10.14.1 HOST_CS ............................................................................................................425
10.14.2 HOST_EP_INTR ..................................................................................................426
10.14.3 HOST_EP_INTR_MASK ......................................................................................427
10.14.4 HOST_TOGGLE ..................................................................................................428
10.14.5 HOST_SHDL_CS .................................................................................................430
10.14.6 HOST_SHDL_SLEEP ..........................................................................................432
10.14.7 HOST_RESP_BASE ............................................................................................433
10.14.8 HOST_RESP_CS ................................................................................................434
10.14.9 HOST_ACTIVE_EP .............................................................................................435
10.14.10 OHCI_REVISION .................................................................................................436
10.14.11 OHCI_CONTROL .................................................................................................437
10.14.12 OHCI_COMMAND_STATUS ...............................................................................438
10.14.13 OHCI_INTERRUPT_STATUS .............................................................................439
10.14.14 OHCI_INTERRUPT_ENABLE .............................................................................440
10.14.15 OHCI_INTERRUPT_DISABLE ............................................................................441
10.14.16 OHCI_FM_INTERVAL .........................................................................................442
10.14.17 OHCI_FM_REMAINING .......................................................................................443
10.14.18 OHCI_FM_NUMBER ...........................................................................................444
10.14.19 OHCI_PERIODIC_START ...................................................................................445
10.14.20 OHCI_LS_THRESHOLD ......................................................................................446
10.14.21 OHCI_RH_PORT_STATUS .................................................................................447
10.14.22 OHCI_EOF ...........................................................................................................449
10.14.23 EHCI_HCCPARAMS ............................................................................................450
10.14.24 EHCI_USBCMD ...................................................................................................451
10.14.25 EHCI_USBSTS ....................................................................................................452
10.14.26 EHCI_USBINTR ...................................................................................................453
10.14.27 EHCI_FRINDEX ...................................................................................................454
10.14.28 EHCI_CONFIGFLAG ...........................................................................................455
10.14.29 EHCI_PORTSC ....................................................................................................456
10.14.30 EHCI_EOF ...........................................................................................................458
10.14.31 SHDL_CHNG_TYPE ............................................................................................459
10.14.32 SHDL_STATE_MACHINE ...................................................................................460
10.14.33 SHDL_INTERNAL_STATUS ................................................................................462
10.14.34 SHDL_OHCI .........................................................................................................464
10.14.35 SHDL_EHCI .........................................................................................................468
10.15 USB3 Link Controller Registers ............................................................................................472
10.15.1 LNK_CONF ..........................................................................................................472
10.15.2 LNK_INTR ...............................................
.............................................................473
10.15.3 LNK_INTR_MASK ................................................................................................475
10.15.4 LNK_ERROR_CONF ...........................................................................................477
10.15.5 LNK_ERROR_STATUS .......................................................................................479
10.15.6 LNK_ERROR_COUNT ........................................................................................481
10.15.7 LNK_ERROR_COUNT_THRESHOLD ................................................................482
10.15.8 LNK_PHY_CONF .................................................................................................483
10.15.9 LNK_PHY_MPLL_STATUS .................................................................................484
10.15.10 LNK_PHY_TX_TRIM ...........................................................................................485
10.15.11 LNK_PHY_ERROR_CONF ..................................................................................486
10.15.12 LNK_PHY_ERROR_STATUS ..............................................................................487
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Contents
10.15.13 LNK_DEVICE_POWER_CONTROL ....................................................................489
10.15.14 LNK_LTSSM_STATE ...........................................................................................491
10.15.15 LNK_LFPS_OBSERVE ........................................................................................492
10.15.16 LNK_COMPLIANCE_PATTERN_0 ......................................................................493
10.15.17 LNK_COMPLIANCE_PATTERN_1 ......................................................................494
10.15.18 LNK_COMPLIANCE_PATTERN_2 ......................................................................495
10.15.19 LNK_COMPLIANCE_PATTERN_3 ......................................................................496
10.15.20 LNK_COMPLIANCE_PATTERN_4 ......................................................................497
10.15.21 LNK_COMPLIANCE_PATTERN_5 ......................................................................498
10.15.22 LNK_COMPLIANCE_PATTERN_6 ......................................................................499
10.15.23 LNK_COMPLIANCE_PATTERN_7 ......................................................................500
10.15.24 LNK_COMPLIANCE_PATTERN_8 ......................................................................501
10.16 USB3 Protocol Layer Registers ............................................................................................502
10.16.1 PROT_CS ............................................................................................................502
10.16.2 PROT_INTR .........................................................................................................504
10.16.3 PROT_INTR_MASK .............................................................................................506
10.16.4 PROT_FRAMECNT .............................................................................................508
10.16.5 PROT_ITP_TIME .................................................................................................509
10.16.6 PROT_ITP_TIMESTAMP .....................................................................................510
10.16.7 PROT_SETUP_DAT ............................................................................................511
10.16.8 PROT_SEQ_NUM ...............................................................................................513
10.16.9 PROT_EP_INTR ..................................................................................................515
10.16.10 PROT_EP_INTR_MASK ......................................................................................516
10.16.11 PROT_EPI_CS1 ..................................................................................................517
10.16.12 PROT_EPI_CS2 ..................................................................................................519
10.16.13 PROT_EPI_UNMAPPED_STREAM ....................................................................520
10.16.14 PROT_EPI_MAPPED_STREAM .........................................................................521
10.16.15 PROT_EPO_CS1 .................................................................................................522
10.16.16 PROT_EPO_CS2 .................................................................................................524
10.16.17 PROT_EPO_UNMAPPED_STREAM ..................................................................525
10.16.18 PROT_EPO_MAPPED_STREAM .......................................................................526
10.17 USB Port - SuperSpeed Ingress Socket Registers...............................................................527
10.17.1 UIBIN_ID ..............................................................................................................527
10.17.2 UIBIN_POWER ....................................................................................................528
10.18 I2S Registers ........................................................................................................................529
10.18.1 I2S_CONFIG ........................................................................................................529
10.18.2 I2S_STATUS ........................................................................................................531
10.18.3 I2S_INTR .............................................................................................................533
10.18.4 I2S_INTR_MASK .................................................................................................534
10.18.5 I2S_EGRESS_DATA_LEFT ...................................
.............................................535
10.18.6 I2S_EGRESS_DATA_RIGHT ..............................................................................536
10.18.7 I2S_COUNTER ....................................................................................................537
10.18.8 I2S_SOCKET .......................................................................................................538
10.18.9 I2S_ID ..................................................................................................................539
10.18.10 I2S_POWER ........................................................................................................540
10.19 I2C Registers ........................................................................................................................541
10.19.1 I2C_CONFIG ........................................................................................................541
10.19.2 I2C_STATUS .......................................................................................................543
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Contents
10.19.3 I2C_INTR .............................................................................................................545
10.19.4 I2C_INTR_MASK .................................................................................................546
10.19.5 I2C_TIMEOUT .....................................................................................................547
10.19.6 I2C_DMA_TIMEOUT ...........................................................................................548
10.19.7 I2C_PREAMBLE_CTRL .......................................................................................549
10.19.8 I2C_PREAMBLE_DATA ......................................................................................550
10.19.9 I2C_PREAMBLE_RPT .........................................................................................552
10.19.10 I2C_COMMAND ...................................................................................................553
10.19.11 I2C_EGRESS_DATA ...........................................................................................555
10.19.12 I2C_INGRESS_DATA ..........................................................................................556
10.19.13 I2C_CLOCK_LOW_COUNT ................................................................................557
10.19.14 I2C_BYTE_COUNT .............................................................................................558
10.19.15 I2C_BYTES_TRANSFERRED .............................................................................559
10.19.16 I2C_SOCKET .......................................................................................................560
10.19.17 I2C_ID ..................................................................................................................561
10.19.18 I2C_POWER ........................................................................................................562
10.20 UART Registers ....................................................................................................................563
10.20.1 UART_CONFIG ...................................................................................................563
10.20.2 UART_STATUS ...................................................................................................565
10.20.3 UART_INTR .........................................................................................................567
10.20.4 UART_INTR_MASK .............................................................................................568
10.20.5 UART_EGRESS_DATA .......................................................................................569
10.20.6 UART_INGRESS_DATA ......................................................................................570
10.20.7 UART_SOCKET ...................................................................................................571
10.20.8 UART_RX_BYTE_COUNT ..................................................................................572
10.20.9 UART_TX_BYTE_COUNT ...................................................................................573
10.20.10 UART_ID ..............................................................................................................574
10.20.11 UART_POWER ....................................................................................................575
10.21 SPI Registers ........................................................................................................................576
10.21.1 SPI_CONFIG .......................................................................................................576
10.21.2 SPI_STATUS .......................................................................................................578
10.21.3 SPI_INTR .............................................................................................................580
10.21.4 SPI_INTR_MASK .................................................................................................581
10.21.5 SPI_EGRESS_DATA ...........................................................................................582
10.21.6 SPI_INGRESS_DATA ..........................................................................................583
10.21.7 SPI_SOCKET .............................................
..........................................................584
10.21.8 SPI_RX_BYTE_COUNT ......................................................................................585
10.21.9 SPI_TX_BYTE_COUNT .......................................................................................586
10.21.10 SPI_ID ..................................................................................................................587
10.21.11 SPI_POWER ........................................................................................................588
10.22 General Purpose IO Block Registers ....................................................................................589
10.22.1 GPIO_SIMPLE .....................................................................................................589
10.22.2 GPIO_INVALUE0 .................................................................................................591
10.22.3 GPIO_INVALUE1 .................................................................................................592
10.22.4 GPIO_INTR0 ........................................................................................................593
10.22.5 GPIO_INTR1 ........................................................................................................594
10.22.6 GPIO_INTR ..........................................................................................................595
10.22.7 GPIO_ID ...............................................................................................................596
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Contents
10.22.8 GPIO_POWER .....................................................................................................597
10.23 General Purpose IO Registers (one pin) ..............................................................................598
10.23.1 PIN_STATUS .......................................................................................................598
10.23.2 PIN_TIMER ..........................................................................................................600
10.23.3 PIN_PERIOD .......................................................................................................601
10.23.4 PIN_THRESHOLD ...............................................................................................602
10.24 Low Performance Peripherals Registers ..............................................................................603
10.24.1 LPP_ID .................................................................................................................603
10.24.2 LPP_POWER .......................................................................................................604
10.25 DMA Socket and Descriptor Registers .................................................................................605
10.25.1 SCK_DSCR ..........................................................................................................605
10.25.2 SCK_SIZE ............................................................................................................607
10.25.3 SCK_COUNT .......................................................................................................608
10.25.4 SCK_STATUS ......................................................................................................609
10.25.5 SCK_INTR ...........................................................................................................612
10.25.6 SCK_INTR_MASK ...............................................................................................614
10.25.7 DSCR_BUFFER ...................................................................................................616
10.25.8 DSCR_SYNC .......................................................................................................617
10.25.9 DSCR_CHAIN ......................................................................................................619
10.25.10 DSCR_SIZE .........................................................................................................620
10.25.11 EVENT .................................................................................................................622
10.26 DMA Adapter Global Registers.............................................................................................623
10.26.1 SCK_INTR ...........................................................................................................623
10.26.2 ADAPTER_STATUS ............................................................................................629
10.26.3 SIB_ID ..................................................................................................................630
10.26.4 SIB_POWER ........................................................................................................631
10.26.5 SDMMC_CMD_IDX .............................................................................................632
10.26.6 SDMMC_CMD_ARG0 ..........................................................................................633
10.26.7 SDMMC_CMD_ARG1 ..........................................................................................634
10.26.8 SDMMC_RESP_IDX ............................................................................................635
10.26.9 SDMMC_RESP_REG0 ........................................................................................636
10.26.10 SDMMC_RESP_REG1 ........................................................................................637
10.26.11 SDMMC_RESP_REG2 ........................................................................................638
10.26.12 SDMMC_RESP_REG3 ........................................................................................639
10.26.13 SDMMC_RESP_REG4 ........................................................................................640
10.26.14 SDMMC_CMD_RESP_FMT ................................................................................641
10.26.15 SDMMC_BLOCK_COUNT ...................................................................................642
10.26.16 SDMMC_BLOCK_LEN ........................................................................................643
10.26.17 SDMMC_MODE_CFG .........................................................................................644
10.26.18 SDMMC_DATA_CFG ..........................................................................................646
10.26.19 SDMMC_CS .........................................................................................................647
10.26.20 SDMMC_STATUS ...............................................................................................649
10.26.21 SDMMC_INTR .....................................................................................................651
10.26.22 SDMMC_INTR_MASK .........................................................................................653
10.26.23 SDMMC_NCR ......................................................................................................655
10.26.24 SDMMC_NCC_NWR ...........................................................................................656
10.26.25 SDMMC_NAC ......................................................................................................657
10.26.26 SDMMC_HW_CTRL ............................................................................................658
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Contents
10.26.27 SDMMC_DLL_CTRL ............................................................................................659
Revision History 660
EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 18
1. Introduction to EZ-USB FX3
EZ-USB® FX3™ is Cypress's high-bandwidth USB 3.0 peripheral controller that provides integrated and flexible features.
FX3 integrates the USB 3.0 and USB 2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S microprocessor for
powerful data processing and for building custom USB SuperSpeed applications.
To provide high-bandwidth access to USB 3.0 data, FX3 contains a hardware unit called General Programmable Interface,
Generation 2 (GPIF II). GPIF II is an enhanced version of the GPIF in FX2LP™, Cypress's USB 2.0 product. GPIF II provides
easy and glueless connectivity to popular interfaces such as asynchronous SRAM and asynchronous and synchronous
address and data multiplexed interfaces. FX3 implements a DMA-centric architecture that enables direct 375-MBps data
transfer from GPIF II to the USB interface without CPU intervention.
An integrated USB 2.0 USB On-The-Go (OTG) controller enables applications in which FX3 may serve dual high-speed roles;
for example, EZ-USB FX3 may function as a High-Speed On-The-Go (HS-OTG) host to USB Mass Storage Class (MSC)
devices and HID-class devices. FX3 contains 512 KB or 256 KB of on-chip SRAM for code and data. EZ-USB FX3 also
provides interfaces to connect to serial peripherals such as UART, SPI, I2C, and I2S. FX3 comes with application
development tools. The software development kit (SDK) provides application examples for accelerating the time to market.
FX3 complies with the USB 3.0 v1.0 specification and is also backward compatible with USB 2.0. It also complies with the
USB 2.0 OTG Specification v2.0.
In addition to these features, FX3S has an integrated storage controller and can support up to two independent mass storage
devices. It can support SD 3.0 and eMMC 4.41 memory cards. It can also support SDIO on these ports.
This TRM describes the following functional blocks of the FX3/FX3S device: CPU subsystem, memory, global control, DMA,
USB, GPIF II, low-bandwidth (serial and GPIO) peripherals, and storage (storage block is specific to FX3S only). Registers
associated with these functional blocks are documented in the Registers chapter on page 228.
The following sections describe the details of USB 3.0 and briefly outline the EZ-USB FX3/FX3S architecture.
1.1 Overview of USB 3.0
This section gives an overview of USB 3.0 and describes the significant changes in each layer from the USB 2.0 specification,
including the new power management features provided in USB 3.0. Refer to AN57294 - USB 101: An Introduction to
Universal Serial Bus 2.0 for more details on USB 2.0. The USB 2.0 and 3.0 specifications can be downloaded from
www.usb.org/developers/docs.
The USB 3.0 specification, released in 2008, allows a maximum signaling rate of 5 Gbps (SuperSpeed), which is 10 times the
signaling rate of High Speed. The USB 3.0 architecture contains three layers: the physical layer, the link layer on top of the
physical layer, and the protocol layer on top of the link layer.
The additional bandwidth provided by USB SuperSpeed transactions can benefit applications such as real-time audio and
video streaming that require a higher bus bandwidth at regular intervals. Mass storage applications can also benefit from the
SuperSpeed bandwidth. FX3 has also been used to implement a high-performance PC-based logic analyzer.
1.1.1 Physical Layer
The physical layer refers to the PHY part of the port and the cable connecting the upstream and downstream ports. USB 3.0
cables have separate shielded differential pairs of lines for transmitting and receiving data. These lines exist along with the
USB 2.0 signals. So a USB 3.0 cable contains a total of nine wires including the four wires that are part of the USB 2.0 cable
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Introduction to EZ-USB FX3
(see Figure 1-1). The SuperSpeed bus employs a dual-simplex approach that allows simultaneous transmission and
reception of packets. In many cases, a SuperSpeed device may be both transmitting and receiving data at the same time. For
example, during burst transactions, a device may be receiving data from the host and returning acknowledgments associated
with the data it already received.
Figure 1-1. Cross-Section of a USB 3.0 Cable
Coming to the power distribution via the USB 3.0 host, 150 mA is considered as the unit load. USB 3.0 host supplies one unit
load of current for unconfigured devices and six unit loads of current for configured devices. The USB 3.0 host detects the
device connection based on the receiver end termination, and the transmitter is responsible for detecting the device
connection. USB 3.0 uses spread-spectrum clocking on its signaling. If spread-spectrum clocking is enabled, then the energy
of the signal is spread over a larger frequency band rather concentrated over a small frequency band at a high level, helping
to reduce the EMI emissions. The USB 3.0 physical layer supports low-frequency periodic signaling (LFPS), which is used to
manage signal initiation and low-power management on the bus on an idle link to consume less power. Ta bl e 1 -1 lists the
differences between the USB 3.0 and USB 2.0 physical layers.
Table 1-1. Differences Between Physical Layers of USB 3.0 and USB 2.0
Feature USB 3.0 USB 2.0
Signaling rate 5 Gbps 480 Mbps
Data transfers Dual simplex Half duplex
Number of pins in the USB cable
Data lines in the cable Shielded differential pair (SDP, twisted, or twinax) Unshielded twisted pair (UTP)
Current supplied by the host
Device detection by the host Receiver end termination Pull-up resistor on D+ or D- lines
9 (VBUS, Ground, D+, D-, SSRX+, SSRX-, SSTX+, SSTX-,
Ground_Drain)
150 mA for unconfigured devices, 900 mA for configured
devices
4 (VBUS, Ground, D+, D-)
100 mA for unconfigured devices, 500 mA for configured devices
1.1.2 Link Layer
The link layer is responsible for maintaining a reliable and robust communication channel between the host and the device.
The Link Training and Status State Machine (LTSSM) at the core of the USB 3.0 link layer establishes the link connectivity
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Introduction to EZ-USB FX3
and link power management states and transitions. LTSSM consists of 12 states, including four operational link states (U0,
U1, U2, U3). The link layer offers these four link power states for better power management:
■ U0-Fully powered; link partners are fully powered and ready to send packets
■ U1-Standby with fast recovery; link is in a low-power state and is not ready to send packets but can transition back to U0
within microseconds
■ U2-Standby with slow recovery; link power saving is greater than U1 and transitioning back to U0 within microseconds to
milliseconds
■ U3-Suspend; greatest power savings and longest recovery back to U0 (milliseconds)
■ U1, U2, and U3 have increasingly longer wakeup times into U0 and thus allow transmitters to go into increasingly deeper
sleep.
■ Four link initialization and training states (Rx.Detect, Polling, Recovery, Hot Reset)
■ Two link test states (Loopback and Compliance mode)
■ SS.Inactive (link error state where USB 3.0 is nonoperable)
■ SS.Disabled (SuperSpeed bus is disabled and operates as USB 2.0 only)
Link commands are used to maintain the link flow control and to initiate a change in the link power state.
1.1.3 Protocol Layer
The protocol layer manages the communication rules between a host and device. The SuperSpeed protocol layer includes
the following improvements to enable better performance, efficiency, and power conservation. The information in this section
is provided as background material; the FX3 logic manages protocol details so the application program can deal directly with
USB data.
1.1.3.1 Unicast Transactions
SuperSpeed transactions are routed directly from a root port to the target device with the help of a route string in the packet
header. Therefore, only links in the direct path between the root port and target device see the traffic, which lets other links in
the topology enter or remain in a low-power state.
1.1.3.2 Token/ Data/Handshake Sequences
A USB 2.0 transaction consists of three packets: token, data, and handshake. A transaction is initiated with the token packet
and it is always from the host. Data packets deliver the payload data, which can be sourced by the host or device. The
handshake packet acknowledges the error-free receipt of data and is sent by the receiver of the data. But with SuperSpeed,
to save bandwidth, the token is incorporated into the data packet for OUT transactions; it is replaced by the handshake for IN
transactions. So an ACK packet acknowledges the previous data packet sent and requests the next data packet. The
following examples clarify the differences between USB 2.0 and USB 3.0 IN and OUT transactions.
1.1.3.2.1 IN Transaction Exam ple
Figure 1-2 on page 22 illustrates the differences between USB 2.0 and SuperSpeed OUT transactions. The example on the
left in Figure 1-2 on page 22 shows the sequence of packets required to perform two USB 2.0 IN transactions that require six
packets:
1. Host broadcasts an IN token packet (1) to initiate the transaction.
2. Device returns the requested data packet (2).
3. Host acknowledges receipt of data with an ACK handshake packet (3).
4. Steps 1-3 are repeated.
The example on the right indicates the packet sequence necessary to perform two back-to-back SuperSpeed IN transactions,
which require only five packets to be exchanged:
1. SuperSpeed uses an ACK header (1) to initiate an IN transaction.
2. The SuperSpeed device returns the data packet (2).
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Introduction to EZ-USB FX3
Host Controller
High-Speed Device
IN Token
DATA
ACK
IN Token
ACK
DATA
Host Controller
SuperSpeed Device
ACK Header
DATA Header
+ Payload
DATA Header
+ Payload
ACK Header
ACK Header
1
4
6
5
1
3
4
2
3
2
5
3. The second ACK header (3) both acknowledges receipt of the data and requests a second transaction.
4. The second data packet (4) is delivered by the device.
5. The final ACK header (5) acknowledges receipt of the data, but does not request additional data.
Figure 1-2. USB 2.0 IN Transaction Versus USB 3.0 IN Transaction
1.1.3.2.2 OUT Transaction Example
Figure 1-3 illustrates the differences between USB 2.0 and SuperSpeed OUT transactions. The example on the left shows
two back-to-back OUT transactions that require six packets:
1. Host broadcasts an OUT token packet (1) to initiate the transaction.
2. Host sends a data packet (2) to the device.
3. Device acknowledges receipt of data with an ACK handshake packet (3).
4. Steps 1-3 are repeated
The right side of Figure 1-3 shows the packet sequence required to perform two back-to-back SuperSpeed OUT transactions,
requiring only 4 packets to be exchanged:
1. SuperSpeed USB uses a data header (1) to initiate an OUT transaction and to deliver data to the device.
2. Device acknowledges receipt of data via an ACK packet (2).
3. The second data packet (3) initiates the second transaction and delivers data to the device.
4. Device acknowledges receipt of data via an ACK packet (4), completing the sequence.
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Introduction to EZ-USB FX3
Host Controller
High-Speed Device
OUT Token
DATA
ACK
OUT Token
DATA
Host Controller
SuperSpeed Device
ACK Header
DATA Header
+ Payload
1
4
5
6
1
3
2
2
ACK
DATA Header
+ Payload
ACK Header
4
3
Figure 1-3. USB 2.0 OUT Transaction Versus USB 3.0 OUT Transaction
1.1.3.3 Data Bursting
The SuperSpeed end-to-end protocol supports transmitting the data in bursts (multiple data packets) without receiving an
acknowledgement to improve latency and performance. The protocol allows efficient bus utilization by concurrently
transmitting and receiving over the bus. A transmitter (host or device) can burst multiple packets of data back to back, and the
receiver can transmit data acknowledgements without interrupting the burst of data packets. Also, the host may
simultaneously schedule multiple OUT bursts to be active at the same time as an IN burst. Devices report their ability to
support bursting in their device descriptors. The maximum burst size is 16, and the actual number to be used represents the
number of data packets that can be sent without receiving an acknowledgement.
This bursting approach is explained in Figure 1-3 with an IN endpoint that supports a burst size of four. The host initiates the
burst transfer and indicates the expected sequence number of the first data packet returned (Seq=0) and the number of
packets it wishes to receive (NumP=4). The target device responds with a burst sequence of four data packets without
receiving any handshakes. A fifth data packet cannot be returned until data packet zero is acknowledged and the host has
indicated a request for another data packet (that is, a second ACK packet with NumP=4). In this burst example, the host
continues to request additional data by keeping the NumP value at 4.
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Figure 1-4. Data Bursting in SuperSpeed
ACK Packet
Host TX
Seq = 0; NumP = 4
Device TX
DATA Packet
Seq = 0
DATA Packet
Seq = 1
DATA Packet
Seq = 2
DATA Packet
Seq = 3
ACK Packet
Seq = 1; NumP = 4
ACK Packet
Seq = 4; NumP = 4
Introduction to EZ-USB FX3
1.1.3.4 End-to-End Flow Control
USB 2.0 uses polling and the NAK handshake packet for flow control. For example, USB keyboards must be constantly polled
by the host software to check for activity. When an IN token packet is delivered and no keyboard activity has occurred, the
keyboard returns a NAK packet. Subsequently, the host software will poll the device again and receive another NAK. This
process continues until there is renewed activity. SuperSpeed flow control uses a poll-once approach coupled with an
asynchronous ready notification. Consider the IN transaction shown in Figure 1-5. An ACK packet initiates the IN transaction
and if a device responds with "NRDY" (Not Ready), then the host stops talking to that device until the device sends the
"ERDY" (ready) packet saying that now it is ready to transmit the data. So the host does not need to continue polling. This can
significantly reduce SuperSpeed traffic and improve link power management.
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Figure 1-5. End-to-End Flow Control in SuperSpeed
ACK Packet
Host TX
Seq = 0; NumP = 4
Device TX
NRDY Packet
DATA Packet
Seq = 0
ACK Packet
Seq = 1; NumP = 3 (Handshake)
ERDY Packet
ACK Packet
Seq = 0; NumP = 4
Introduction to EZ-USB FX3
1.1.3.5 Streams
USB 3.0 enhanced the bulk transfer capabilities by adding a concept called "streams." This allows a device to accept multiple
commands on a pipe from the host and to complete them out of order using the stream IDs.
Table 1-2 lists the differences between the USB 3.0 and USB 2.0 protocol layers:
Table 1-2. Differences Between USB 3.0 and USB 2.0 Protocol Layers
Bus transaction protocol
Data transfer types
Maximum packet size
Control 512 64
Interrupt 1024 1024
Bulk
Isochronous 1024 1024
1.2 SuperSpeed Power Management
SuperSpeed USB provides a much improved mechanism for entering and exiting low-power states. USB 2.0 implements a
feature known as "Suspend" that forces devices to limit current consumption to 2.5 mA. Entry into the low-power state
requires a minimum of 3 ms, and exit requires more than 20 ms. SuperSpeed power management provides finer granularity
when entering low-power states and reduces entry and exit times. The device can also initiate the low-power link states when
it is idle.
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Feature USB 3.0 USB 2.0
Host directly routes the packet to the targeted device with the help of
route string; exception-isochronous timestamp packet
Asynchronous traffic flow Polled traffic flow
Simultaneous IN/OUTs IN or Out
USB 2.0 types with SuperSpeed constraints; bulk has streams capability
Host broadcasts the packets to all devices-no route
string
Four types: Control, interrupt, bulk, isochronous
1024
Supports streaming functionality Does not support
Introduction to EZ-USB FX3
Power management features are implemented at all layers:
The physical layer supports the remote wakeup signaling.
The link layer supports low-power link state entry and exit with the help of LTSSM and link commands. It offers four link power
states (U0, U1, U2, and U3) for better power management. The following architectural features aid in SuperSpeed link power
management:
■ The much higher transmission rates mean that SuperSpeed transactions complete very quickly, leaving links in the idle
state for a longer period of time.
■ The Unicast approach involves only the links in the direct path between the originating root port and target device, leaving
other links idle.
■ The "poll once and notify" mechanism used in SuperSpeed end-to-end flow control reduces overall link traffic.
Protocol layer supports endpoint busy/ready notifications.
1.2.1 Function Power Management
SuperSpeed power management includes the ability to place a specific function (an interface or a set of interfaces) into a
suspended state. This means that a multifunction device can have some functions suspended while others remain fully
operational. Functions are placed into suspend under software control. The asynchronous Function Wake notification tells
software that a suspended function or device is requesting a remote wakeup.
1.3 FX3/FX3S Features
EZ-USB FX3/FX3S supports the following features.
■ Universal Serial Bus (USB) integration
❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification revision 1.0
❐ 5-Gbps USB 3.0 PHY
❐ HS-OTG host and peripheral compliant with OTG Supplement version 2.0
❐ 32 physical endpoints
■ General Programmable Interface (GPIF II)*
❐ Programmable GPIF II, enabling connectivity to a wide range of external devices
❐ Interface frequency of up to 100 MHz
❐ 8-, 16-, and 32-bit data bus
❐ As many as 16 configurable control signals
■ 32-bit CPU
❐ ARM926EJ core with 200-MHz operation
❐ 512 KB or 256 KB embedded SRAM
■ Additional connectivity to the following peripherals:
❐ I2C master controller up to 1 MHz
❐ I2S master (transmitter only) at sampling frequencies of 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, and
192 kHz
❐ UART support of up to 4 Mbps
❐ SPI master at 33 MHz
■ Selectable clock input frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
■ Ultra low-power in core power-down mode
❐ Less than 60 μA with VBATT on and 20 μA with VBATT off
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Introduction to EZ-USB FX3
❐ Independent power domains for core and interfaces
❐ Core and USB operation at 1.2 V
❐ GPIF II, I2S, UART, and SPI operation at 1.8 to 3.3 V
❐ I2C and JTAG operation at 1.2 to 3.3 V
■ Storage interfaces*
❐ Mass storage support
❐ SD 3.0 (SDXC) UHS-1
❐ eMMC 4.41
❐ Two ports that can support memory card sizes up to 2 TB
❐ Built-in RAID (implemented in firmware) with support for RAID0 and RAID1
■ System I/O expansion with two secure digital I/O (SDIO 3.0) ports
■ Support for USB-attached storage (UAS), mass-storage class (MSC), human interface device (HID), full, and Turbo-
MTP™
*Storage interfaces are available only with FX3S and its GPIF data bus width is limited to 16 bits.
Table 1-3. Feature Differences Between FX3 and FX3S
Feature EZ-USB FX3 EZ-USB FX3S
GPIF 8/16/32-bit 8/16-bit
Storage ports No 1 or 2 ports (SD3.0, eMMC4.41, SDIO3.0)
USB 3.0, USB 2.0 Device Yes Yes
HS-OTG Yes Yes
CPU ARM9, 200 MHz ARM9, 200 MHz
Embedded SRAM 256 KB/512 KB 256 KB/512 KB
Serial Interfaces* I2C, SPI, I2S, UART I2C, SPI, I2S, UART
Boot Options I2C, SPI, USB, GPIF based All FX3 boot options + eMMC based boot options
Package 121-ball BGA, 10 x 10 mm, 0.8 mm pitch 121-ball BGA, 10 x 10 mm, 0.8 mm pitch
*All serial interfaces might not be available under all configuration options. Refer to the pin description section in the
datasheet for details.
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1.3.1 FX3 Block Diagram
32
EPs
GPIF II
SS
Peripheral
HS/FS/LS
OTGHost
JTAG
UART SPI
CTL[15:0]
INT#
RESET#
TDI
TDO
TRST#
TMS
TCK
DQ[31:0]/[15:0]
PMODE[2:0]
SSRX +
SSRX SSTX +
SSTX -
D +
D -
FSLC[0]
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
XTALIN
XTALOUT
OTG_ID
I2SI2C
SRAM
(512kB/256kB)
ARM9
USB
HS/FS
Peripheral
DMA Interconnect
I2C_SCL
I2C_SDA
TX
RX
CTS
RTS
SSN
SCLK
MISO
MOSI
I2S_CLK
I2S_SD
I2S_WS
I2S_MCLK
Introduction to EZ-USB FX3
Figure 1-6. FX3 Block Diagram
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1.3.2 FX3S Block Diagram
32
EPs
GPIF II
SS
Peripheral
HS/FS/LS
OTGHost
JTAG
UART
SPI
CTL[15:0]
INT#
RESET#
TDI
TDO
TRST#
TMS
TCK
DQ[15:0]
PMODE[2:0]
SSRX +
SSRX SSTX +
SSTX -
D +
D -
FSLC[0]
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
XTALIN
XTALOUT
OTG_ID
I2S
I2C
SRAM
(512kB/256kB)
ARM9
USB
HS/FS
Peripheral
DMA
Interconnect
I2C_SCL
I2C_SDA
S1_CMD
S1_WP
S1_D[7:0]
SD/MMC controller
S0-port S1-port
S1_CLK
S0_CLK
S0_CMD
S0_WP
S0_D[7:0]
S0S1_INS
Introduction to EZ-USB FX3
Figure 1-7. FX3S Block Diagram
Note: For more details on pin mapping and their descriptions, refer to FX3 and FX3S datasheets.
1.4 Functional Overview
1.4.1 CPU
FX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU. The core has direct access to 16 KB of instruction tightly
coupled memory (TCM) and 8 KB of data TCM. The ARM926EJ-S processor also has associated instruction cache (I-cache)
and data cache (D-cache) memories. Both the instruction and data caches are 8 KB.
FX3 integrates 512 KB or 256 KB (depending on the part number) of embedded SRAM for storing code and data. The
ARM926EJ-S core provides a JTAG interface for firmware debugging.
FX3 interrupts are managed through the standard ARM PrimeCell Vectored Interrupt Controller (PL192) block. This interrupt
controller provides vectored interrupt support with configurable priorities for all interrupt sources.
Examples of the FX3 firmware are available with the Cypress EZ-USB FX3 Development Kit.
For more information about the CPU subsystem, refer to the FX3 CPU Subsystem chapter on page 34.
For more information about the memory map, refer to the Memory and System Interconnect chapter on page 44.
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Introduction to EZ-USB FX3
1.4.2 DMA
FX3 enables efficient and flexible DMA transfers between the various peripherals (such as USB, GPIF II, I2S, SPI, and
UART), requiring firmware only to configure data accesses between peripherals. The data transfers are managed by
distributed DMA controllers within each peripheral. For more information about the FX3 DMA interconnect, refer to the FX3
DMA Subsystem chapter on page 58.
1.4.3 USB Interface
The FX3 USB interface supports the following:
■ USB SuperSpeed and High-Speed peripheral functionality is compliant with USB 3.0 specification revision 1.0 and is
backward compatible with the USB 2.0 specification.
■ As a USB peripheral, FX3 supports SuperSpeed, High-Speed, and Full-Speed transfers. As a host, FX3 supports High-
Speed, Full-Speed, and Low-Speed transfers.
■ Complies with OTG Supplement revision 2.0, supporting dual-role operation. As an OTG host, FX3 supports
■ USB classes such as Mass Storage (MSC) and Human Interface Device (HID).
■ Carkit Pass-through UART functionality on USB D+/D- lines based on the CEA-936A specification
■ 16 IN and 16 OUT endpoints
■ CONTROL, BULK, INTERRUPT, and ISOCHRONOUS endpoints
■ USB 3.0 BULK streams feature
For more information about the USB block, refer to the Universal Serial Bus (USB) chapter on page 78.
1.4.4 GPIF II
The GPIF II is a programmable state machine that enables a flexible interface that may function either as a master or slave to
industry-standard or proprietary interfaces. The high-performance GPIF II interface provides functionality similar to, but more
advanced than, the FX2LP™ GPIF and Slave FIFO interfaces. Both parallel and serial interfaces may be implemented with
GPIF II.
The GPIF II implements an interface by creating a GPIF II state machine. GPIF II state transitions are based on input signals,
and the control output signals are driven as a result of the GPIF II state transitions. Some popular interfaces that can be
implemented with GPIF II are the Slave FIFO interface, SRAM, Address/Data bus interfaces, and Address Multiplexed
(ADMux) interfaces.
For more information about the synchronous Slave FIFO interface, refer to the application note AN65974 - Designing with the
EZ-USB FX3 Slave FIFO Interface.
The key features of GPIF II are:
■ Functions as a master or slave
■ Provides 256 firmware programmable states
■ Supports 8-bit, 16-bit, 24-bit, and 32-bit parallel data buses
■ Enables interface frequencies up to 100 MHz
■ Supports 14 configurable control pins when a 32-bit data bus is used. All control pins can be either input or outputor bidi-
rectional.
■ Supports 16 configurable control pins when a 16- or 8-bit data bus is used. All control pins can be either input or output or
bidirectional.
Cypress's GPIF II Designer tool enables GPIF II designs to be developed quickly and includes examples of common
interfaces. For more information about the GPIF II block, refer to the General Programmable Interface II (GPIF II) chapter on
page 120.
EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 30
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