CYPRESS CYWUSB6935 User Manual

CYWUSB6935

WirelessUSB™ LR 2.4-GHz DSSS Radio SoC

1.0 Features

• 2.4-GHz radio transceiver

• Operates in the unlicensed Industrial, Scientific, and
Medical (ISM) band (2.4 GHz–2.483 GHz)

• –95-dBm receive sensitivity

• Up to 0dBm output power

• Range of up to 50 meters or more

• Data throughput of up to 62.5 kbits/sec

• Highly integrated low cost, minimal number of external
components required

• Dual DSSS reconfigurable baseband correlators

• SPI microcontroller interface (up to 2-MHz data rate)

• 13-MHz input clock operation

• Low standby current < 1 µA

• Integrated 32-bit Manufacturing ID

• Operating voltage from 2.7V to 3.6V

• Operating temperature from –40° to 85°C

• Offered in a small footprint 48 QFN

2.0 Functional Description

The CYWUSB6935 transce iver is a single-chi p 2.4-GHz Direct
Sequence Spread Spectrum (DSSS) Gaussian Frequency
Shift Keying (GFSK) baseband modem radio that connects
directly to a microcontroller via a simple serial peripheral
interface.

The CYWUSB6935 is offered in an industrial temperature
range 48-pin QFN and a commercial temperature range 48­pin QFN.

3.0 Applications

• Building/Home Automation
—Climate Control

—Lighting Control
—Smart Appliances
—On-Site Paging Systems
—Alarm and Security

• Industrial Control
—Inventory Managem ent

—Factory Automation
—Data Acquisition

• Automatic Meter Reading (AMR)

• Transportation
—Diagnostics

—Remote Keyless Entry

•Consumer / PC
—Locator Alarms

—Presenter Tools
—Remote Controls
—Toys

DIOVAL

DIO

GFSK

Modulator

GFSK

Demodulator

RFOUT

RFIN

IRQ

SS

SCK
MISO
MOSI

RESET

PD

Digital

SERDES

A

SERDES

B

X13

X13IN

DSSS

Baseband

A

DSSS

Baseband

B

Synthesizer

X13OUT

Figure 3-1. CYWUSB6935 Simplified Block Diagram

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document 38-16008 Rev. *A Revised October 28, 2004

CYWUSB6935

3.1 Applications Support

The CYWUSB6935 is supported by both the CY3632
WirelessUSB Developmen t Kit and th e CY3635 W ireles sUSB
N:1 Development Kit. The CY3635 development kit provides
all of the materials and documents needed to cut the cord on
multipoint to poin t and point-to-p oint low ban dwidth, high node
density applications including four small form-factor sensor
boards and a hub board th at conn ect s to Wi reless USB LR RF
module boards, a software app lication that gra phically demo n­strates the multipoint to point protocol, comprehensive
WirelessUSB protocol code examples and all of the
associated schematics, gerber files and bill of materials. The
WirelessUSB N:1 Development Kit is also supported by the
WirelessUSB Listener Tool.

4.0 Functional Overview

The CYWUSB6935 provides a complete SPI-to-a ntenna radio
modem. The CYWUSB6935 is designed to implement
wireless devices operating in the worldwide 2.4-GHz Indus­trial, Scientific, and Medical (ISM) frequen cy ba nd (2 .40 0G Hz

- 2.4835GHz). It is in tended for sys tems com pliant with worl d­wide regulations covered by ETSI EN 301 489-1 V1.4 .1, ETSI
EN 300 328-1 V1.3.1 (Europ ean Countries); FCC CFR 47 Part
15 (USA and Industry Canada) and ARIB STD-T66 (Japan).

The CYWUSB6935 contains a 2.4-GHz radio transceiver, a
GFSK modem, and a dual DSSS reconfigurable baseband.
The radio and baseband are both code- and frequency-agile.
Forty-nine spreading codes selected for optimal performance
(Gold codes) are supported across 78 1-MHz channels
yielding a theoretical spectral capacity of 3822 channels. The
CYWUSB6935 supports a range of up to 50 meters or more.

4.1 2.4-GHz Radio

The receiver and transmitter are a single-conversion, low­Intermediate Frequency (low-IF) architecture with fully
integrated IF channel matched filters to achieve high perfor­mance in the presence of interference. An integrated Power
Amplifier (P A) provide s an output power control range of 30 dB
in seven steps.

Table 4-1. Internal PA Output Power Step Table

P A Setting T ypical Output Power (dBm)

70
6–2.4
5–5.6
4–9.7
3–16.4
2–20.8
1–24.8
0–29.0

Both the receiver and transmitter integrated Voltage
Controlled Oscillator (VCO) and synthes izer have the ag ility to
cover the complete 2.4-GHz GFSK radio transmitter ISM
band. The synthesizer provides the frequency-hopping local
oscillator for the transmitter and receiver. The VCO loop filter
is also integrated on-chip.

4.2 GFSK Modem

The transmitter uses a DSP-based vector modulator to
convert the 1-MHz chips to an accurate GFSK carrier.

The receiver uses a fully integrated Frequency Modulat or (FM)
detector with automatic data slicer to demodulate the GFSK
signal.

4.3 Dual DSSS Baseband

Data is converted to DSSS chips by a digital spreader. De­spreading is performed by an oversampled correlator. The
DSSS baseband cancels spurious noise and assembles
properly correlated data bytes.

The DSSS baseban d h as th ree ope rati ng modes: 64 chips /b it
Single Channel, 32 chips/bit Single Channel, and 32 chips/bit
Single Channel Dual Data Rate (DDR).

4.3.1 64 chips/bit Single Chan nel

The baseband supports a single data stream operating at

15.625 kbits/sec. The advantage of selecting this mode is its
ability to tolerate a noisy environment. This is because the

15.625 kbits/sec data stream utilizes the longest PN Code
resulting in the high es t p r oba bil ity for recovering packe t s ov er
the air. This mode can also be selected for systems requiring
data transmissi ons over lon ger ranges.

4.3.2 32 chips/bit Single Chan nel

The baseband supports a single data stream operating at

31.25 kbits/sec.

4.3.3 32 chips/bit Single Channel Dual Data Rate (DDR)

The baseband spread s bits in p airs and s upports a si ngle data
stream operating at 62.5 kbits/sec.

4.4 Serializer/Deserializer (SERDES)

CYWUSB6935 provides a data Serializer/Deserializer
(SERDES), which provides byte-level framing of transmit and
receive data. Bytes for transmission are loaded into the
SERDES and receive bytes are read from the SERDES via the
SPI interface. The SERDES provides double buffering of
transmit and receive dat a. While on e byte is bein g transmitted
by the radio the next byte can be written to the SERDES data
register insuring there are no breaks in transmitted data.

After a receive byte has been received it is loaded into the
SERDES data register and can be read at any time until the

byte is received, at which time the old contents of the

next
SERDES data register wil l be overwritten.

4.5 Application Interfaces

CYWUSB6935 has a fu lly sy nchronous SPI slave interface f or
connectivity to the application MCU. Configuration and byte­oriented data transfer can be performe d over this interface. An
interrupt is provided to trigger real time events.

An optional SERDES Bypas s mode (DIO) is provided for a ppli­cations that require a synchronous serial bit-oriented data
path. This interface is for data only.

Document 38-16008 Rev. *A Page 2 of 32

CYWUSB6935

4.6 Clocking and Power Management

A 13-MHz crystal is directly connected to X13IN and X13
without the need for external capacitors. The CYWUSB6935
has a progr ammable tr im capabil ity for ad justing t he on-ch ip
load capacitance supplied to the crystal. The Radio Frequency
(RF) circuitry has on-chip decoupling capacitors. The
CYWUSB6935 is powere d from a 2.7V to 3 .6V DC supply. The
CYWUSB6935 can be sh utdown to a fully static state u sing the

pin.

PD
Below are the requirements for the crystal to be directly

connected to X13IN and X13:

• Nominal Frequency: 13 MHz

• Operating Mode: Fundamen tal Mode

• Resonance Mode: Paralle l Reson ant

• Frequency Stability:

• Series Resistance: ≤ 100 ohms

• Load Capacitance: 10 pF

• Drive Level: 10uW–100 uW

± 30 ppm

4.7 Receive Signal Strength Indicator (RSSI)

The RSSI register (Reg 0x22) returns the relative signal
strength of the ON-channel signal power and can be used to:

1. Determine the connection quality

2. Determine the value of the noise floor

3. Check for a quiet channel before transmitting.

The internal RSSI voltage is sampled through a 5-bit analog­to-digital converter (ADC). A state machine controls the
conversion process. Under normal conditions, the RSSI state
machine initia tes a c onv ersion when an ON-ch ann el ca rrie r i s
detected and remains abov e the noise floor for over 50uS. The
conversion produces a 5-bit value in the RSSI register (Reg
0x22, bits 4:0) along with a valid bit, RSSI register (Reg 0x22,
bit 5). The state machine then remains in HALT mode and
does not reset for a new conversion until the receive mode is
toggled off and on. Once a connection has been established,
the RSSI register can be read to determine the relative
connection quality of the channel . A RSSI register value lower
than 10 indicates that the received signal strength is low, a
value greater than 28 indicates a strong signal level.

To check for a quiet channel before transmitting, first set up
receive mode properl y and read the RSSI register (Reg 0 x22).
If the valid bit is zero, then force the Carrier Detect register
(Reg 0x2F, bit 7=1) to initiate an ADC conversion. Then, wait
greater than 50uS and read the RSSI register again. Next,
clear the Carrier Detect Register (Reg 0x2F, bit 7=0) and turn
the receiver OFF. Measuring the noise floor of a quiet channel
is inherently a 'noisy' process so, for best results, this
procedure should be repeated several times (~20) to compute
an average no ise floor level. A RSSI re gister value of 0-10
indicates a channel that is relatively quiet. A RSSI register
value greater than 10 indicates the channel is probably being
used. A RSSI register value greater than 28 indicates the
presence of a strong signal.

5.0 Application Interfaces

5.1 SPI Interface

The CYWUSB6935 has a four-wire SPI communication
interface between an a ppl ic ation MCU and one or more sl av e
devices. The SPI interface s upports single-byte an d multi- byte
serial transfers. The four-wire SPI communications interface
consists of Master Out-Slave In (MOSI), Master In-Slave Out
(MISO), Serial Clock (SCK), and Slave Select (SS

The SPI receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI
pin. Data to the application MCU is shifted out on the MISO
pin. The active-low Slave Selec t (SS)
initiate a SPI transfer.

The application MCU can initiate a SPI data transfer via a
multi-byte transact ion. T he first byt e is the Command/Add ress
byte, and the following bytes are the data bytes as shown in
Figure 5-1 through Figure 5-4. The SS
deasserted between bytes. The SPI communications is as
follows:

• Command Direction (bit 7) = “0 ” Enabl es SPI read transac­tion. A “1” enables SPI write transactions.

• Command Increment (b it 6) = “1” Enables SPI aut o address
increment. When se t, the addres s field automa tically i ncre­ments at the en d of each data byte in a bur s t access, ot h­erwise the same address is accessed.

• Six bits of address.

• Eight bits of data.

The SPI communications interface has a burst mechanism,
where the command byte can be followed by as many data
bytes as desired. A burst transaction is terminated by
deasserting the slave select (SS
tions, the application MCU must abide by the timing shown in
Figure 12-2.

The SPI communications i nter fac e s ing le re ad a nd b urs t rea d
sequences are shown in Figure 5-2 and Figure 5-3 , respec­tively.

The SPI communication s interfac e single write and burs t write
sequences are shown in Figure 5-4 and Figure 5-5 , respec­tively.

pin must be asserted to

signal should not be

= 1). For burst read transac-

).

Document 38-16008 Rev. *A Page 3 of 32

CYWUSB6935

Byte 1 Byte 1+N

Bit # 7 6 [5:0] [7:0]

Bit Name DIR INC Address Data

Figure 5-1. SPI Transaction Format

SCK

SS

addrcm d

A0A1A2A3A4A5

MOSI

DIR INC

00

data to mcu

MISO

D6D7

D0D1D2D3D4D5

Figure 5-2. SPI Single Read Sequence

SCK

SS

MOSI

MISO

DIR INC

01

addrcm d

A0A1A2A3A4A5

da ta to mcu

D6D7

1

D0D1D2D3D4D5

data to mcu

D6D7

1+N

D0D1D2D3D4D5

SCK

SS

MOSI

MISO

SCK

SS

MOSI

MISO

DIR INC

10

DIR INC

11

Figure 5-3. SPI Burst Read Sequence

addrcmd

D6D7

A0A1A2A3A4A5

data fro m mcu

Figure 5-4. SPI Single Write Sequence

addrcm d

da ta fro m mcu

D6D7

A0A1A2A3A4A5

D0D1D2D3D4D5

1

data from mcu

D0D1D2D3D4D5

D6D7

1+N

D0D1D2D3D4D5

Figure 5-5. SPI Burst Write Sequence

Document 38-16008 Rev. *A Page 4 of 32

CYWUSB6935

5.2 DIO Interface

The DIO communications interface is an optional SERDES
bypass data-only transfer interface. In receive mode, DIO and
DIOVAL are valid after the falling edge of IRQ, which clocks

IRQ

DIOVAL

v7v6v5v4v3v2

v9v8v1v0

data to mcu

DIO

d1d0

d7d6d5d4d3d2

Figure 5-6. DIO Receive Sequence

IRQ

DIOVAL

v1v0

v9v8

v7v6v5v4v3v2

data from mcu

DIO

d1d0

d7d6d5d4d3d2

Figure 5-7. DIO Transmit Sequence

the data as shown in

Figure 5-6. In transmit mode, DIO and

DIOVAL are sampled on the falling edge of the IRQ, which
clocks the data as shown in

Figure 5-7. The application MCU

samples the DIO and DIOVAL on the rising edge of IRQ.

v...v14v1 3v12v11v10

d...d14d13d12d11d1 0d9d8

v...v1 4v13v12v11v10

d...d1 4d13d12d11d10d9d8

5.3 Interrupts

The CYWUSB6935 features thre e se t s o f interrup t s: trans mi t,
received, and a wake interrupt. These interrupts all share a
single pin (IRQ), but can be independently enabled/disabled.
In transmit mode, all receive interrupts are automatically
disabled, and in receive mode all transmit interrupts are
automatically disabled. However, the contents of the enable
registers are preserve d when swit ching between tran smit an d
receive modes.

Interrupts are ena bled and the st atus read thr ough 6 registers:
Receive Interrupt Enable (Reg 0x07), Recei ve Interrupt S t atus
(Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit
Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake
Status (Reg 0x1D).

If more than 1 interrupt is enabled at any time, it is necessary
to read the relevant interrupt st atus register to determine which
event caused the IRQ pin to assert. Even when a given
interrupt source is disabled, the status of the condition that
would otherwise cause an interrupt can be determined by
reading the appropriate int errupt st atus regis ter. It is therefore
possible to use th e devic es with out mak ing us e of the I RQ pin
at all. Firmware can poll the interrupt status register(s) to wait
for an event, rather than using the IRQ pin.

The polarity of all interrupt s can be s et by writing to the Co nfig­uration register (Reg 0x05), and it is possible to configure the
IRQ pin to be o pen drain (if a ctive low) o r open source (if active
high).

5.3.1 Wake Interrupt

When the PD pin is low, the oscillator is stopped. After PD is
deasserted, the oscillator takes time to start, and until it has
done so, it is not safe to use the SPI interface. The wake

interrupt indicates that the oscillator has started, and that the
device is ready to receive SPI transfers.

The wake interrupt is enabled by setting bit 0 of the Wake
Enable register (Reg 0x1C, bit 0=1). Whether or not a wake
interrupt is pendin g is indicated by the state of bit 0 of the Wake
Status register (Reg 0x1D, bit 0). Reading the Wake Status
register (Reg 0x1D) clears the interrupt.

5.3.2 T ran sm it Inte rrupts

Four interrupts a re p rov id ed t o fl ag the oc cu rren ce of t rans m it
events. The interrupts are enabled by writing to the Transmit
Interrupt Enable register (Reg 0x0D), and their status may be
determined by reading the Transmit Interrupt Status register
(Reg 0x0E). If more than 1 interrupt i s enabled , it is neces sary
to read the Transmit Interrupt Status register (Reg 0x0E) to
determine which event caused the IRQ pin to assert.

The function and operatio n of these interrupts are des cribed in
detail in

Section 7.0.

5.3.3 Receive Interrupts

Eight interrupts are provided to flag the occurrence of receive
events, four each fo r SERDES A and B. In 64 c hips /bit and 3 2
chips/bit DDR modes, only the SERDES A interrupts are
available, and the SERDES B interrupts will never trigger,
even if enabled. The interrupts are enabled by writing to the
Receive Interrupt Enab le regis ter (Reg 0x 07), and their st atu s
may be determin ed by reading the Rece ive Interrupt Status
register (Reg 0x08 ). If m ore th an on e int errup t i s en abl ed, it i s
necessary to read the Receive Interrupt Status register (Reg
0x08) to determine whic h e ven t ca us ed th e IRQ pin to as se rt.

The function and operatio n of these interrupts are des cribed in
detail in

Section 7.0.

Document 38-16008 Rev. *A Page 5 of 32

CYWUSB6935

6.0 Application Examples

Figure 6-1 shows a block di agram example of a typ ical battery

powered device using the CYWUSB6935 chip.

Battery

Application

Hardware

LDO/

DC2DC

+

-

PSoC

8-bit MCU

Figure 6-1. CYWUSB6935 Battery Powered Device

Vcc





3.3 V

RESET

PD

IRQ

SPI

4

Figure 6-2 shows an application example of a WirelessUSB

LR alarm system where a single hub node is connected to an
alarm panel. The hub node wirelessly receives information
from multiple sensor nodes in order to control the alarm panel.

2.0 pF

PCB Tr ace

Wig g l e
Antenna

1.2 pF

27 pF

Vcc

RFOUT

Wir elessUSB LR

RFIN

0.1µF

2.0 pF

13M Hz
Crystal

3.3 nH

2.2 nH

ALARM PANEL

R

S

2

3

2

W irelessUSB LR +

PSoC

W irelessUSB LR

W irelessUSB LR

W irelessUSB LR

W irelessUSB LR PSoC + KEYPAD

Figure 6-2. WirelessUSB LR Alarm Syste m

PSoC + SMOKE

DETECTOR

PSoC + MOTION

DETECTOR

PSoC + DOOR

SENSOR

…

Document 38-16008 Rev. *A Page 6 of 32

CYWUSB6935

7.0 Register Descriptions

Table 7-1 displays the list of registers inside the

CYWUSB6935 that are addressable through the SPI interfac e.
All registers are read and writable, except where noted.

Table 7-1. CYWUSB6935 Register Map

Register Name Mnemonic

Revision ID REG_ID 0x00 9 0x07 RO
Reserved RESERVED 0x01 8 0x00 RW
Reserved RESERVED 0x02 8 0x00 RW
Control REG_CONTROL 0x03 9 0x00 RW
Data Rate REG_DATA_RATE 0x04 10 0x00 RW
Configuration REG_CONFIG 0x05 11 0x01 RW
SERDES Control REG_SERDES_CTL 0x06 11 0x03 RW
Receive SERDES Interrupt Enable REG_RX_INT_EN 0x07 12 0x00 RW
Receive SERDES Interrupt Status REG_RX_INT_STAT 0x08 13 0x00 RO
Receive SERDES Data A REG_RX_DATA_A 0x09 14 0x00 RO
Receive SERDES Valid A REG_RX_VALID_A 0x0A 14 0x00 RO
Receive SERDES Data B REG_RX_DATA_B 0x0B 14 0x00 RO
Receive SERDES Valid B REG_RX_VALID_B 0x0C 14 0x00 RO
Transmit SERDES Interrupt Enable REG_TX_INT_EN 0x0D 15 0x00 RW
Transmit SERDES Interrupt Status REG_TX_INT_STAT 0x0E 15 0x00 RO
Transmit SERDES Data REG_TX_DATA 0x0F 16 0x00 RW
Transmit SERDES Valid REG_TX_VALID 0x10 16 0x00 RW
PN Code REG_PN_CODE 0x18–0x11 16
Threshold Low REG_THRESHOLD_L 0x19 17 0x08 RW
Threshold High REG_THRESHOLD_H 0x1A 17 0x38 RW
Wake Enable REG_WAKE_EN 0x1C 18 0x00 RW
Wake Status REG_WAKE_STAT 0x1D 18 0x01 RO
Analog Control REG_ANALOG_CTL 0x20 18 0x04 RW
Channel REG_CHANNEL 0x21 19 0x00 RW
Receive Signal Strength Indicator REG_RSSI 0x22 19 0x00 RO
Power Control REG_PA 0x23 19 0x0 0 RW
Crystal Adjust REG_CRYSTAL_ADJ 0x24 20 0x00 RW
VCO Calibration REG_VCO_CAL 0x26 20 0x00 RW
Reg Power Control REG_PWR_CTL 0x2E 21 0x00 RW
Carrier Detect REG_CARRIER_DETECT 0x2F 21 0x00 RW
Clock Manual REG_CLOCK_MANUAL 0x32 21 0x00 RW
Clock Enable REG_CLOCK_ENABLE 0x33 21 0x00 RW
Synthesizer Lock Count REG_SYN_LOCK_CNT 0x38 22 0x64 RW
Manufacturing ID REG_MID 0x3C–0x3F 22 – RO

[1]

CYWUSB6935

Address Page Default Access

0x1E8B6A3DE0E9B222

RW

Note:

1. All registers are accessed Little Endian.

Document 38-16008 Rev. *A Page 7 of 32

CYWUSB6935

Addr: 0x00 REG_ID Default: 0x07

76543210

Silicon ID Product ID

Figure 7-1. Revision ID Register

Bit Name Description
7:4 Silicon ID These are the Silicon ID revision bits. 0000 = Rev A, 0001 = Rev B, etc. These bits are read-only.
3:0 Product ID These are the Product ID revision bits. Fixed at value 0111. These bits are read-only.

Addr: 0x01 RESERVED Default: 0x00

76543210

Reserved

Figure 7-2. Reserved

Bit Name Description

7:0 Reserved These bits are reserved and should be written with zeroes.

Addr: 0x02 RESERVED Default: 0x00

76543210

Reserved

Figure 7-3. Reserved

Bit Name Description

7:0 Reserved These bits are reserved and should be written with zeroes.

Document 38-16008 Rev. *A Page 8 of 32

CYWUSB6935

Addr: 0x03 REG_CONTROL Default: 0x00

76543210

RX

Enable

TX

Enable

PN Code

Select

Auto Syn

Count Select

Auto Internal PA

Disable

Internal PA

Enable

Reserved Reserved

Figure 7-4. Control

Bit Name Description

7 RX Enable The Receive Enable bit is used to place the IC in receive mode.

6 TX Enable The Transmit Enable bit is used to place the IC in transmit mode.

5 PN Code Select The Ps eudo-Noise Code Select bit selects between the upper or lower half of the 64 chips/bit PN code.

4 Auto Syn Count

Select

3 Auto Internal PA

Disable

2 Internal PA

Enable

1 Reserv ed This bit is reserved and should be written with a one.
0 Reserv ed This bit is reserved and should be written with a zero.

1 = Receive Enabled
0 = Receive Disabled

1 = Transmit Enabled
0 = Transmit Disabled

1 = 32 Most Significant Bits of PN code are used
0 = 32 Least Significant Bits of PN code are used

This bit applies only when the Code Width bit is set to 32 chips/bit PN codes (Reg 0x04, bit 2=1).
The Auto Synthesizer Count Select bit is used to select the method of determining the settle ti me of the synthesizer .

The two options are a programmable settle time based on the value in Syn Lock Count register (Reg 0x38), in units
of 2us, or by the auto detection of the synthesizer lock.

1 = Synthesizer settle time is based on a count in Syn Lock Count register (Reg 0x38)
0 = Synthesizer settle time is based on the internal synthesizer lock signal

It is recommended that the Auto Syn Count Select bit is set to 1 as that guarantees a consistent settle time for the
synthesizer.

The Auto Internal PA Disable bit is used to determine the method of controlling the Internal Power Amplifier. The
two options are automatic control by the baseband or by firmware through register writes. For external PA usage,
please see the description of the REG_ANALOG_CTL register (Reg 0x20).

1 = Register controlled Internal PA Enable
0 = Auto controlled Internal PA Enable

When this bit is set to 1, the enabled state of the Internal PA is directly controlled by bit Internal PA Enable (Reg
0x03, bit 2). It is recommended that this bit is set to 0, leaving

The Internal PA Enable bit is used to enable or disable the Internal Power Amplifier.

1 = Internal Power Amplifier Enabled
0 = Internal Power Amplifier Disabled

This bit only applies when the Auto Internal P A Disable bit is selected (Reg 0x03, bit 3=1), otherwise this bit is don’t
care.

the PA control to the baseband.

Document 38-16008 Rev. *A Page 9 of 32

CYWUSB6935

Addr: 0x04 REG_DATA_RATE Default: 0x00

76543210

Reserved Code Width Data Rate Sample Rate

Figure 7-5. Data Rate

Bit Name Description

7:3 Reserved

[2]

2

Code Width The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes.

[2]

Data Rate The Data Rate bit allows the user to select Double Data Rate mode of operation which delivers a raw data rate of

1

[2]

Sample Rate The Sample Rate bit allows the use of the 12x sampling when using 32 chips/bit PN codes and Normal Data Rate.

0

These bits are reserved and should be written with zeroes.

1 = 32 chips/bit PN codes
0 = 64 chips/bit PN codes

The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to inter­ference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when double
data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well as more
robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits are impacted
and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit 1), and Sample
Rate (Reg 0x04, bit 0).

62.5kbits/sec.
1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions)

0 = Normal Data Rate - 1 bit per PN code

This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit (Reg
0x04, bit 2=1). When using Double Data Rate, the raw data throughput is 62.5 kbits/sec because every 32 chips/bit
PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is placed in the PN code
register. This 64 chips/bit PN code is then split into two and used by the baseband to offer the Double Data Rate
capability.
enables the user to potentially correlate data using two differing 32 chips/bit PN codes.

Using 12x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or Double Data
Rate this bit is don’t care. The only time when 12x oversampling can be selected is when a 32 chips/bit PN code is
being used with Normal Data Rate.

When using Normal Data Rate, the raw data throughput is 32kbits/sec. Additionally, Normal Data Rate

1 = 12x Oversampling
0 = 6x Oversampling

Note:

2. The following Reg 0x04, bits 2:0 values are no t valid:

• 001–Not Valid

• 010–Not Valid

• 011–Not Valid

• 111–Not Valid

Document 38-16008 Rev. *A Page 10 of 32