Cypress CYV15G0404RB User Manual
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CYV15G0404RB
Independent Clock Quad HOTLink II™
Deserializing Reclocke
Features
• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Quad channel video reclocking deserializer
— 195 to 1500 Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Supports reception of either 1.485 or 1.485/1.001 Gbps data
rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
• Selectable differential PECL-compatible serial inputs
— Internal DC restoration
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power: 3W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
•0.25µ BiCMOS technology
Functional Description
The C YV15G0404RB Ind ependent Clock Quad HOT Link II™
Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling data transfer
over a variety of high speed se ri al li n ks i n cl ud i n g SMPTE 292
and SMPTE 259 video applications. It supports signaling rates
in the range of 195 to 1500 Mbps for each serial link. The four
channels are independent and can simultaneously operate at
different rates. Each receive channel accepts serial data and
converts it to 10-bit parallel characters and presents these
characters to an Output Register. The received serial data can
also be reclocked and retransmitted through the reclocker
serial outputs. Figure 1, "HOTLink II™ System Connections,"
on page 2 illustrates typical connections between independent
video coprocessors and corresponding CYV15G0404RB
Reclocking Deserializer and CYV15G0403TB Serializer chips.
The CYV15G0404RB is SMPTE-259M and SMPTE-292M
compliant according to SMPTE EG34-1999 Pathological Test
Requirements.
As a second generation HOTLink device, the
CYV15G0404RB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices.
Each channel of the CYV15G0404RB Quad HOTLink II device
accepts a serial bit-stream from one of two selectable
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. The
device reclocks and retransmits recovered bit-stream through
the reclocker serial outputs. It also deserializes the recovered
serial data and presents it to the destination host system.
Each channel contains an independent BIST pattern checker.
This BIST hardware enables at speed testing of the
high-speed serial data paths in each receive section of this
device, each transmit section of a connected HOTLink II
device, and across the interconnecting links.
The CYV15G0404RB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include
multi-format routers, switchers, format converters, SDI
monitors, and camera control units.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-02102 Rev. *C Revised February 16, 2007
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Figure 1. HOTLink II™ System Connections
Reclocked
Outputs
CYV15G0404RB
10
Video Coprocesso r
10
Independent
Channel
10
10
CYV15G0403TB
Serializer
Serial Links
Reclocked
Outputs
Reclocking Deserializer
CYV15G0404RB Deserializing Reclocker Logic Block Diagram
RXDA[9:0]
TRGCLKA±
RXDB[9:0]
TRGCLKB±
RXDC[9:0]
Independent
Channel
CYV15G0404RB
TRGCLKC±
10
10
10
Video Coprocessor
10
RXDD[9:0]
TRGCLKD±
Deserializer
Reclocker
ROUTA1±
ROUTA2±
x10
RX
INA1±
x10
Deserializer
Reclocker
INA2±
ROUTB1±
ROUTB2±
RX
INB1±
Reclocker
INB2±
x10
Deserializer
±
±
ROUTC1
ROUTC2
RX
±
INC1
x10
Deserializer
Reclocker
±
±
INC2
±
ROUTD1
ROUTD2
RX
±
IND1
±
IND2
Document #: 38-02102 Rev. *C Page 2 of 27
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CYV15G0404RB
Reclocking Deserializer Path Block Diagram
TRGRATEA
TRGCLKA
SDASEL[2..1]A[1:0]
LDTDEN
INSELA
INA1+
INA1–
INA2+
INA2–
ULCA
SPDSELA
RXPLLPDA
Recovered Character Clock
RECLKOA
REPDOA
x2
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Recovered Serial Data
Reclocker
Output PLL
Clock Multiplier A
Character-Rate Clock A
10
Shifter
RXBISTA[1:0]
RXRATEA
ROE[2..1]A
10
BIST LFSR
JTAG
Boundary
Scan
Controller
Output
Register
÷2
Register
10
ROE[2..1]A
= Internal Signal
RESET
TRST
TMS
TCLK
TDI
TDO
LFIA
RXDA[9:0]
BISTSTA
RXCLKA+
RXCLKA–
ROUTA1+
ROUTA1–
ROUTA2+
ROUTA2–
TRGCLKB
LDTDEN
INSELB
INB1+
INB1–
INB2+
INB2–
ULCB
SPDSELB
RECLKOB
REPDOB
TRGRATEB
SDASEL[2..1]B[1:0]
RXPLLPDB
x2
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Recovered Character Clock
Reclocker
Output PLL
Clock Multiplier B
Character-Rate Clock B
10
Shifter
RXBISTB[1:0]
RXRATEB
Recovered Serial Data
ROE[2..1]B
10
BIST LFSR
Output
Register
Register
÷2
10
ROE[2..1]B
LFIB
RXDB[9:0]
BISTSTB
RXCLKB+
RXCLKB–
ROUTB1+
ROUTB1–
ROUTB2+
ROUTB2–
Document #: 38-02102 Rev. *C Page 3 of 27
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CYV15G0404RB
Reclocking Deserializer Path Block Diagram (continued)
TRGRATEC
TRGCLKC
SDASEL[2..1]C[1:0]
LDTDEN
INSELC
INC1+
INC1–
INC2+
INC2–
ULCC
SPDSELC
RXPLLPDC
Recovered Character Clock
RECLKOC
REPDOC
x2
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Reclocker
Output PLL
Clock Multiplier C
Character-Rate Clock C
10
Shifter
RXBISTC[1:0]
RXRATEC
Recovered Serial Data
ROE[2..1]C
10
BIST LFSR
Output
Register
Register
÷2
10
ROE[2..1]C
= Internal Signal
LFIC
RXDC[9:0]
BISTSTC
RXCLKC+
RXCLKC–
ROUTC1+
ROUTC1–
ROUTC2+
ROUTC2–
TRGCLKD
LDTDEN
INSELD
IND1+
IND1–
IND2+
IND2–
ULCD
SPDSELD
RECLKOD
REPDOD
TRGRATED
SDASEL[2..1]D[1:0]
RXPLLPDD
x2
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Recovered Character Clock
Reclocker
Output PLL
Clock Multiplier D
Character-Rate Clock D
10
Shifter
RXBISTD[1:0]
RXRATED
Recovered Serial Data
ROE[2..1]D
10
BIST LFSR
Output
Register
Register
÷2
10
ROE[2..1]D
LFID
RXDD[9:0]
BISTSTD
RXCLKD+
RXCLKD–
ROUTD1+
ROUTD1–
ROUTD2+
ROUTD2–
Document #: 38-02102 Rev. *C Page 4 of 27
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CYV15G0404RB
Device Configuration and Control Block Diagram
WREN
ADDR[3:0]
DATA[7:0]
Device Configuration
and Control Interface
= Internal Signal
RXBIST[A..D]
RXRATE[A..D]
SDASEL[A..D][1:0]
RXPLLPD[A..D]
ROE[2..1][A..D]
GLEN[11..0]
FGLEN[2..0]
Document #: 38-02102 Rev. *C Page 5 of 27
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CYV15G0404RB
Pin Configuration (Top View)
[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
IN
ROUT
C1–
C1–INC2–
B
IN
ROUT
C1+
C1+INC2+
C
TDI TMS INSELC INSELB
D
TCLK RESET INSELD INSELA
E
VCCVCCVCCV
F
RX
DC[8]RXDC[9]
G
H
J
K
L
M
N
WREN
GND
GND GND GND GND GND GND GND GND
GND GND GND GND
RX
TRG
DC[4]
CLKC–
RX
TRG
DC[5]
CLKC+
RX
DC[6]RXDC[7]
GND GND GND GND GND GND GND GND
ROUT
C2–
ROUT
C2+
CC
VCCV
CC
GND GND
GND GND
LFIC
GND
RE
V
CC
PDOC
V
CC
V
CC
V
CC
V
CC
IN
ROUT
D1–
D1–
IN
ROUT
D1+
D1+
ULCD ULCC
ULCA SPD
SELC
GND
GND
GND
GND
IN
D2–
IN
D2+
DATA
[7]
DATA
[6]
ROUT
D2–INA1–
ROUT
D2+INA1+
DATA
[5]
DATA
[4]
DATA
[3]
DATA
[2]
ROUT
A1–
ROUT
A1+
DATA
[1]
DATA
[0]
IN
GND
A2–
IN
GND
A2+
GND V
CC
GND GND
ROUT
A2–
ROUT
A2+
SPD
SELD
ULCB
IN
V
CC
B1–
IN
V
CC
B1+
LDTD ENTRST
V
CC
V
NC V
CC
VCCVCCVCCV
V
CC
SPD
SELB
BIST
STBRXDB[2]RXDB[7]RXDB[4]
RX
DB[5]RXDB[6]RXDB[9]
RX
DB[8]RXCLKB+RXCLKB–
TRG
CLKB+
CLKB–REPDOB
ROUT
B1–INB2–
ROUT
B1+INB2+
CC
RX
DB[0]RECLKOBRXDB[1]
NC
ROUT
B2–
ROUT
B2+
TDO
GND
SCAN
TMEN3
EN2
SPD
SELARXDB[3]
LFIB
GND
TRG
GND
CC
P
RX
DC[3]RXDC[2]RXDC[1]RXDC[0]
R
BIST
STCRECLKOCRXCLKC+RXCLKC–
T
VCCVCCVCCV
U
VCCVCCVCCVCCV
V
VCCVCCV
W
VCCV
CC
Y
VCCV
CC
Note
1. NC = Do not connect.
CC
DD[8]
LFID RX
CLKD–
RX
DD[9]
CLKD+
RX
RX
CC
CC
V
CC
V
CC
V
CC
RX
DD[4]RXDD[3]
RX
DD[5]RXDD[1]
RX
DD[6]RXDD[0]
RX
DD[7]RXDD[2]
GND GND
BIST
GND
STD
ADDR
GND
[3]
RE
GND
CLKOD
ADDR
TRG
[0]
CLKD–
ADDR
TRG
[2]
CLKD+RECLKOA
ADDR
[1]RXCLKA+REPDOA
NC
GND
CLKA–
GND GND GND VCCV
GND GND VCCV
GND GND VCCV
RX
GND GND VCCV
GND GND GND GND
VCCVCCVCCV
VCCVCCVCCV
RX
CC
CC
CC
CC
V
DA[4]
DA[9]RXDA[5]RXDA[2]RXDA[1]
PDOD
CC
RX
LFIA TRG
CLKA+RXDA[6]RXDA[3]
RE
TRG
CLKA–RXDA[8]RXDA[7]
BIST
STARXDA[0]
CC
CC
Document #: 38-02102 Rev. *C Page 6 of 27
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CYV15G0404RB
Pin Configuration (Bottom View)
[1]
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ROUT
A
B2–INB2–
ROUT
B
B2+INB2+
TDO
C
TMEN3 SCAN
D
VCCVCCVCCV
E
RX
F
DB[1]RECLKOBRXDB[0]
RX
G
DB[3]
GND GND GND GND GND GND GND GND
H
RX
J
DB[4]RXDB[7]RXDB[2]
GND
EN2
SPD
SELA
ROUT
B1–INB1–
ROUT
B1+INB1+
TRST LDTD
EN
V
NC V
CC
CC
V
CC
SPD
NC
SELB
BIST
STB
V
V
V
CC
CC
CC
CC
ROUT
A2–INA2–
ROUT
A2+INA2+
SPD
SELD
ULCB
GND
GND
VCCGND
GND GND
ROUT
A1–INA1–
ROUT
A1+INA1+
DATA
[1]
DATA
[0]
DATA
[3]
DATA
[2]
ROUT
D2–IND2–
ROUT
D2+IND2+
DATA
[5]
DATA
[4]
DATA
[7]
DATA
[6]
GND
GND
GND
GND
ROUT
D1–IND1–
ROUT
D1+IND1+
ULCC ULCD
SPD
ULCA
SELC
ROUT
V
CC
C2–INC2–
ROUT
V
CC
C2+INC2+
INSELB INSELC TMS TDI
V
CC
INSELA INSELD RESET TCLK
V
CC
VCCVCCVCCV
VCCV
GND GND
GND GND GND GND
CC
ROUT
C1–INC1–
ROUT
C1+INC1+
RX
DC[9]RXDC[8]
WREN
GND
CC
LFIB RX
K
L
M
N
P
R
T
U
V
W
Y
DB[9]RXDB[6]RXDB[5]
RX
GND
CLKB–RXCLKB+RXDB[8]
RE
TRG
GND
PDOB
CLKB–
TRG
CLKB+
GND GND GND GND GND GND GND GND
GND GND GND GND
VCCVCCVCCV
VCCVCCVCCV
RX
BIST
DA[0]
STA
RX
DA[1]RXDA[2]RXDA[5]RXDA[9]
RX
DA[3]RXDA[6]
RX
DA[7]RXDA[8]
CLKA+
CLKA–REPDOD
V
CC
TRG
TRG
CC
CC
RX
VCCVCCGND GND GND
DA[4]
VCCVCCGND GND
LFIA
VCCVCCGND GND
VCCVCCGND GND
TRG
CLKD–
RE
TRG
CLKOA
CLKD+
RE
PDOARXCLKA+
RX
GND
CLKA–
ADDR
[0]
ADDR
[2]
ADDR
[1]
NC RE
GND GND
BIST
GND
STD
ADDR
GND
[3]
GND
CLKOD
RX
DD[3]RXDD[4]
RX
DD[1]RXDD[5]
RX
DD[0]RXDD[6]
RX
DD[2]RXDD[7]
GND GND
LFIC TRG
GND
RE
V
PDOC
DC[0]RXDC[1]RXDC[2]RXDC[3]
CLKC–RXCLKC+RECLKOC
CC
RX
RX
VCCVCCVCCV
VCCVCCVCCVCCV
RX
V
CC
V
CC
V
CC
VCCVCCV
DD[8]
RX
LFID
CLKD–
RX
CLKD+RXDD[9]
TRG
CLKC–RXDC[4]
CLKC+RXDC[5]
RX
DC[7]RXDC[6]
BIST
STC
CC
CC
CC
VCCV
CC
VCCV
CC
Document #: 38-02102 Rev. *C Page 7 of 27
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Pin Definitions
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name IO Characteristics Signal Description
Receive Path Data and Status Signals
RXDA[9:0]
RXDB[9:0]
RXDC[9:0]
RXDD[9:0]
BISTSTA
BISTSTB
BISTSTC
BISTSTD
REPDOA
REPDOB
REPDOC
REPDOD
Receive Path Clock Signals
TRGCLKA±
TRGCLKB±
TRGCLKC±
TRGCLKD±
RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±
RECLKOA
RECLKOB
RECLKOC
RECLKOD
Device Control Signals
RESET
LVTTL Output,
synchronous to the
RXCLK± output
LVTTL Output,
synchronous to the
RXCLKx± output
Asynchronous to
reclocker output
channel
enable / disable
Differential LVPECL or
single-ended
LVTTL input clock
LVTTL Output Clock Receive Clock Output. RXCLKx± is the receive interface clock that controls
LVTTL Output Reclocker Clock Output
LVTTL Input,
asynchronous,
internal pull up
Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the
receive interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs
are complementary clocks operating at the character rate. The RXDx[9:0] outputs
for the associated receive channels follow the rising edge of RXCLKx+ or the
falling edge of RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock
outputs are complementary clocks operating at half the character rate. The
RXDx[9:0] outputs for the associated receive channels follow both the falling and
rising edges of the associated RXCLKx± clock outputs.
When BIST is enabled on the receive channel, the RXDx[1:0] and BISTSTx
outputs present the BIST status. See Table 5, “Receive BIST Status Bits,” on
page 17 for each status that the BIST state machine reports. Also, while BIST is
enabled, ignore the RXDx[9:2] outputs.
BIST Status Outp ut. When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])
displays the status of the BIST reception. See T able 5, “Receive BIST S tat us Bits,”
on page 17 for the BIST status for each combination of BISTSTx and RXDx[1:0].
When RXBISTx[1:0] ≠ 10, ignore BISTSTx.
Reclocker Powered Down Status Output. REPDOx asserts HIGH when the
associated channel’s reclocker output logic powers down. This occurs when
disabling ROE2x and ROE1x by setting ROE2x = 0 and ROE1x = 0.
CDR PLL Training Clock. The frequency detector (Range Controller) of the
associated receive PLL uses the TRGCLKx± clock inputs as the reference source
to reduce PLL acquisition time.
In the presence of valid serial data, the recovered clock output of the receive CDR
PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.
When a single-ended LVCMOS or LVTTL clock source drives the clock, connect
the clock source to either the true or complement TRGCLKx input, and leave the
alternate TRGCLKx input open (floating). When an LVPECL clock source drives
it, the clock must be a differential clock, using both inputs.
timing of the RXDx[9:0] parallel outputs. These true and complement clocks
control timing of data output transfers. These clocks output continuously at either
the half-character rate (1/20 the serial bit-rate) or character rate (1/1 0 the serial
bit-rate) of the data being received, as selected by RXRATEx.
. The associated reclocker output PLL synthesizes the
RECLKOx output clock, which operates synchronous to the internal recovered
character clock. RECLKOx operates at either the same frequency as RXCLKx±
(RXRATEx = 0), or at twice the frequency of RXCLKx± (RXRATEx = 1). The
reclocker clock outputs have no fixed phase relationship to RXCLKx±.
Asynchronous Device Reset. RESET initializes all state machines, counters,
and configuration latches in the device to a known state. RESET
for a minimum pulse width. When the reset is removed, all state machines,
counters and configuration latches are at an initial state. According to the JTAG
specifications, the device RESET
JTAG controller has to be reset separately. Refer to “JTAG Support” on page 17
for the methods to reset the JTAG state machine. See Table 3, “Device Configu-
ration and Control Latch Descriptions,” on page 14 for the in itialize values of the
device configuration latches.
CYV15G0404RB
must assert LOW
cannot reset the JTAG controller . Therefore, the
Document #: 38-02102 Rev. *C Page 8 of 27
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CYV15G0404RB
Pin Definitions (continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name IO Characteristics Signal Description
LDTDEN LVTTL Input,
internal pull up
ULCA
ULCB
LVTTL Input,
internal pull up
ULCC
ULCD
[2]
SPDSELA
SPDSELB
3-Level Select
static control input
SPDSELC
SPDSELD
INSELA
INSELB
LVTTL Input,
asynchronous
INSELC
INSELD
LFIA
LFIB
LVTTL Output,
asynchronous
LFIC
LFID
Device Configuration and Control Bus Signals
WREN
LV TTL input,
asynchronous,
internal pull up
ADDR[3:0] LVTTL input
asynchronous,
internal pull up
Notes
2. Use 3-Level Select inputs for static configuration. These are ternary input s th at use logic le vels of L OW, MID, and HIGH. To implement the LOW level, connect
directly to V
which allows it to self bias to the proper level.
3. See “Device Configuration and Control Interface” on page13 for detailed information about the operation of the Configuration Interface.
(ground). To implement the HIGH level, connect directly to VCC (power). To implement the MID level, do not connect the input (leave floating),
SS
Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal
Level Detector, Range Controller, and Transition Density Detector are all enabled
to determine if the RXPLL tracks TRGCLKx± or the selected input serial data
stream. If the Signal Level Detector, Range Controller, or Transition Density
Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks
to TRGCLKx± until they become valid. The SDASEL[A..D][1:0] inputs configure
the trip level of the Signal Level Detector. The Transition Density Detector limit is
one transition in every 60 consecutive bits. When LDTDEN is LOW, only the
Range Controller determines if the RXPLL tracks TRGCLKx± or the selected input
serial data stream. Set LDTDEN = HIGH.
Use Local Clock. When ULCx is LOW, the RXPLL locks to TRGCLKx± instead
of the received serial data stream. While ULCx
is LOW, the LFIx for the associ ated
channel is LOW, indicating a link fault.
When ULCx
is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications that need a stable
RXCLKx±. When valid data transitions are absent for a long time, or the high-gain
differential serial inputs (INx±) are left floating, the RXCLKx± outputs may briefly
be different from TRGCLKx±.
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate
range of each channel’s receive PLL.
LOW = 195–400 MBd
MID = 400–800 MBd
HIGH = 800–1500 MBd.
Receive Input Selector. The INSELx input determines which external serial bit
stream passes to the receiver’s Clock and Data Recovery circuit. When INSELx
is HIGH, the Primary Differential Serial Data Input, INx1±, is the associated receive
channel. When INSELx is LOW, the Secondary Differential Serial Data Input,
INx2±, is the associated receive channel.
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
logical OR of six internal conditions. LFIx
asserts LOW when any of the following
conditions is true:
• Received serial data rate is outside expected range
• Analog amplitude is below expected levels
• Transition density is lower than expected
• Receive is channel disabled
is LOW
•ULCx
• TRGCLKx± is absent.
Control Write Enable. The WREN input writes the values of the DATA[7:0] bus
into the latch specified by the address location on the ADDR[3:0] bus.
[3]
Control Addressing Bus. The ADDR[3:0] bus is the input address bus that
configures the device. The WREN
into the latch specified by the address location on the ADDR[3:0] bus.
input writes the values of the DATA[7:0] bus
[3]
Table 3,
“Device Configuration and Control Latch Descriptions,” on page 14 lists the config-
uration latches within the device, and the initiali zation value of the latches when
RESET
is asserted. Table 4, “Device Control Latch Configuration Table,” on
page 16 shows how the latches are mapped in the device.
Document #: 38-02102 Rev. *C Page 9 of 27
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