• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Quad channel video reclocking deserializer
— 195 to 1500 Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Supports reception of either 1.485 or 1.485/1.001 Gbps data
rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
• Selectable differential PECL-compatible serial inputs
— Internal DC restoration
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power: 3W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
•0.25µ BiCMOS technology
Functional Description
The C YV15G0404RB Ind ependent Clock Quad HOT Link II™
Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling data transfer
over a variety of high speed se ri al li n ks i n cl ud i n g SMPTE 292
and SMPTE 259 video applications. It supports signaling rates
in the range of 195 to 1500 Mbps for each serial link. The four
channels are independent and can simultaneously operate at
different rates. Each receive channel accepts serial data and
converts it to 10-bit parallel characters and presents these
characters to an Output Register. The received serial data can
also be reclocked and retransmitted through the reclocker
serial outputs. Figure 1, "HOTLink II™ System Connections,"
on page 2 illustrates typical connections between independent
video coprocessors and corresponding CYV15G0404RB
Reclocking Deserializer and CYV15G0403TB Serializer chips.
The CYV15G0404RB is SMPTE-259M and SMPTE-292M
compliant according to SMPTE EG34-1999 Pathological Test
Requirements.
As a second generation HOTLink device, the
CYV15G0404RB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices.
Each channel of the CYV15G0404RB Quad HOTLink II device
accepts a serial bit-stream from one of two selectable
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. The
device reclocks and retransmits recovered bit-stream through
the reclocker serial outputs. It also deserializes the recovered
serial data and presents it to the destination host system.
Each channel contains an independent BIST pattern checker.
This BIST hardware enables at speed testing of the
high-speed serial data paths in each receive section of this
device, each transmit section of a connected HOTLink II
device, and across the interconnecting links.
The CYV15G0404RB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include
multi-format routers, switchers, format converters, SDI
monitors, and camera control units.
Cypress Semiconductor Corporation•198 Champion Court•San Jose, CA 95134-1709•408-943-2600
Document #: 38-02102 Rev. *C Revised February 16, 2007
Pin Definitions
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
NameIO CharacteristicsSignal Description
Receive Path Data and Status Signals
RXDA[9:0]
RXDB[9:0]
RXDC[9:0]
RXDD[9:0]
BISTSTA
BISTSTB
BISTSTC
BISTSTD
REPDOA
REPDOB
REPDOC
REPDOD
Receive Path Clock Signals
TRGCLKA±
TRGCLKB±
TRGCLKC±
TRGCLKD±
RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±
RECLKOA
RECLKOB
RECLKOC
RECLKOD
Device Control Signals
RESET
LVTTL Output,
synchronous to the
RXCLK± output
LVTTL Output,
synchronous to the
RXCLKx± output
Asynchronous to
reclocker output
channel
enable / disable
Differential LVPECL or
single-ended
LVTTL input clock
LVTTL Output Clock Receive Clock Output. RXCLKx± is the receive interface clock that controls
LVTTL OutputReclocker Clock Output
LVTTL Input,
asynchronous,
internal pull up
Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the
receive interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs
are complementary clocks operating at the character rate. The RXDx[9:0] outputs
for the associated receive channels follow the rising edge of RXCLKx+ or the
falling edge of RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock
outputs are complementary clocks operating at half the character rate. The
RXDx[9:0] outputs for the associated receive channels follow both the falling and
rising edges of the associated RXCLKx± clock outputs.
When BIST is enabled on the receive channel, the RXDx[1:0] and BISTSTx
outputs present the BIST status. See Table 5, “Receive BIST Status Bits,” on
page 17 for each status that the BIST state machine reports. Also, while BIST is
enabled, ignore the RXDx[9:2] outputs.
BIST Status Outp ut. When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])
displays the status of the BIST reception. See T able 5, “Receive BIST S tat us Bits,”
on page 17 for the BIST status for each combination of BISTSTx and RXDx[1:0].
When RXBISTx[1:0] ≠ 10, ignore BISTSTx.
Reclocker Powered Down Status Output. REPDOx asserts HIGH when the
associated channel’s reclocker output logic powers down. This occurs when
disabling ROE2x and ROE1x by setting ROE2x = 0 and ROE1x = 0.
CDR PLL Training Clock. The frequency detector (Range Controller) of the
associated receive PLL uses the TRGCLKx± clock inputs as the reference source
to reduce PLL acquisition time.
In the presence of valid serial data, the recovered clock output of the receive CDR
PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.
When a single-ended LVCMOS or LVTTL clock source drives the clock, connect
the clock source to either the true or complement TRGCLKx input, and leave the
alternate TRGCLKx input open (floating). When an LVPECL clock source drives
it, the clock must be a differential clock, using both inputs.
timing of the RXDx[9:0] parallel outputs. These true and complement clocks
control timing of data output transfers. These clocks output continuously at either
the half-character rate (1/20 the serial bit-rate) or character rate (1/1 0 the serial
bit-rate) of the data being received, as selected by RXRATEx.
. The associated reclocker output PLL synthesizes the
RECLKOx output clock, which operates synchronous to the internal recovered
character clock. RECLKOx operates at either the same frequency as RXCLKx±
(RXRATEx = 0), or at twice the frequency of RXCLKx± (RXRATEx = 1). The
reclocker clock outputs have no fixed phase relationship to RXCLKx±.
Asynchronous Device Reset. RESET initializes all state machines, counters,
and configuration latches in the device to a known state. RESET
for a minimum pulse width. When the reset is removed, all state machines,
counters and configuration latches are at an initial state. According to the JTAG
specifications, the device RESET
JTAG controller has to be reset separately. Refer to “JTAG Support” on page 17
for the methods to reset the JTAG state machine. See Table 3, “Device Configu-
ration and Control Latch Descriptions,” on page 14 for the in itialize values of the
device configuration latches.
CYV15G0404RB
must assert LOW
cannot reset the JTAG controller . Therefore, the
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CYV15G0404RB
Pin Definitions (continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
NameIO CharacteristicsSignal Description
LDTDENLVTTL Input,
internal pull up
ULCA
ULCB
LVTTL Input,
internal pull up
ULCC
ULCD
[2]
SPDSELA
SPDSELB
3-Level Select
static control input
SPDSELC
SPDSELD
INSELA
INSELB
LVTTL Input,
asynchronous
INSELC
INSELD
LFIA
LFIB
LVTTL Output,
asynchronous
LFIC
LFID
Device Configuration and Control Bus Signals
WREN
LV TTL input,
asynchronous,
internal pull up
ADDR[3:0]LVTTL input
asynchronous,
internal pull up
Notes
2. Use 3-Level Select inputs for static configuration. These are ternary input s th at use logic le vels of L OW, MID, and HIGH. To implement the LOW level, connect
directly to V
which allows it to self bias to the proper level.
3. See “Device Configuration and Control Interface” on page13 for detailed information about the operation of the Configuration Interface.
(ground). To implement the HIGH level, connect directly to VCC (power). To implement the MID level, do not connect the input (leave floating),
SS
Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal
Level Detector, Range Controller, and Transition Density Detector are all enabled
to determine if the RXPLL tracks TRGCLKx± or the selected input serial data
stream. If the Signal Level Detector, Range Controller, or Transition Density
Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks
to TRGCLKx± until they become valid. The SDASEL[A..D][1:0] inputs configure
the trip level of the Signal Level Detector. The Transition Density Detector limit is
one transition in every 60 consecutive bits. When LDTDEN is LOW, only the
Range Controller determines if the RXPLL tracks TRGCLKx± or the selected input
serial data stream. Set LDTDEN = HIGH.
Use Local Clock. When ULCx is LOW, the RXPLL locks to TRGCLKx± instead
of the received serial data stream. While ULCx
is LOW, the LFIx for the associ ated
channel is LOW, indicating a link fault.
When ULCx
is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications that need a stable
RXCLKx±. When valid data transitions are absent for a long time, or the high-gain
differential serial inputs (INx±) are left floating, the RXCLKx± outputs may briefly
be different from TRGCLKx±.
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate
range of each channel’s receive PLL.
Receive Input Selector. The INSELx input determines which external serial bit
stream passes to the receiver’s Clock and Data Recovery circuit. When INSELx
is HIGH, the Primary Differential Serial Data Input, INx1±, is the associated receive
channel. When INSELx is LOW, the Secondary Differential Serial Data Input,
INx2±, is the associated receive channel.
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
logical OR of six internal conditions. LFIx
asserts LOW when any of the following
conditions is true:
• Received serial data rate is outside expected range
• Analog amplitude is below expected levels
• Transition density is lower than expected
• Receive is channel disabled
is LOW
•ULCx
• TRGCLKx± is absent.
Control Write Enable. The WREN input writes the values of the DATA[7:0] bus
into the latch specified by the address location on the ADDR[3:0] bus.
[3]
Control Addressing Bus. The ADDR[3:0] bus is the input address bus that
configures the device. The WREN
into the latch specified by the address location on the ADDR[3:0] bus.
input writes the values of the DATA[7:0] bus
[3]
Table 3,
“Device Configuration and Control Latch Descriptions,” on page 14 lists the config-
uration latches within the device, and the initiali zation value of the latches when
RESET
is asserted. Table 4, “Device Control Latch Configuration Table,” on
page 16 shows how the latches are mapped in the device.
Document #: 38-02102 Rev. *CPage 9 of 27
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Pin Definitions (continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Differential InputPrimary Differential Serial Data Input. The INx1± input accepts the serial data
INB1±
INC1±
IND1±
INA2±
Differential InputSecondary Differential Serial Data Input. The INx2± input accepts the serial
INB2±
INC2±
IND2±
JTAG Interface
TMSLVTTL Input,
internal pull up
TCLKLVTTL Input,
internal pull down
Note
4. See Device Configuration and Control Interface for detailed information on the internal latches.
Control Data Bus. The DATA[7:0] bus is the input data bus that configures the
device. The WREN
input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.
ration and Control Latch Descriptions,” on page 14 lists the configuration latches
within the device, and the initialization value of the latches when RESET is
asserted. Table 4, “Device Control Latch Configuration T able,” on page 16 shows
the way the latches are mapped in the device.
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Receive Channel Power Control.
Receive BIST Disabled.
Reclocker Differential Serial Output Driver 2 Enable.
Reclocker Differential Serial Output Driver 1 Enable.
Global Latch Enable.
Force Global Latch Enable.
Factory Test 2. The SCANEN2 input is for factory testing only. Leave this input
as a NO CONNECT, or GND only.
Factory Test 3. The TMEN3 input is for factory testing only . Leave this input as a
NO CONNECT, or GND only.
Primary Differential Serial Data Output. The ROUTx1± PECL-compatible CML
outputs (+3.3V referenced) can drive terminated transmission lines or standard
fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
Secondary Differential Serial Data Output. The ROUTx2± PECL-compatible
CML outputs (+3.3V referenced) are capable of driving terminated transmi ssion
lines or standard fiber-optic transmitter modules, and must be AC coupled for
PECL-compatible connections.
stream for deserialization. The INx1± serial stream passes to the receive CDR
circuit to extract the data content when INSELx = HIGH.
data stream for deserialization. The INx2± serial stream passes to the receiver
CDR circuit to extract the data content when INSELx = LOW.
Test Mode Select. Controls access to the JTAG Test Modes. If TMS is HIGH for
5 TCLK cycles, the JTAG test controller resets.
>
JTAG Test Clock.
CYV15G0404RB
[3]
Table 3, “Device Configu-
Document #: 38-02102 Rev. *CPage 10 of 27
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CYV15G0404RB
Pin Definitions (continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
NameIO CharacteristicsSignal Description
TDO3-State LVTTL OutputTest Data Out. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
TDILVTTL Input,
internal pull up
TRST
Power
V
CC
GNDSignal and Power Ground for all internal circuits.
LVTTL Input,
internal pull up
Test Data In. JTAG data input port.
JTAG reset signal. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
+3.3V Power.
CYV15G0404RB HOTLink II Operation
The CYV15G0404RB is a highly configurable, independent
clocking, quad-channel reclocking deserializer that supports
reliable transfer of large quantities of digital video data, using
high-speed serial links from multiple sources to multiple destinations. This device supports four 10-bit channels.
CYV15G0404RB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INx1± and INx2±, are
available on each channel to accept serial data streams. The
associated INSELx input selects the active Serial Line
Receiver on a channel. The Serial Line Receiver inputs are
differential, and can accommodate wire interconnect and
filtering losses or transmission line attenuation greater than
16 dB. For normal operation, these inputs must receive a
signal of at least VI
differential. Each Line Receiver can be DC or AC coupled to
+3.3V powered fiber-optic interface modules (any ECL/PECL
family, not limited to 100K PECL) or AC coupled to +5V
powered optical modules. The common mode tolerance of
these line receivers accommodates a wide range of signal
termination voltages. Each receiver provides internal DC
restoration, to the center of the receiver’s common mode
range, for AC coupled signals.
Signal Detect/Link Fault
Each selected Line Receiver (that is, that routed to the clock
and data recovery PLL) is simultaneously monitored for
• Analog amplitude above amplitude level selected by
SDASELx
• Transition density above the specified limit
• Range controls reporting the received data stream inside
normal frequency range (±1500 ppm
• Receive channel enabled
• Reference clock present
not asserted.
•ULCx
> 100 mV, or 200 mV peak-to-peak
DIFF
[21]
)
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx
receive channel, which changes synchronous to the receive
interface clock.
Analog Amplitude
While most signal monitors are based on fixe d co nstants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high noise
environments. The SDASELx latch sets the analog amplitude
level detection via the device configuration interface. The
SDASELx latch sets the trip point for the detection of a valid
signal at one of three levels, as listed in Table 1. This control
input affects the analog monitors for all receive channels. The
Analog Signal Detect monitors are active for the Line Receiver,
as selected by the associated INSELx input.
Table 1. Analog Amplitude Detect Valid Signal Levels
SDASEL Typical Signal with Peak Amplitudes Above
Transition Density
The Transition Detection logic checks for the absence of
transitions spanning greater than six transmission characters
(60 bits). If there are no transitions in the data received, the
Detection logic for that channel asserts LFIx
Range Controls
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) samples the
incoming data stream. This logic ensures that the VCO
(Link Fault Indicator) output associated with each
[5]
00Analog Signal Detector is disabled
01140 mV p-p differential
10280 mV p-p differential
11420 mV p-p differential
.
Note
5. The peak amplitudes listed in this table are for typical waveforms that generally have 3–4 transitions for every ten bit s. In a worst case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0 101...). Signal peak amplitudes l evels within this environment type could increase
the values in the table above by approximately 100 mV.
Document #: 38-02102 Rev. *CPage 11 of 27
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CYV15G0404RB
operates at, or near the rate of the incoming data stream for
two primary cases:
• When the incoming data stream resumes after a time in
which it was “missing.”
• When the incoming data stream is outside the acceptable
signaling rate range.
T o perform this function, periodically compare the frequency of
the RXPLL VCO to the frequency of the TRGCLKx± input. If
the VCO is running at a frequency beyond ±1500 ppm
defined by the TRGCLKx± frequency, it is periodically forced
to the correct frequency (as defined by TRGCLKx±, SPDSELx,
and TRGRATEx) and then released in an attempt to lock to the
input data stream.
Calculate the sampling and relock period of the Range Control
as follows: RANGE_CONTROL_SAMPLING_PERIOD =
(RECOVERED BYTE CLOCK PERIOD) * (4096).
During the time that the Range Control forces the RXPLL VCO
to track TRGCLKx±, the LFIx
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx
Table 2 lists the operating serial signaling rate and allowable
range of TRGCLK± frequencies.
Table 2. Operating Speed Settings
SPDSELxTRGRATEx
LOW
MID (Open)120–40400–800
HIGH140–75800–1500
Receive Channel Enabled
The CYV15G0404RB contains four receive channels that it
can independently enable and disable. Each channel are
enabled or disabled separately through the RXPLLPDx input
latch as controlled by the device configuration interface.
RXPLLPDx latch = 0 disables the associated PLL and analog
circuitry of the channel. Any disabled channel indicates a
constant link fault condition on the LFIx output. RXPLLPDx =
1 enables the associated PLL and receive channel to receive
a serial stream.
Note When a disabled receive channel is reenabled, the
status of the associated LFIx
outputs for the associated channel may be indetermin ate for
up to 2 ms.
Clock/Data Recovery
A separate CDR block within each receive channel performs
the extraction of a bit rate clock and recovery of bits from each
received serial stream. An integrated PLL that tracks the
frequency of the transitions in the incoming bit stream and
aligns the phase of the internal bit rate clock to the transitions
1Reserved195–400
019.5–40
040–80
080–150
output is asserted LOW. After a
is HIGH.
TRGCLKx±
Frequency
(MHz)
output and data on the parallel
Rate (Mbps)
[21]
Signaling
as
in the selected serial data stream performs the clock extraction
function.
Each CDR accepts a character-rate (bit-rate ÷ 10) or
half-character-rate (bit-rate ÷ 20) training clock from the
associated TRGCLKx± input. This TRGCLKx± input is used to
• Ensure that the VCO (within the CDR) is operating at the
correct frequency (rather than a harmonic of the bit rate)
• Reduce PLL acquisition time
• Limit unlocked frequency excursions of the CDR VCO when
there is no input data present at the selected Serial Line
Receiver.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the signaling rate of the
recovered data stream is outside the limits set by the range
control monitors, the CDR tracks TRGCLKx± instead of the
data stream. Once the CDR output (RXCLK±) frequency
returns close to TRGCLKx± frequency, the CDR input
switches back to the input data stream. If no data is present at
the selected line receiver, this switching behavior may cause
brief RXCLK± frequency excursions from TRGCLKx±.
However, the LFIx
stream. The frequency of TRGCLKx± must be within ±1500
[21]
ppm
of the frequency of the clock that drives the reference
clock input of the remote transmitter, to ensure a lock to the
incoming data stream. This large ppm tolerance allows the
CDR PLL to reliably receive a 1.485 or 1.485/1.001 Gbps
SMPTE HD-SDI data stream with a constant TRGCLK
frequency.
For systems using multiple or redundant connections, use the
LFIx output to select an alternate data stream. When the
device detects an LFIx
selection of the associated INx1± and INx2± input through the
associated INSELx input. When a port switch takes place, the
receive PLL for that channel reacquires the new serial stream.
Reclocker
Each receive channel performs a reclocker function on the
incoming serial data. To do this, the Clock and Data Recovery
PLL first recovers the clock from the data. The recovered clock
retimes the data and then passes it to an output register. It also
passes the recovered character clock from the receive PLL to
the reclocker output PLL, which generates the bit clock that
clocks the retimed data into the output register. This data
stream is then transmitted through the differential serial
outputs.
Reclocker Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50Ω transmission lines. These drivers accept data from the
reclocker output register in the reclocker channel. These
drivers have signal swings equivalent to that of standard PECL
drivers, and can drive AC coupled optical modules or transmission lines.
Reclocker Output Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled using the configu ration interface, it
internally powers down to reduce device power. If both
output indicates the validity of the input data
indication, external logic toggles
Document #: 38-02102 Rev. *CPage 12 of 27
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CYV15G0404RB
reclocker serial drivers for a channel are in this disabled state,
the associated internal reclocker logic also powers down. The
deserialization logic and parallel outputs remain enabled. A
device reset (RESET sampled LOW) disables all output
drivers.
Note When the disabled reclocker function (that is, both
outputs disabled) is reenabled, the data on the reclocker serial
outputs may not meet all timing specifications for up to 250 µs.
Output Bus
Each receive channel presents a 10-bit data signal (and a
BIST status signal when RXBISTx[1:0] = 10).
Receive BIST Operation
Each receiver channel contains an internal pattern checker
that is used to validate both device and link operation. These
pattern checkers are enabled by the associated RXBISTx[1:0]
latch through the device configuration interface. When
enabled, a register in the associated receive channel becomes
a signature pattern generator and checker by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence. This provides a
predictable, yet pseudorandom, sequence that can be
matched to an identical LFSR in the attached Transmitter(s).
When synchronized with the received data stream, the
associated Receiver checks each character from the deserializer with each character generated by the LFSR and
indicates compare errors and BIST status at the RXDx[1:0]
and BISTSTx bits of the Output Register.
The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates
010b or 100b for one character period per BIST loop to
indicate loop completion. Use this status to check test pattern
progress.
Table 5, “Receive BIST Status Bits,” on page 17 lists the
specific status reported by the BIST state machine. The
receive status outputs report these same codes.
If the number of invalid characters received exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR
to look for the start of the BIST sequence again.
A device reset (RESET
Enable Latches to disable BIST on all channels.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the {BISTSTx,
RXDx[0], RXDx[1]} bits identify the present state of the BIST
compare operation.
The BIST state machine has multiple states, as shown in
Figure 2, "Receive BIST State Machine," on page 18 and
Table 5, “Receive BIST Status Bits,” on page 17. When the
receive PLL detects an out-of-lock condition, it forces the BIST
state to the St art-of-BIST state, regardless of the present state
of the BIST state machine. If the number of detected errors
ever exceeds the number of valid matches by greater than 16,
the state machine is forced to the WAIT_FOR_BIST state,
where it monitors the receive path for the first character of the
next BIST sequence.
sampled LOW) presets the BIST
Power Control
The CYV15G0404RB supports user control of the powered up
or down state of each transmit and receive channel. The
RXPLLPDx latch controls the receive channels through the
device configuration interface. RXPLLPDx = 0 disables the
associated PLL and analog circuitry of the channel. The OE1x
and the OE2x latches control the transmit channels via the
device configuration interface. The ROE1x and the ROE2x
latches control the reclocker function through the device
configuration interface. When the configuration interface
disables a driver, the driver internally powers down to reduce
device power. If both serial drivers for a channel are in this
disabled state, the associated internal logic for that channel
also powers down. The reclocker serial drivers being disabled
in turn disables the reclocker function, but the deserialization
logic and parallel outputs remain enabled.
Device Reset State
Assertion of RESET
configuration latches in the device to a reset state.
Additionally, the JTAG controller must be reset for valid
operation (even if not performing JTAG testing). See “JTAG
Support” on page 17 for JTAG st ate machine initialization. See
Table 3, “Device Configuration and Control Latch Descriptions,” on page 14 for the initi alize values of th e configuration
latches.
Following a device reset, enable the receive channels used for
normal operation. Do this by sequencing the appropriate
values on the device configuration interface.
resets all state machines, counters, and
[3]
Device Configuration and Control Interface
Configure the CYV15G0404RB through the configuration
interface. The configuration interface enables the device to be
configured globally or enables each channel to be configured
independently. Table 3, “Device Configuration and Control
Latch Descriptions,” on p age 14 lists the configuration latches
within the device, including the initialization value of the
latches on the assertion of RESET
Latch Configuration T able,” on page 16 shows how the latches
are mapped in the device. Each row in Table 4 maps to an 8-bit
latch bank. There are 16 such write only latch banks. When
= 0, the logic value in the DAT A[7:0] latches to the latch
WREN
bank specified by the values in ADDR[3:0]. The second
column of Table 4 specifies the channels associated with the
corresponding latch bank. For example, the first three latch
banks (0, 1, and 2) consist of configuration bits for channel A.
Latch banks 12, 13, and 14 consist of Global configuration bits,
and the last latch bank (15) is the Mask latch bank, which can
be configured to perform bit-by-bit configuration.
Global Enable Function
The global enable function, controlled by the GLENx bits, is a
feature that can reduce the number of write operations needed
to set up the latch banks. This function is beneficial in systems
that use a common configuration in multiple channels. The
GLENx bit is present in bit 0 of latch banks 0 through 11 only.
Its default value (1) enables the global update of the latch
bank's contents. Setting the GLENx bit to 0 disables this
functionality.
. Table 4, “Device Control
Document #: 38-02102 Rev. *CPage 13 of 27
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CYV15G0404RB
Latch Banks 12, 13, and 14 load values in the related latch
banks in globally. A write operation to latch bank 12 performs
a global write to latch banks 0, 3, 6, and 9, depending on the
value of GLENx in these latch banks; latch bank 13 performs
a global write to latch banks 1, 4, 7, and 10; and latch bank 14
performs a global write to latch banks 2, 5, 8, and 11. The
GLENx bit cannot be modified by a global write operation.
Force Global Enable Function
FGLENx forces the global update of the target latch banks, but
does not change the contents of the GLENx bits. If FGLENx =
1 for the associated global channel, FGLENx forces the global
update of the target latch banks.
Mask Function
An additional latch bank (15) is a global mask vector that
controls the update of the configuration latch banks on a
bit-by-bit basis. A logic 1 in a bit location enables the update
of that same location of the target latch bank(s), whereas a
logic 0 disables it. The reset value of this latch bank is FFh,
thereby making its use optional by default. Th e mask latch
bank is not maskable. The bit 0 value of the mask latch bank
does not affect the FGLEN functionality.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by two static and one dynamic
Table 3. Device Configuration and Control Latch Descriptions
Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRA TEx selects the rate
of the RXCLKx± clock output.
When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered
clock operating at half the character rate. Data for the associated receive channels must latch alternately
on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0, the RXCLKx± clock outputs are complementary clocks that follow the recovered
clock operating at the character rate. Data for the associated receive channels must latch on the rising
edge of RXCLKx+ or falling edge of RXCLKx–.
Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the
SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the
INx1± Primary Differential Serial Data Inputs.
When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the
SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the
INx2± Secondary Differential Serial Data Inputs.
When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled
When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
Traini ng Clock Rate Select. The initialization value of the TRGRA TEx latch = 0. TRGRATEx selects the
clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx = 0, the
associated TRGCLKx± input is not multiplied before it is passed to the CDR PLL. When TRGRATEx = 1,
the TRGCLKx± input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and SPDSELx
= LOW is an invalid state and this combination is reserved.
latch banks. The S type contains those settings that normally
do not change for a given application, whereas the D type
controls the settings that might change during the application's
lifetime. The first and second rows of each channel (address
numbers 0, 1, 3, 4, 6, 7, 9, and 10) are the static control
latches. The third row of latches for each channel (address
numbers 2, 5, 8, and 11) are the dynamic control latches that
are associated with enabling dynamic functions within the
device.
Latch Bank 14 is also useful for those users that do not need
the latch based programmable feature of the device. This latch
bank is used in those applications that do not need to modify
the default value of the static latch banks, and that can afford
global (that is, not independent) control of the dynamic signals.
In this case, this feature becomes available when ADDR[3:0]
is unchanged with a value of “1110” and WREN
The signals present in DATA[7:0] effectively become global
control pins, and for the latch banks 2, 5, 8, and 11.
Static Latch Values
There are some latches in the table that have a static value
(that is, 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be
configured with their corresponding value each time that their
associated latch bank is configured. The latches that have an
‘X’ are don’t cares and can be configured with any value
is asserted.
Document #: 38-02102 Rev. *CPage 14 of 27
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CYV15G0404RB
Table 3. Device Configuration and Control Latch Descriptions (continued)
GLEN[11..0]Global Enable. The initialization value of the GLENx latch = 1. The GLENx reconfigures several channels
FGLEN[2..0]Force Glob al Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a
Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects whether
the associated receive channel is enabled or powered down. RXPLLPDx = 0 powers down the associated
receive PLL and analog circuitry. RXPLLPDx = 1 enables the associated receive PLL and analog circuitry.
Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTx[1:0] latch = 11.
For SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (1 1). RXBISTx[1:0]
selects whether receive BIST is disabled or enabled and sets the associated channel for SMPTE data
reception. RXBISTx[1:0] = 01 disables the receiver BIST function and sets the associated channel to
receive SMPTE data. RXBISTx[1:0] = 10 enables the receive BIST function and sets the associated
channel to receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are invalid states.
Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the
ROE2x latch = 0. ROE2x selects whether the ROUT2± secondary differential output drivers are enabled
or disabled. ROE2x = 1 enables the associated serial data output driver, allowing data to be transmitted
from the transmit shifter. ROE2x = 0 disables the associated serial data output driver. When the configuration interface disables a driver, the driver internally powers down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated internal logic for that channel also powers
down. A device reset (RESET sampled LOW) disables all output drivers.
Reclocker Primary Differential Serial Data Output Driver Enable. The initialization value of the ROE1x
latch = 0. ROE1x selects whether the ROUT1± primary differential output drivers are enabled or disabled.
ROE1x = 1 enables the associated serial data output driver, allowing data to be transmitted from the
transmit shifter. ROE1x = 0 disables the associated serial data output driver. When the configuration
interface disables a driver, the driver internally powers down to reduce device power. If both serial drivers
for a channel are in this disabled state, the associated internal logic for that channel also powers down.
A device reset (RESET sampled LOW) disables all output drivers.
simultaneously in applications where several channels may have the same configuration. When GLENx
= 1 for a given address, that address can participate in a global configuration. When GLENx = 0 for a
given address, that address cannot participate in a global configuration.
GLobal ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global
channel, FGLEN forces the global update of the target latch banks.
Device Configuration Strategy
Follow these steps to load the configuration latches on each
channel:
1. Pulse RESET
resets all four channels. Initialize the JTAG state machine
to its reset state, as detailed in “JT AG Support” on page 17.
2. Set the static latch banks for the target channel. You can
perform this step using a global operation, if the application
Document #: 38-02102 Rev. *CPage 15 of 27
Low after device power up. This operation
permits it. [This is an optional step if the default settings
match the desired configuration.]
3. Set the dynamic bank of latches for the target channel.
Enable the Receive PLLs and set each channel for SMPTE
data reception (RXBISTx[1:0] = 01) or BIST data reception
(RXBISTx[1:0] = 10). You can perform this step using a
global operation, if the application permits it. [Required
step.]
GLOBAL DRXBISTGL[1]RXPLLPDGLRXBISTGL[0]XROE2GLROE1GLXFGLEN2N/A
MASKDD7D6D5D4D3D2D1D011111111
Reset
Value
Document #: 38-02102 Rev. *CPage 16 of 27
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CYV15G0404RB
JTAG Support
The CYV15G0404RB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the avai lable JTAG
modes, boundary scan and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the TRGCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
To ensure valid device operation after power-up (including
non-JTAG operation), the JTAG state machine must also be
initialized to a reset state. This must be done in addition to the
device reset (using RESET
using TRST
asserted), or by asserting TMS HIGH for at least 5 consecutive
TCLK cycles. This is necessary in order to ensure that the
Table 5. Receive BIST Status Bits
{BISTSTx, RXDx[0],
(assert it LOW and deassert it or leave it
RXDx[1]}
000, 001BIST Data Compare. Character compared correctly.
010BIST Last Go od. Last Character of BIST sequence detected and valid.
01 1Reserved.
100BIST Last Bad. Last Character of BIST sequence detected invalid.
101BIST Start. Receive BIST is enabled on this channel, but character compares have not yet
110BIST Error. While comparing characters, a mismatch was found in one or more of the character bits.
111BIST Wait. The receiver is comparing characters, but has not yet found the start of BIST character to
). Initialize the JTAG st ate machine
commenced. This also indicates a PLL Out of Lock condition.
enable the LFSR.
JTAG controller does not enter any of the test modes after
device power-up. In this JTAG reset state, the rest of the
device will operate normally.
Note The order of device reset (using RESET
initialization does not matter.
3-Level Select Inputs
Each 3-Level select input reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0404RB is ‘0C811069’x.
Description
Receive BIST Status
(Receive BIST = Enabled)
) and JTAG
Document #: 38-02102 Rev. *CPage 17 of 27
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Figure 2. Receive BIST State Machine
CYV15G0404RB
{BISTSTx, RXDx[0], RXDx[1]} =
BIST_WAIT (111)
No
Yes, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_DATA_COMPARE (000, 001)
Mismatch
Start of
BIST Detected
Compare
Next Character
Monitor Data
Received
{BISTSTx, RXDx[0],
RXDx[1]} =
BIST_START (101)
Receive BIST
Detected LOW
RX PLL
Out of Lock
Yes
Yes, {BISTSTx, RXDx[0], RXDx[1]} =
Auto-Abort
Condition
No
End-of-BIST
State
BIST_LAST_BAD (100)
No, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_ERROR (110)
Match
End-of-BIST
State
Yes, {BISTSTx, RXDx[0], RXDx[1]} =
BIST_LAST_GOOD (010)
{BISTSTx, RXDx[0], RXDx[1]} =
BIST_DATA_COMPARE (000, 001)
No
Document #: 38-02102 Rev. *CPage 18 of 27
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CYV15G0404RB
Maximum Ratings
Static Discharge Voltage..........................................> 2000 V
(MIL-STD-883, Method 3015)
Excedding maximum ratings may shorten the device life. User
guidelines are not tested
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +3.8V
DC Voltage Applied to LVTTL Outputs
in High-Z State.......................................–0.5V to V
CC
+ 0.5V
Output Current into LVTTL Outputs (LOW)..................60 mA
DC Input Voltage....................................–0.5V to V
CC
+ 0.5V
Latch Up Current....................................................> 200 mA
Power Up Requirements
The CYV15G0404RB requires one power supply. The voltage
on any input or I/O pin cannot exceed the power pin during
power up.
6. Teste d one output at a time, output shorted for less than one second, less than 10% duty cycle.
7. This is the minimum difference in voltage between the true and complement inputs required t o ensure detection of a logic-1 or logic-0. A logi c-1 exists whe n the
true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.
8. The common mode range defines the allowable range of TRGCLKx+ and TRGCLKx− when TRGCLKx+ = TRGCLKx−. This marks the zero-crossing between
the true and complement inputs as the signal switches between a logic-1 and a logic-0.
Document #: 38-02102 Rev. *CPage 19 of 27
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CYV15G0404RB
CYV15G0404RB DC Electrical Characteristics (continued)
100Ω differential load450900mV
150Ω differential load5601000m V
CC
Max.1350µA
IHE
Min.–700µA
ILE
+1.25+3.1V
– 0.5V) max.
(V
CC
Commercial9101270mA
MAX
Industrial1320mA
Commercial9001270mA
125 MHz
Industrial1320mA
V
3.3V
R1
R1 = 590Ω
R2 = 435Ω
≤ 7 pF
C
L
(Includes fixture and
probe capacitance)
(a) LVTTL Output Test Load
Vth=1.4V
GND
≤ 1ns
2.0V
0.8V
(c) LVTTL Input Test Waveform
Notes
9. The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
10.Maximum I
outputs unloaded.
11. Typical I
channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel output s are unloaded.
12.Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
13.The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
is measured with VCC = MAX, TA = 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and
CC
is measured under similar conditions except with VCC = 3.3V, TA = 25°C, with all channels enabled and one Serial Line Driver for each transmit
CC
C
3.0V
L
2.0V
0.8V
R2
[12]
Vth=1.4V
≤ 1 ns
[13]
V
IHE
V
ILE
≤ 270 ps
20%
RL= 100Ω
(Includes fixture and
probe capacitance)
(b) CML Output Test Load
V
80%
V
(d) CML/LVPECL Input Test Waveform
IHE
ILE
R
80%
L
[12]
20%
≤ 270 ps
Document #: 38-02102 Rev. *CPage 20 of 27
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CYV15G0404RB
CYV15G0404RB AC Electrical Characteristics
ParameterDescriptionMinMaxUnit
CYV15G0404RB Receiver LVTTL Switching Characteristics Over the Operating Range
f
RS
t
RXCLKP
t
RXCLKD
RXCLKR
[14]
RXCLKF
[18]
RXDv–
[18]
RXDv+
ROS
RECLKO
RECLKOD
[14]
t
t
t
t
f
t
t
CYV15G0404RB TRGCLKx Switching Characteristics Over the Operating Range
f
TRG
TRGCLK
t
TRGH
t
TRGL
[20]
t
TRGD
[14, 15, 16, 17]
t
TRGR
[14, 15, 16, 17]
t
TRGF
[21]
t
TRGRX
CYV15G0404RB Bus Configuration Write Timing Characteristics Over th e Operating Range
t
DATAH
t
DATAS
t
WRENP
CYV15G0404RB JTAG Test Clock Characteristics Over the Operating Range
f
TCLK
t
TCLK
RXCLKx± Clock Output Frequency9.75150MHz
RXCLKx± Period = 1/f
RS
6.66102.56ns
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)–1.0+1.0ns
RXCLKx± Rise Time0.31.2ns
RXCLKx± Fall Time0.31.2ns
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)5UI–2.0
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)5UI–1.3
Status and Data Valid Time to RXCLKx± (RXRATEx = 0)5UI–1.8
Status and Data Valid Time to RXCLKx± (RXRATEx = 1)5UI–2.6
[19]
[19]
[19]
[19]
RECLKOx Clock Frequency19.5150MHz
RECLKOx Period = 1/f
ROS
6.6651.28ns
RECLKOx Duty Cycle centered at 60% HIGH time–1.90ns
TRGCLKx Clock Frequency19.5150MHz
TRGCLKx Period = 1/f
REF
6.651.28ns
TRGCLKx HIGH Time (TRGRATEx = 1)(Half Rate)5.9ns
TRGCLKx HIGH Time (TRGRATEx = 0)(Full Rate)2.9
[14]
TRGCLKx LOW Time (TRGRATEx = 1)(Half Rate)5.9ns
TRGCLKx LOW Time (TRGRATEx = 0)(Full Rate)2.9
[14]
TRGCLKx Duty Cycle3070%
TRGCLKx Rise Time (20%–80%)2ns
TRGCLKx Fall Time (20%–80%)2ns
TRGCLKx Frequency Referenced to Received Clock Frequency–0.15+0.15%
Bus Configuration Data Hold0ns
Bus Configuration Data Setup10ns
Bus Configuration WREN Pulse Width10ns
JTAG Test Clock Frequency20MHz
JTAG Test Clock Period50ns
ns
ns
ns
ns
ns
ns
Notes
14.Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
15.The ratio of rise time to falling time must not vary by greater than 2:1.
16.For a given operating frequency, neither rise nor fall specification can be greater than 20% of the clock cycle period or th e data sheet maximum time.
17.All transmit AC timing parameters measured with 1ns typical rise time and fall time.
18. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
19.Receiver UI (Unit Interval) is c a l c u l a t e d a s 1 / (f
20.The duty cycle specification is a simultaneous condition with the t
cycle cannot be as large as 30%–70%.
21.TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
TRGCLKx± must be within ±1500 PPM (±0.15%) of the tra nsmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.
* 20) (when TRGRATEx = 1) or 1/(f
TRG
REFH
and t
* 10) (when TRGRATEx = 0). In an operating link this is equivalent to tB.
TRG
parameters. This means that at faster character rates the TRGCLKx± duty
REFL
Document #: 38-02102 Rev. *CPage 21 of 27
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CYV15G0404RB
CYV15G0404RB AC Electrical Characteristics (continued)
ParameterDescriptionMinMaxUnit
CYV15G0404RB Device RESET Characteristics Over the Operating Range
t
RST
CYV15G0404RB Reclocker Serial Output Characteristics Over the Operating Range
ParameterDescriptionConditionMin.Max.Unit
t
B
[14]
t
RISE
[14]
t
FALL
PLL Characteristics
Device RESET Pulse Width30ns
Bit Time5128660ps
CML Output Rise Time 20−80% (CML Test Load)SPDSELx = HIGH50270ps
SPDSELx = MID100500ps
SPDSELx =LOW1801000ps
CML Output Fall Time 80−20% (CML Test Load)SPDSELx = HIGH5027 0ps
SPDSELx = MID100500ps
SPDSELx =LOW1801000ps
ParameterDescription ConditionMinTypMaxUnit
CYV15G0404RB Reclocker Output PLL Characteristics
t
JRGENSD
t
JRGENHD
[14, 22]
[14, 22]
Reclocker Jitter Generation - SD Data RateTRGCLKx = 27 MHz133ps
Reclocker Jitter Generation - HD Data RateTRGCLKx = 148.5 MHz107ps
CYV15G0404RB Receive PLL Characteristics Over the Operating Range
t
RXLOCK
Receive PLL Lock to Input Data Stream (cold start)376kUI
22.Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide bandwidth digit al sampling oscilloscope. The
measurement was recorded after 10,000 histogram hits , time referenced to REFCLKx± of the transmit channel.
Document #: 38-02102 Rev. *CPage 22 of 27
[+] Feedback
Switching Waveforms for the CYV15G0404RB HOTLink II Receiver
CYV15G0404RB
Receive Interface
Read Timing
RXRATEx = 0
RXCLKx+
RXCLKx–
RXDx[9:0]
Receive Interface
Read Timing
RXRATEx = 1
RXCLKx+
RXCLKx–
t
RXCLKP
t
RXDV
–
t
RXDV+
t
RXCLKP
t
RXDV
–
RXDx[9:0]
t
RXDV+
CYV15G0404RB HOTLink II Bus Configuration Switching Waveforms
Bus Configuration
Write Timing
ADDR[3:0]
DATA[7:0]
t
WRENP
t
WREN
DATAS
t
DATAH
Document #: 38-02102 Rev. *CPage 23 of 27
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CYV15G0404RB
Table 6. Package Coordinate Signal Allocation
Ball
Signal NameSignal Type
ID
A01INC1–CML INC07ULCC
A02ROUTC1–CML OUTC08GNDGROUNDF18RXDB[0]LVTTL OUT
A03INC2–CML INC09DATA[7]LVTTL IN PUF19RECLKOBLVTTL OUT
A04ROUTC2–CML OUTC10DATA[ 5]LVTTL IN PUF20RXDB[1]LVTTL OUT
A05VCCPOWERC11DATA[3]LVTTL IN PUG01GNDGROUND
A06IND1–CML INC12DATA[1]LVTTL IN PUG02WREN
A07ROUTD1–CML OUTC13GNDGROUNDG03GNDGROUND
A08GNDGROUNDC14VCCPOWERG04GNDGROUND
A09IND2–CML INC15SPDSELD3-LEVEL SELG17SPDSELB3-LEVEL SEL
A10ROUTD2–CML OUTC16VCCPOWERG18NCNO CONNECT
A1 1INA1–CML INC17LDTDENLVTTL IN PUG19SPDSELA3-LEVEL SEL
A12ROUTA1–CML OUTC18TRST
A13GNDGROUNDC19GNDGROUNDH01GNDGROUND
A14INA2–CML INC20TDOLVTTL 3-S OUTH02GNDGROUND
A15ROUTA2–CML OUTD01TCLKLVTTL IN PDH03GNDGROUND
A16VCCPOWERD02RESET
A17INB1–CML IND03INSELDLVTTL INH17GNDGROUND
A18ROUTB1–CML OUTD04INSELALVTTL INH18GNDGROUND
A19INB2–CML IND05VCCPOWERH19GNDGROUND
A20ROUTB2–CML OUTD06ULCA
B01INC1+CML IND07SPDSELC3-LEVEL SELJ01GNDGROUND
B02ROUTC1+CML OUTD08GNDGROUNDJ02GNDGROUND
B03INC2+CML IND09DATA[6]LVTTL IN PUJ03GNDGROUND
B04ROUTC2+CML OUTD10DATA[4]LVTTL IN PUJ04GNDGROUND
B05VCCPOWERD11DATA[2]LVTTL IN PUJ17BISTSTBLVTTL OUT
B06IND1+CML IND12DATA[0]LVTTL IN PUJ18RXDB[2]LVTTL OUT
B07ROUTD1+CML OUTD13GNDGROUNDJ19RXDB[7]LVTTL OUT
B08GNDGROUNDD14GNDGROUNDJ20RXDB[4]LVTTL OUT
B09IND2+CML IND15ULCB
B10ROUTD2+CML OUTD16VCCPOWERK02TRGCLKC–PECL IN
B1 1INA1+CML IND17NCNO CONNECTK03GNDGROUND
B12ROUTA1+CML OUTD18VCCPOWERK04GNDGROUND
B13GNDGROUNDD19SCANEN2LVTTL IN PDK17RXDB[5]LVTTL OUT
B14INA2+CML IND20TMEN3L VTTL IN PDK18RXDB[6]L VTTL OUT
B15ROUTA2+CML OUTE01VCCPOWERK19RXDB[9]LVTTL OUT
B16VCCPOWERE02VCCPOWERK20LFIB
B17INB1+CML INE03VCCPOWERL01RXDC[5]LVTTL OUT
B18ROUTB1+CML OUTE04VCCPOWERL02TRGCLKC+PECL IN
B19INB2+CML INE17VCCPOWERL03LFIC
Ball
Signal NameSignal Type
ID
Ball
Signal NameSignal Type
ID
LVTTL IN PUF17VCCPOWER
LV TTL IN PU
LVTTL IN PUG20RXDB[3]LVTTL OUT
LVTTL IN PUH0 4GNDGROUND
LVTTL IN PUH2 0GNDGROUND
LVTTL IN PUK01RXDC[4]LVTTL OUT
LVTTL OUT
LVTTL OUT
Document #: 38-02102 Rev. *CPage 24 of 27
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CYV15G0404RB
Table 6. Package Coordinate Signal Allocation (continued)
Ball
Signal NameSignal Type
ID
B20ROUTB2+CML OUTE18VCCPOWERL04GNDGROUND
C01TDILVTTL IN PUE19VCCPOWERL17RXDB[8]LVTTL OUT
C02TMSLVTTL IN PUE20VCCPOWERL18RXCLKB+LVTTL OUT
C03IN S ELCLVTTL INF01RXDC[8]LVTTL OUTL19RXCLKB–LVTTL OUT
C04INSELBLVTTL INF02RXDC[9]LVTTL OUTL20GNDGROUND
C05VCCPOWERF03VCCPOWERM01RXDC[6]LVTTL OUT
C06ULCD
M03VCCPOWERU03VCCPOWERW03LFID
M04REPDOCL VTTL OUTU04VCCPOWERW04RXCLKD–LVTTL OUT
M17TRGCLKB+PECL INU05VCCPOWERW05VCCPOWER
M18TRGCLKB–PECL INU06RXDD[4]LVTTL OUTW06RXDD[6]LVTTL OUT
M19REPDOBLVTTL OUTU07RXDD[3]LVTTL OUTW07RXDD[0]LVTTL OUT
M20GNDGROUNDU08GNDGROUNDW08GNDGROUND
N01GNDGROUNDU09GNDGROUNDW09ADDR [3]LVTTL IN PU
N02GNDGROUNDU10ADDR [0]LVTTL IN PUW10ADDR [1]LVTTL IN PU
N03GNDGROUNDU11TRGCLKD–PECL INW11RXCLKA+LVTTL OUT
N04GNDGROUNDU12GNDGROUNDW12REPDOALVTTL OUT
N17GNDGROUNDU13GNDGROUNDW13GNDGROUND
N18GNDGROUNDU14GNDGROUNDW14GNDGROUND
N19GNDGROUNDU15VCCPOWERW15VCCPOWER
N20GNDGROUNDU16VCCPOWERW16VCCPOWER
P01RXDC[3]LVTTL OUTU17RXDA[4]LVTTL OUTW17LFIA
P02RXDC[2]LVTTL OUTU18VCCPOWERW18TRGCLKA+PECL IN
P03RXDC[1]LVTTL OUTU19BISTSTALVTTL OUTW19RXDA[6]LVTTL OUT
P04RXDC[0]LVTTL OUTU20RXDA[0]LVTTL OUTW20RXDA[3]LVTTL OUT
P17GNDGROUNDV01VCCPOWERY01VCCPOWER
P18GNDGROUNDV02VCCPOWERY02VCCPOWER
P19GNDGROUNDV03VCCPOWERY03RXDD[9]LVTTL OUT
P20GNDGROUNDV04RXDD[8]LVTTL OUTY04RXCLKD+LVTTL OUT
R01BISTSTCLVTTL OUTV05VCCPOWERY05VCCPOWER
R02RECLKOCLVTTL OUTV06RXDD[5]LVTTL OUTY06RXDD[7]LVTTL OUT
R03RXCLKC+LVTTL OUTV07RXDD[1]LVTTL OUTY07RXDD[2]LVTTL OUT
R04RXCLKC–LVTTL OUTV08GNDGROUNDY08GNDGROUND
R17VCCPOWERV09BISTSTDLVTTL OUTY09RECLKODLVTTL OUT
R18VCCPOWERV10ADDR [2]LVTTL IN PUY10NCNO CONNECT
R19VCCPOWERV11TRGCLKD+PECL INY11GNDGROUND
R20VCCPOWERV12RECLKOALVTTL OUTY12RXCLKA–LVTTL OUT
T01VCCPOWERV13GNDGROUNDY13GNDGROUND
T02VCCPOWERV14GNDGROUNDY14GNDGROUND
LVTTL IN PU F04VCCPOWERM02RXDC[7]LVTTL OUT
Ball
Signal NameSignal Type
ID
Ball
Signal NameSignal Type
ID
LVTTL OUT
LVTTL OUT
Document #: 38-02102 Rev. *CPage 25 of 27
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Table 6. Package Coordinate Signal Allocation (continued)
SECTIO
CYV15G0404RB
Ball
Signal NameSignal Type
ID
Ball
Signal NameSignal Type
ID
Ball
Signal NameSignal Type
ID
T03VCCPOWERV15VCCPOWERY15VCCPOWER
T04VCCPOWERV16VCCPOWERY16VCCPOWER
T17VCCPOWERV17RXDA[9]LVTTL OUTY17REPDODLVTTL OUT
T18VCCPOWERV18RXDA[5]LVTTL OUTY18TRGCLKA–PECL IN
T19VCCPOWERV19RXDA[2]LVTTL OUTY19RXDA[8]LVTTL OUT
T20VCCPOWERV20RXDA[1]LVTTL OUTY20RXDA[7]LVTTL OUT
U01VCCPOWERW01VCCPOWER
U02VCCPOWERW02VCCPOWER
Figure 3. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256
TOP VIEW
27.00±0.13
A1 CORNER I.D.
1.57±0.175
0.97 REF.
0.20(4X)
A
27.00±0.13
B
0.15 C
Ø0.15 M C
Ø0.30 M C
Ø0.75±0.15(256X)
BOTTOM VIEW (BALL SIDE)
BA
A
0.50 MIN.
20
18
19
17
24.13
16
14
12
10
15
13
11
R 2.5 Max (4X)
A
A1 CORNER I.D.
8
6
4
9
2
7
5
3
1
A
B
C
D
E
F
G
12.065
H
J
K
L
M
N
P
R
T
U
1.27
V
W
Y
24.13
0.60±0.10
C
26°
TYP.
SEATING PLANE
SIDE VIEW
0.15 C
0.20 MIN
TOP OF MOLD COMPOUND
TO TOP OF BALLS
N A-A
51-85123-*E
HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document may be the trademarks of their respective holders.
**246850See ECNFRENew Data Sheet
*A338721See ECNSUAAdded Pb-Free package option availability
*B384307See ECNAGTRevised setup and hold times (t
*C789283See ECNKKVTMPClarification to the need and procedure to initialize the JTAG controller
ISSUE
DATE
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
, t
RXDv–
(during test and non-test mode) to ensure valid device power-up. No
changes have been made to the device specifications or characterestics.
RXDv+
)
Document #: 38-02102 Rev. *CPage 27 of 27
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