Cypress CYV15G0404DXB User Manual

CYV15G0404DXB

Independent Clock Quad HOTLink II™

Transceiver with Reclocker

Features

Video Coprocessor

Serial Links

10

10

10

10

10

10

10

10

Video Coprocessor

10

10

10

10

10

10

10

10

Serial Links

Serial Links

Serial Links

Cable

Connections

Independent

CYV15G0404DXB

Independent

Reclocker

Reclocker

Channel

CYV15G0404DXB

Channel

■ Quad channel transceiver for 195 to 1500 MBaud serial

signaling rate

❐ Aggregate throughput of up to 12 Gbits/second

■ Second-generation HOTLink

■ Compliant to multiple standards
❐ SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ES-

CON, and Gigabit Ethernet (IEEE802.3z)

❐ 10 bit uncoded data or 8B/10B coded data

■ Truly independent channels
❐ Each channel is able to:

• Perform reclocker function

• Operate at a different signaling rate

• Transport a different data format

■ Internal phase-locked loops (PLLs) with no external PLL

components

■ Selectable differential PECL compatible serial inputs per

channel

❐ Internal DC restoration

■ Redundant differential PECL compatible serial outputs per

channel

❐ No external bias resistors required
❐ Signaling rate controlled edge rates
❐ Source matched for 50Ω transmission lines

■ MultiFrame™ Receive Framer provides alignment options
❐ Comma or full K28.5 detect
❐ Single or multibyte Framer for byte alignment

❐ Low latency option

■ Selectable input and output clocking options

®

technology

Figure 1. HOTLink II™ System Connections

■ Synchronous LVTTL parallel interface

■ JTAG boundary scan

■ Built In Self Test (BIST) for at-speed link testing

■ Link quality indicator by channel
❐ Analog signal detect
❐ Digital signal detect

■ Low power 3W at 3.3V typical

■ Single 3.3V supply

■ 256 ball thermally enhanced BGA

■ 0.25μ BiCMOS technology

■ JTAG device ID ‘0C811069’x

Functional Description

The CYV15G0404DXB Independent Clock Quad HOTLink II™
Transceiver is a point-to-point or point-to-multipoint communica­tions building block enabling the transfer of data over a variety of
high speed serial links including SMPTE 292, SMPTE 259, and
DVB-ASI video applications. The signaling rate can be anywhere
in the range of 195 to 1500 MBaud for each serial link. Each
channel operates independently with its own reference clock
allowing different rates. Each transmit channel accepts parallel
characters in an input register, encodes each character for
transport, and then converts it to serial data. Each receive
channel accepts serial data and converts it to parallel data,
decodes the data into characters, and presents these characters
to an output register. The received serial data can also be
reclocked and retransmitted through the serial outputs. Figure 1
illustrates typical connections between independent video
coprocessors and corresponding CYV15G0404DXB chips.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-02097 Rev. *B Revised December 14, 2007

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CYV15G0404DXB

The CYV15G0404DXB satisfies the SMPTE-259M and

CYV15G0404DXB T ransceiver Logic Block Diagram

x10

Serializer

Phase

Encoder

8B/10B

Decoder

8B/10B

x11

Framer

Deserializer

TX

RX

x10

Serializer

Encoder

8B/10B

Decoder

8B/10B

x11

Framer

Deserializer

TX

RX

x10

Serializer

Encoder

8B/10B

Decoder

8B/10B

x11

Framer

Deserializer

TX

RX

x10

Serializer

Encoder

8B/10B

Decoder

8B/10B

x11

Framer

Deserializer

TX

RX

TXDA[7:0]

RXDA[7:0]

TXDB[7:0]

RXDB[7:0]

TXDC[7:0]

RXDC[7:0]

TXDD[7:0]

RXDD[7:0]

OUTA1±

OUTA2±

INA1±

INA2±

OUTB1±

OUTB2±

INB1±

INB2±

OUTC1±

OUTC2±

INC1±

INC2±

OUTD1±

OUTD2±

IND1±

IND2±

Align

Buffer

Phase

Align

Buffer

Phase

Align

Buffer

Phase

Align

Buffer

Elasticity

Buffer

Elasticity

Buffer

Elasticity

Buffer

Elasticity

Buffer

TXCTA[1:0]

RXSTA[2:0]

TXCTB[1:0]

RXSTB[2:0]

TXCTC[1:0]

RXSTC[2:0]

TXCTD[1:0]

RXSTD[2:0]

REFCLKA±

REFCLKB±

REFCLKC±

REFCLKD±

SMPTE-292M compliance according to SMPTE EG34-1999
Pathological Test Requirements.

As a second generation HOTLink device, the CYV15G0404DXB
extends the HOTLink family with enhanced levels of integration and
faster data rates, while maintaining serial link compatibility (data,
command, and BIST) with other HOTLink devices. The transmit
(TX) section of the CYV15G0404DXB Quad HOTLink II consists of
four independent byte-wide channels. Each channel accepts
either 8-bit data characters or preencoded 10-bit transmission
characters. Data characters may be passed from the transmit
input register to an integrated 8B/10B Encoder to improve their
serial transmission characteristics. These encoded characters
are then serialized and output from dual Positive ECL (PECL)
compatible differential transmission-line drivers at a bit rate of
either 10 or 20 times the input reference clock for that channel.

The receive (RX) section of the CYV15G0404DXB Quad
HOTLink II consists of four independent byte wide channels.
Each channel accepts a serial bit stream from one of two
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. Each
recovered bit stream is deserialized and framed into characters,

8B/10B decoded, and checked for transmission errors.
Recovered decoded characters are then written to an internal
elasticity buffer, and presented to the destination host system.

The integrated 8B/10B encoder or decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface.

The parallel IO interface may be configured for numerous forms
of clocking to provide the highest flexibility in system archi­tecture. In addition to clocking the transmit path with a local
reference clock, the receive interface may also be configured to
present data relative to a recovered clock or to a local reference
clock.

Each transmit and receive channel contains an independent
BIST pattern generator and checker. This BIST hardware allows
at speed testing of the high speed serial data paths in each
transmit and receive section, and across the interconnecting
links.

The CYV15G0404DXB is ideal for port applications where
different data rates and serial interface standards are necessary
for each channel. Some applications include multi-format routers
and switchers.

Document #: 38-02097 Rev. *B Page 2 of 44

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CYV15G0404DXB

Shifter

TXLBA

TXLBC

Transmit Path Block Diagram

TXRATEA

Input

Register

Phase-Align

Buffer

Encoder

BIST LFSR

SPDSELA

REFCLKA+
REFCLKA–

Transmit PLL

Clock Multiplier

TXCLKA

Bit-Rate Clock

Character-Rate Clock A

OUTA1+
OUTA1–

OUTA2+
OUTA2–

8

TXRATEB

Input

Register

Phase-Align

Buffer

Encoder

BIST LFSR

Shifter

SPDSELB

REFCLKB+

REFCLKB–

Bit-Rate Clock

Character-Rate Clock B

OUTB1+
OUTB1–

OUTB2+
OUTB2–

Input

Register

Phase-Align

Buffer

8B/10B

BIST LFSR

Transmit PLL

Clock Multiplier A

Input

Register

Phase-Align

Buffer

8B/10B

BIST LFSR

Shifter

TXCLKB

TXRATEC

Input

Register

Phase-Align

Buffer

8B/10B

BIST LFSR

SPDSELC

REFCLKC+
REFCLKC–

TXCLKC

Bit-Rate Clock

Character-Rate Clock C

TXRATED

Input

Register

Phase-Align

Buffer

8B/10B

BIST LFSR

Shifter

SPDSELD

REFCLKD+

REFCLKD–

Transmit PLL

Clock Multiplier D

TXCLKD

Bit-Rate Clock

Character-Rate Clock D

OUTD1+
OUTD1–

OUTD2+
OUTD2–

OUTC1+
OUTC1–

OUTC2+
OUTC2–

TXCTA[1:0]

TXDD[7:0]

OEA[2..1]

TXBIST

ENCBYPA

TXCKSELA

= Internal Signal

TXERRA

TXERRB

TXERRD

TXERRC

TXCLKOA

TXCLKOB

TXCLKOC

TXCLKOD

TXDA[7:0]

2

TXDB[7:0]

8

2

TXCTB[1:0]

8

2

TXDC[7:0]

TXCTC[1:0]

8

2

TXCTD[1:0]

10

10

10

10

10 10 10 10

10

10

10 10

10 10

10

10

A

ENCBYPB

ENCBYPC

ENCBYPD

TXBIST

B

TXBIST

C

TXBISTD

OEB[2..1]

OEC[2..1]

OED[2..1]

PABRSTA

PABRSTB

PABRSTC

PABRSTD

OEA[2..1]

OEB[2..1]

OEC[2..1]

OED[2..1]

TXLBD

Shifter

TXLBB

Transmit PLL

Clock Multiplier B

Transmit PLL

Clock Multiplier C

10

TXCKSELB

0

TXCKSELC

10

TXCKSELD

10

RECLCK[A..D] are Internal Reclocker Signals

Encoder

Encoder

Encoder

Encoder

1

RECLCKA

RECLCKB

RECLCKC

RECLCKD

TXLB[A..D] are Internal Serial Loopback Signals

Document #: 38-02097 Rev. *B Page 3 of 44

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CYV15G0404DXB

INA1+
INA1–

INA2+
INA2–

INSELA

INB1+
INB1–

INB2+
INB2–

INSELB

INC1+
INC1–

INC2+
INC2–

INSELC

IND1+
IND1–

IND2+
IND2–

INSELD

Clock &

Data

Recovery

PLL

Shifter

Clock &

Data

Recovery

PLL

Shifter

Clock &

Data

Recovery

PLL

Shifter

Clock &

Data

Recovery

PLL

Shifter

LFID

LFIC

LFIB

LFIA

8

RXSTC[2:0]

RXDC[7:0]

3

8

RXSTB[2:0]

RXDB[7:0]

3

8

RXSTD[2:0]

RXDD[7:0]

3

8

RXSTA[2:0]

RXDA[7:0]

3

Receive

Signal

Monitor

Receive

Signal

Monitor

Receive

Signal

Monitor

Receive

Signal

Monitor

Output

Register

Output

Register

Output

Register

Output

Register

Elasticity

Buffer

Framer

RXCLKD+
RXCLKD–

10B/8B

BIST

Elasticity

Buffer

10B/8B

BIST

Framer

Elasticity

Buffer

10B/8B

BIST

Framer

Elasticity

Buffer

10B/8B

BIST

Framer

÷2

RXCLKC+
RXCLKC–

÷2

RXCLKB+
RXCLKB–

÷2

RXCLKA+
RXCLKA–

÷2

RXRATE[A..D]

FRAMCHAR[A..D]

RFEN[A..D]

JTAG

Boundary

Scan

Controller

TDO

TMS
TCLK
TDI

Clock

Select

Clock

Select

Clock

Select

Clock

Select

RXCKSEL[A..D]

RESET

Receive Path Block

= Internal Signal

RXPLLPDA

RFMODE[A..D][1:0]

LPENA

RXBIST[A..D]

DECMODE[A..D]

LPENB

LPENC

LPEND

TRST

RXPLLPDB

RXPLLPDC

RCLKEND

RXPLLPDD

DECBYP[A..D]

SPDSELA

SPDSELB

SPDSELC

SPDSELD

ULCB

ULCA

ULCC

ULCD

LDTDEN

TXLBD

TXLBC

TXLBB

TXLBA

RECLCK[A..D] are Internal Reclocker Signals

SDASEL[A..D][1:0]

RCLKENC

RCLKENB

RCLKENA

RECLCKD

RECLCKC

RECLCKB

RECLCKA

TXLB[A..D] are Internal Serial Loopback Signals

Document #: 38-02097 Rev. *B Page 4 of 44

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CYV15G0404DXB

WREN
ADDR[3:0]
DATA[7:0]

Device Configuration and Control Block

= Internal Signal

RXRATE[A..D]

FRAMCHAR[A..D]

RFEN[A..D]

RXCKSEL[A..D]

RFMODE[A..D][1:0]

RXBIST[A..D]

DECMODE[A..D]

DECBYP[A..D]

SDASEL[A..D][1:0]
RXPLLPD[A..D]
TXRATE[A..D]
TXCKSEL[A..D]

TXBIST[A..D]
OE[A..D][2..1]

PABRST[A..D]

ENCBYP[A..D]
GLEN[1 1..0]
FLEN[2..0]

Device Configura-

tion and Control

Interface

Document #: 38-02097 Rev. *B Page 5 of 44

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CYV15G0404DXB

Pin Configuration (Top View)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A

IN

OUT

C1–

C1–INC2–

B

IN

OUT

C1+

C1+INC2+

C

TDI TMS INSELC INSELB

D

TCLK INSELD INSELA

E

VCCVCCVCCV

F

RX

DC[6]RXDC[7]TXDC[0]

G

TX

WREN TX

DC[7]

H

GND GND GND GND GNDGNDGNDGND

J

TX

CTC[1]TXDC[5]TXDC[2]TXDC[3]

K

RX

REF

DC[2]

CLKC–TXCTC[0]TXCLKC

L

RX

REF

DC[3]

CLKC+

M

RX

DC[4]RXDC[5]

N

GND GND GND GND GNDGNDGNDGND

OUT

C2–

OUT

C2+

CC

RCLK

END

DC[4]TXDC[1]

LFIC TX

DC[6]

RCLK

ENCTXERRC

V

CC

V

CC

V

CC

V

CC

IN

OUT

D1–

D1–

IN

OUT

D1+

D1+

ULCD ULCC

ULCA SPD

SELC

GND

GND

GND

GND

IN

D2–

IN

D2+

DATA

[7]

DATA

[6]

OUT

D2–INA1–

OUT

D2+INA1+

DATA

DATA

[5]

DATA

DATA

[4]

OUT

A1–

OUT
A1+

DATA

[3]

[1]

DATA

[2]

[0]

GND

GND

GND

GND

IN

OUT

A2–

A2–

IN

OUT

A2+

A2+

RCLK

SPD

ENB

SELD

LPENB ULCB

IN

V

CC

V

CC

V

CC

V

CC

OUT

B1–

B1–INB2–

IN

OUT

B1+

B1+INB2+

LDTD ENTRST LPEND TDO

LPENA VCC SCAN

VCCVCCVCCV

RCLK

ENARXSTB[1]TXCLKOBRXSTB[0]

SPD

SELBLPENC

RX

STB[2]RXDB[0]RXDB[5]RXDB[2]

RX

DB[3]RXDB[4]RXDB[7]

RX

DB[6]RXCLKB+RXCLKB–TXDB[6]

REF

REF

CLKB+

CLKB–TXERRBTXCLKB

OUT

B2–

OUT

B2+

TMEN3

EN2

CC

SPD

SELARXDB[1]

LFIB

P

RX

DC[1]RXDC[0]RXSTC[0]RXSTC[1]

R

RX

STC[2]TXCLKOCRXCLKC+RXCLKC–

T

VCCVCCVCCV

U

TX

DD[0]TXDD[1]TXDD[2]TXCTD[1]

V

TX

DD[3]TXDD[4]TXCTD[0]RXDD[6]

W

TX

DD[5]TXDD[7]

Y

TX

DD[6]TXCLKDRXDD[7]

LFID RX

CLKD–

RX

CLKD+

CC

V

CC

V

CC

V

CC

V

CC

RX

DD[2]RXDD[1]

RX

DD[3]RXSTD[0]

RX

DD[4]RXSTD[1]

RX

DD[5]RXDD[0]

GND

GND

GND

GND

TX

CTA[1]

RX

STD[2]

ADDR

[3]

TX

CLKOD

ADDR

REF

[0]

CLKD–TXDA[1]

ADDR

REF

[2]

CLKD+TXCLKOA

ADDR

[1]RXCLKA+TXERRA

[1]

NC

TX

CLKARXCLKA–

GND

GND

GND

GND

TX

DA[4]TXCTA[0]

TX

DA[3]TXDA[7]

TX

DA[2]TXDA[6]

TX

DA[0]TXDA[5]

TX

DB[5]TXDB[4]TXDB[3]TXDB[2]

TX

DB[1]TXDB[0]TXCTB[1]TXDB[7]

VCCVCCVCCV

RX

V

CC

DA[2]TXCTB[0]RXSTA[2]RXSTA[1]

RX

V

CC

DA[7]RXDA[3]RXDA[0]RXSTA[0]

LFIA REF

V

CC

V

CC

CLKA+RXDA[4]RXDA[1]

TX

REF

ERRD

CLKA–RXDA[6]RXDA[5]

CC

Document #: 38-02097 Rev. *B Page 6 of 44

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CYV15G0404DXB

Pin Configuration (Bottom View)

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A

OUT
B2–INB2–

OUT

B1–INB1–

V

CC

OUT

A2–INA2–

GND

OUT

A1–INA1–

OUT

D2–IND2–

GND

OUT
D1–IND1–

V

CC

OUT

C2–INC2–

OUT

C1–INC1–

OUT

B

B2+INB2+

TDO LP

C

TMEN3 SCAN

D

VCCVCCVCCV

E

RX

F

STB[0]TXCLKOBRXSTB[1]

RX

G

DB[1]

GND GND GND GND GNDGNDGNDGND

H

RX

J

DB[2]RXDB[5]RXDB[0]RXSTB[2]

LFIB RX

K

TX

L

DB[6]RXCLKB–RXCLKB+RXDB[6]

TX

M

CLKBTXERRB

OUT

B1+INB1+

TRST LDTD

END

EN2

SPD

SELALPENC

DB[7]RXDB[4]RXDB[3]

VCC LP

REF

CLKB–

EN

ENA

CC

RCLK

ENA

SPD

SELB

REF

CLKB+

V

CC

V

CC

V

CC

OUT

A2+INA2+

SPD

RCLK

SELD

ENB

ULCB LP

ENB

GND

GND

GND

OUT

A1+INA1+

DATA

DATA

[1]

DATA

DATA

[0]

[3]

[2]

OUT

D2+IND2+

DATA

[5]

DATA

[4]

DATA

[7]

DATA

[6]

GND

GND

GND

OUT
D1+IND1+

ULCC ULCD

SPD

ULCA

SELC

OUT

V

CC

C2+IN2+

IN

V

CC

SELBINSELC

IN

V

CC

SELAINSELD

VCCVCCVCCV

RCLK

ENDTXDC[0]RXDC[7]RxDC[6]

TX

DC[1]TXDC[4]

TX

DC[3]TXDC[2]TXDC[5]TXCTC[1]

TX

CLKCTXCTC[0]

TX

LFIC REF

DC[6]

TX

RCLK

ERRC

ENCRXDC[5]RXDC[4]

OUT

TMS TDI

RESET TCLK

WREN TX

REF

CLKC–RXDC[2]

CLKC+RXDC[3]

C1+INC1+

CC

DC[7]

GND GND GND GND GNDGNDGNDGND

N

TX

P

DB[2]TXDB[3]TXDB[4]TXDB[5]

TX

R

DB[7]TXCTB[1]TXDB[0]TXDB[1]

VCCVCCVCCV

T

RX

U

STA[1]RXSTA[2]TXCTB[0]RXDA[2]

RX

V

STA[0]RXDA[0]RXDA[3]RXDA[7]

RX

W

DA[1]RXDA[4]

RX

Y

DA[5]RXDA[6]

CC

REF

LFIA

CLKA+

REF

CLKA–TXERRD

V

CC

V

CC

V

CC

V

CC

TX

CTA[0]TXDA[4]

TX

DA[7]TXDA[3]

TX

DA[6]TXDA[2]

TX

DA[5]TXDA[0]

GND

GND

GND

GND

TX

REF

DA[1]

CLKD–

TX

REF

CLKOA

CLKD+

TX

ERRARXCLKA+

RX

CLKA–TXCLKA

ADDR

[0]

ADDR

[2]RXSTD[2]

ADDR

[1]

[1]

NC

CLKOD

TXC

TA[1]

ADDR

[3]

TX

GND

GND

GND

GND

RX

DD[1]RXDD[2]

RX

STD[0]RXDD[3]

RX

STD[1]RXDD[4]

RX

DD[0]RXDD[5]

RX

STC[1]RXSTC[0]RXDC[0]RXDC[1]

RX

CLKC–RXCLKC+TXCLKOCRXSTC[2]

VCCVCCVCCV

TX

V

CC

CTD[1]TXDD[2]TXDD[1]TXDD[0]

RX

V

CC

DD[6]TXCTD[0]TXDD[4]TXDD[3]

RX

V

CC

V

CC

LFID TX

CLKD–

RX

CLKD+RXDD[7]TXCLKDTXDD[6]

CC

DD[7]TXDD[5]

Note

1. NC=Do Not Connect

Document #: 38-02097 Rev. *B Page 7 of 44

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CYV15G0404DXB

Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver

Name I/O Characteristics Signal Description
Transmit Path Data and Status Signals

TXDA[7:0]
TXDB[7:0]
TXDC[7:0]
TXDD[7:0]

TXCTA[1:0]
TXCTB[1:0]
TXCTC[1:0]
TXCTD[1:0]

TXERRA
TXERRB
TXERRC
TXERRD

Transmit Path Clock Signals

REFCLKA±
REFCLKB±
REFCLKC±
REFCLKD±

TXCLKA
TXCLKB
TXCLKC
TXCLKD

Notes

2. When REFCLKx± is configured for half rate operation, these inputs are sampled relative to both the ri sing and falling edges of the associated REFCLKx±.

3. When REFCLKx± is configured for half rate operation, these outputs are presented relative to both the risin g and falling edges of the associated REFCLKx±.

LVTTL Input,
synchronous,
sampled by the
associated
TXCLKx↑ or
REFCLKx↑

[2]

LVTTL Input,
synchronous,
sampled by the
associated
TXCLKx↑ or
REFCLKx↑

[2]

LVTTL Output,
synchronous to
REFCLKx↑

[3]

,
synchronous to
RXCLKx when
selected as
REFCLKx,
asynchronous to
transmit channel
enable/disable,
asynchronous to loss
or return of
REFCLKx±

Differential LVPECL
or single ended
LVTTL input clock

LVTTL Clock Input,
internal pull down

Transmit Data Inputs. TXDx[7:0] data inputs are captured on the rising edge of the
transmit interface clock. The transmit interface clock is selected by the TXCKSELx
latch via the device configuration interface, and passed to the encoder or Transmit
Shifter. When the Encoder is enabled, TXDx[7:0] specifies the specific data or
command character sent.

Transm it Contr ol. TXCTx[1:0] inputs are captured on the rising edge of the transmit
interface clock. The transmit interface clock is selected by the TXCKSELx latch
through the device configuration interface, and passed to the encoder or transmit
shifter. The TXCTA[1:0] inputs identify how the associated TXDx[ 7:0 ] charac ters are
interpreted. When the encoder is bypassed, these inputs are interpreted as data bits.
When the encoder is enabled, these inputs determine if the TXDx[7:0] character is
encoded as data, a special character code, or replaced with other special character
codes. See Table 3 for details.

Transmit Path Error. TXERRx is asserted HIGH to indicate detection of a transmit
phase align buffer underflow or overflow. If an underflow or overflow condition is
detected, TXERRx, for the channel in error, is asserted HIGH and remains asserted
until either a word sync sequence is transmitted on that channel, or the transmit
phase align buffer is recentered with the PABRSTx latch through the device configu­ration interface. When TXBISTx = 0, the BIST progress is presented on the
associated TXERRx output. The TXERRx signal pulses HIGH for one transmit
character clock period to indicate a pass through the BIST sequence once every 511
or 527 (depending on RXCKSELx) character times. If RXCKSELx = 1, a one
character pulse occurs every 527 character times. If RXCKSELx = 0, a one character
pulse occurs every 511 character times.

TXERRx is also asserted HIGH, when any of these conditions is true:

■ The TXPLL for the associated channel is powered down. This occurs when OE2x

and OE1x for a given channel are simultaneous disabled by setting OE2x = 0 and
OE1x = 0.

■ The absence of the REFCLKx± signal.

Reference Clock. REFCLKx± clock inputs are used as the timing references for the
transmit and receive PLLs. These input clocks may also be selected to clock the
transmit and receive parallel interfaces. When driven by a single ended LVCMOS or
LVTTL clock source, connect the clock source to either the true or complement
REFCLKx input, and leave the alternate REFCLKx input open (floating). When driven
by an L VPECL clock source, the clock must be a differential clock, using both inputs.

Transmit Path Input Clock. When configuration latch TXCKSELx = 0, the
associated TXCLKx input is selected as the character-rate input clock for the
TXDx[7:0] and TXCTx[1:0] inputs. In this mode, the TXCLKx input must be
frequency-coherent to its associated TXCLKOx output clock, but may be offset in
phase by any amount. Once initialized, TXCLKx is allowed to drift in phase as much
as ±180 degrees. If the input phase of TXCLKx drifts beyond the handling capacity
of the phase align buffer, TXERRx is asserted to indicate the loss of data, and remains
asserted until the phase align buffer is initialized. The phase of the TXCLKx i nput
clock relative to its associated REFCLKx± is initialized when the configuration latch
PABRSTx is written as 0. When the associated TXERRx is deasserted, the phase
align buffer is initialized and input characters are correctly captured.

Document #: 38-02097 Rev. *B Page 8 of 44

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CYV15G0404DXB

Pin Definitions (continued)
CYV15G0404DXB Quad HOTLink II Transceiver

Name I/O Characteristics Signal Description

TXCLKOA
TXCLKOB
TXCLKOC
TXCLKOD

Receive Path Data and Status Signals

RXDA[7:0]
RXDB[7:0]
RXDC[7:0]
RXDD[7:0]

RXSTA[2:0]
RXSTB[2:0]
RXSTC[2:0]
RXSTD[2:0]

Receive Path Clock Signals

RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±

Device Control Signals

RESET

LV TTL Output Transmit Clock Output. TXCLKOx output clock is synthesized by each channel’s

transmit PLL and operates synchronous to the internal transmit character clock.
TXCLKOx operates at either the same frequency as REFCLKx± (TXRATE = 0), or at
twice the frequency of REFCLKx± (TXRATE = 1). The transmit clock outputs have no
fixed phase relationship to REFCLKx±.

LVTTL Output,
synchronous to the
selected RXCLK±
output or REFCLKx±
input

LVTTL Output,
synchronous to the
selected RXCLK±
output or REFCLKx±
input

LVTTL Output Clock Receive Clock Output. RXCLKx± is the receive interface clock used to control timing

LVTTL Input,
asynchronous,
internal pull up

Parallel Data Output. RXDx[7:0] parallel data outputs change relative to the receive
interface clock. The receive interface clock is selected by the RXCKSELx latch. If
RXCLKx± is a full rate clock, the RXCLKx± clock outputs are complementary clocks
operating at the character rate. The RXDx[7:0] outputs for the associated receive
channels follow rising edge of RXCLKx+ or falling edge of RXCLKx–. If RXCLKx± is
a half rate clock, the RXCLKx± clock outputs are complementary clocks operating at
half the character rate. The RXDx[7:0] outputs for the associated receive channels
follow both the falling and rising edges of the associated RXCLKx± clock outputs.

Parallel Status Output. RXSTA[2:0] status outputs change relative to the receive
interface clock. The receive interface clock is selected by the RXCKSELx latch. If
RXCLKx± is a full rate clock, the RXCLKx± clock outputs are complementary clocks
operating at the character rate. The RXSTAx[2:0] outputs for the associated receive
channels follow rising edge of RXCLKx+ or falling edge of RXCLKx–. If RXCLKx± is
a half rate clock, the RXCLKx± clock outputs are complementary clocks operating at
half the character rate. The RXSTAx[2:0] outputs for the associated receive channels
follow both the falling and rising edges of the associated RXCLKx± clock outputs.
When the decoder is bypassed, RXSTx[1:0] become the two low-order bits of the
10-bit received character. RXSTx[2] = HIGH indicates the presence of a Comma
character in the Output Register. When the decoder is enabled, RXSTx[2:0] provide
status of the received signal. See Table 11 for a list of received character status.

of the RXDx[7:0] and RXSTA[2:0] parallel outputs. The source of the RXCLKx±
outputs is selected by the RXCKSELx latch via the device configuration interface.
These true and complement clocks are used to control timing of data output transfers.
These clocks are output continuously at either the dual-character rate (1/20
serial bit-rate) or character rate (1/10
as selected by RXRATEx. When configured such that the output data path is clocked
by the REFCLKx± instead of a recovered clock, the RXCLKx± output drivers present
a buffered or divided form (depending on RXRATEx) of the associated REFCLKx±
that are delayed in phase to align with the data. This phase difference allows the user
to select the optimal clock (REFCLKx± or RXCLK±) for setup or hold timing for their
specific system.

When REFCLKx± is a full rate clock, the RXCLKx± rate depends on the value of
RXRATEx.

When REFCLKx± is a half rate clock and RXCKSELx = 0, the RXCLKx± rate depends
on the value of RXRATEx.

When REFCLKx± is a half rate clock and RXCKSELx=1, the RXCLKx± rate does not
depend on the value of RXRATEx and operates at the same rate as REFCLKx±.

Asynchronous Device Reset. RESET
configuration latches in the device to a known state. RESET
for a minimum pulse width. When the reset is removed, all state machines, counters,
and configuration latches are at an initial state. As per the JTAG specifications, the
device RESET
to be reset separately. Refer to JTAG Support on page 23 for the methods to reset
the JTAG state machine. See Table 9 for the initialize values of the device configu-
ration latches.

cannot reset the JTAG controller. Therefore, the JTAG controller has

th

th

the serial bit-rate) of the data being received,

initializes all state machines, counters, and

must be asserted LOW

the

Document #: 38-02097 Rev. *B Page 9 of 44

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CYV15G0404DXB

Pin Definitions (continued)
CYV15G0404DXB Quad HOTLink II Transceiver

Name I/O Characteristics Signal Description

LDTDEN LVTTL Input,

internal pull up

RCLKENA
RCLKENB

LVTTL Input,
internal pull down

RCLKENC
RCLKEND

ULCA
ULCB

LVTTL Input,
internal pull up

ULCC
ULCD

SPDSELA
SPDSELB

3-Level Select
static control input

[4]

SPDSELC
SPDSELD

INSELA
INSELB

LVTTL Input,
asynchronous

INSELC
INSELD

LPENA
LPENB
LPENC

LVTTL Input,
asynchronous,
internal pull down

LPEND

Notes

4. 3-Level Select inputs are used for static configuration. These are ternary inpu ts that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to V
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.

5. See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface.

SS

Level Detect Transition Density Enable. When LDTDEN is HIGH, the signal level
detector, range controller , and transition density detector are all enabled to determine
if the RXPLL tracks REFCLKx± or the selected input serial data stream. If the signal
level detector, range controller, or transition density detector are out of their
respective limits while LDTDEN is HIGH, the RXPLL locks to REFCLK± until such a
time they become valid. The (SDASEL[A..D][1:0]) configure the trip level of the signal
level detector. The transition density detector limit is one transition in every 60
consecutive bits. When LDTDEN is LOW, only the range controller determines if the
RXPLL tracks REFCLKx± or the selected input serial data stream. For the cases
when RXCKSELx = 0 (recovered clock), it is recommended to set LDTDEN = HIGH.

Reclocker Enable. When RCLKENx is HIGH, the RXPLL performs clock and data
recovery functions on the input serial data stream and routes the deserialized data
to the RXDx[7:0] and RXSTA[2:0] parallel data outputs as configured by DECBYPx.
It also presents the reclocked serial data to the enabled differential serial outputs.

When RCLKENx is LOW, the receive reclocker is disabled and the TXDx[7:0] parallel
data inputs and TXCTx[1:0] inputs are interpreted (as configured by ENCBYPx) to
generate appropriate 10-bit characters that are presented to the differential serial
outputs.

The reclocker feature is optimized to be used for SMPTE video applications.
Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to REFCLKx±

instead of the received serial data stream. While ULCx

is LOW, the LFIx for the

associated channel is LOW indicating a link fault.
When ULCx

is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications in which a stable
RXCLKx± is needed. In cases when there is an absence of valid data transitions for
a long period of time, or the high-gain differential serial inputs (INx±) are left floating,
there may be brief frequency excursions of the RXCLKx± outputs from REFCLKx±.

Serial Rate Select. The SPDSELx inputs specify the operating signaling rate range
of each channel’s transmit and receive PLL.

LOW = 195 – 400 MBd
MID = 400 – 800 MBd
HIGH = 800 – 1500 MBd.
Receive Input Selector. The INSELx input determines which external serial bit

stream is passed to the receiver’s clock and data recovery circuit. When INSELx is
HIGH, the primary differential serial data input, INx1±, is selected for the associated
receive channel. When INSELx is LOW, the secondary differential serial data input,
INx2±, is selected for the associated receive channel.

Loop Back Enable. The LPENx input enables the internal serial loop back for the
associated channel. When LPENx is HIGH, the transmit serial data from the
associated channel is internally routed to the associated receive Clock an d Data
Recovery (CDR) circuit. All enabled serial drivers on the channel are forced to differ­ential logic-1, and the serial data inputs are ignored. When LPENx is LOW, the
internal serial loop back function is disabled.

(ground). The HIGH level is usually implemented by direct connection to VCC (power). The MID level is usually

Document #: 38-02097 Rev. *B Page 10 of 44

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CYV15G0404DXB

Pin Definitions (continued)
CYV15G0404DXB Quad HOTLink II Transceiver

Name I/O Characteristics Signal Description

LFIA
LFIB
LFIC
LFID

Device Configuration and Control Bus Signals

WREN

ADDR[3:0] LVTTL input

DATA[7:0] LVTTL input

Internal Device Configuration Latches

RFMODE[A..D][1:0] In ternal Latch
FRAMCHAR[A..D] Internal Latch
DECMODE[A..D] Internal Latch
DECBYP[A..D] Internal Latch
RXCKSEL[A..D] Internal Latch
RXRATE[A..D] Internal Latch
SDASEL[A..D][1:0] Internal Latch
ENCBYP[A..D] Internal Latch
TXCKSEL[A..D] Internal Latch
TXRATE[A..D] Internal Latch
RFEN[A..D] Internal Latch
RXPLLPD[A..D] Internal Latch
RXBIST[A..D] Internal Latch
TXBIST[A..D] Internal Latch
OE2[A..D] Internal Latch
OE1[A..D] Internal Latch
PABRST[A..D] Internal Latch
GLEN[11..0] Internal Latch
FGLEN[2..0] Internal Latch

Note

6. See Device Configuration and Control Interface for detailed information on the internal latches.

LVTTL Output,
asynchronous

LVTTL input,
asynchronous,
internal pull up

asynchronous,
internal pull up

asynchronous,
internal pull up

Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
logical OR of five internal conditions. LFIx
tions are true:

■ Received serial data rate outside expected range

■ Analog amplitude below expected levels

■ Transition density lower than expected

■ Receive channel disabled

■ ULCx is LOW

■ No REFCLKx±.

Control Write Enable. The WREN input writes the values of the DATA[7:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.

Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DAT A[7:0] bus into the
latch specified by the address location on the AD DR[3:0] bus.
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET

. Table 10 shows how the latches are mapped in the device.

Control Data Bus. The DATA[7:0] bus is the input data bus used to configure the
device. The WREN

input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.
latches within the device, and the initialization value of the latches upon the assertion
of RESET. Table 10 shows how the latches are mapped in the device.

[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]

Reframe Mode Select.
Framing Character Select.
Receiver Decoder Mode Select.
Receiver Decoder Bypass.
Receive Clock Select.
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Transmit Encoder Bypass.
Transmit Clock Select.
Transmit PLL Clock Rate Select.
Reframe Enable.
Receive Channel Power Control.
Receive Bist Disabled.
Transmit Bist Disabled.
Differential Serial Output Driver 2 Enable.
Differential Serial Output Driver 1 Enable.
Transmit Clock Phase Alignment Buffer Reset.
Global Latch Enable.
Force Global Latch Enable.

is asserted LOW when any of these condi -

[5]

[5]

Table 9 lists the

[5]

Table 9 lists the configuration

Document #: 38-02097 Rev. *B Page 11 of 44

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CYV15G0404DXB

Pin Definitions (continued)
CYV15G0404DXB Quad HOTLink II Transceiver

Name I/O Characteristics Signal Description

Factory Test Modes

SCANEN2 LVTTL input,

internal pull down

TMEN3 LVTTL input,

internal pull down

Analog I/O

OUTA1±
OUTB1±
OUTC1±
OUTD1±

OUTA2±
OUTB2±
OUTC2±
OUTD2±

INA1±
INB1±
INC1±
IND1±

INA2±
INB2±
INC2±
IND2±

JTAG Interface

TMS LVTTL Input,

TCLK LVTTL Input,

TDO 3-State LVTTL Output Test Data Out. JTAG data output buf fer . High-Z while JTAG test mode is not selected.
TDI LVTTL Input,

TRST

Power

V

CC

GND Signal and Power Ground for all internal circuits.

CML Differentia l
Output

CML Differentia l
Output

Differential Input Primary Differential Serial Data Input. The INx1± input accepts the serial data

Differential Input Secondary Differentia l Serial Data Input. The INx2± input accepts the serial data

internal pull up

internal pull down

internal pull up
LVTTL Input,

internal pull up

Factory Test 2. SCANEN2 input is for factory testing only . Leave this input as a NO
CONNECT or GND only.

Factory Test 3. TMEN3 input is for factory testing only. Leave this input as a NO
CONNECT or GND only.

Primary Differential Serial Data Output. The OUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC coupled for PECL
compatible connections.

Secondary Differential Serial Data Output. The OUTx2± PECL-comp atible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard fiber
optic transmitter modules, and must be AC coupled for PECL comp atible connections.

stream for deserialization and decoding. The INx1± serial stream is passed to the
receive CDR circuit to extract the data content when INSELx = HIGH.

stream for deserialization and decoding. The INx2± serial stream is passed to the
receiver CDR circuit to extract the data content when INSELx = LOW.

Te s t M o d e S e lect. Used to control access to the JTAG Test Modes. If maintained
high for ≥5 TCLK cycles, the JTAG test controller is reset.

JTAG Test Clock.

Test Data In. JTAG data input port.

JTAG reset signal. When asserted (LOW), this input asynchronously resets the

JT AG test access port controller.

+3.3V Power.

CYV15G0404DXB HOTLink II Operation

The CYV15G0404DXB is a highly configurable, independent
clocking, quad-channel transceiver designed to support reliable
transfer of large quantities of data, using high speed serial links
from multiple sources to multiple destinations. This device
supports four single byte channels.

CYV15G0404DXB Transmit Data Path

Input Register

The bits in the Input Register for each channel support different
assignments, based on if the input data is encoded or
unencoded. These assignments are shown in Table 1.

When the ENCODER is enabled, each input register capture s
eight data bits and two control bits on each input clock cycle.

Document #: 38-02097 Rev. *B Page 12 of 44

When the encoder is bypassed, the control bits are part of the
preencoded 10-bit character.

When the encoder is enabled, the TXCTx[1:0] bits are inter­preted along with the associated TXDx[7:0] character to
generate a specific 10-bit transmission character.

Phase Align Buffer

Data from each input register is passed to the associated phase
align buffer, when the TXDx[7:0] and TXCTx[1:0] input registers
are clocked using TXCLKx¦ (TXCKSELx = 0 and TXRA TEx = 0).
When the TXDx[7:0] and TXCTx[1:0] input registers are clocked
using REFCLKx± (TXCKSELx = 1) and REFCLKx± is a full rate
clock, the associated phase alignment buffer in the transmit path
is bypassed. These buffers are used to absorb clock phase
differences between the TXCLKx input clock and the internal
character clock for that channel.

[+] Feedback [+] Feedback

CYV15G0404DXB

Once initialized, TXCLKx is allowed to drift in phase as much as
±180 degrees. If the input phase of TXCLKx drifts beyond the
handling capacity of the phase align buffer, TXERRx is asserted
to indicate the loss of data, and remains asserted until the phase
align buffer is initialized. The phase of the TXCLKx relative to its
associated internal character rate clock is initialized when the
configuration latch PABRSTx is written as 0. When the
associated TXERRx is deasserted, the phase align buffer is
initialized and input characters are correctly captured.

Table 1. Input Register Bit Assignments

[7]

Signal Name Unencoded Encoded

TXDx[0] (LSB) DINx[0] TXDx[0]

TXDx[1] DINx[1] TXDx[1]
TXDx[2] DINx[2] TXDx[2]
TXDx[3] DINx[3] TXDx[3]
TXDx[4] DINx[4] TXDx[4]
TXDx[5] DINx[5] TXDx[5]
TXDx[6] DINx[6] TXDx[6]
TXDx[7] DINx[7] TXDx[7]

TXCTx[0] DINx[8] TXCTx[0]

TXCTx[1] (MSB) DINx[9] TXCTx[1]

Note

7. LSB shifted out first.

If the phase offset between the initialized location of the input
clock and REFCLKx exceeds the skew handling capabilities of
the phase align buffer, an error is reported on that channel’s
TXERRx output. This output indicates an error continuously until
the phase align buffer for that channel is reset. While the error
remains active, the transmitter for that channel outputs a
continuous C0.7 character to indicate to the remote receiver that
an error condition is present in the link.

Each phase align buffer may be individually reset w ith minimal
disruption of the serial data stream. When a phase align buffer
error is present, the transmission of a word sync sequence
recenters the phase align buffer and clears the error indication.

Note. K28.5 characters may be added or removed from the data
stream during the phase align buffer reset operation. When used
with non-Cypress devices that require a complete 16-character
word sync sequence for proper receive elasticity buffer
operation, follow the phase alignment buffer reset by a word sync
sequence to ensure proper operation.

Encoder

Each character received from the Input register or phase align
buffer is passed to the encoder logic. This block interprets each
character and any associated control bits, and outputs a 10-bit
transmission character.

Depending on the operational mode, the generated transmission
character may be

■ The 10-bit preencoded character accepted in the input register.

■ The 10-bit equivalent of the 8-bit Data character accepted in

the input register

■ The 10-bit equivalent of the 8-bit Special Character code

accepted in the input register

■ The 10-bit equivalent of the C0.7 violation character if a phase

align buffer overflow or underflow error is present

■ A character that is part of the 511-character BIST sequence

■ A K28.5 character generated as an individual character or as

part of the 16-character Word Sync Sequence

Data Encoding

Raw data, as received directly from the transmit input register, is
seldom in a form suitable for transmission across a serial link.
The characters must usually be processed or transformed to
guarantee

■ a minimum transition density (to allow the receive PLL to extract

a clock from the serial data stream)

■ A DC-balance in the signaling (to prevent baseline wander)

■ Run length limits in the serial data (to limit the bandwidth

requirements of the serial link)

■ the remote receiver a way of determining the correct character

boundaries (framing)

When the encoder is enabled (ENCBYPx = 1), th e characters
transmitted are converted from data or special character codes
to 10-bit transmission characters, using an integrated 8B/10B
encoder. When directed to encode the character as a special
character code, the encoder uses the special character encoding
rules listed in Table 15. When directed to encode the character
as a data character, it is encoded using the data character
encoding rules in Table 14.

The 8B/10B encoder is standards compliant with ANSI/NCITS
ASC X3.230-1994 Fibre Channel, IEEE 802.3z Gigabit Ethernet,
the IBM® ESCON® and FICON™ channels, ETSI DVB-ASI, and
ATM Forum st andards for data transport.

Many of the special character codes listed in Table 15 may be
generated by more than one input character. The
CYV15G0404DXB is designed to support two independent (but
non-overlapping) special character code tables. This allows the
CYV15G0404DXB to operate in mixed environments with other
Cypress HOTLink devices using the enhanced Cypress
command code set, and the reduced command sets of other
non-Cypress devices. Even when used in an environment that
normally uses non-Cypress Special Character codes, the
selective use of Cypress command codes can permit operation
where running disparity and error handling must be managed.

Following conversion of each input character from eight bits to a
10-bit transmission character, it is passed to the transmit shifter
and is shifted out LSB first, as required by ANSI and IEEE
standards for 8B/10B coded serial data streams.

Document #: 38-02097 Rev. *B Page 13 of 44

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CYV15G0404DXB

Transmit Modes

Encoder Bypass

When the Encoder is bypassed, the character captured from the
TXDx[7:0] and TXCTx[1:0] input register is passed directly to the
transmit shifter without modification. With the encoder bypassed,
the TXCTx[1:0] inputs are considered part of the data character
and do not perform a control function that would otherwise
modify the interpretation of the TXDx[7:0] bits. The bit usage and
mapping of these control bits when the Encoder is bypassed is
shown in Table 2.

Table 2. Encoder Bypass Mode

Signal Name Bus Weight 10B Name

TXDx[0] (LSB) 2

TXDx[1] 2
TXDx[2] 2
TXDx[3] 2
TXDx[4] 2
TXDx[5] 2
TXDx[6] 2
TXDx[7] 2

TXCTx[0] 2

TXCTx[1] (MSB) 2

0
1
2
3
4
5
6
7
8
9

When the encoder is enabled, the TXCTx[1:0] data control bits
control the interpretation of the TXDx[7:0] bits and the characters
generated by them. These bits are interpreted as listed in

Table 3.

Table 3. Transmit Modes

TXCTx[1] TXCTx[0] Characters Generated

0 0 Encoded data character
0 1 K28.5 fill character
1 0 Special character code
1 1 16-character Word Sync Sequence

Word Sync Sequence

When TXCTx[1:0] = 11, a 16-character sequence of K28.5
characters, known as a word sync sequence, is generated on the
associated channel. This sequence of K28.5 characters may
start with either a positive or negative disparity K28.5 (as deter­mined by the current running disparity and the 8B/10B coding
rules). The disparity of the second and third K28.5 characters in
this sequence are reversed from what normal 8B/10B coding
rules would generate. The remaining K28.5 characters in the
sequence follow all 8B/10B coding rules. The disparity of the
generated K28.5 characters in this sequence follow a pattern of
either ++––+–+–+–+–+–+– or ––++–+–+–+–+–+–+.

The generation of this sequence, once started, cannot be
stopped until all 16 characters have been sent. The content of
the associated input registers are ignored for the duration of this

[7]

a

b
c
d
e

i

f
g
h

j

sequence. At the end of this sequence, if the TXCTx[1:0] = 11
condition is sampled again, the sequence restarts and remains
uninterruptible for the following 15 character clocks.

Transmit BIST

Each transmit channel contains an internal pattern generator that
can be used to validate both the link and device operation. These
generators are enabled by the associated TXBISTx latch
through the device configuration interface. When enabled, a
register in the associated transmit channel becomes a signature
pattern generator by logically converting to a Linear Feedback
Shift Register (LFSR). This LFSR generates a 511-character (or
526-character) sequence that includes all data and special
character codes, including the explicit violation symbols. This
provides a predictable yet pseudo-random sequence that can be
matched to an identical LFSR in the attached Receiver(s).

A device reset (RESET sampled LOW) presets the BIST enable
latches to disable BIST on all channels.

All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel. If the receive channels are configured for
reference clock operation, each pass is preceded by a
16-character word sync sequence to allow elasticity buffer
alignment and management of clock frequency variations.

Transmit PLL Clock Multiplier

Each Transmit PLL Clock Multiplier accepts a character rate or
half character-rate external clock at the associated REFCLKx±
input, and that clock is multiplied by 10 or 20 (as selected by
TXRATEx) to generate a bit rate clock for use by the transmit
shifter. It also provides a character rate clock used by the
transmit paths, and outputs this character rate clock as
TXCLKOx.

Each clock multiplier PLL is able to accept a REFCLKx± input
between 19.5 MHz and 150 MHz, however, this clock range is
limited by the operating mode of the CYV15G0404DXB clock
multiplier (TXRATEx) and by the level on the associated
SPDSELx input.

SPDSELx are 3-level select
operating ranges for the serial data outputs and inputs of the
associated channel. The operating serial signaling rate and
allowable range of REFCLKx± frequencies are listed in Table 4.

Table 4. Operating Speed Settings

SPDSELx TXRATE

LOW

1 reserved 195 – 400
0 19.5 – 40

MID (Open) 1 20 – 40 400 – 800

0 40 – 80

HIGH 1 40 – 75 800 – 1500

0 80 – 150

[4]

inputs that select one of three

REFCLKx±
Frequency

(MHz)

Signaling

Rate (MBaud)

Document #: 38-02097 Rev. *B Page 14 of 44

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