Cypress CYV15G0104TRB User Manual

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CYV15G0104TRB

Independent Clock HOTLink II™ Serializer and

Reclocking Deserialize

Features

• Second-generation HOTLink® technology

• Compliant to SMPTE 292M and SMPTE 259M video
standards

• Single channel video serializer plus single channel
video reclocking deserializer

—195- to 1500-Mbps serial data signaling rate
—Simultaneous operation at different signaling rates

• Supports reception of either 1.485 or 1.485/1.001 Gbps
data rate with the same training clock

• Internal phase-locked loops (PLLs) with no external
PLL components

• Supports half-rate and full-rate clocking

• Selectable differential PECL-compatible serial inputs

—Internal DC-restoration

• Redundant differential PECL-compatible serial outputs

—No external bias resistors required
—Internal source termination
—Signaling-rate controlled edge-rates

• Synchron ous LVTTL parallel interface

• JTAG boundary scan

• Built-In Self-Test (BIST) for at-speed link testing

• Link Qu ality Indicator

—Analog signal detect
—Digital signal detect

• Low-power 1.8W @ 3.3V typical

• Single 3.3V supply

• Thermally enhanced BGA

• Pb-Free package option available

•0.25µ BiCMOS technology

Functional Description

The CYV15G0104TRB Independent Clock HOTLink II™
Serializer and Reclocking Deserializer is a point-to-point or
point-to-multipoint communications building block enabling

transfer of data over a variety of high-speed serial links
including SMPTE 292M and SMPTE 259M video applications.
It supports signaling rates in the range of 195 to 1500 Mbps
per serial link. The transmit and receive channels are
independent and can operate simultaneously at different
rates. The transmit channel accepts 10-bit parallel characters
in an Input Register and converts them to serial data. The
receive channel accepts serial data and converts it to 10-bit
parallel characters and presents these characters to an Output
Register. The received serial data can also be reclocked and
retransmitted through the reclocker serial outputs. Figure 1
illustrates typical connections between independent video co­processors and corresponding CYV15G0104TRB chips.

The CYV15G0104TRB satisfies the SMPTE 259M and
SMPTE 292M compliance as per SMPTE EG34-1999 Patho­logical Test Requirements.

As a second-generation HOTLink device, the
CYV15G0104TRB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices. The transmit (TX) channel of the CYV15G0104TRB
HOTLink II device accepts scrambled 10-bit transmission
characters. These characters are serialized and output from
dual Positive ECL (PECL) compatible differential trans­mission-line drivers at a bit-rate of either 10- or 20-times the
input reference clock for that channel.

The receive (RX) channel of the CYV15G0104TRB HOTLink
II device accepts a serial bit-stream from one of two selectable
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. The
recovered bit-stream is reclocked and retransmitted through
the reclocker serial outputs. Also, the recovered serial data is
deserialized and presented to the destination host system.

The transmit and receive channels contain an independent
BIST pattern generator and checker, respectively. This BIST
hardware allows at-speed testing of the high-speed serial data
paths in each transmit and receive section, and across the
interconnecting links.

Reclocked

Output

Video Coprocessor

10

10

Independent

CYV15G0104TRB

Channel

Device

Serial

Links

Reclocked

Output

Independent

Channel

CYV15G0104TRB

Device

10

10

Video Coprocessor

Figure 1. HOTLink II™ System Connections

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-02100 Rev. *B Revised July 8, 2005

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CYV15G0104TRB

The CYV15G0104TRB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include multi-

format routers, switchers, format converters, SDI monitors,
cameras, and camera control units.

CYV15G0104TRB Serializer and Reclocking Deserializer Logic Block Diagram

TXDB[9:0]

REFCLKB±

Deserializer

Reclocker

x10

RXDA[9:0]

RX

TRGCLKA±

x10

Phase

Align

Buffer

Serializer

TX

INA1±

INA2±

TOUTB1±

ROUTA1±

ROUTA2±

TOUTB2±

Document #: 38-02100 Rev. *B Page 2 of 27

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CYV15G0104TRB

Reclocking Deserializer Path Block Diagram

TRGRATEA

TRGCLKA

SDASEL[2..1]A[1:0]

LDTDEN

INSELA

INA1+
INA1–

INA2+
INA2–

ULCA

SPDSELA

RXPLLPDA

Recovered Character Clock

RECLKOA
REPDOA

x2

Receive

Signal

Monitor

Clock &

Data

Recovery

PLL

Recovered Serial Data

Reclocker

Output PLL

Clock Multiplier

Character-Rate Clock

10

Shifter

RXBISTA[1:0]

RXRATEA

ROE[2..1]A

Boundary
Controller

10

BIST LFSR

Bit-Rate Clock

JTAG

Scan

Output

Register

Register

÷2

10

ROE[2..1]A

RESET
TRST

TMS
TCLK
TDI

TDO

LFIA

RXDA[9:0]

BISTSTA

RXCLKA+
RXCLKA–

ROUTA1+
ROUTA1–

ROUTA2+
ROUTA2–

Serializer Path Block Diagram

REFCLKB+
REFCLKB–

SPDSELB
TXCLKOB

TXERRB
TXCLKB

TXDB[9:0]

TXRATEB

TXCKSELB

10

10

Input

Transmit PLL

Transmit PLL

Clock Multiplier

Clock Multiplier

Character-Rate Clock

10

Register

PABRSTB

Buffer

Buffer

Phase-Align

Phase-Align

Device Configuration and Control Block Diagram

WREN
ADDR[2:0]
DATA[6:0]

Device Configuration
and Control Interface

Bit-Rate Clock

TOE[2..1]B

TXBISTB

10

BIST LFSR

RXRATEA
RXPLLPDA
TRGRATEA
TXRATEB
TXCKSELB
PABRSTB
SDASEL[2..1]A[1:0]
TOE[2..1]B
ROE[2..1]A

RXBISTA[1:0]

TXBISTB

10

Shifter

= Internal Signal

TOE[2..1]B

TOUTB1+
TOUTB1–

TOUTB2+
TOUTB2–

= Internal Signal

Document #: 38-02100 Rev. *B Page 3 of 27

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CYV15G0104TRB

Pin Configuration (Top View)

[1]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A

NC NC NC NC V

B

VCCNC V

C

TDI TMS

D

TCLK RESET

E

VCCVCCVCCV

F

NC NC V

G

H

J

WREN

GND

GND GND GND GND GND GND GND GND

GND GND GND GND NC NC NC NC

CC

VCCVCCV

INSELA

V

CC

CC

GND GND NC NC

CC

NC VCCV

CC

V

CC

CC

NC V

TOUT

NC

CC

B1–

TOUT

B1+

GND GND

GND NC

NC NC GND

ULCA

NC GND

DATA

[6]

DATA

[5]

TOUT

B2–INA1–

TOUT

B2+INA1+

DATA

[4]

DATA

[3]

ROUT

GND

A1–

ROUT

GND

A1+

DATA

DATA

[2]

DATA

[1]

GND NC

[0]

GND GND GND NC V

IN

A2–

IN

A2+

ROUT

A2–

ROUT

A2+

SPD

SELB

VCCV

CC

V

NC NC NC NC

CC

LDTD ENTRST

V

CC

NC V

CC

VCCVCCVCCV

CC

NC V

CC

CC

GND

SCAN

EN2

NC

TDO

TMEN3

NC NC NC

SPD

NC

SELA

CC

K

NC NC GND GND NC NC NC NC

L

NC NC NC GND NC NC NC GND

M

NC NC NC NC NC NC NC GND

N

GND GND GND GND GND GND GND GND

P

NC NC NC NC GND GND GND GND

R

NC NC NC NC VCCVCCVCCV

T

VCCVCCVCCV

U

TX

DB[0]TXDB[1]TXDB[2]TXDB[9]

V

TX

DB[3]TXDB[4]TXDB[8]

W

TX

DB[5]TXDB[7]

Y

TX

DB[6]TXCLKB

CC

NC V

NC NC V

NC NC V

V

NC NC GND GND

CC

NC NC GND NC GND

CC

NC NC GND

CC

NC NC GND

CC

ADDR

[2]

TX

CLKOB

ADDR

[0]

CLKB–

CLKB+RECLKOA

ADDR

[1]RXCLKA+

NC GND

REF

GND GND GND VCCV

REF

GND GND VCCV

REPDO

GND GND VCCV

A

RX

GND GND VCCV

CLKA–

VCCVCCVCCV

RX

CC

CC

CC

CC

V

DA[4]

DA[9]RXDA[5]RXDA[2]RXDA[1]

ERRB

CC

RX

LFIA TRG

CLKA+RXDA[6]RXDA[3]

TX

TRG

CLKA–RXDA[8]RXDA[7]

BIST

STARXDA[0]

CC

CC

Note:

1. NC = Do not connect.

Document #: 38-02100 Rev. *B Page 4 of 27

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CYV15G0104TRB

Pin Configuration (Bottom View)

[1]

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A

NC V

B

NC NC NC NC V

C

TDO

D

TMEN3 SCAN

E

VCCVCCVCCV

F

NC NC NC V

G

NC

H

GND GND GND GND GND GND GND GND

J

NC NC NC NC GND GND GND GND

NC VCCV

CC

TRST LDTD

GND

EN2

SPD

SELA

EN

V

NC V

CC

CC

CC

NC NC GND GND

ROUT

CC

A2–INA2–

ROUT

CC

A2+INA2+

SPD

V

CC

CC

NC GND

SELB

NC GND GND GND

GND

GND

ROUT

A1–INA1–

ROUT

A1+INA1+

DATA

[0]

DATA

[2]

DATA

[1]

TOUT

B2–

TOUT

B2+

DATA

[4]

DATA

[3]

GND GND

NC GND

DATA

[6]

DATA

[5]

TOUT

NC V

B1–

TOUT

VCCV

B1+

GND NC NC VCCVCCV

GND NC

ULCA

NC NC NC NC

CC

NC V

CC

INSELA

V

CC

VCCVCCVCCV

NC V

CC

CC

V

CC

CC

NC V

CC

TMS TDI

RESET TCLK

CC

NC NC

WREN

GND

K

NC NC NC NC GND GND NC NC

L

GNDNCNCNC GND NC NC NC

M

GNDNCNCNC NC NC NC NC

N

GND GND GND GND GND GND GND GND

P

GND GND GND GND NC NC NC NC

R

VCCVCCVCCV

T

VCCVCCVCCV

U

RX

BIST

DA[0]

STA

V

RX

DA[1]RXDA[2]RXDA[5]RXDA[9]

W

RX

DA[3]RXDA[6]

Y

RX

DA[7]RXDA[8]

CC

CC

RX

V

CC

DA[4]

TRG

LFIA

CLKA+

TRG

CLKA–TXERRB

VCCVCCGND GND GND

VCCVCCGND GND

VCCVCCGND GND

VCCVCCGND GND

RE

CLKOA

REPDOARX

RX

CLKA–

REF

ADDR

CLKB–

REF

CLKB+

CLKA+

GND NC

GND GND NC NC V

[0]

GND NC GND NC NC V

ADDR

ADDR

[1]

GND NC NC V

[2]

TX

GND NC NC V

CLKOB

NC NC NC NC

VCCVCCVCCV

TX

CC

DB[9]TXDB[2]TXDB[1]TXDB[0]

TX

NC

CC

CC

CC

DB[8]TXDB[4]TXDB[3]

NC NC

NC NC

CC

TX

DB[7]TXDB[5]

TX

CLKBTXDB[6]

Document #: 38-02100 Rev. *B Page 5 of 27

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CYV15G0104TRB

Pin Definitions
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer

Name I/O Characteristics Signal Description
Transmit Path Data and Status Signals

TXDB[9:0] LVTTL Input,

synchronous,
sampled by
TXCLKB↑ or
REFCLKB↑

[2]

TXERRB LVTTL Output,

synchronous to
REFCLKB↑

[3]

,
asynchronous to
transmit channel
enable / disable,
asynchronous to loss
or return of
REFCLKB±

Transmit Path Clock Signals

REFCLKB± Differential LVPECL

or single-ended
LVTTL input clock

TXCLKB LVTTL Clock Input,

internal pull-down

TXCLKOB LVTTL Output Transmit Clock Output. TXCLKOB output clock is synthesized by the transmit PLL and

Receive Path Data and Status Signals

RXDA[9:0] LVTTL Output,

synchronous to the
RXCLKA ± output

Notes:

2. When REFCLKB± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated RE FCLKB±.

3. When REFCLKB± is configured for half-rate operation, this output is presented relative to both the rising and falling edges of the associated REFCLKB±.

Trans mit D ata In puts. TXDB[9:0] data inputs are captured on the risin g edge of the
transmit interface clock. The transmit interface clock is selected by the TXCKSELB latch
via the device configuration interface.

Transmit Path Error. TXERRB is asserted HIGH to indicate detection of a transmit
Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is
detected, TXERRB, is asserted HIGH and remains asserted until the transmit Phase-Align
Buffer is re-centered with the PABRSTB latch via the device configuration interface. When
TXBISTB = 0, the BIST progress is presented on the TXERRB output. The TXERRB
signal pulses HIGH for one transmit-character clock period to indicate a pass through the
BIST sequence once every 511 character times.

TXERRB is also asserted HIGH, when any of the following conditions is true:

• The TXPLL is powered down. This occurs when TOE2B and TOE1B are both disabled
by setting TOE2B = 0 and TOE1B = 0.

• The absence of the REFCLKB± signal.

Reference Clock. REFCLKB± clock inputs are used as the timing reference for the
transmit PLL. This input clock may also be selected to clock the transmit parallel interface.
When driven by a single-ended LVCMOS or L VTTL clock source, connect the clock source
to either the true or complement REFCLKB input, and leave the alternate REFCLKB input
open (floating). When driven by an LVPECL clock source, the clock must be a differential
clock, using both inputs.

Transmit Path Input Clock. When configuration latch TXCKSELB = 0, the associated
TXCLKB input is selected as the character-rate input clock for the TXDB[9:0] input. In this
mode, the TXCLKB input must be frequency-coherent to its TXCLKOB output clock, but
may be offset in phase by any amount. Once initialized, TXCLKB is allowed to drift in
phase by as much as ±180 degrees. If the input phase of TXCLKB drifts beyond the
handling capacity of the Phase Align Buffer, TXERRB is asserted to indicate the loss of
data, and remains asserted until the Phase Align Buffer is initialized. The phase of
TXCLKB relative to REFCLKB± is initialized when the configuration latch PABRSTB is
written as 0. When TXERRB is deasserted, the Phase Align Buffer is initialized and input
characters are correctly captured.

operates synchronous to the internal transmit character clock. TXCLKOB operates at
either the same frequency as REFCLKB± (TXRATEB = 0), or at twice the frequency of
REFCLKB± (TXRATEB = 1). The transmit clock outputs have no fixed phase relationship
to REFCLKB±.

Parallel Data Output. RXDA[9:0] parallel data outputs change relative to the receive
interface clock. If RXCLKA± is a full-rate clock, the RXCLKA± clock outputs are comple­mentary clocks operating at the character rate. The RXDA[9:0] outputs for the associated
receive channels follow rising edge of RXCLKA+ or falling edge of RXCLKA–. If RXCLKA±
is a half-rate clock, the RXCLKA± clock outputs are complementary clocks operating at
half the character rate. The RXDA[9:0] outputs for the associated receive channels follow
both the falling and rising edges of the associated RXCLKA± clock outputs.

When BIST is enabled on the receive channel, the BIST status is presented on the
RXDA[1:0] and BISTSTA outputs. See Table 6 for each status reported by the BIST state
machine. Also, while BIST is enabled, the RXDA[9:2] outputs should be ignored.

Document #: 38-02100 Rev. *B Page 6 of 27

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CYV15G0104TRB

Pin Definitions (continued)
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer

Name I/O Characteristics Signal Description

BISTSTA LVTTL Output,

synchronous to the
RXCLKA ± output

REPDOA Asynchronous to

reclocker output
channel
enable/disable

Receive Path Clock Signals

TRGCLKA± Differential LVPECL

or single-ended
LVTTL input clock

RXCLKA± LVTTL Output Clock Receive Clock Output. RXCLKA± is the receive interface clock used to control timing of

RECLKOA LVTTL Output Reclocker Clock Output. RECLKOA output clock is synthesized by the reclocker output

Device Control Signals

RESET

LDTDEN LVTTL Input,

ULCA

LVTTL Input,
asynchronous,
internal pull-up

internal pull-up

LVTTL Input,
internal pull-up

BIST Status Output. When RXBISTA[1:0] = 10, BISTSTA (along with RXDA[1:0])
displays the status of the BIST reception. See Table 6 for the BIST status reported for
each combination of BISTSTA and RXDA[1:0].

When RXBISTA[1:0] ≠ 10, BISTSTA should be ignored.
Reclocker Powered Down Status Output. REPDOA is asserted HIGH, when the

reclocker output logic is powered down. This occurs when ROE2A and ROE1A are both
disabled by setting ROE2A = 0 and ROE1A = 0.

CDR PLL Training Clock. TRGCLKA± clock inputs are used as the reference source for
the frequency detector (Range Controller) of the receive PLL to reduce PLL acquisition
time.

In the presence of valid serial data, the recovered clock output of the receive CDR PLL
(RXCLKA±) has no frequency or phase relationship with TRGCLKA±.

When driven by a single-ended LVCMOS or L VTTL clock source, connect the clock source
to either the true or complement TRGCLKA input, and leave the alternate TRGCLKA input
open (floating). When driven by an LVPECL clock source, the clock must be a differential
clock, using both inputs.

the RXDA[9:0] parallel outputs. These true and complement clocks are used to control
timing of data output transfers. These clocks are output continuously at either the half­character rate (1/20
data being received, as selected by RXRATEA.

PLL and operates synchronous to the internal recovered character clock. RECLKOA
operates at either the same frequency as RXCLKA± (RXRATEA = 0), or at twice the
frequency of RXCLKA± (RXRATEA = 1).The reclocker clock outputs have no fixed phase
relationship to RXCLKA±.

Asynchronous Device Reset. RESET
configuration latches in the device to a known state. RESET
minimum pulse width. When the reset is removed, all state machines, counters and config­uration latches are at an initial state. See Table 4 for the initialize values of the device
configuration latches.

Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level
Detector, Range Controller, and Transition Density Detector are all enabled to determine
if the RXPLL tracks TRGCLKA± or the selected input serial data stream. If the Signal Level
Detector, Range Controller , or Transition Density Detector are out of their respective limits
while LDTDEN is HIGH, the RXPLL locks to TRGCLKA± until such a time they become
valid. SDASEL[2..1]A[1:0] is used to configure the trip level of the Signal Level Detector.
The Transition Density Detector limit is one transition in every 60 consecutive bits. When
LDTDEN is LOW, only the Range Controller is used to determine if the RXPLL tracks
TRGCLKA± or the selected input serial data stream. it is recommended to set LDTDEN
= HIGH.

Use Local Clock. When ULCA is LOW, the RXPLL is forced to lock to TRGCLKA± instead
of the received serial data stream. While ULCA
LOW indicating a link fault.

When ULCA
input data streams. This function is used in applications in which a stable RXCLKA± is
needed. In cases when there is an absence of valid data transitions for a long period of
time, or the high-gain differential serial inputs (INA±) are left floating, there may be brief
frequency excursions of the RXCLKA± outputs from TRGCLKA±.

th

the serial bit-rate) or character rate (1/10th the serial bit-rate) of the

initializes all state machines, counters, and

must be asserted LOW for a

is LOW, the link fault indicator LFIA is

is HIGH, the RXPLL performs Clock and Data Recovery functions on the

Document #: 38-02100 Rev. *B Page 7 of 27

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CYV15G0104TRB

Pin Definitions (continued)
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer

Name I/O Characteristics Signal Description

SPDSELA
SPDSELB

3-Level Select
static control input

INSELA LVTTL Input,

asynchronous

LFIA

LVTTL Output,
asynchronous

Device Configuration and Control Bus Signals

WREN LVTTL input,

asynchronous,
internal pull-up

ADDR[2:0] LVTTL input

asynchronous,
internal pull-up

DATA[6:0] LVTTL input

asynchronous,
internal pull-up

Internal Device Configuration Latches

RXRATEA Internal Latch
SDASEL[2..1]

Internal Latch

A[1:0]
TXCKSELB Internal Latch
TXRATEB Internal Latch
TRGRATEA Internal Latch
RXPLLPDA Internal Latch
RXBISTA[1:0] Internal Latch
TXBISTB Internal Latch
TOE2B Internal Latch
TOE1B Internal Latch

Notes:

4. 3-Level Select inputs are used for stati c configuration. These are terna ry inputs tha t make use of logic levels of LOW , MI D, and HIGH. The LOW level is usually
implemented by direct connection to V
implemented by not connecting the input (left floating), whi ch allows it to self bias to the proper level.

5. See Device Configuration and Control Interface for detailed informa tion on the operation of the Configuration Interface.

6. See Device Configuration and Control Interface for detailed informa tion on the internal latches.

[4]

Serial Rate Select. The SPDSELA and SPDSELB inputs specify the operating signaling­rate range of the receive and transmit PLL, respectively.

LOW = 195 – 400 MBd
MID = 400 – 800 MBd
HIGH = 800 – 1500 MBd.
Receive Input Selector. The INSELA in put determines which external serial bit stream

is passed to the receiver’s Clock and Data Recovery circuit. When INSELA is HIGH, the
Primary Differential Serial Data Input, INA1±, is selected for the receive channel. When
INSELA is LOW, the Secondary Differential Serial Data Input, INA2±, is selected for the
receive channel.

Link Fault Indication Output. LFIA is an output status indicator signal. LFIA is the logical
OR of six internal conditions. LFIA

is asserted LOW when any of the following conditions

is true:

• Received serial data rate outside expected range

• Analog ampl itude below expected levels

• Transition density lower than expected

• Receive channel disabled

•ULCA

is LOW

• Absence of TRGCL KA±.

Control Write Enable. The WREN input writes the values of the DATA[6:0] bus into the
latch specified by the address location on the ADDR[2:0] bus.

[5]

Control Addressing Bus. The ADDR[2:0] bus is the input address bus used to configure
the device. The WREN input writes the values of the DAT A[6:0] bus into the latch specified
by the address location on the ADDR[2:0] bus.

[5]

Table 4 lists the configuration latches
within the device, and the initialization value of the latches upon the assertion of RESET
Table 5 shows how the latches are mapped in the device.

Control Data Bus. The DA TA[6:0] bus is the input data bus used to configure the device.
The WREN
location on the ADDR[2:0] bus.
and the initialization value of the latches upon the assertion of RESET

input writes the values of the DAT A[6:0] bus into the latch specified by address

[5 ]

Table 4 lists the configuration latches within the device,

. Table 5 shows how

the latches are mapped in the device.

[6]
[6]

[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]

Receive Clock Rate Select.
Signal Detect Amplitude Select.

Transmit Clock Select.
Transmit PLL Clock Rate Select.
Reclocker Output PLL Clock Rate Select.
Receive Channel Power Control.
Receive Bist Disabled.
Transmit Bist Disabled.
Transmitter Differential Serial Output Driver 2 Enable.
Transmitter Differential Serial Output Driver 1 Enable.

(ground). The HIGH level is usually implemented by direct connection to VCC (power). The MID level is usually

SS

.

Document #: 38-02100 Rev. *B Page 8 of 27

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CYV15G0104TRB

Pin Definitions (continued)
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer

Name I/O Characteristics Signal Description

ROE2A Internal Latch
ROE1A Internal Latch
PABRSTB Internal Latch

Factory Test Modes

SCANEN2 LVTTL input,

TMEN3 LVTTL input,

Analog I/O

TOUTB1± CML Differential

TOUTB2± CML Differential

ROUTA1± CML Differential

ROUTA2± CML Differential

INA1± Differential Input Primary Differential Serial Data Input. The INA1± input accepts the serial data stream

INA2± Differential Input Secondary Differential Serial Data Input. The INA2± input accepts the serial data

JTAG Interface

TMS LVTTL Input,

TCLK LVTTL Input,

TDO 3-State LVTTL Output Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected.
TDI LVTTL Input,

TRST

Power

V

CC

GND Signal and Power Ground for all internal circuits.

internal pull-down

internal pull-down

Output

Output

Output

Output

internal pull-up

internal pull-down

internal pull-up
LVTTL Input,

internal pull-up

[6]
[6]
[6]

Reclocker Differential Serial Output Driver 2 Enable.
Reclocker Differential Serial Output Driver 1 Enable.
Transmit Clock Phase Alignment Buffer Reset.

Factory Test 2. SCANEN2 input is for factory testing only . This input may be left as a NO

CONNECT, or GND only.
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a NO

CONNECT, or GND only.

Transmitter Primary Differential Serial Data Outpu t. The transmitter TOUTB 1± PECL­compatible CML outputs (+3.3V referenced) are capable of driving terminated trans­mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.

Transmitter Secondary Differential Serial Data Output. T he transmitter TOUTB2± PE CL­compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines
or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.

Reclocker Primary Differential Serial Data Output. The reclocker ROUTA1± PECL­compatible CML outputs (+3.3V referenced) are capable of driving terminated trans­mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.

Rec loc ker Secondary Differential Serial Data Output. The reclocker ROUTA2± PECL­compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines
or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.

for deserialization. The INA1± serial stream is passed to the receive CDR circuit to extract
the data content when INSELA = HIGH.

stream for deserialization. The INA2± serial stream is passed to the receiver CDR circuit
to extract the data content when INSELA = LOW.

Test Mode Select. Used to control access to the JT AG Test Modes. If maintained high for
≥5 TCLK cycles, the JTAG test controller is reset.

JTAG Test Clock.

Test Data In. JTAG data input port.

JTAG reset signal. When asserted (LOW), this input asynchronously resets the JTAG

test access port controller.

+3.3V Power.

CYV15G0104TRB HOTLink II Operation

The CYV15G0104TRB is a highly configurable, independent
clocking device designed to support reliable transfer of large
quantities of digital video data, using high-speed serial links
from multiple sources to multiple destinations.

Document #: 38-02100 Rev. *B Page 9 of 27

CYV15G0104TRB Transmit Data Path

Input Register

The parallel input bus TXDB[9:0] can be clocked in using
TXCLKB (TXCKSELB = 0) or REFCLKB (TXCKSELB = 1).

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