Cypress CYTVII-B-E-1M-176-CPU User Manual

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CYTVII-B-E-1M-176-CPU Evaluation Board

User Guide

CYTVII-B-E-1M-176-CPU

Evaluation Board User Guide

Document Number. 002-22883 Rev. *C

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

www.cypress.com

Copyrights

© Cypress Semiconductor Corporation, 2018-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.

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Disclaimer of Schematics and Layouts: This material constitutes a reference design. CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO. THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all changes.

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 2

1. Introduction

This user guide provides instructions to use the CYTVII-B-E-1M-176-CPU and CYTVII-B-E-176-SO evaluation boards, collectively referred to as 'CPU board' in this document. This is an evaluation platform for the CYT2B78CABES Traveo II device. The board can be used standalone for basic validation or in combination with the CYTVII-B-E-BB Traveo II baseboard (available separately from Cypress). This document assumes that you will work with the combination (CPU board + baseboard), and provides guidance to use features of the evaluation platform. The Device Port Pin Connections on Baseboard and CPU board schematic used in this document is for CYTVII-B-E-1M-176CPU Rev C and Rev 1.0 boards and CYTVII-B-E-176-SO Rev C and Rev 1.0 boards only.

1.1 Precautions and Warnings

The evaluation board must be handled by qualified personnel who are aware of the capabilities of the boards. You must ensure your own safety arising from electrical hazards and other sources. You must carefully handle the board, which is a delicate PCB, and ensure that it is not subjected to bending or other stresses.

The CPU board is shipped with a 12 V DC power adapter. This adapter can be plugged into the AC mains supply anywhere in the world and is designed to receive 100-240 V AC V @ 50/60 Hz. While powering the board, you must connect only the power adapter supplied with the evaluation board and not any other part.

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 4

2. Overview

Figure 2-1 shows the CYTVII-B-E-176-SO board. Insert a Traveo II device into the IC socket

(marked in red) while the evaluation board is powered OFF.

Figure 2-1. CYTVII-B-E-176-SO Board

A variant of the CPU board (CYTVII-B-E-1M-176-CPU) is also available, where the Traveo II device is soldered directly onto the PCB. Functionally, the CYTVII-B-E-1M-176-CPU and CYTVII-B-E-176SO boards are identical, except that the device can be easily replaced in the latter. Figure 2-3 shows the CYTVII-B-E-1M-176-CPU mounted on baseboard.

Another variant of the CPU board is available which has 100-pin socket mounted on it. The CPU board referred as a CYTVII-B-E-1M-100-SO board.

The CPU board is meant to be used along with a Traveo II baseboard (CYTVII-B-E-BB). The baseboard brings out all important interface connections such as CAN, LIN, SPI EEPROM, CXPI, and Flexray, and can be used in conjunction with several CPU boards of the Traveo II family. Figure 2-2 shows the baseboard.

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 5

Figure 2-2. Traveo II Base board (CYTVII-B-E-BB)

Overview

Two Samtec connectors on the CPU board and corresponding mating connectors on the baseboard are used to connect signals across the two boards. When put together, the boards appear as shown in Figure 2-3.

Figure 2-3. Combination of CPU Board and TVII Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 6

2.1 Functional Overview

The CPU board has the following features:

1. One Traveo II device, either soldered or mounted on a socket (U4).

2. PMIC to generate the 5 V and 3.3 V output depending on the Jumper J23 selection, which powers the CPU board and the baseboard (if connected).

3. Programming interface (JTAG-20, MiniProg3, SWD, and IDC-20, Mictor trace port) to connect several programming tools such as IAR I-jet, Green Hills GHS, MiniProg.

4. USB-UART interface for terminal logging (J12).

5. One user switch (SW3) and one user LED (LED5) for standalone operation without the baseboard.

6. Reset controller with manual reset switch (SW2) and voltage supervision.

7. Measurement of device current on VDDIO, VDDA, and VDDD using jumpers J6, J8, and J10 respectively.

8. Samtec connector interface (J21 and J22) for connecting to the baseboard CYTVII-B-E-BB.

The Traveo II baseboard has the following features:

1. Six CAN-FD transceivers based on TJA1057GT (Dual connectors P6, P7, P8).

2. Four CAN-FD transceivers based on TJA1145T, with SPI-based transceiver configuration (Dual connectors P9, P10).

3. Six LIN transceivers based on TJA1021T (Dual connectors (Dual connectors P3, P4, P5).

4. Two Flexray transceivers based on TJA1081TS (Dual connector P2).

5. One CXPI transceiver based on S6BT112A01 (Connector P1).

6. One SPI EEPROM 25LC320A (U9).

7. Five user switches (SW1 through SW5), 10 user LEDs (USER_LED0 through USER_LED9) and one potentiometer (POT1) for analog input.

8. Pin headers to access all I/Os of the TVII device (when a CPU board is connected to the baseboard).

9. Samtec connector interface (J38 and J84) for connecting to a CPU board.

Overview

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 7

3. Operation

This section describes the operation of the CPU board and the baseboard. It is assumed that you have connected the CPU board to the baseboard using the Samtec interface and inserted a TVII device into the IC socket (applicable to SO boards only). The following method can be used to operate the CPU board and the baseboard.

1. For socketed CPU board, ensure that the device is inserted into the socket. Remove the four screws on the socket using the screwdriver provided in the box and open the socket cover. If the device is not present, place one carefully using a vacuum picker or a pair of tweezers.

2. Ensure that the pin 1 of the device is near the arrow mark (near C14) as shown in Figure 3-1. You must also ensure that the angle of placing the device is such that the pins on all four sides of the LQFP package match well with the socket pins. Align the device slightly if required.

Figure 3-1. Orientation of Device when Inserted in Socket

3. Put the socket cover and fix the four screws such that the socket cover tightly sits on the socket base.

4. A 12V wall adapter board is supplied along with the CPU board. Connect the 12 V wall adapter to the barrel connector marked “12V DC” on the CPU board. Connect its plug to a mains socket using one of the four plug adapters provided in the white box (depending on the geographical location and the socket type available).

5. Ensure that jumpers J23 (default 5 V: J23_1 and J23_2), J5, J6, J8, J10 (current measurement jumpers) are inserted on the CPU board. You can select the 3.3 V power rails for CPU board by shorting J23_2 and J23_2 as per their application or hardware setup.

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 8

Operation

6. Turn ON the mains supply to the wall adapter. Turn ON the switch SW1 on the CPU board. The LED labelled PWR should light up.

7. Connect an appropriate programming tool to one of the programming interfaces (J17, J18, J19, J20). Programming tool options are:

❐ GHS Trace on J20

❐ IAR I-jet on J18 or J19

❐ MiniProg3 on J19

8. Install the appropriate programming IDE on a PC. The programming IDE (GHS Multi, IAR EWB, CYP, and so on) should be able to detect a device (read the device ID) and to load a firmware HEX file (.sreg) into the device flash successfully. As part of the release package, various firmware examples compiled in several programming IDEs are available. Some examples use specific transceivers on the baseboard.

9. To start with, use the LED blink example provided with the release package to test the functioning of the board.

10. Connect a USB-mini cable to J12 and the other end to a PC. Open Tera Term or your preferred terminal logging application and set the appropriate port and baud rate (typically 115,200 baud, 8, N, 1). Ensure that jumpers J11 and J13 are inserted on the CPU board. Some firmware examples provide data logs from the device or ask for user inputs over the terminal.

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 9

4. Connections and Settings

Ensure that the following jumpers are inserted on the baseboard to use each transceiver on the baseboard with respective firmware examples which activate each functionality of the device.

1. CAN0.0 from the device uses the CAN0 and CAN6 transceiver on the baseboard. These transceivers are selectable through jumpers on baseboard. (connect jumpers J70, J71, J72 for CAN0 and J94, J109, J110, J105, J104, J106 and J103 for CAN6)

2. CAN0.1 from the device uses the CAN1 and CAN7 transceiver on the baseboard. These transceivers are selectable through jumpers on baseboard.(connect jumpers J66, J67, J68 for CAN1 and J97, J95, J101, J96, J98, J99 and J100 for CAN7)

3. CAN0.2 from the device uses the CAN2 and CAN8 transceiver on the baseboard. These transceivers are selectable through jumpers on baseboard.(connect jumpers J81, J82, J83 for CAN2 and J111, J112, J113, J115, J116, J118 and J117 for CAN8)

4. CAN1.0 from the device uses the CAN3 and CAN9 transceiver on the baseboard. These transceivers are selectable through jumpers on baseboard.(connect jumpers J76, J77, J78 for CAN3 and J114, J131, J125, J121, J122, J123 and J124 for CAN9)

5. CAN1.1 from the device uses the CAN4 transceiver on the baseboard (connect jumpers J91, J92, J93)

6. CAN1.2 from the device uses the CAN5 transceiver on the baseboard (connect jumpers J86, J87, J88)

7. LIN0 from the device uses the LIN0 transceiver on the baseboard (connect jumpers J58, J59, J60, J63)

8. LIN1 from the device uses the LIN1 transceiver on the baseboard (connect jumpers J51, J52, J53, J56)

9. LIN2 from the device uses the LIN2 transceiver on the baseboard (connect jumpers J37, J39, J40, J43)

10. LIN3 from the device uses the LIN3 transceiver on the baseboard (connect jumpers J30, J31, J32, J35)

11. LIN4 from the device uses the LIN4 transceiver on the baseboard (connect jumpers J22, J23, J24, J27)

12. LIN6 from the device uses the LIN5 transceiver on the baseboard (connect jumpers J10, J16, J17, J20)

13. EEPROM on the baseboard is enabled by connecting jumpers J47, J48, J49.

14. The user switch functionality is enabled by connecting jumper J102.

15. The potentiometer functionality is enabled by connecting jumper J89.

In addition, power is supplied to the baseboard by connecting jumper J80 in the '5V' position and must always be connected. Once a specific functionality is chosen by connecting the jumpers listed above, ensure that the appropriate firmware is loaded onto the device. Incorrect firmware can result in port pins being configured incorrectly leading to bus contention and damage to hardware. For example, if you connect jumpers related to CAN0.0, you must ensure that firmware configures the related ports as CAN pins.

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 10

Contact Cypress technical support for firmware examples.

Connections and Settings

Apart from these interface transceivers that can be used for specific functions, all pins of the device are also accessible on the baseboard using pin headers JP1 through JP12.

The device port pins are connected to pin headers on the baseboard as listed in Table 4-1.

Table 4-1. Device Port Pin Connections on Baseboard

Access Pin

Port Pin Pin Function

P0.0

P0.1

P0.2

P0.3

P1.0 PWM_12/PWM_13_N/TC_12_TR0/TC_13_TR1/SCB0_SCL/SCB0_MISO JP8.4

P1.1 PWM_11/PWM_12_N/TC_11_TR0/TC_12_TR1/SCB0_SDA/SCB0_MOSI JP8.3

P1.2 PWM_10/PWM_11_N/TC_10_TR0/TC_11_TR1/SCB0_CLK/TRIG_IN[0] JP8.6

P1.3 PWM_8/PWM_10_N/TC_8_TR0/TC_10_TR1/SCB0_SEL0/TRIG_IN[1] JP8.5

P10.0

P10.1

P10.2 PWM_30/PWM_29_N/TC_30_TR0/TC_29_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK JP6.13

P10.3 PWM_31/PWM_30_N/TC_31_TR0/TC_30_TR1/SCB4_CTS/SCB4_SEL0 JP6.16

P10.4 PWM_32/PWM_31_N/TC_32_TR0/TC_31_TR1/SCB4_SEL1/ADC[1]_0 JP6.17

P10.5 PWM_33/PWM_32_N/TC_33_TR0/TC_32_TR1/SCB4_SEL2/ADC[1]_1 JP1.7

P10.6 PWM_34/PWM_33_N/TC_34_TR0/TC_33_TR1/ADC[1]_2 JP1.8

P10.7 PWM_35/PWM_34_N/TC_35_TR0/TC_34_TR1/ADC[1]_3 JP1.13

P11.0 ADC[0]_M JP9.6

P11.1 ADC[1]_M JP9.5

P11.2 ADC[2]_M JP9.8

P12.0 PWM_36/PWM_35_N/TC_36_TR0/TC_35_TR1/CAN0_2_TX/TRIG_IN[20]/ADC[1]_4 JP10.8

P12.1

P12.2

P12.3 PWM_39/PWM_38_N/TC_39_TR0/TC_38_TR1/EXT_MUX[1]_0/LIN6_TX/ADC[1]_7 JP1.10

P12.4 PWM_40/PWM_39_N/TC_40_TR0/TC_39_TR1/EXT_MUX[1]_1/ADC[1]_8 JP10.13

P12.5 PWM_41/PWM_40_N/TC_41_TR0/TC_40_TR1/EXT_MUX[1]_2/ADC[1]_9 JP1.14

P12.6 PWM_42/PWM_41_N/TC_42_TR0/TC_41_TR1/ADC[1]_10 JP2.18

P12.7 PWM_43/PWM_42_N/TC_43_TR0/TC_42_TR1/ADC[1]_11 JP2.17

P13.0

PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA/SCB0_MISO/ LIN1_RX

PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL/SCB0_MOSI/ LIN1_TX

PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/ LIN1_EN/CAN0_1_TX

PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/CAN0_1_RX

PWM_28/PWM_27_N/TC_28_TR0/TC_27_TR1/SCB4_RX/SCB4_MISO/ TRIG_IN[18]

PWM_29/PWM_28_N/TC_29_TR0/TC_28_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/ TRIG_IN[19]

PWM_37/PWM_36_N/TC_37_TR0/TC_36_TR1/LIN6_EN/CAN0_2_RX/TRIG_IN[21]/ ADC[1]_5

PWM_38/PWM_37_N/TC_38_TR0/TC_37_TR1/EXT_MUX[1]_EN/LIN6_RX/ ADC[1]_6

PWM_M_8/PWM_43_N/TC_M_8_TR0/TC_43_TR1/EXT_MUX[2]_0/SCB3_RX/ SCB3_MISO/ADC[1]_12

on

Baseboard

JP6.15

JP6.14

JP6.9

JP6.8

JP9.16

JP9.15

JP10.7

JP1.9

JP10.4

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 11

Connections and Settings

Table 4-1. Device Port Pin Connections on Baseboard (continued)

Access Pin

Port Pin Pin Function

P13.1

P13.2

P13.3

P13.4 PWM_M_10/PWM_45_N/TC_M_10_TR0/TC_45_TR1/SCB3_SEL1/ADC[1]_16JP6.4

P13.5 PWM_46/PWM_M_10_N/TC_46_TR0/TC_M_10_TR1/SCB3_SEL2/ADC[1]_17JP2.7

P13.6

P13.7 PWM_47/PWM_M_11_N/TC_47_TR0/TC_M_11_TR1/TRIG_IN[23]/ADC[1]_19 JP2.15

P14.0

P14.1

P14.2

P14.3

P14.4 PWM_52/PWM_51_N/TC_52_TR0/TC_51_TR1/SCB2_SEL1/LIN6_EN/ADC[1]_24 JP7.12

P14.5 PWM_53/PWM_52_N/TC_53_TR0/TC_52_TR1/SCB2_SEL2/ADC[1]_25 JP7.16

P14.6 PWM_54/PWM_53_N/TC_54_TR0/TC_53_TR1/TRIG_IN[24]/ADC[1]_26 JP7.17

P14.7 PWM_55/PWM_54_N/TC_55_TR0/TC_54_TR1/TRIG_IN[25]/ADC[1]_27 JP3.3

P15.0 PWM_56/PWM_55_N/TC_56_TR0/TC_55_TR1/ADC[1]_28 JP3.5

P15.1 PWM_57/PWM_56_N/TC_57_TR0/TC_56_TR1/ADC[1]_29 JP3.7

P15.2 PWM_58/PWM_57_N/TC_58_TR0/TC_57_TR1/ADC[1]_30 JP3.9

P15.3 PWM_59/PWM_58_N/TC_59_TR0/TC_58_TR1/ADC[1]_31 JP3.11

P16.0 PWM_60/PWM_59_N/TC_60_TR0/TC_59_TR1/PWM_H_0 JP3.13

P16.1 PWM_61/PWM_60_N/TC_61_TR0/TC_60_TR1/PWM_H_0_N JP3.15

P16.2 PWM_62/PWM_61_N/TC_62_TR0/TC_61_TR1/PWM_H_1 JP3.17

P16.3 PWM_62/PWM_62_N/TC_62_TR0/TC_62_TR1/PWM_H_1_N JP4.3

P17.0 PWM_61/PWM_62_N/TC_61_TR0/TC_62_TR1/CAN1_1_TX JP11.8

P17.1

P17.2

P17.3

P17.4

P17.5 PWM_56/PWM_57_N/TC_56_TR0/TC_57_TR1/SCB3_SEL1 JP3.10

P17.6 PWM_M_4/PWM_56_N/TC_M_4_TR0/TC_56_TR1/SCB3_SEL2 JP3.8

P17.7 PWM_M_5/PWM_M_4_N/TC_M_5_TR0/TC_M_4_TR1 JP3.6

PWM_44/PWM_M_8_N/TC_44_TR0/TC_M_8_TR1/EXT_MUX[2]_1/SCB3_TX/ SCB3_SDA/SCB3_MOSI/ADC[1]_13

PWM_M_9/PWM_44_N/TC_M_9_TR0/TC_44_TR1/EXT_MUX[2]_2/SCB3_RTS/ SCB3_SCL/SCB3_CLK/ADC[1]_14

PWM_45/PWM_M_9_N/TC_45_TR0/TC_M_9_TR1/EXT_MUX[2]_EN/SCB3_CTS/ SCB3_SEL0/ADC[1]_15

PWM_M_11/PWM_46_N/TC_M_11_TR0/TC_46_TR1/SCB3_SEL3/TRIG_IN[22]/ ADC[1]_18

PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/SCB2_RX/SCB2_MISO/ CAN1_0_TX/ADC[1]_20

PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/SCB2_TX/SCB2_SDA/SCB2_MOSI/ CAN1_0_RX/ADC[1]_21

PWM_50/PWM_49_N/TC_50_TR0/TC_49_TR1/SCB2_RTS/SCB2_SCL/SCB2_CLK/ LIN6_RX/ADC[1]_22

PWM_51/PWM_50_N/TC_51_TR0/TC_50_TR1/SCB2_CTS/SCB2_SEL0/LIN6_TX/ ADC[1]_23

PWM_60/PWM_61_N/TC_60_TR0/TC_61_TR1/PWM_H_2/SCB3_RX/SCB3_MISO/ CAN1_1_RX

PWM_59/PWM_60_N/TC_59_TR0/TC_60_TR1/PWM_H_2_N/SCB3_TX/ SCB3_SDA/SCB3_MOSI

PWM_58/PWM_59_N/TC_58_TR0/TC_59_TR1/PWM_H_3/SCB3_RTS/SCB3_SCL/ SCB3_CLK/TRIG_IN[26]

PWM_57/PWM_58_N/TC_57_TR0/TC_58_TR1/PWM_H_3_N/SCB3_CTS/SCB3_SEL0/TRIG_IN[27]

on

Baseboard

JP10.3

JP10.16

JP1.5

JP2.11

JP3.12

JP3.14

JP1.11

JP7.8

JP11.7

JP2.3

JP4.5

JP4.11

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 12

Connections and Settings

Table 4-1. Device Port Pin Connections on Baseboard (continued)

Access Pin

Port Pin Pin Function

P18.0

P18.1

P18.2

P18.3

P18.4

P18.5

P18.6

P18.7

P19.0

P19.1

P19.2

P19.3

P19.4 PWM_29/PWM_28_N/TC_29_TR0/TC_28_TR1/TC_H_2_TR0/SCB2_SEL1 JP3.4

P20.0 PWM_30/PWM_29_N/TC_30_TR0/TC_29_TR1/TC_H_2_TR1/SCB2_SEL2/LIN5_RX JP7.4

P20.1 PWM_49/PWM_30_N/TC_49_TR0/TC_30_TR1/TC_H_3_TR0/LIN5_TX JP7.5

P20.2 PWM_48/PWM_49_N/TC_48_TR0/TC_49_TR1/TC_H_3_TR1/LIN5_EN JP4.14

P20.3

P20.4

P20.5 PWM_45/PWM_46_N/TC_45_TR0/TC_46_TR1/SCB1_RTS/SCB1_SCL/SCB1_CLK JP5.9

P20.6 PWM_44/PWM_45_N/TC_44_TR0/TC_45_TR1/SCB1_CTS/SCB1_SEL0 JP5.7

P20.7 PWM_43/PWM_44_N/TC_43_TR0/TC_44_TR1/SCB1_SEL1 JP5.6

P2.0

P2.1

P2.2

P2.3

P2.4 PWM_3/PWM_4_N/TC_3_TR0/TC_4_TR1/SCB7_SEL1/LIN5_TX/TRIG_IN[6]JP8.8

PWM_M_6/PWM_M_5_N/TC_M_6_TR0/TC_M_5_TR1/PWM_H_0/SCB1_RX/ SCB1_MISO/FAULT_OUT_0/ADC[2]_0

PWM_M_7/PWM_M_6_N/TC_M_7_TR0/TC_M_6_TR1/PWM_H_0_N/SCB1_TX/ SCB1_SDA/SCB1_MOSI/

FAULT_OUT_1/ADC[2]_1

PWM_55/PWM_M_7_N/TC_55_TR0/TC_M_7_TR1/PWM_H_1/SCB1_RTS/ SCB1_SCL/SCB1_CLK/ADC[2]_2

PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/PWM_H_1_N/SCB1_CTS/SCB1_SEL0/TRACE_CLOCK/ADC[2]_3

PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_DATA_0/ADC[2]_4

PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/ TRACE_DATA_1/ADC[2]_5

PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/PWM_H_3/SCB1_SEL3/ CAN1_2_TX/TRACE_DATA_2/ADC[2]_6

PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/PWM_H_3_N/CAN1_2_RX/ TRACE_DATA_3/ADC[2]_7

PWM_M_3/PWM_50_N/TC_M_3_TR0/TC_50_TR1/TC_H_0_TR0/SCB2_RX/ SCB2_MISO/FAULT_OUT_2

PWM_26/PWM_M_3_N/TC_26_TR0/TC_M_3_TR1/TC_H_0_TR1/SCB2_TX/ SCB2_SDA/SCB2_MOSI/FAULT_OUT_3

PWM_27/PWM_26_N/TC_27_TR0/TC_26_TR1/TC_H_1_TR0/SCB2_RTS/ SCB2_SCL/SCB2_CLK/TRIG_IN[28]

PWM_28/PWM_27_N/TC_28_TR0/TC_27_TR1/TC_H_1_TR1/SCB2_CTS/SCB2_SEL0/TRIG_IN[29]

PWM_47/PWM_48_N/TC_47_TR0/TC_48_TR1/SCB1_RX/SCB1_MISO/ CAN1_2_TX

PWM_46/PWM_47_N/TC_46_TR0/TC_47_TR1/SCB1_TX/SCB1_SDA/SCB1_MOSI/ CAN1_2_RX

PWM_7/PWM_8_N/TC_7_TR0/TC_8_TR1/SCB7_RX/SCB0_SEL1/SCB7_MISO/ LIN0_RX/CAN0_0_TX/ SWJ_TRSTN/TRIG_IN[2]

PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/SCB7_TX/SCB7_SDA/SCB0_SEL2/ SCB7_MOSI/LIN0_TX/ CAN0_0_RX/TRIG_IN[3]

PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/SCB7_RTS/SCB7_SCL/SCB0_SEL3/ SCB7_CLK/LIN0_EN/TRIG_IN[4]

PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/SCB7_CTS/SCB7_SEL0/LIN5_RX/ TRIG_IN[5]

on

Baseboard

JP3.18

JP3.16

JP9.17

JP4.4

JP9.18

JP12.4

JP11.6

JP11.5

JP7.9

JP7.13

JP6.5

JP6.10

JP4.15

JP5.8

#NA

JP1.4

JP1.6

JP10.11

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 13

Connections and Settings

Table 4-1. Device Port Pin Connections on Baseboard (continued)

Access Pin

Port Pin Pin Function

P2.5 PWM_2/PWM_3_N/TC_2_TR0/TC_3_TR1/SCB7_SEL2/LIN5_EN/TRIG_IN[7]JP8.7

P21.0 PWM_42/PWM_43_N/TC_42_TR0/TC_43_TR1/SCB1_SEL2/WCO_IN #N/A

P21.1 PWM_41/PWM_42_N/TC_41_TR0/TC_42_TR1/WCO_OUT #N/A

P21.2 PWM_40/PWM_41_N/TC_40_TR0/TC_41_TR1/TRIG_DBG[1]/EXT_CLK/ECO_IN #N/A

P21.3 PWM_39/PWM_40_N/TC_39_TR0/TC_40_TR1/ECO_OUT #N/A

P21.4 PWM_38/PWM_39_N/TC_38_TR0/TC_39_TR1/HIBERNATE_WAKEUP[0] JP5.5

P21.5 PWM_37/PWM_38_N/TC_37_TR0/TC_38_TR1/LIN0_RX JP1.3

P21.6 PWM_36/PWM_37_N/TC_36_TR0/TC_37_TR1/LIN0_TX JP5.10

P21.7 PWM_35/PWM_36_N/TC_35_TR0/TC_36_TR1/LIN0_EN/CAL_SUP_NZ/RTC_CAL JP5.18

P22.0

P22.1

P22.2

P22.3

P22.4 PWM_30/PWM_31_N/TC_30_TR0/TC_31_TR1/SCB6_SEL1/TRACE_CLOCK JP5.11

P22.5 PWM_29/PWM_30_N/TC_29_TR0/TC_30_TR1/SCB6_SEL2/LIN7_RX JP5.12

P22.6 PWM_28/PWM_29_N/TC_28_TR0/TC_29_TR1/LIN7_TX JP5.13

P22.7 PWM_27/PWM_28_N/TC_27_TR0/TC_28_TR1/LIN7_EN JP5.14

P23.0

P23.1

P23.2

P23.3

P23.4

P23.5 PWM_24/PWM_25_N/TC_24_TR0/TC_25_TR1/SCB7_SEL2/SWJ_SWCLK_TCLK #N/A

P23.6 PWM_23/PWM_24_N/TC_23_TR0/TC_24_TR1/SWJ_SWDIO_TMS #N/A

P23.7

P3.0 PWM_1/PWM_2_N/TC_1_TR0/TC_2_TR1/SCB6_RX/SCB6_MISO/TRIG_DBG[0] JP10.14

P3.1

P3.2

P3.3 PWM_M_2/PWM_M_3_N/TC_M_2_TR0/TC_M_3_TR1/SCB6_CTS/SCB6_SEL0 JP8.9

P3.4 PWM_M_1/PWM_M_2_N/TC_M_1_TR0/TC_M_2_TR1/SCB6_SEL1 JP8.12

P3.5 PWM_M_0/PWM_M_1_N/TC_M_0_TR0/TC_M_1_TR1/SCB6_SEL2 JP8.11

PWM_34/PWM_35_N/TC_34_TR0/TC_35_TR1/SCB6_RX/SCB6_MISO/ CAN1_1_TX/TRACE_DATA_0

PWM_33/PWM_34_N/TC_33_TR0/TC_34_TR1/SCB6_TX/SCB6_SDA/SCB6_MOSI/ CAN1_1_RX/TRACE_DATA_1

PWM_32/PWM_33_N/TC_32_TR0/TC_33_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK/ TRACE_DATA_2

PWM_31/PWM_32_N/TC_31_TR0/TC_32_TR1/SCB6_CTS/SCB6_SEL0/TRACE_DATA_3

PWM_M_8/PWM_27_N/TC_M_8_TR0/TC_27_TR1/SCB7_RX/SCB7_MISO/ CAN1_0_TX/FAULT_OUT_0

PWM_M_9/PWM_M_8_N/TC_M_9_TR0/TC_M_8_TR1/SCB7_TX/SCB7_SDA/ SCB7_MOSI/CAN1_0_RX/FAULT_OUT_1

PWM_M_10/PWM_M_9_N/TC_M_10_TR0/TC_M_9_TR1/SCB7_RTS/SCB7_SCL/ SCB7_CLK/FAULT_OUT_2

PWM_M_11/PWM_M_10_N/TC_M_11_TR0/TC_M_10_TR1/SCB7_CTS/SCB7_SEL0/FAULT_OUT_3/TRIG_IN[30]

PWM_25/PWM_M_11_N/TC_25_TR0/TC_M_11_TR1/SCB7_SEL1/TRIG_DBG[0]/ SWJ_SWO_TDO/TRIG_IN[31]

PWM_22/PWM_23_N/TC_22_TR0/TC_23_TR1/CAL_SUP_NZ/SWJ_SWDOE_TDI/ EXT_CLK/HIBERNATE_WAKEUP[1]

PWM_0/PWM_1_N/TC_0_TR0/TC_1_TR1/SCB6_TX/SCB6_SDA/SCB6_MOSI/ TRIG_DBG[1]

PWM_M_3/PWM_0_N/TC_M_3_TR0/TC_0_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK

on

Baseboard

JP4.6

JP4.8

JP4.10

JP4.12

JP5.15

JP5.16

JP5.17

JP7.10

JP4.7

JP4.9

JP11.4

JP8.10

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 14

Connections and Settings

Table 4-1. Device Port Pin Connections on Baseboard (continued)

Access Pin

Port Pin Pin Function

Baseboard

P4.0

P4.1

P4.2

P4.3

P4.4 PWM_8/PWM_7_N/TC_8_TR0/TC_7_TR1/SCB5_SEL1/CAN0_1_RX JP8.18

P5.0 PWM_9/PWM_8_N/TC_9_TR0/TC_8_TR1/SCB5_SEL2/LIN7_RX JP11.3

P5.1 PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1/LIN7_TX JP10.15

P5.2 PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1/LIN7_EN JP10.18

P5.3 PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1/LIN2_RX JP2.5

P5.4 PWM_13/PWM_12_N/TC_13_TR0/TC_12_TR1/LIN2_TX JP8.17

P5.5 PWM_14/PWM_13_N/TC_14_TR0/TC_13_TR1/LIN2_EN JP10.6

P6.0

P6.1

P6.2

P6.3

P6.4 PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SCB4_SEL1/LIN4_TX/ADC[0]_4 JP2.14

P6.5 PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5 JP2.16

P6.6 PWM_M_3/PWM_2_N/TC_M_3_TR0/TC_2_TR1/SCB4_SEL3/TRIG_IN[8]/ADC[0]_6 JP10.5

P6.7 PWM_3/PWM_M_3_N/TC_3_TR0/TC_M_3_TR1/TRIG_IN[9]/ADC[0]_7 JP11.11

P7.0

P7.1

P7.2

P7.3

P7.4 PWM_M_6/PWM_16_N/TC_M_6_TR0/TC_16_TR1/SCB5_SEL1/ADC[0]_12 JP10.9

P7.5 PWM_17/PWM_M_6_N/TC_17_TR0/TC_M_6_TR1/SCB5_SEL2/ADC[0]_13 JP10.12

P7.6 PWM_M_7/PWM_17_N/TC_M_7_TR0/TC_17_TR1/TRIG_IN[16]/ADC[0]_14 JP11.12

P7.7 PWM_18/PWM_M_7_N/TC_18_TR0/TC_M_7_TR1/TRIG_IN[17]/ADC[0]_15 JP11.9

P8.0 PWM_19/PWM_18_N/TC_19_TR0/TC_18_TR1/LIN2_RX/CAN0_0_TX JP6.12

P8.1

P8.2 PWM_21/PWM_20_N/TC_21_TR0/TC_20_TR1/LIN2_EN/TRIG_IN[15]/ADC[0]_17 JP2.8

PWM_4/PWM_M_0_N/TC_4_TR0/TC_M_0_TR1/EXT_MUX[0]_0/SCB5_RX/ SCB5_MISO/ LIN1_RX/TRIG_IN[10]

PWM_5/PWM_4_N/TC_5_TR0/TC_4_TR1/EXT_MUX[0]_1/SCB5_TX/SCB5_SDA/ SCB5_MOSI/LIN1_TX/TRIG_IN[11]

PWM_6/PWM_5_N/TC_6_TR0/TC_5_TR1/EXT_MUX[0]_2/SCB5_RTS/SCB5_SCL/ SCB5_CLK/LIN1_EN/TRIG_IN[12]

PWM_7/PWM_6_N/TC_7_TR0/TC_6_TR1/EXT_MUX[0]_EN/SCB5_CTS/SCB5_SEL0/ CAN0_1_TX/TRIG_IN[13]

PWM_M_0/PWM_14_N/TC_M_0_TR0/TC_14_TR1/SCB4_RX/SCB4_MISO/ LIN3_RX/ADC[0]_0

PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1

PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/ CAN0_2_TX/ADC[0]_2

PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SCB4_CTS/SCB4_SEL0/LIN4_RX/ CAN0_2_RX/ CAL_SUP_NZ/ADC[0]_3

PWM_M_4/PWM_3_N/TC_M_4_TR0/TC_3_TR1/SCB5_RX/SCB5_MISO/LIN4_RX/ ADC[0]_8

PWM_15/PWM_M_4_N/TC_15_TR0/TC_M_4_TR1/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN4_TX/ADC[0]_9

PWM_M_5/PWM_15_N/TC_M_5_TR0/TC_15_TR1/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN4_EN/ADC[0]_10

PWM_16/PWM_M_5_N/TC_16_TR0/TC_M_5_TR1/SCB5_CTS/SCB5_SEL0/ ADC[0]_11

PWM_20/PWM_19_N/TC_20_TR0/TC_19_TR1/LIN2_TX/CAN0_0_RX/TRIG_IN[14]/ ADC[0]_16

JP8.14

JP8.13

JP8.16

JP8.15

JP2.9

JP2.10

#NA

JP12.3

JP12.6

JP12.5

JP10.10

JP6.11

on

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 15

Connections and Settings

Table 4-1. Device Port Pin Connections on Baseboard (continued)

Access Pin

Port Pin Pin Function

Baseboard

P8.3 PWM_22/PWM_21_N/TC_22_TR0/TC_21_TR1/TRIG_DBG[0]/ADC[0]_18 JP11.1 0

P8.4 PWM_23/PWM_22_N/TC_23_TR0/TC_22_TR1/TRIG_DBG[1]/ADC[0]_19 JP9.9

P9.0 PWM_24/PWM_23_N/TC_24_TR0/TC_23_TR1/ADC[0]_20 JP9.12

P9.1 PWM_25/PWM_24_N/TC_25_TR0/TC_24_TR1/ADC[0]_21 JP9.11

P9.2 PWM_26/PWM_25_N/TC_26_TR0/TC_25_TR1/ADC[0]_22 JP9.14

P9.3 PWM_27/PWM_26_N/TC_27_TR0/TC_26_TR1/ADC[0]_23 JP9.13

VCCD VCCD #NA

VDDA VDDA JP1.17

VDDD VDDD JP1.15

VDDIO VDDIO JP1.16

VREFH VREFH #NA

VREFL VREFL #NA

VSSA VSSA / VSSD / VSSIO/ Ground JP1.19

XRES XRES JP12.16

on

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 16

A. Schematics of CPU Board

This appendix contains the schematics of TVII-B-E-1M board.

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 17

Figure A-1. Block Diagram of CPU Board

5

4

3

2

1

D D

C C

B B

A A

BOARD TO BOARD CONNECTOR-2

RESET CONTROLLER

USB TO UART TRANSCEIVER

PROGRAM/DEBUG INTERFACE

POWER SUPPLY

GPIO

(PMIC 5V OUTPUT)

(JTAG,SWD,ETM)

(180 PIN SAMTEC CONNECTOR)

BOARD TO BOARD CONNECTOR-1

(180 PIN SAMTEC CONNECTOR)

(Data Only)

WITH RESET BUTTON

1 I/O SWITCH 1 I/O LED

SYSTEM ARCHITECTURE

TVII-B-E-1M-B0

DEVICE

(LDO 3V3 OUTPUT)

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

SCH Title :

Page Title :

CYTVII-B-E-1M-B0-176-CPU-BOARD

BLOCK DIAGRAM

Size

Document Number R ev

Date: Sheet of

Drawn By Approved By

6239956 C

A4

220

Monday, April 01, 2019

VJYM SPPD

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 18

Figure A-2. Power Architecture

5

4

3

2

1

D

C C

B B

A A

12V POWER INPUT

PMIC(5V,1A)

BOARD TO BOARD CONNECTOR-1

BOARD TO BOARD CONNECTOR-2

UART TO USB CONVERTER

USB CONNECTOR

DEBUG INTERFACE

VCC_12V

VCC

USB_VIN

RESET CONTROLLER

ARM ETM MICTOR, ARM STANDARD JTAG, CORTEX DEBUG + ETM, CORTEX DEBUG

POWER ARCHITECTURE

TRAVEO II MCU

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

SCH Title :

Size

Document Number R ev

Date: Sheet of

Page Title :

Drawn By Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

320

Monday, April 01, 2019

POWER ARCHITECTURE

VJYM SPPD

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 19

Figure A-3. 5V Power Input

5

4

3

2 1

D D

C C

B B

A A

12V POWER INPUT

12V to 5V PMIC

4A

RT

SYNC LX2

PG

MODE BST

FUSE_12V ZENER_12V

LX1

VCC12V_EXT

VCC_12V

VCC_PMIC

VCC_12V

VCCOUT

VCC_PMIC

SCH Title :

Size

Document Number R ev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

420

Monday, April 01, 2019

5V POWER INPUT

VJYM SPPD

SW1

500SSP1S2M2QEA

1

2

3

C1

22uF

C3

4.7uF

J16

HDR_1X2

1

2

R5

0E

U1

S6BP201A1AST2B000

PGND1

1

PVIN

3

BST

4

VIN

5

ENA

6

MODE

7

VCC

8

GND

9

PG

10

SYNC

11

RT

12

FB

13

PGND2

16

EP

17

VOUT

14

LX1

2

LX2

15

TP4

THRU HOLE

R13

0E

C10

0.1uF

J1

HDR_1X2

1

2

D3

SMAJ12CA

2 1

C60

0.1uF

FL2 30E

BLM21PG300SH1D

1 2

C6 0.1uF

J3

CON_PWRJACK3_RAPC722

1

2

3

C22

0.1uF

J2

HDR_1X2

1

2

TP8

5002

R4 1M_1%

C21

0.1uF

C2

22uF

R15

0E

DNI

L1 2.2uH

D2

B120-13

2 1

C18

10uF

R3

22K

F1

1.6A

1 2

C23

1uF

C24

47uF

+

C25

100uF_25V

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 20

Figure A-4. 3V3 LDO Regulator

5

4

3

2

1

D D

C C

B B

A A

3V3 LDO REGULATOR

LED5V

VCC_12V

VCC_LDO

VCC_PMIC VCC VCC_LDO

VCC

SCH Title :

Size

Document Number R ev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

520

Monday, April 01, 2019

3V3 LDO REGULATOR

VJYM SPPD

R21 220E

TP5

THRU HOLE

C61

10 uF

C62

22 uF

C64

0.1uF

LD2

LTST-C150GKT

2 1

U12

NCP1117DT33T5G

1

GND

OUT

2

IN

3

J23

3 Pin Jumper

1 2 3

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 21

Figure A-5. Debug Interface

5

4

3

2

1

D D

C C

B B

A A

DEBUG INTERFACE

ARM ETM MICTOR

ARM STANDARD JTAG

CORTEX DEBUG + ETM

CORTEX DEBUG

TRSTN SWDOE_TDI SWDIO_TMS SWCLK_TCLK

SWO_TDO SRST_IDC20

NRST_CORTEX20

TRSTN

TRACE_CTL TRACE_DATA_0

SRST_MICTOR SWO_TDO

SWCLK_TCLK SWDIO_TMS SWDOE_TDI

TRACE_CLOCK

TRACE_DATA_3 TRACE_DATA_2 TRACE_DATA_1

NRST_CORTEX20

TRSTN

NRST_CORTEX10SRST_IDC20

TRSTN

SRST_MICTOR

TRSTN

SWDIO_TMS

SWO_TDO

SWCLK_TCLK

SWDOE_TDI NRST_CORTEX10

VCC

VCCVCC

VCC

TRACE_CLOCK {13,19} TRACE_DATA_0 {14,19} TRACE_DATA_1 {14,19} TRACE_DATA_2 {14,19} TRACE_DATA_3 {14,19}

SWDIO_TMS {14,19} SWCLK_TCLK {14,19} SWO_TDO {14,19} SWDOE_TDI {14,19}

CPU_XRES {6,7,14,18}

CPU_XRES {6,7,14,18}CPU_XRES {6,7,14,18}

CPU_XRES {6,7,14,18}

TRSTN {9,19}

SCH Title :

Size

Document Number

Rev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956

C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

620

Monday, April 01, 2019

DEBUG INTERFACE

VJYM SPPD

R67 0ER79 0E

R77

10K

R87 20E

R86

10K

DNI

R55

10K

R82

10K

R61

0E

R74

10K

R58 0E

R69 0E

DNI

R68 0E

DNI

J18

CON_BOX_2X10_M

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

R80 0E

DNI

R92 0E

J19

CON_BOX_2X5_M

1 3 5 7 9

2 4 6 8 10

R72

10K

C46

0.1uF

R84

10K

DNI

TP9

THRU HOLE

C47

0.1uF

C45

0.1uF

R91

10K

DNI

R83

10K

DNI

R76 0EDNI

J17

CON_MICTOR_2X19_F

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37

394041

42

43

R51 20E

R85

10K

DNI

R88

10K

DNI

R75

10K

DNI

R90 0E

DNI

R57 20E

R73

10K

J20

CON_BOX_2X10_M

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

R81

10K

R64

0E

R63 10K

R78

10K

DNI

R89

10K

DNI

C48

0.1uF

LD6

LTST-C150GKT

21

R59 0E

R49

220E

R70 0E

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 22

Figure A-6. UART to USB & RESERT

5

4

3

2

1

D D

C C

B B

A A

OVERLAP THE VCCIO_USB PADS OF R25 & R26

DEFAULT CLOSE

USB TO UART TRANSCEIVER

DEFAULT CLOSE

RESET CONTROLLER

PLACE NEAR PLACE NEAR

DEFAULT CLOSE

SENSE PIN

VDD PIN

CTS RTS

DTR DSR

DCD

RI

RST_UART

TXLED RXLED

VCCD

TXD RXD

RST_OUTRST_SW RST_MR

RST_MR

CT

USBDM_CONN USBDP_CONN

USBDM

USBDP

USBDP USBDM

VCCIO_USB

USB_VIN

VCCIO_USB

VCC_USB

VCC

VCCVCC

VCC

VCCIO_USB

CPU_XRES {6,14,18}

UART_SCB3_RX{12,16}

UART_SCB3_TX{12,16}

SCH Title :

Size

Document Number Re v

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

720

Monday, April 01, 2019

UART TO USB & RESET

VJYM SPPD

C11

1000pF

C29

4.7uF

R24 220E

R27 0E

J11

HDR_1X2

1

2

C15

0.1uF

DNI

J9 HDR_1X2

1

2

R31

10K

DNI

R23 1K

R14

10K

J13

HDR_1X2

1

2

LD3

LTST-C150GKT

21

J12 CON_MUSB-B_5_F

VBUS

1

D+

3

D-

2

ID

4

SH1

SH2

GND

5

TP6

THRU HOLE

FL4 600E

1 2

R29 0E

DNI

D1

SD05C-01FTG

12

R19 22K

C30

1uF

SW2

1

3

2

4

R26 0E

R9

10K

R99 0E

DNI

R97 0E

DNI

LD4

LTST-C150GKT

21

R20 100E_1%

LD1

LTST-C150GKT

2 1

L2

90E

1

3

2

4

R8 220E

C7

0.1uF

C26

4.7uF

C34

10000pF

C28

0.1uF

R98 0E

C27

0.1uF

R22 220E

FL3

600E

12

U2

TPS3808G50DBVT

RESET

1

GND

2

MR

3

CT

4

SENSE

5

VDD

6

R30

4.7K

DNI

U5

CY7C65213-28PVXI

TXD

1

RTS#

3

VCCIO

4

RXD

5

GND

7

GPIO5

8

DCD#

10

CTS#

11

GPIO4

12

GPIO2

13

GPIO3

14

VCCD

17

GND

18

RESET#

19

GND

21

GPIO1

22

GPIO0

23

NC1

24

NC2

25

DNU

26

GPIO6

27

GPIO7

28

VCC

20

USBDP

15

USBDM

16

RI#

6

DTR#

2

DSR#

9

R25

0E

DNI

C13

0.1uF

R28 0E

DNI

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 23

Figure A-7. GPIO, Clock, and Filter

5

4

3

2

1

D D

C C

B B

A A

Damping resistor, need to be tuned

The return path from Capacitor, must be wired to the VSSA

USER LED

PUSH BUTTON

RC FILTER

ECO & WCO

DEFAULT CLOSE

GPIO_LED

GPIO_SW

VCC

GPIO_038{11}

GPIO_039{11}

GPIO_040{11}

CPU_WCO_IN {18} CPU_WCO_OUT {18} CPU_ECO_IN {18} CPU_ECO_OUT {18}

BB_CAN2_RXD_N{11,18}

BB_CAN2_TXD_N{11}

ECI/BTB{8,14}

WCI/BTB{8,14}

WCO/BTB{8,14}

ECI/BTB{8,14} ECO/BTB{8,14}

WCI/BTB{8,14}

ECI/BTB {8,14}

ECO/BTB {8,14}

WCO/BTB{8,14}

GPIO_082 {16}

GPIO_083 {16}

GPIO_084 {16}

BB_CAN2_RXD {16}

BB_CAN2_TXD {16}

GPIO_018 {10,16,19}

GPIO_023{10,16,19}

SCH Title :

Size

Document Number R ev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

820

Monday, April 01, 2019

GPIO,CLOCK AND FILTER

VJYM SPPD

R44 0E

Y2

16.000MHz

1

4 2

3

TPS5

TPS3

C41

0.1uF

DNI

C43

0.1uF

DNI

R40 0E

TPS1

C42

0.1uF

DNI

Y1

32.768KHz

1 4

2 3

R45 0E

TPS4

R48 20E

R11 0EDNI

R16 0EDNI

R47

10K

R12 0EDNI

TPS6

R32 0E

C44

0.1uF

LD5

LTST-C150GKT

2 1

C38

0.1uF

DNI

R18 0EDNI

R39 0E

C4

12pF

J7

CON_MCXJACK5_F

2

1

3 4 5

J14

HDR_1X2

1

2

C5

12pF

R17 0EDNI

R46 1K

C9 10pF

TPS7

J15

HDR_1X2

1

2

SW3

PTS810 SJG 250 SMTR LFS

1

3

2

4

C8 10pF

TPS2

C40

0.1uF

DNI

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 24

Figure A-8. LQFP-176 P1

5

4

3

2

1

D D

C C

B B

A A

BB_LIN1_RX{18}

BB_LIN1_SLP{17,18}

BB_CAN1_TXD{17,18}

BB_LIN1_TX{18}

BB_CAN7_TXD{17,18} BB_CAN1_RXD{17,18}

TRSTN{6,19}

BB_LIN0_TX{18}

BB_LIN0_SLP{18}

BB_CAN7_RXD{17,18}

BB_CAN2_S{16}

BB_CAN3_S{16}

BB_CAN6_WAKE{16}

GPIO_001{16}

GPIO_002{16}

GPIO_003{16}

GPIO_004{16}

GPIO_005{16}

GPIO_006{16}

GPIO_007{16}

GPIO_008{16}

GPIO_009{16}

GPIO_010{16}

GPIO_011{16}

GPIO_012{16}

GPIO_014{16}

GPIO_015{16}

GPIO_013{16}

SCH Title :

Size

Document Number Rev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

920

Monday, April 01, 2019

LQFP-176 P1

VJYM SPPD

U4A

LQFP_176_1M_B0

P0.0_PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA/SCB0_MISO/LIN1_RX

2

P0.1_PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL/SCB0_MOSI/LIN1_TX

3

P0.2_PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/LIN1_EN/CAN0_1_TX

4

P0.3_PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/CAN0_1_RX

5

P1.0_PWM_12/PWM_13_N/TC_12_TR0/TC_13_TR1/SCB0_SCL/SCB0_MISO

6

P1.1_PWM_11/PWM_12_N/TC_11_TR0/TC_12_TR1/SCB0_SDA/SCB0_MOSI

7

P1.2_PWM_10/PWM_11_N/TC_10_TR0/TC_11_TR1/SCB0_CLK/TRIG_IN[0]

8

P1.3_PWM_8/PWM_10_N/TC_8_TR0/TC_10_TR1/SCB0_SEL0/TRIG_IN[1]

9

P2.0_PWM_7/PWM_8_N/TC_7_TR0/TC_8_TR1/SCB7_RX/SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2]

10

P2.1_PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/SCB7_TX/SCB7_SDA/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3]

11

P2.2_PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/SCB7_RTS/SCB7_SCL/SCB0_SEL3/SCB7_CLK/LIN0_EN/TRIG_IN[4]

12

P2.3_PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/SCB7_CTS/SCB7_SEL0/LIN5_RX/TRIG_IN[5]

13

P2.4_PWM_3/PWM_4_N/TC_3_TR0/TC_4_TR1/SCB7_SEL1/LIN5_TX/TRIG_IN[6]

14

P2.5_PWM_2/PWM_3_N/TC_2_TR0/TC_3_TR1/SCB7_SEL2/LIN5_EN/TRIG_IN[7]

15

P3.0_PWM_1/PWM_2_N/TC_1_TR0/TC_2_TR1/SCB6_RX/SCB6_MISO/TRIG_DBG[0]

16

P3.1_PWM_0/PWM_1_N/TC_0_TR0/TC_1_TR1/SCB6_TX/SCB6_SDA/SCB6_MOSI/TRIG_DBG[1]

17

P3.2_PWM_M_3/PWM_0_N/TC_M_3_TR0/TC_0_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK

18

P3.3_PWM_M_2/PWM_M_3_N/TC_M_2_TR0/TC_M_3_TR1/SCB6_CTS/SCB6_SEL0

19

P3.4_PWM_M_1/PWM_M_2_N/TC_M_1_TR0/TC_M_2_TR1/SCB6_SEL1

20

P3.5_PWM_M_0/PWM_M_1_N/TC_M_0_TR0/TC_M_1_TR1/SCB6_SEL2

21

P4.0_PWM_4/PWM_M_0_N/TC_4_TR0/TC_M_0_TR1/EXT_MUX[0]_0/SCB5_RX/SCB5_MISO/LIN1_RX/TRIG_IN[10]

24

P4.1_PWM_5/PWM_4_N/TC_5_TR0/TC_4_TR1/EXT_MUX[0]_1/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN1_TX/TRIG_IN[11]

25

P4.2_PWM_6/PWM_5_N/TC_6_TR0/TC_5_TR1/EXT_MUX[0]_2/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN1_EN/TRIG_IN[12]

26

P4.3_PWM_7/PWM_6_N/TC_7_TR0/TC_6_TR1/EXT_MUX[0]_EN/SCB5_CTS/SCB5_SEL0/CAN0_1_TX/TRIG_IN[13]

27

P4.4_PWM_8/PWM_7_N/TC_8_TR0/TC_7_TR1/SCB5_SEL1/CAN0_1_RX

28

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 25

Figure A-9. LQFP-176 P2

5

4

3

2

1

D D

C C

B B

A A

BB_LIN2_RX{18}

BB_LIN3_RX{19}

BB_LIN3_TX{19}

BB_LIN3_SLP{17,19}

BB_LIN4_RX{17,19}

BB_LIN4_TX{19}

BB_LIN4_SLP{8,16,19}

BB_CAN_SPI1_MISO{18}

BB_CAN_SPI1_MOSI{18}

BB_CAN_SPI1_CLK{18}

BB_CAN_SPI1_SS0{16}

BB_CAN_SPI1_SS1{16}

BB_CAN8_TXD{17,19}

BB_CAN8_RXD{17,19}

BB_CAN_SPI1_SS2{16}

BB_CAN0_TXD{17,18}

BB_LIN2_TX{17,18} BB_CAN0_RXD{17,18} BB_CAN6_RXD{17,18}

BB_LIN2_SLP{8,16,19}

BB_CAN6_TXD{17,18}

BB_CAN7_WAKE{16}

BB_CAN8_WAKE{17}

BB_CAN9_WAKE{17}

GPIO_016{16}

GPIO_017{16}

GPIO_019{16}

GPIO_020{17}

GPIO_021{17}

GPIO_022{17}

GPIO_018{8,16,19}

GPIO_023{8,16,19}

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

SCH Title :

Size

Document Number R ev

Date: Sheet of

Page Title :

Drawn By Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

10 20

Monday, April 01, 2019

LQFP-176 P2

VJYM SPPD

U4B

LQFP_176_1M_B0

P5.0_PWM_9/PWM_8_N/TC_9_TR0/TC_8_TR1/SCB5_SEL2/LIN7_RX

29

P5.1_PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1/LIN7_TX

30

P5.2_PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1/LIN7_EN

31

P5.3_PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1/LIN2_RX

32

P5.4_PWM_13/PWM_12_N/TC_13_TR0/TC_12_TR1/LIN2_TX

33

P5.5_PWM_14/PWM_13_N/TC_14_TR0/TC_13_TR1/LIN2_EN

34

P6.0_PWM_M_0/PWM_14_N/TC_M_0_TR0/TC_14_TR1/SCB4_RX/SCB4_MISO/LIN3_RX/ADC[0]_0

35

P6.1_PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1

36

P6.2_PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/CAN0_2_TX/ADC[0]_2

37

P6.3_PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SCB4_CTS/SCB4_SEL0/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3

38

P6.4_PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SCB4_SEL1/LIN4_TX/ADC[0]_4

39

P6.5_PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5

40

P6.6_PWM_M_3/PWM_2_N/TC_M_3_TR0/TC_2_TR1/SCB4_SEL3/TRIG_IN[8]/ADC[0]_6

41

P6.7_PWM_3/PWM_M_3_N/TC_3_TR0/TC_M_3_TR1/TRIG_IN[9]/ADC[0]_7

42

P7.0_PWM_M_4/PWM_3_N/TC_M_4_TR0/TC_3_TR1/SCB5_RX/SCB5_MISO/LIN4_RX/ADC[0]_8

48

P7.1_PWM_15/PWM_M_4_N/TC_15_TR0/TC_M_4_TR1/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN4_TX/ADC[0]_9

49

P7.2_PWM_M_5/PWM_15_N/TC_M_5_TR0/TC_15_TR1/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN4_EN/ADC[0]_10

50

P7.3_PWM_16/PWM_M_5_N/TC_16_TR0/TC_M_5_TR1/SCB5_CTS/SCB5_SEL0/ADC[0]_11

51

P7.4_PWM_M_6/PWM_16_N/TC_M_6_TR0/TC_16_TR1/SCB5_SEL1/ADC[0]_12

52

P7.5_PWM_17/PWM_M_6_N/TC_17_TR0/TC_M_6_TR1/SCB5_SEL2/ADC[0]_13

53

P7.6_PWM_M_7/PWM_17_N/TC_M_7_TR0/TC_17_TR1/TRIG_IN[16]/ADC[0]_14

54

P7.7_PWM_18/PWM_M_7_N/TC_18_TR0/TC_M_7_TR1/TRIG_IN[17]/ADC[0]_15

55

P8.0_PWM_19/PWM_18_N/TC_19_TR0/TC_18_TR1/LIN2_RX/CAN0_0_TX

56

P8.1_PWM_20/PWM_19_N/TC_20_TR0/TC_19_TR1/LIN2_TX/CAN0_0_RX/TRIG_IN[14]/ADC[0]_16

57

P8.2_PWM_21/PWM_20_N/TC_21_TR0/TC_20_TR1/LIN2_EN/TRIG_IN[15]/ADC[0]_17

58

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 26

Figure A-10. LQFP-176 P3

5

4

3

2

1

D D

C C

B B

A A

BB_CAN2_TXD_N{8}

BB_LIN5_SLP{8,18}

BB_CAN2_RXD_N{8,18}

BB_LIN5_RX{18}

BB_LIN5_TX{18}

BB_CAN4_S{16}

BB_USER_BUTTON_4{16}

GPIO_024{17}

GPIO_025{16}

GPIO_026{16}

GPIO_027{16}

GPIO_028{16}

GPIO_029{16}

GPIO_034{18}

GPIO_035{18}

GPIO_036{18}

GPIO_037{18}

GPIO_038{8}

GPIO_039{8}

GPIO_040{8}

GPIO_041{18}

GPIO_042{19}

GPIO_043{19}

GPIO_030{16}

GPIO_032{18}

GPIO_031{16}

GPIO_033{18}

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

SCH Title :

Size

Document Number R ev

Date: Sheet of

Page Title :

Drawn By Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

11 20

Monday, April 01, 2019

LQFP-176 P3

VJYM SPPD

U4C

LQFP_176_1M_B0

P8.3_PWM_22/PWM_21_N/TC_22_TR0/TC_21_TR1/TRIG_DBG[0]/ADC[0]_18

59

P8.4_PWM_23/PWM_22_N/TC_23_TR0/TC_22_TR1/TRIG_DBG[1]/ADC[0]_19

60

P9.0_PWM_24/PWM_23_N/TC_24_TR0/TC_23_TR1/ADC[0]_20

61

P9.1_PWM_25/PWM_24_N/TC_25_TR0/TC_24_TR1/ADC[0]_21

62

P9.2_PWM_26/PWM_25_N/TC_26_TR0/TC_25_TR1/ADC[0]_22

63

P9.3_PWM_27/PWM_26_N/TC_27_TR0/TC_26_TR1/ADC[0]_23

64

P10.0_PWM_28/PWM_27_N/TC_28_TR0/TC_27_TR1/SCB4_RX/SCB4_MISO/TRIG_IN[18]

65

P10.1_PWM_29/PWM_28_N/TC_29_TR0/TC_28_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/TRIG_IN[19]

66

P10.2_PWM_30/PWM_29_N/TC_30_TR0/TC_29_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK

67

P10.3_PWM_31/PWM_30_N/TC_31_TR0/TC_30_TR1/SCB4_CTS/SCB4_SEL0

68

P10.4_PWM_32/PWM_31_N/TC_32_TR0/TC_31_TR1/SCB4_SEL1/ADC[1]_0

69

P10.5_PWM_33/PWM_32_N/TC_33_TR0/TC_32_TR1/SCB4_SEL2/ADC[1]_1

70

P10.6_PWM_34/PWM_33_N/TC_34_TR0/TC_33_TR1/ADC[1]_2

71

P10.7_PWM_35/PWM_34_N/TC_35_TR0/TC_34_TR1/ADC[1]_3

72

P11.0_ADC[0]_M

73

P11.1_ADC[1]_M

74

P11.2_ADC[2]_M

75

P12.0_PWM_36/PWM_35_N/TC_36_TR0/TC_35_TR1/CAN0_2_TX/TRIG_IN[20]/ADC[1]_4

80

P12.1_PWM_37/PWM_36_N/TC_37_TR0/TC_36_TR1/LIN6_EN/CAN0_2_RX/TRIG_IN[21]/ADC[1]_5

81

P12.2_PWM_38/PWM_37_N/TC_38_TR0/TC_37_TR1/EXT_MUX[1]_EN/LIN6_RX/ADC[1]_6

82

P12.3_PWM_39/PWM_38_N/TC_39_TR0/TC_38_TR1/EXT_MUX[1]_0/LIN6_TX/ADC[1]_7

83

P12.4_PWM_40/PWM_39_N/TC_40_TR0/TC_39_TR1/EXT_MUX[1]_1/ADC[1]_8

84

P12.5_PWM_41/PWM_40_N/TC_41_TR0/TC_40_TR1/EXT_MUX[1]_2/ADC[1]_9

85

P12.6_PWM_42/PWM_41_N/TC_42_TR0/TC_41_TR1/ADC[1]_10

86

P12.7_PWM_43/PWM_42_N/TC_43_TR0/TC_42_TR1/ADC[1]_11

87

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 27

Figure A-11. LQFP-176 P4

5

4

3

2

1

D D

C C

B B

A A

UART_SCB3_RX{7,16}

UART_SCB3_TX{7,16}

BB_CAN3_TXD{17,19} BB_CAN9_TXD{17,19}

BB_CAN3_RXD{17,19} BB_CAN9_RXD{17,19}

BB_CAN4_TXD{17}

BB_CAN4_RXD{17}

BB_CAN5_S{16,19} BB_USER_LED6{16,19} BB_LIN0_WAKE{18,19} BB_USER_LED7{18,19} BB_LIN1_WAKE{18} BB_USER_LED8{18} BB_LIN2_WAKE{18} BB_USER_LED9{18} BB_LIN3_WAKE{19}

BB_USER_BUTTON_1{19}

BB_LIN4_WAKE{19}

BB_USER_BUTTON_2{19}

BB_LIN5_WAKE{18,19}

BB_USER_BUTTON_3{18,19}

BB_USER_LED5{19}

GPIO_044{19}

GPIO_045{19}

GPIO_046{19}

GPIO_047{19}

GPIO_048{19}

GPIO_049{19}

GPIO_050{19}

GPIO_051{19}

GPIO_052{19}

GPIO_053{19}

GPIO_054{19}

GPIO_055{19}

SCH Title :

Size

Document Number R ev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

12 20

Monday, April 01, 2019

LQFP-176 P4

VJYM SPPD

U4D

LQFP_176_1M_B0

P13.0_PWM_M_8/PWM_43_N/TC_M_8_TR0/TC_43_TR1/EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12

90

P13.1_PWM_44/PWM_M_8_N/TC_44_TR0/TC_M_8_TR1/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13

91

P13.2_PWM_M_9/PWM_44_N/TC_M_9_TR0/TC_44_TR1/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14

92

P13.3_PWM_45/PWM_M_9_N/TC_45_TR0/TC_M_9_TR1/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15

93

P13.4_PWM_M_10/PWM_45_N/TC_M_10_TR0/TC_45_TR1/SCB3_SEL1/ADC[1]_16

94

P13.5_PWM_46/PWM_M_10_N/TC_46_TR0/TC_M_10_TR1/SCB3_SEL2/ADC[1]_17

95

P13.6_PWM_M_11/PWM_46_N/TC_M_11_TR0/TC_46_TR1/SCB3_SEL3/TRIG_IN[22]/ADC[1]_18

96

P13.7_PWM_47/PWM_M_11_N/TC_47_TR0/TC_M_11_TR1/TRIG_IN[23]/ADC[1]_19

97

P14.0_PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/SCB2_RX/SCB2_MISO/CAN1_0_TX/ADC[1]_20

98

P14.1_PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/SCB2_TX/SCB2_SDA/SCB2_MOSI/CAN1_0_RX/ADC[1]_21

99

P14.2_PWM_50/PWM_49_N/TC_50_TR0/TC_49_TR1/SCB2_RTS/SCB2_SCL/SCB2_CLK/LIN6_RX/ADC[1]_22

100

P14.3_PWM_51/PWM_50_N/TC_51_TR0/TC_50_TR1/SCB2_CTS/SCB2_SEL0/LIN6_TX/ADC[1]_23

101

P14.4_PWM_52/PWM_51_N/TC_52_TR0/TC_51_TR1/SCB2_SEL1/LIN6_EN/ADC[1]_24

102

P14.5_PWM_53/PWM_52_N/TC_53_TR0/TC_52_TR1/SCB2_SEL2/ADC[1]_25

103

P14.6_PWM_54/PWM_53_N/TC_54_TR0/TC_53_TR1/TRIG_IN[24]/ADC[1]_26

104

P14.7_PWM_55/PWM_54_N/TC_55_TR0/TC_54_TR1/TRIG_IN[25]/ADC[1]_27

105

P15.0_PWM_56/PWM_55_N/TC_56_TR0/TC_55_TR1/ADC[1]_28

106

P15.1_PWM_57/PWM_56_N/TC_57_TR0/TC_56_TR1/ADC[1]_29

107

P15.2_PWM_58/PWM_57_N/TC_58_TR0/TC_57_TR1/ADC[1]_30

108

P15.3_PWM_59/PWM_58_N/TC_59_TR0/TC_58_TR1/ADC[1]_31

109

P16.0_PWM_60/PWM_59_N/TC_60_TR0/TC_59_TR1/PWM_H_0

112

P16.1_PWM_61/PWM_60_N/TC_61_TR0/TC_60_TR1/PWM_H_0_N

113

P16.2_PWM_62/PWM_61_N/TC_62_TR0/TC_61_TR1/PWM_H_1

114

P16.3_PWM_62/PWM_62_N/TC_62_TR0/TC_62_TR1/PWM_H_1_N

115

P17.0_PWM_61/PWM_62_N/TC_61_TR0/TC_62_TR1/CAN1_1_TX

116

P17.1_PWM_60/PWM_61_N/TC_60_TR0/TC_61_TR1/PWM_H_2/SCB3_RX/SCB3_MISO/CAN1_1_RX

117

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 28

Figure A-12. LQFP-176 P5

5

4

3

2

1

D D

C C

B B

A A

(12,21,23)

BB_SPI0_MISO{19}

BB_SPI0_MOSI{19}

BB_SPI0_CLK{16}

TRACE_CLOCK{6,19}

BB_SPI0_SS{16}

BB_CAN5_TXD{17}

BB_CAN5_RXD{17}

BB_USER_LED4{18,19}

BB_SPI0_WP{18,19}

GPIO_061{18,19}

BB_USER_LED3{19}

BB_USER_LED2{19}

BB_CAN0_S{18,19}

BB_CAN1_S{16,18}

BB_SPI0_HOLD{18,19}

BB_USER_BUTTON_5{18,19}

GPIO_056{19}

GPIO_057{19}

GPIO_058{19}

GPIO_059{19}

GPIO_060{19}

GPIO_062{19}

GPIO_063{19}

GPIO_064{19}

GPIO_065{19}

GPIO_066{19}

GPIO_067{19}

GPIO_068{19}

GPIO_069{19}

BB_USER_LED0{16,18}

SCH Title :

Size

Document Number R ev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

13 20

Monday, April 01, 2019

LQFP-176 P5

VJYM SPPD

U4E

LQFP_176_1M_B0

P17.2_PWM_59/PWM_60_N/TC_59_TR0/TC_60_TR1/PWM_H_2_N/SCB3_TX/SCB3_SDA/SCB3_MOSI

118

P17.3_PWM_58/PWM_59_N/TC_58_TR0/TC_59_TR1/PWM_H_3/SCB3_RTS/SCB3_SCL/SCB3_CLK/TRIG_IN[26]

119

P17.4_PWM_57/PWM_58_N/TC_57_TR0/TC_58_TR1/PWM_H_3_N/SCB3_CTS/SCB3_SEL0/TRIG_IN[27]

120

P17.5_PWM_56/PWM_57_N/TC_56_TR0/TC_57_TR1/SCB3_SEL1

121

P17.6_PWM_M_4/PWM_56_N/TC_M_4_TR0/TC_56_TR1/SCB3_SEL2

122

P17.7_PWM_M_5/PWM_M_4_N/TC_M_5_TR0/TC_M_4_TR1

123

P18.0_PWM_M_6/PWM_M_5_N/TC_M_6_TR0/TC_M_5_TR1/PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0

124

P18.1_PWM_M_7/PWM_M_6_N/TC_M_7_TR0/TC_M_6_TR1/PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/FAULT_OUT_1/ADC[2]_1

125

P18.2_PWM_55/PWM_M_7_N/TC_55_TR0/TC_M_7_TR1/PWM_H_1/SCB1_RTS/SCB1_SCL/SCB1_CLK/ADC[2]_2

126

P18.3_PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/PWM_H_1_N/SCB1_CTS/SCB1_SEL0/TRACE_CLOCK/ADC[2]_3

127

P18.4_PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_DATA_0/ADC[2]_4

128

P18.5_PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5

129

P18.6_PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/PWM_H_3/SCB1_SEL3/CAN1_2_TX/TRACE_DATA_2/ADC[2]_6

130

P18.7_PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/PWM_H_3_N/CAN1_2_RX/TRACE_DATA_3/ADC[2]_7

131

P19.0_PWM_M_3/PWM_50_N/TC_M_3_TR0/TC_50_TR1/TC_H_0_TR0/SCB2_RX/SCB2_MISO/FAULT_OUT_2

134

P19.1_PWM_26/PWM_M_3_N/TC_26_TR0/TC_M_3_TR1/TC_H_0_TR1/SCB2_TX/SCB2_SDA/SCB2_MOSI/FAULT_OUT_3

135

P19.2_PWM_27/PWM_26_N/TC_27_TR0/TC_26_TR1/TC_H_1_TR0/SCB2_RTS/SCB2_SCL/SCB2_CLK/TRIG_IN[28]

136

P19.3_PWM_28/PWM_27_N/TC_28_TR0/TC_27_TR1/TC_H_1_TR1/SCB2_CTS/SCB2_SEL0/TRIG_IN[29]

137

P19.4_PWM_29/PWM_28_N/TC_29_TR0/TC_28_TR1/TC_H_2_TR0/SCB2_SEL1

138

P20.0_PWM_30/PWM_29_N/TC_30_TR0/TC_29_TR1/TC_H_2_TR1/SCB2_SEL2/LIN5_RX

139

P20.1_PWM_49/PWM_30_N/TC_49_TR0/TC_30_TR1/TC_H_3_TR0/LIN5_TX

140

P20.2_PWM_48/PWM_49_N/TC_48_TR0/TC_49_TR1/TC_H_3_TR1/LIN5_EN

141

P20.3_PWM_47/PWM_48_N/TC_47_TR0/TC_48_TR1/SCB1_RX/SCB1_MISO/CAN1_2_TX

142

P20.4_PWM_46/PWM_47_N/TC_46_TR0/TC_47_TR1/SCB1_TX/SCB1_SDA/SCB1_MOSI/CAN1_2_RX

143

P20.5_PWM_45/PWM_46_N/TC_45_TR0/TC_46_TR1/SCB1_RTS/SCB1_SCL/SCB1_CLK

144

P20.6_PWM_44/PWM_45_N/TC_44_TR0/TC_45_TR1/SCB1_CTS/SCB1_SEL0

145

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 29

Figure A-13. LQFP-176 P6

Document Number

Rev

C

5

4

3

2

1

D D

C C

B B

A A

VCC

WCO/BTB{8}

WCI/BTB{8}

ECI/BTB{8}

ECO/BTB{8}

CPU_XRES{6,7,14,18}

BB_LIN0_RX{18}

TRACE_DATA_0{6,19}

TRACE_DATA_1{6,19}

TRACE_DATA_2{6,19}

TRACE_DATA_3{6,19}

CPU_XRES{6,7,14,18}

SWO_TDO{6,19}

SWCLK_TCLK{6,19}

SWDIO_TMS{6,19}

SWDOE_TDI{6,19}

BB_USER_LED1{19}

GPIO_070{19}

GPIO_071{19}

GPIO_072{19}

GPIO_073{18}

GPIO_074{19}

GPIO_075{19}

GPIO_076{19}

GPIO_077{19}

GPIO_078{19}

GPIO_079{18}

GPIO_080{18}

SCH Title :

Size

Date:

Sheet o f

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

14 20

Monday, April 01, 2019

LQFP-176 P6

VJYM SPPD

R6

4.7K

U4F

LQFP_176_1M_B0

P20.7_PWM_43/PWM_44_N/TC_43_TR0/TC_44_TR1/SCB1_SEL1

146

P21.0_PWM_42/PWM_43_N/TC_42_TR0/TC_43_TR1/SCB1_SEL2/WCO_IN

147

P21.1_PWM_41/PWM_42_N/TC_41_TR0/TC_42_TR1/WCO_OUT

148

P21.2_PWM_40/PWM_41_N/TC_40_TR0/TC_41_TR1/TRIG_DBG[1]/EXT_CLK/ECO_IN

149

P21.3_PWM_39/PWM_40_N/TC_39_TR0/TC_40_TR1/ECO_OUT

150

P21.4_PWM_38/PWM_39_N/TC_38_TR0/TC_39_TR1/HIBERNATE_WAKEUP[0]

151

XRES

152

P21.5_PWM_37/PWM_38_N/TC_37_TR0/TC_38_TR1/LIN0_RX

157

P21.6_PWM_36/PWM_37_N/TC_36_TR0/TC_37_TR1/LIN0_TX

158

P21.7_PWM_35/PWM_36_N/TC_35_TR0/TC_36_TR1/LIN0_EN/CAL_SUP_NZ/RTC_CAL

159

P22.0_PWM_34/PWM_35_N/TC_34_TR0/TC_35_TR1/SCB6_RX/SCB6_MISO/CAN1_1_TX/TRACE_DATA_0

160

P22.1_PWM_33/PWM_34_N/TC_33_TR0/TC_34_TR1/SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN1_1_RX/TRACE_DATA_1

161

P22.2_PWM_32/PWM_33_N/TC_32_TR0/TC_33_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK/TRACE_DATA_2

162

P22.3_PWM_31/PWM_32_N/TC_31_TR0/TC_32_TR1/SCB6_CTS/SCB6_SEL0/TRACE_DATA_3

163

P22.4_PWM_30/PWM_31_N/TC_30_TR0/TC_31_TR1/SCB6_SEL1/TRACE_CLOCK

164

P22.5_PWM_29/PWM_30_N/TC_29_TR0/TC_30_TR1/SCB6_SEL2/LIN7_RX

165

P22.6_PWM_28/PWM_29_N/TC_28_TR0/TC_29_TR1/LIN7_TX

166

P22.7_PWM_27/PWM_28_N/TC_27_TR0/TC_28_TR1/LIN7_EN

167

P23.0_PWM_M_8/PWM_27_N/TC_M_8_TR0/TC_27_TR1/SCB7_RX/SCB7_MISO/CAN1_0_TX/FAULT_OUT_0

168

P23.1_PWM_M_9/PWM_M_8_N/TC_M_9_TR0/TC_M_8_TR1/SCB7_TX/SCB7_SDA/SCB7_MOSI/CAN1_0_RX/FAULT_OUT_1

169

P23.2_PWM_M_10/PWM_M_9_N/TC_M_10_TR0/TC_M_9_TR1/SCB7_RTS/SCB7_SCL/SCB7_CLK/FAULT_OUT_2

170

P23.3_PWM_M_11/PWM_M_10_N/TC_M_11_TR0/TC_M_10_TR1/SCB7_CTS/SCB7_SEL0/FAULT_OUT_3/TRIG_IN[30]

171

P23.4_PWM_25/PWM_M_11_N/TC_25_TR0/TC_M_11_TR1/SCB7_SEL1/TRIG_DBG[0]/SWJ_SWO_TDO/TRIG_IN[31]

172

P23.5_PWM_24/PWM_25_N/TC_24_TR0/TC_25_TR1/SCB7_SEL2/SWJ_SWCLK_TCLK

173

P23.6_PWM_23/PWM_24_N/TC_23_TR0/TC_24_TR1/SWJ_SWDIO_TMS

174

P23.7_PWM_22/PWM_23_N/TC_22_TR0/TC_23_TR1/CAL_SUP_NZ/SWJ_SWDOE_TDI/EXT_CLK/HIBERNATE_WAKEUP[1]

175

C49

1nF

R7

4.7K

DNI

R10 0E

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 30

Figure A-14. LQFP-176 P7

5

4

3

2

1

D D

C C

B B

A A

PROCESSOR POWER

DEFAULT CLOSE

On each VDDIO/VSSIO

TEST POINTS

ANALOG REFERENCE

pin pair a 4.7uF and a 0.1uF is required

On each VDDIO/VSSIO pin pair a 10uF and a 0.1uF

is required

4.7uF capacitor needs to be placed near pin 156

Place one 0.1uF capacitor near each of the VCCD pins

CPU_BB_VDDA

CPU_BB_VDDD

VCC

CPU_BB_VDDIO

VCC_FL

CPU_BB_VDDA

CPU_BB_VDDD CPU_BB_VDDIO

CPU_VCCD

CPU_VREFL {16}

CPU_VREFH {16}

VREFL_N{15}

VREFH_N{15}

VREFL_N {15} VREFH_N {15}

SCH Title :

Size

Document Number

Rev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956

C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

15 20

Monday, April 01, 2019

LQFP-176 P7

VJYM SPPD

TP7

+

C32

4.7uF_20V

+

C39

2.2uF_16V

TP2

C50

0.1uF

+

C35

4.7uF_20V

+

C59

4.7uF_20V

U4G

LQFP_176_1M_B0

VCCD

47

VCCD

156

VREFL

76

VREFH

79

VDDA

78

VDDD

43

VDDD

153

VDDD

22

VDDIO_1

44

VDDIO_2

88

VDDD

110

VDDD

132

VDDD

176

VSSD

133

VSSD

111

VSSD

89

VSSD

45

VSSD

23

VSSD

1

VSSA

77

VSSD

46

VSSD

154

VSSD

155

J6

HDR_1X2

1

2

+

C52

4.7uF_20V

C33

0.1uF

C31

0.1uF

C17

0.1uF

R41 0E

DNI

TP3

R43 0E

R42 0E

DNI

+

C53

4.7uF_20V

+

C14

4.7uF_20V

C55

0.1uF

+

C56

10uF_16V

C57

0.1uF

C37

0.1uF

+

C19

4.7uF_20V

C58

0.1uF

+

C51

10uF_16V

C12

4.7uF

TP1

C20

0.1uF

C16

0.1uF

J5

HDR_1X2

1

2

J10

HDR_1X2

1

2

R38 0E

J8

HDR_1X2

1

2

FL1 30E

BLM21PG300SH1D

1 2

C36

0.1uF

C54

0.1uF

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 31

Figure A-15. Board to Board Connector- J22A

5

4

3

2

1

D D

C C

B B

A A

BOARD TO BOARD CONNECTOR

This connects to J84

on the TVII Base board

(12,18,23)

BB_CAN_SPI1_SS0 {10} BB_CAN_SPI1_SS1 {10} BB_CAN_SPI1_SS2 {10}

BB_CAN2_TXD {8}

UART_SCB3_TX {7,12}

BB_SPI0_CLK {13}

BB_SPI0_SS {13}

BB_CAN2_RXD {8}

UART_SCB3_RX {7,12}

BB_CAN6_WAKE {9} BB_CAN7_WAKE {10}

BB_CAN2_S {9} BB_CAN3_S {9} BB_CAN4_S {11} BB_CAN5_S {12,19}

BB_USER_BUTTON_4 {11}

GPIO_018{8,10,19}

GPIO_082{8} GPIO_083{8}

GPIO_084{8}

CPU_VREFL{15}

CPU_VREFH{15}

GPIO_025{11} GPIO_026{11}

GPIO_027{11} GPIO_028{11} GPIO_029{11}

GPIO_030{11}

GPIO_001 {9} GPIO_002 {9} GPIO_003 {9} GPIO_004 {9}

GPIO_005 {9} GPIO_006 {9}

GPIO_007 {9} GPIO_008 {9} GPIO_009 {9} GPIO_010 {9}

GPIO_011 {9} GPIO_012 {9} GPIO_013 {9} GPIO_014 {9}

GPIO_015 {9} GPIO_016 {10}

GPIO_017 {10} GPIO_019 {10}

GPIO_031{11}

GPIO_023{8,10,19}

BB_USER_LED0 {13,18}

SCH Title :

Size

Document Number R ev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

16 20

Monday, April 01, 2019

B TO B CONNECTOR- J22A

VJYM SPPD

J22A

CON_PMC_2X90_F

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

181

182

183

184

185

186

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 32

Figure A-16. Board to Board Connector- J22B

5

4

3

2

1

D D

C C

B B

A A

BOARD TO BOARD CONNECTOR

Place R100 closer to the Samtec Connector J22

This connects to J84

on the TVII Base board

VBTOB_3.3V

VBTOB_3.3V VCC_LDO

BB_CAN7_TXD{9,18}

BB_CAN7_RXD{9,18}

BB_CAN8_TXD{10,19} BB_CAN8_RXD{10,19}

BB_CAN6_TXD{10,18}

BB_CAN9_TXD{12,19} BB_CAN9_RXD{12,19}

BB_CAN4_TXD {12} BB_CAN4_RXD {12}

BB_CAN5_RXD {13}

BB_CAN5_TXD {13}

BB_CAN8_WAKE {10} BB_CAN9_WAKE {10}

GPIO_020{10} GPIO_021{10} GPIO_022{10} GPIO_024{11}

BB_CAN6_RXD{10,18}

SCH Title :

Size

Document Number R ev

Page Title :

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

B TO B CONNECTOR- J22B

Drawn By Approved By VJYM SPPD

R100 0E

J22B

CON_PMC_2X90_F

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

187

188

189

190

191

192

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 33

Figure A-17. Board to Board Connector- J21A

5

4

3

2

1

D D

C C

B B

A A

BOARD TO BOARD CONNECTOR

GND

Place R1 closer to Samtec Connector J22

Place R96,R95,R94,R93 closer to respective CPU pins

This connects to J38

on the TVII Base board

VBTOB_5V

VBTOB_5V VCC_12V

CPU_BB_VDDA

CPU_BB_VDDIO

VCC_PMIC

CPU_BB_VDDD

BB_LIN0_WAKE{12,19}

BB_LIN1_WAKE {12}

BB_LIN2_WAKE{12}

BB_SPI0_WP {13,19}

BB_SPI0_HOLD {13,19}

BB_CAN0_S {13,19}

BB_CAN1_S{13,16}

CPU_WCO_IN {8} CPU_WCO_OUT {8} CPU_ECO_IN {8} CPU_ECO_OUT {8}

CPU_XRES {6,7,14}

BB_LIN5_WAKE{12,19}

BB_USER_LED8 {12}

BB_USER_LED9 {12}

GPIO_035{11} GPIO_036{11}

GPIO_037{11} GPIO_041{11}

GPIO_032{11}

GPIO_080 {14} GPIO_079 {14}

GPIO_033{11} GPIO_034{11}

BB_LIN1_TX{9} BB_LIN1_RX{9}

BB_LIN1_SLP {9,17}

BB_CAN1_RXD{9,17}

BB_CAN1_TXD{9,17}

BB_LIN0_TX{9}

BB_LIN0_SLP{9}

BB_LIN2_RX{10}

BB_CAN_SPI1_MISO {10}

BB_CAN0_TXD{10,17}

BB_CAN_SPI1_MOSI {10} BB_CAN_SPI1_CLK {10}

BB_LIN2_TX{10,17}

BB_LIN5_SLP{8,11}

BB_LIN5_RX{11} BB_LIN5_TX{11}

BB_LIN0_RX{14}

BB_CAN0_RXD{10,17}

GPIO_073 {14}

SCH Title :

Size

Document Number

Rev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956

C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

18 20

Monday, April 01, 2019

B TO B CONNECTOR- J21A

VJYM

SPPD

R96 0E DNI

R94 0E DNI

R95 0E DNI

R2 0E

R93 0E DNI

J21A

CON_PMC_2X90_F

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

181

182

183

184

185

186

R1 0E

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 34

Figure A-18. Board to Board Connector- J21B

5

4

3

2

1

D D

C C

B B

A A

BOARD TO BOARD CONNECTOR

This connects to J38

on the TVII Base board

BB_LIN3_WAKE{12}

BB_USER_LED5{12} BB_USER_LED6{12,16} BB_USER_LED7{12,18}

BB_USER_BUTTON_1{12} BB_USER_BUTTON_2{12} BB_USER_BUTTON_3{12,18}

BB_USER_LED4{13,18}

GPIO_061{13,18}

BB_USER_LED2{13} BB_USER_LED3{13}

BB_USER_BUTTON_5{13,18}

BB_LIN4_WAKE{12}

BB_USER_LED1{14}

GPIO_078 {14} GPIO_077 {14} GPIO_076 {14} GPIO_075 {14} GPIO_074 {14}

GPIO_072 {14} GPIO_068 {13}

GPIO_069 {13}

GPIO_067 {13}

GPIO_070 {14} GPIO_071 {14}

GPIO_066 {13}

GPIO_065 {13}

GPIO_064 {13} GPIO_063 {13}

GPIO_059 {13} GPIO_058 {13}

GPIO_057 {13}

GPIO_056 {13}

GPIO_055 {12}

GPIO_044{12}

GPIO_045{12}

GPIO_046{12}

GPIO_043{11}

GPIO_042{11}

GPIO_047{12} GPIO_048{12} GPIO_049{12} GPIO_050{12} GPIO_051{12} GPIO_052{12} GPIO_053{12} GPIO_054{12}

BB_LIN3_RX{10} BB_LIN3_TX{10}

BB_LIN3_SLP{10,17}

BB_LIN4_RX{10,17} BB_LIN4_TX{10}

BB_LIN4_SLP{8,10,16}

BB_LIN2_SLP{8,10,16}

BB_CAN3_TXD {12,17} BB_CAN3_RXD {12,17}

BB_SPI0_MISO{13}

BB_SPI0_MOSI{13}

GPIO_060 {13}

GPIO_062 {13}

TRACE_DATA_3 {6,14}

TRACE_DATA_2 {6,14}

SWDOE_TDI {6,14}

TRACE_DATA_1 {6,14}

TRACE_DATA_0 {6,14}

SWO_TDO {6,14}

TRACE_CLOCK {6,13}

SWDIO_TMS {6,14} SWCLK_TCLK {6,14}

TRSTN {6,9}

SCH Title :

Size

Document Number R ev

Date: Sheet of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

6239956 C

CYTVII-B-E-1M-B0-176-CPU-BOARD

A4

19 20

Monday, April 01, 2019

B TO B CONNECTOR- J21B

VJYM SPPD

R62

0E DNI

R71 0E DNI

J21B

CON_PMC_2X90_F

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

187

188

189

190

191

192

R53

0E DNI

R50 0E DNI

R65

0E DNI

R66

0E DNI

R52 0E DNI

R54

0E

DNI

R60

0E

DNI

R56 0E DNI

Schematics of CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 35

B. Component Assembly on CPU Board

ART FILM - PASSY

PRIMARY_ASSEMBLY

J16

J17

J18 J19

R72 R83

R56

R57

C45

C48

R64

R61

R52

R79

R80

R81

R82

R74 R86

R75 R85

R53

R50

R62

R49

LD6

R20

R51

R54

C47

C46

R63

R60

R65

R66

R71

R58

R55

R59

R73

R84

R90

R77

R78

R69

R70

R67

R68

R87 R89

R76

R91

R92

TP9

SW3

TP7

C44

R47

R39

C40

R42

R43

C38

R32

C26

C27

C22

C23

C18

C6

L1

J5

R3

R5

R4

J3

J2

J23

FL1

J6

J7

Y1

C5

R18

R17

R10 C9 R16

C8

C12

C17

100

C16

C14

C7

R14

R8

J1

R1

J9

R9

R20

C13

SW2

LD1

D1

U2

C11

U4

U3

25

26

50

1

76

75

51

R12

R19

C15

R6

R7

R11

C20

C19

C4

Y2

R2

TP1

TP2

TPS1

TPS2

TP3

J8

J10

C1

C2

U1

C3

C60

C10

R28

R29

R30

R31

C29

C34

C30

C28

FL3

LD4

LD3

LD2

C43

R40

R45

R44

J14

C35

C31

C36

C41

C37

C42

TPS5

TPS6

TPS3

TPS4

TPS7

C39

R48

J15

R41

R38

C33

C32

R46

J13

J11

R27

R26

R25

R15

R13

F1

SW1

R23

U5

C25

C24

FL2

C21

TP6

TP4

TP5

D2

R22

R21

D3

R24

J12

L2

FL4

LD5

TP8

R88

This appendix shows the top and bottom assembly of the PCB.

Figure B-1. Top Assembly of the PCB

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 36

Figure B-2. Bottom Assembly of the PCB

ART FILM - SASSY

J21

J22

R100

C61

PCB - EDGE

U12

C62

R99

R98

R97

C53

C59

C58

C57

C55

C50

C56

C52

C51

C49

C54

C64

R93

R94

R95

R96

SECONDARY_ASSEMBLY

Component Assembly on CPU Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 37

C. Schematics of Base Board

This appendix contains the schematics of the Base board on which CPU Board is mounted.

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 38

Figure C-1. Block Diagram of Base Board

5

4

3

2

1

D D

C C

B B

A A

SCH Title :

Size

Document Number Re v

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

A

TRAVEO II BASE BOARD

B

318

Wednesday, November 20, 2019

BLOCK DIAGRAM

BALA K SHANTANU

SCH Title :

Size

Document Number Re v

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

A

TRAVEO II BASE BOARD

B

318

Wednesday, November 20, 2019

BLOCK DIAGRAM

BALA K SHANTANU

SCH Title :

Size

Document Number Re v

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

A

TRAVEO II BASE BOARD

B

318

Wednesday, November 20, 2019

BLOCK DIAGRAM

BALA K SHANTANU

TRAVEO II EVM BASE BOARD

POWER INPUTS (12V, 5V &

3.3V) FROM CPU OR ADAPTER BOARD

BOARD TO BOARD CONNECTORS

(QTH-090-03-L-D-A)

USER LED’S

PUSH-BUTTON

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 39

Figure C-2. BTOB Connector-01

5

4

3

2

1

D D

C C

B B

A A

BTOB CONNECTOR-01

Default 1-2

P_3V3

VCC_3V3P_3V3

VCC_3V3

VDD_IO_W VDD_IO

VCC_5V

BB_PWM_117 BB_PWM_217 BB_PWM_317 BB_PWM_417 BB_PWM_517 BB_PWM_617 BB_PWM_717 BB_ADC_217 BB_ADC_317 BB_ADC_417 BB_ADC_517 BB_ADC_617 BB_ADC_717

BB_ADC_817

CAN6_TXD8

CAN6_RXD

8

CAN7_TXD8

CAN7_RXD8

CAN8_TXD9

CAN8_RXD9

CAN9_TXD9

CAN9_RXD9

BB_USER_LED0 16,18 SPI0_SS 15,17 SPI0_CLK 15,17

UART1_TX 17 UART1_RTS 17

UART1_RX 17

UART1_CTS 17 CAN2_TXD 6,17 CAN2_RXD 6,17

CAN2_S 6,17 CAN3_S 6,17 CAN4_S 7,17 CAN5_S 7,17 CAN6_WAKE 8,17 CAN7_WAKE 8,17

CAN8_WAKE 9,17

CAN9_WAKE 9,17 CAN5_TXD 7,17 CAN5_RXD 7,17 CAN4_TXD 7,17 CAN4_RXD 7,17

DEBUG_GPIO_117 DEBUG_GPIO_217 DEBUG_GPIO_317 DEBUG_GPIO_417

BB_EXP1_GPIO_1 18 BB_EXP1_GPIO_2 18 BB_EXP1_GPIO_3 18 BB_EXP1_GPIO_4 18

BB_EXP1_GPIO_7 18 BB_EXP1_GPIO_8 18 BB_EXP1_GPIO_9 18 BB_EXP1_GPIO_10 18

BB_EXP1_GPIO_11 18 BB_EXP1_GPIO_12 18 BB_EXP1_GPIO_13 18 BB_EXP1_GPIO_14 18

BB_EXP1_GPIO_5 18 BB_EXP1_GPIO_6 18

BB_EXP1_GPIO_15 18 BB_EXP1_GPIO_16 18

BB_USER_BUTTON_4 16,17

CAN_SPI1_SS0 8,17 CAN_SPI1_SS1 8,17 CAN_SPI1_SS2 9,17

SCH Title :

Size

Document Number Re v

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

A

TRAVEO II BASE BOARD

B

418

Wednesday, November 20, 2019

BTOB CONNECTOR-01

BALA K SHANTANU

SCH Title :

Size

Document Number Re v

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

A

TRAVEO II BASE BOARD

B

418

Wednesday, November 20, 2019

BTOB CONNECTOR-01

BALA K SHANTANU

SCH Title :

Size

Document Number Re v

Date:

Sheet

of

Page Title :

Drawn By

CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

A

TRAVEO II BASE BOARD

B

418

Wednesday, November 20, 2019

BTOB CONNECTOR-01

BALA K SHANTANU

C10

0.1uF

TP9

TP20

TP13

TP10

J84A

CON_PMC_2X90_M

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

181

182

183

184

185

186

J80 HDR_1X3

123

FL3

600E

1

2

TP14

C8

0.1uF

LD13SML-P12YTT86

21

TP16

TP11

J84B

CON_PMC_2X90_M

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

187

188

189

190

191

192

TP15

R21

1K

5% 0402

TP6

TP17TP12

TP7

TP18

FL4

600E

1 2

C9 10uF

TP8

TP19

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 40

Figure C-3. BTOB Connector-02

5

4

3

2

1

D D

C C

B B

A A

BTOB CONNECTOR-02

Default closed

Default closed Default closed

BB_I2C1_SDA

BB_I2C1_SCL

P_5V

P_12V

P_5V

VBATP_12V VDD_IO

VCC_5V

CAN1_RXD6,17

CAN1_TXD

6,17

CAN1_S

6,17

CAN0_RXD6,17

CAN0_TXD

6,17

LIN1_TXD

10,17

LIN1_RXD10,17

LIN0_WAKE10,17 LIN0_SLP

10,17

LIN0_RXD10,17

LIN0_TXD

10,17

CXPI_SELMS

15,17

CXPI_NSLP15,17

CXPI_RXD15,17

CXPI_TXD

15,17

LIN5_WAKE

12,17

LIN5_SLP

12,17

LIN5_RXD12,17

LIN5_TXD

12,17

LIN2_WAKE

11,17

LIN2_RXD11,17

LIN2_TXD

11,17

LIN2_SLP11,17

LIN3_WAKE11,17 LIN3_SLP11,17

LIN3_RXD11,17

LIN3_TXD

11,17

LIN4_WAKE12,17 LIN4_SLP12,17

LIN4_RXD12,17

LIN4_TXD12,17

BB_I2C1_SDA17

BB_I2C1_SCL17

CXPI_CLK15,18 BB_GPIO_3718

BB_HPMC_1 17 BB_HPMC_3 17 BB_HPMC_4 17

CAN_SPI1_SCK 8,9,18

BB_BOARD_RSTX_SET

BB_BOARD_RSTX

BB_GPIO_48 18 BB_GPIO_49 18 BB_GPIO_50 18 BB_GPIO_51 18 BB_GPIO_52 18 BB_GPIO_53 18 BB_GPIO_54 18 BB_GPIO_55 18

BB_GPIO_56_RESET 18

BB_PWM_8 18 BB_PWM_9 18 BB_PWM_10 18

UART0_RTS 18

UART0_TX 18

UART0_RX 18

UART0_CTS 18

SPI2_MOSI 18 SPI2_CLK 18

SPI2_MISO 18

SPI2_SS 18 CAN3_TXD 6,18 CAN3_RXD 6,18

FRA_RXD13 FRA_TXD13 FRA_TXEN13 FRA_STBN13 FRA_EN

13

FRA_ERRN

13

FRA_WAKE13

BB_USER_BUTTON_116,17 BB_USER_BUTTON_216,17 BB_USER_BUTTON_316,17

BB_USER_BUTTON_516,17

BB_USER_LED116,18 BB_USER_LED216,18 BB_USER_LED316,18 BB_USER_LED416,18 BB_USER_LED516,18 BB_USER_LED616,18 BB_USER_LED716,18

BB_USER_LED8 16,17

BB_USER_LED9 16,17

BB_ADC_POT15,18

BB_ADC_118

DEBUG_GPIO_518 DEBUG_GPIO_618 DEBUG_GPIO_718 DEBUG_GPIO_818 DEBUG_GPIO_918 DEBUG_GPIO_1018 DEBUG_GPIO_1118 DEBUG_GPIO_1218

DEBUG_GPIO_13 18 DEBUG_GPIO_14 18 DEBUG_GPIO_15 18 DEBUG_GPIO_16 18 DEBUG_GPIO_17 18 DEBUG_GPIO_18 18 DEBUG_GPIO_19 18 DEBUG_GPIO_20 18

DEBUG_GPIO_21 5 DEBUG_GPIO_22 5 DEBUG_GPIO_23 18 DEBUG_GPIO_24 18 DEBUG_GPIO_25 5

DEBUG_GPIO_26 18 DEBUG_GPIO_27 18

BB_EXP2_GPIO_1 18 BB_EXP2_GPIO_2 18

BB_EXP2_GPIO_3 18 BB_EXP2_GPIO_4 18 BB_EXP2_GPIO_5 18

BB_EXP2_GPIO_6 18 BB_EXP2_GPIO_7 18 BB_EXP2_GPIO_8 18 BB_EXP2_GPIO_9 18 BB_EXP2_GPIO_10 18

BB_EXP2_GPIO_11 18 BB_EXP2_GPIO_12 18 BB_EXP2_GPIO_13 18 BB_EXP2_GPIO_14 18

BB_EXP2_GPIO_15 18 BB_EXP2_GPIO_16 18

SPI0_HOLD 15,18

SUPPLY_INH 14,17

SPI0_MISO15,18

SPI0_MOSI15,18

BB_HPMC_2 17

FRB_RXD14 FRB_TXD14 FRB_TXEN14 FRB_STBN14 FRB_EN14

FRB_ERRN14 FRB_WAKE14

BB_ADC_917

BB_ADC_1017 BB_ADC_1117

CAN0_S 6,17 LIN1_WAKE 10,17 LIN1_SLP 10,17

SPI0_WP 15,17

CAN_SP I1_MISO 8,9, 18

CAN_SPI1_MOSI 8 ,9,18

DEBUG_GPIO_21 5 DEBUG_GPIO_21_W 18 DEBUG_GPIO_22 5

DEBUG_GPIO_22_W 18

DEBUG_GPIO_25 5 DEBUG_GPIO_25_W 18

SCH Title :

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Wednesday, November 20, 2019

BTOB CONNECTOR-02

BALA K SHANTANU

SCH Title :

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Wednesday, November 20, 2019

BTOB CONNECTOR-02

BALA K SHANTANU

SCH Title :

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Wednesday, November 20, 2019

BTOB CONNECTOR-02

BALA K SHANTANU

J38A

CON_PMC_2X90_M

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

181

182

183

184

185

186

C3

0.1uF

C1 10uF

J132

HDR_1X2

1 2

R2

1K

5% 0402

R101 4.7K_1%

DNI

TP5

J134

HDR_1X2

1 2

C2

0.1uF

TP2

C6

0.1uF

TP4

LD1SML-P12YTT86

21

FL2

600E

1 2

C4 10uF

R102 4.7K_1%

DNI

J133

HDR_1X2

1 2

TP3

C5

0.1uF

LD2SML-P12YTT86

2

1

FL1

600E

1

2

R3 1K

5% 0402

J38B

CON_PMC_2X90_M

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

187

188

189

190

191

192

TP1

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 41

Figure C-4. CAN-FD_0 to 3

5

4

3

2

1

D D

C C

B B

A A

CAN_FD_0 CAN_FD_1

CAN_FD_2 CAN_FD_3

Default Closed

Default Open

Default Open Default Open

CAN0_L

CAN0_H

CAN0_L_W

CAN0_S_W

CAN0_RXD_W

CAN0_TXD_W

CAN1_L

CAN1_H

CAN1_S_W

CAN1_RXD_W

CAN1_TXD_W

CAN2_L

CAN2_H

CAN2_S_W

CAN2_RXD_W

CAN2_TXD_W

CAN3_L

CAN3_H

CAN3_S_W

CAN3_RXD_W

CAN3_TXD_W

CAN0_H_W

CAN1_L_W

CAN1_H_W

CAN2_L_W

CAN2_H_W

CAN3_L_W

CAN3_H_W

CAN0_H

CAN0_L

CAN1_H

CAN1_L

CAN2_H

CAN2_L

CAN3_H

CAN3_L

VDD_IO

CAN0_TXD5,17

CAN0_RXD5,17

CAN0_S

5,17

CAN1_TXD

5,17

CAN1_RXD5,17

CAN1_S5,17

CAN2_TXD4,17

CAN2_RXD

4,17

CAN2_S4,17

CAN3_TXD

5,18

CAN3_RXD5,18

CAN3_S4,17

SCH Title :

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Wednesday, November 20, 2019

CAN-FD_0 TO 3

BALA K SHANTANU

SCH Title :

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CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

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Wednesday, November 20, 2019

CAN-FD_0 TO 3

BALA K SHANTANU

SCH Title :

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CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

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B

618

Wednesday, November 20, 2019

CAN-FD_0 TO 3

BALA K SHANTANU

J65 HDR_1X2

1

2

C55

0.1uF

R107 10K

R96 120E

U15

TJA1057GT

TXD

1

GND

2

VCC

3

RXD

4

NC

5

CANL

6

CANH

7

S

8

R108 0E

J76 HDR_1X2

1

2

R105 0E

J70 HDR_1X2

1

2

P7B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

R93 10K

J82 HDR_1X2

1

2

J75 HDR_1X2

1

2

R94 0E

P7A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

U12

TJA1057GT

TXD

1

GND

2

VCC

3

RXD

4

NC

5

CANL

6

CANH

7

S

8

R106 120E

P6A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

+

C52

22uF_20V

P6B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

J71 HDR_1X2

1

2

+

C56

22uF_20V

J83 HDR_1X2

1

2

R99

0E

R97 10K

J67 HDR_1X2

1

2

R104 0E

U13

TJA1057GT

TXD

1

GND

2

VCC

3

RXD

4

NC

5

CANL

6

CANH

7

S

8

C57

0.1uF

+

C50

22uF_20V

J81 HDR_1X2

1

2

J68 HDR_1X2

1

2

C53

0.1uF

J72 HDR_1X2

1

2

J79 HDR_1X2

1

2

R109

0E

R98

0E

J77 HDR_1X2

1

2

J69 HDR_1X2

1

2

R110 120E

C51

0.1uF

J66 HDR_1X2

1

2

R103 10K

U14

TJA1057GT

TXD

1

GND

2

VCC

3

RXD

4

NC

5

CANL

6

CANH

7

S

8

+

C54

22uF_20V

J78 HDR_1X2

1

2

R95 0E

R100 120E

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 42

Figure C-5. CAN-FD_4 to 7

5

4

3

2

1

D D

C C

B B

A A

CAN_FD_4 CAN_FD_5

Default Open

Default OpenDefault Closed

Default Closed

CAN4_L_W

CAN4_H_W

CAN4_L

CAN4_H

CAN4_S_W

CAN4_RXD_W

CAN4_TXD_W

CAN5_L_W

CAN5_H_W

CAN5_L

CAN5_H

CAN5_S_W

CAN5_RXD_W

CAN5_TXD_W

CAN4_H

CAN4_L

CAN5_H

CAN5_L

VDD_IO

CAN4_TXD

4,17

CAN4_RXD4,17

CAN4_S

4,17

CAN5_TXD4,17

CAN5_RXD4,17

CAN5_S4,17

SCH Title :

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Approved By

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B

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Wednesday, November 20, 2019

CAN-FD_4 TO 7

BALA K SHAN TANU

SCH Title :

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CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600

Approved By

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B

718

Wednesday, November 20, 2019

CAN-FD_4 TO 7

BALA K SHAN TANU

SCH Title :

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Approved By

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B

718

Wednesday, November 20, 2019

CAN-FD_4 TO 7

BALA K SHAN TANU

J87 HDR_1X2

1

2

U17

TJA1057GT

TXD

1

GND

2

VCC

3

RXD

4

NC

5

CANL

6

CANH

7

S

8

+

C58

22uF_20V

J88 HDR_1X2

1

2

R111 10K

J90 HDR_1X2

1

2

+

C62

22uF_20V

C59

0.1uF

U16

TJA1057GT

TXD

1

GND

2

VCC

3

RXD

4

NC

5

CANL

6

CANH

7

S

8

R119 120E

R117

0E

J86 HDR_1X2

1

2

R113 0E

J92 HDR_1X2

1

2

P8A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

P8B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

J93 HDR_1X2

1

2

R116 10K

R112 0E

J85 HDR_1X2

1

2

C63

0.1uF

J91 HDR_1X2

1

2

R114 120E

R118

0E

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 43

Figure C-6. CAN-FD_6 & 7

5

4

3

2

1

D D

C C

B B

A A

Default Closed

Default Open

Default closed

Default Closed

Default Open

desolc tluafeD

desolc tluafe

D

CAN_FD_6 CAN_FD_7

Default closed Default closed

Default closed

CAN6_RXD_W

CAN6_TXD_W

CAN6_H

CAN6_L

CAN6_INH_W

CAN6_L_W

CAN6_H_W

CAN6_L

CAN6_H

CAN_SPI1_MOSI_W CAN_SPI1_MISO_W

CAN_SPI1_MISO_W

CAN_SPI1_SCK_W

CAN_SPI1_SS0_W

CAN6_WAKE_W

CAN_SPI1_SCK_W

CAN_SPI1_SS0_W

CAN7_RXD_W

CAN7_TXD_W

CAN7_H

CAN7_L

CAN7_INH_W

CAN7_L_W

CAN7_H_W

CAN7_L

CAN7_H

CAN_SP I1_MISO_W

CAN7_WAKE_W

CAN_SPI1_SCK_W

CAN_SPI1_MOSI_W CAN_SPI1_MOSI_W

CAN_SPI1_SS1_W

CAN_SPI1_MOSI_W CAN_SPI1_MISO_W

CAN_SPI1_SCK_W

CAN_SPI1_SS1_W

VDD_IO

VBAT

VDD_IO VBAT

VDD_IO VDD_IO

VDD_IO VBAT

VCC_5V VCC_5V

VCC_5V

CAN6_TXD

4

CAN6_RXD

4

CAN6_INH 14

CAN_SP I1_MISO 5,8,9 ,18

CAN_SPI1_SCK 5,8,9,18

CAN_SPI1_SS0 4,17

CAN7_TXD4 CAN7_RXD4

CAN7_INH 14

CAN_SP I1_MISO 5,8, 9,18

CAN_SPI1_SCK 5,8,9,18

CAN7_WAKE4,17CAN6_WAKE4,17

CAN_SPI1_MOSI 5,8,9,18

CAN_SPI1_SS1 4,17

CAN_SPI1_MOSI_W8,9

CAN_SPI1_SCK_W

8,9

CAN_SPI1_MISO_W8,9

CAN_SPI1_MOSI_W8,9

CAN_SPI1_SCK_W8,9

CAN_SPI1_MISO_W8,9

SCH Title :

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818

Wednesday, November 20, 2019

CAN-FD_6 & 7

BALA K SHANTANU

SCH Title :

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Approved By

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B

818

Wednesday, November 20, 2019

CAN-FD_6 & 7

BALA K SHANTANU

SCH Title :

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Approved By

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B

818

Wednesday, November 20, 2019

CAN-FD_6 & 7

BALA K SHANTANU

J100

HDR_1X2

1 2

R129

0E

+

C67 22uF_20V

C77

0.1uF

R120 0E

R131 120E

J95 HDR_1X2

1

2

J104

HDR_1X2

1 2

P9A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

J103

HDR_1X2

1 2

R124 10K

J107 HDR_1X2

1

2

J97 HDR_1X2

1

2

R122

4.7K_1%

+

C66 22uF_20V

R132

4.7K_1%

C71

0.1uF

R121 0E

J101

HDR_1X2

1

2

U18

TJA1145T

TXD

1

GND

2

VCC

3

RXD

4

VIO

5

SDO

6

INH

7

SCK

8

WAKE

9

BAT

10

SDI

11

CANL

12

CANH

13

SCSN

14

C80

4.7uF

J110

HDR_1X2

1

2

J98

HDR_1X2

1 2

C68

0.1uF

J99

HDR_1X2

1 2

R127 10K

J106

HDR_1X2

1 2

R125

0E

C78

0.1uF

R126

0E

P9B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

J96

HDR_1X2

1 2

J109 HDR_1X2

1

2

R130 120E

J105

HDR_1X2

1 2

C70

0.1uF

U19

TJA1145T

TXD

1

GND

2

VCC

3

RXD

4

VIO

5

SDO

6

INH

7

SCK

8

WAKE

9

BAT

10

SDI

11

CANL

12

CANH

13

SCSN

14

J108 HDR_1X2

1

2

C79

4.7uF

J94 HDR_1X2

1

2

R128

0E

C69

0.1uF

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 44

Figure C-7. CAN-FD_8 & 9

5

4

3

2

1

D D

C C

B B

A A

Default Closed

Default Open

Default closed

Default Closed

Default Open

desolc tluafeDdesolc tluafeD

CAN_FD_8 CAN_FD_9

Default closed

CAN8_RXD_W

CAN8_TXD_W

CAN8_H

CAN8_L

CAN8_INH_W

CAN8_L_W

CAN8_H_W

CAN8_L

CAN8_H

CAN_SPI1_MISO_W

CAN8_WAKE_W

CAN_SPI1_SCK_W

CAN9_RXD_W

CAN9_TXD_W

CAN9_H

CAN9_L

CAN9_INH_W

CAN9_L_W

CAN9_H_W

CAN9_L

CAN9_H

CAN_SP I1_MISO_W

CAN9_WAKE_W

CAN_SPI1_SCK_W

CAN_SPI1_MOSI_W

CAN_SPI1_SS2_W

CAN_SPI1_MOSI_W

CAN_SPI1_SS2_W

CAN_SPI1_MOSI_W CAN_SPI1_MISO_W

CAN_SPI1_SCK_W

CAN_SPI1_SS2_W

CAN_SPI1_MOSI_W CAN_SPI1_MISO_W

CAN_SPI1_SCK_W

CAN_SPI1_SS2_W

VDD_IO

VBAT

VDD_IO VBAT

VDD_IO VDD_IO

VDD_IO VBAT VDD_IO VBAT

VCC_5V

VCC_5V VCC_5V

CAN8_TXD4

CAN8_RXD4

CAN8_INH 14

CAN_SP I1_MISO 5,8,9 ,18

CAN_SPI1_SCK 5,8,9,18

CAN9_TXD4

CAN9_RXD4

CAN9_INH 14

CAN_SP I1_MISO 5,8, 9,18

CAN_SPI1_SCK 5,8,9,18

CAN9_WAKE4,17CAN8_WAKE

4,17

CAN_SPI1_MOSI 5,8,9,18

CAN_SPI1_SS2 4,9,17

CAN_SPI1_MOSI 5,8,9,18

CAN_SPI1_SS2 4,9,17

CAN_SPI1_MOSI_W

8,9

CAN_SPI1_SCK_W8,9

CAN_SPI1_MISO_W8,9

CAN_SPI1_MOSI_W8,9

CAN_SPI1_SCK_W8,9

CAN_SPI1_MISO_W8,9

SCH Title :

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Wednesday, November 20, 2019

CAN-FD_8 & 9

BALA K SHANTANU

SCH Title :

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Wednesday, November 20, 2019

CAN-FD_8 & 9

BALA K SHANTANU

SCH Title :

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918

Wednesday, November 20, 2019

CAN-FD_8 & 9

BALA K SHANTANU

J131 HDR_1X2

1

2

C86

0.1uF

P10A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

J118

HDR_1X2

1 2

R140 0E

J116

HDR_1X2

1 2

C90

4.7uF

J119 HDR_1X2

1

2

+

C81 22uF_20V

J120 HDR_1X2

1

2

J111

HDR_1X2

1

2

C85

0.1uF

J112 HDR_1X2

1

2

J124

HDR_1X2

1 2

J114 HDR_1X2

1

2

R134 0E

C88

0.1uF

R133 0E

J125

HDR_1X2

1

2

J115

HDR_1X2

1 2

J121

HDR_1X2

1 2

C84

0.1uF

C83

0.1uF

R138 10K

C89

4.7uF

J117

HDR_1X2

1 2

+

C82 22uF_20V

U21

TJA1145T

TXD

1

GND

2

VCC

3

RXD

4

VIO

5

SDO

6

INH

7

SCK

8

WAKE

9

BAT

10

SDI

11

CANL

12

CANH

13

SCSN

14

R144

4.7K_1%

C87

0.1uF

U20

TJA1145T

TXD

1

GND

2

VCC

3

RXD

4

VIO

5

SDO

6

INH

7

SCK

8

WAKE

9

BAT

10

SDI

11

CANL

12

CANH

13

SCSN

14

R136 0E

P10B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

R135 10K

J123

HDR_1X2

1 2

J122

HDR_1X2

1 2

R141

4.7K_1%

R137 0E

R143 120E

R142 120E

J113 HDR_1X2

1

2

R139

0E

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 45

Figure C-8. LIN INTERFACE_0 to 1

5

4

3

2

1

D D

C C

B B

A A

LIN0_INTERFACE LIN1_INTERFACE

Default closed

Default ClosedDefault Closed

Default ClosedDefault Closed Default Closed

Default Open

LIN0_TXD_WLIN0_WAKE_N LIN0_RXD_W

LIN1_WAKE_N

LIN0_BUS LIN1_BUS

LIN1_RXD_W

LIN1_TXD_W

LIN0_WAKE_N

LIN1_WAKE_N

LIN0_EN

LIN1_EN

LIN0_BUS

LIN0_BUS_W

LIN1_BUSLIN1_BUS_W

LIN0_EN

LIN0_BUS

LIN1_EN

LIN1_BUS

VDD_IO

LIN_VS

VDD_IO

LIN_VS

VBAT

VDD_IO

VBAT VBAT

VDD_IO

LIN0_INH 14

LIN1_INH 14

LIN0_RXD 5,17

LIN0_TXD 5,17

LIN1_RXD 5,17

LIN1_TXD 5,17

LIN0_SLP5,17

LIN1_SLP5,17

LIN0_WAKE5,17

LIN1_WAKE5,17

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LIN INTERFACE_0 TO 1

BALA K SHANTANU

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LIN INTERFACE_0 TO 1

BALA K SHANTANU

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10 18

Wednesday, November 20, 2019

LIN INTERFACE_0 TO 1

BALA K SHANTANU

R86

4.7K_1%

U11

TJA1021T/20/C

SLP_N

2

WAKE_N

3

GND

5

LIN

6

VBAT

7

INH

8

TXD

4

RXD

1

C49 220pF

C44 1000pF

P5B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

J57

HDR_1X3

1 2 3

R88 0E

J55 HDR_1X2

1

2

D23

1N4002-T

21

J56 HDR_1X2

1

2

+

C46 22uF_20V

J53 HDR_1X2

1

2

P5A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

C48 1000pF

R92 1K

J61 HDR_1X2

1

2

R85

4.7K_1%

J62 HDR_1X2

1

2

C43

0.1uF

U10

TJA1021T/20/C

SLP_N

2

WAKE_N

3

GND

5

LIN

6

VBAT

7

INH

8

TXD

4

RXD

1

R84

4.7K_1%

R7 0ER11

0E

J44

HDR_1X3

1 2 3

J52

HDR_1X2

1 2

J60 HDR_1X2

1

2

R87 1K

R90

4.7K_1%

+

C42 22uF_20V

D26

1N4002-T

2

1

J54 HDR_1X2

1

2

J63 HDR_1X2

1

2

R91

4.7K_1%

C47

0.1uF

R89

4.7K_1%

J58 HDR_1X2

1

2

D25

1N4148W-7-F

21

J59

HDR_1X2

1 2

D24

1N4148W-7-F

21

J51 HDR_1X2

1

2

R83 0E

C45 220pF

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 46

Figure C-9. LIN INTERFACE_2 to 3

5

4

3

2

1

D D

C C

B B

A A

LIN2_INTERFACE LIN3_INTERFACE

Default closed

Default Closed

Default Open

LIN2_WAKE_N

LIN2_BUS

LIN3_WAKE_N

LIN3_BUS

LIN3_EN

LIN2_BUS

LIN3_BUS

LIN2_RXD_W

LIN2_TXD_W

LIN3_RXD_W

LIN3_TXD_W

LIN2_WAKE_N

LIN2_EN

LIN3_WAKE_N LIN3_EN

LIN2_BUS

LIN2_BUS_W LIN3_BUSLIN3_BUS_W

LIN2_EN

VDD_IOVDD_IO

LIN_VS LIN_VS

VBAT

VBAT VBAT

VDD_IO VDD _IO

VDD_IO VDD_IO

LIN3_INH 14

LIN2_INH 14

LIN2_RXD 5,17

LIN2_TXD 5,17

LIN3_RXD 5,17

LIN3_TXD 5,17

LIN2_SLP5,17 LIN3_SLP5,17LIN2_WAKE

5,17

LIN3_WAKE5,17

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Wednesday, November 20, 2019

LIN INTERFACE_2 TO 3

BALA K SHANTANU

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Wednesday, November 20, 2019

LIN INTERFACE_2 TO 3

BALA K SHANTANU

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11 18

Wednesday, November 20, 2019

LIN INTERFACE_2 TO 3

BALA K SHANTANU

J34 HDR_1X2

1

2

D14

1N4002-T

21

C37

0.1uF

R70

4.7K_1%

P4A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

R77 1K

D16

1N4148W-7-F

21

R6

0E

J39

HDR_1X2

1 2

U7

TJA1021T/20/C

SLP_N

2

WAKE_N

3

GND

5

LIN

6

VBAT

7

INH

8

TXD

4

RXD

1

C33

0.1uF

C35 220pF

R67

0E

+

C36 22uF_20V

C34 1000pF

R69

4.7K_1%

J43 HDR_1X2

1

2

J37 HDR_1X2

1

2

D22

1N4148W-7-F

2

1

J40 HDR_1X2

1

2

+

C32 22uF_20V

R68

4.7K_1%

R72

0E

C39 220pF

J35 HDR_1X2

1

2

U8

TJA1021T/20/C

SLP_N

2

WAKE_N

3

GND

5

LIN

6

VBAT

7

INH

8

TXD

4

RXD

1

J31

HDR_1X2

1 2

J32 HDR_1X2

1

2

C38 1000pF

R5 0E

R75

4.7K_1%

J41 HDR_1X2

1

2

J42 HDR_1X2

1

2

J33 HDR_1X2

1

2

R71 1K

J36

HDR_1X3

1 2 3

J30 HDR_1X2

1

2

R74

4.7K_1%

J28

HDR_1X3

1 2 3

P4B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

D21

1N4002-T

2

1

R73

4.7K_1%

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 47

Figure C-10. LIN INTERFACE_4 to 5

5

4

3

2

1

D D

C C

B B

A A

LIN4_INTERFACE LIN5_INTERFACE

Default closed Default closed

Default Closed

Default Closed Default Closed

Default Open Default Open

LIN4_WAKE_N

LIN4_BUS

LIN5_WAKE_N

LIN5_BUS

LIN5_EN

LIN4_EN

LIN4_BUS LIN5_BUS

LIN4_RXD_W

LIN4_TXD_W

LIN5_RXD_W

LIN5_TXD_W

LIN4_WAKE_N LIN4_EN

LIN5_WAKE_N LIN5_EN

LIN4_BUSLIN4_BUS_W

LIN5_BUSLIN5_BUS_W

VDD_IOVDD_IO

LIN_VS LIN_VS

VBAT

VDD_IO VDD_IO VDD_IO VDD _IO

LIN5_INH 14LIN4_INH 14

LIN4_RXD 5,17

LIN4_TXD 5,17

LIN5_RXD 5,17

LIN5_TXD 5,17

LIN4_SLP

5,17

LIN5_SLP5,17LIN4_WAKE5,17 LIN5_WAKE5,17

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Wednesday, November 20, 2019

LIN INTERFACE_4 TO 5

BALA K SHANTANU

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Wednesday, November 20, 2019

LIN INTERFACE_4 TO 5

BALA K SHANTANU

SCH Title :

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12 18

Wednesday, November 20, 2019

LIN INTERFACE_4 TO 5

BALA K SHANTANU

R57

0E

C26 1000pF

R59

4.7K_1%

R4 0E

D10

1N4148W-7-F

2

1

J23

HDR_1X2

1 2

J27 HDR_1X2

1

2

D9

1N4002-T

2

1

J21

HDR_1X3

1 2 3

J18 HDR_1X2

1

2

U5

TJA1021T/20/C

SLP_N

2

WAKE_N

3

GND

5

LIN

6

VBAT

7

INH

8

TXD

4

RXD

1

J20 HDR_1X2

1

2

R62

0E

C31 220pF

J24 HDR_1X2

1

2

J15

HDR_1X3

1 2 3

J26 HDR_1X2

1

2

D7

1N4002-T

21

J17 HDR_1X2

1

2

J22 HDR_1X2

1

2

C30 1000pF

R58

4.7K_1%

C29

0.1uF

J25 HDR_1X2

1

2

R65

4.7K_1%

C24

0.1uF

P3B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

R61 1K

J19 HDR_1X2

1

2

U6

TJA1021T/20/C

SLP_N

2

WAKE_N

3

GND

5

LIN

6

VBAT

7

INH

8

TXD

4

RXD

1

+

C28 22uF_20V

R1 0E

J16

HDR_1X2

1 2

R64

4.7K_1%

P3A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

+

C25 22uF_20V

J10 HDR_1X2

1

2

R66 1K

R63

4.7K_1%

D8

1N4148W-7-F

21

R60

4.7K_1%

C27 220pF

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 48

Figure C-11. Flexray-01 & RESET

5

4

3

2

1

D D

C C

B B

A A

Default 1-2

Place C67, C68, C69 &C70 close to pin

FLEXRAY INTERFACE -01 RESET

FRA_EN_W

FRA_STBN_W

FRA_BGE

FRA_TXD_W

FRA_TXEN_W

FRA_RXD_W

FRA_BP FRA_BM

BB_RST_NP

FRA_EN_W

FRA_WAKE_N

FRA_BP_W FRA_BM_W

FRA_INH_W

FRA_ERRN_W

FRA_WAKE

VDD_IO VBAT

VDD_IO

VBAT

VDD_IO

FRA_STBN5

FRA_TXD5

FRA_TXEN5

FRA_RXD5

FRA_EN5

FRA_INH 14

FRA_ERRN 5

FRA_WAKE5

SCH Title :

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FLEXRAY-01 & RESET

BALA K SHANTANU

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Wednesday, November 20, 2019

FLEXRAY-01 & RESET

BALA K SHANTANU

SCH Title :

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Wednesday, November 20, 2019

FLEXRAY-01 & RESET

BALA K SHANTANU

R50 0E

R46 0E

R47 0E

P2A

CON_DSUB_9_MM

A1

A6

A2

A7

A3

A8

A4

A9

A5

SH1

SH2

SW6

7914J-1-000E

1 3

2 4

R13 10K

R45 0E

R41

10K

R39

10K

C15

0.1uF

C14

0.1uF

J7

HDR_1X3

1

2

3

C22

4.7uF

C7

0.1uF

R25 0E

R48 0E

R28 1M

J64

HDR_1X2

1

2

R32

10K

U3

TJA1081TS

INH

1

EN

2

VIO

3

TXD

4

TXEN

5

RXD

6

BGE

7

STBN

8

RXEN

9

ERRN

10

VBAT

11

WAKE

12

GND

13

BM

14

BP

15

VCC

16

R34 0E

C21

0.1uF

L2

4000E

1

32

4

R49 0E

L4 180nH

R23 0E

DNI

C12

4.7uF

R36

10K

R30 100E

U1

LM3724IM5-4.63/NOPB

GND1GND

2

RESET

3

MR

4

VCC

5

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 49

Figure C-12. Flexray-02 & INH

5

4

3

2

1

D D

C C

B B

A A

Default 1-2

Place C72, C73, C74 & C75 close to pin

FLEXRAY INTERFACE-02 SUPPLY_INH

Default Closed

FRB_EN_W

FRB_STBN_W

FRB_BGE

FRB_EN_W

FRB_WAKE_N

FRB_BP_W FRB_BM_W

FRB_INH_W

FRB_TXD_W

FRB_ERRN_W

FRB_TXEN_W

FRB_RXD_W

FRB_BP FRB_BM

FRB_WAKE

SUPPLY_INH_W

VBAT

VDD_IO

FRB_STBN5

FRB_EN5

FRB_INH 14

FRB_ERRN 5FRB_TXD5

FRB_TXEN5

FRB_RXD5

FRB_WAKE5

LIN0_INH10 SUPPLY_INH 5,17

LIN1_INH10

LIN2_INH11

LIN3_INH11

LIN4_INH

12

LIN5_INH12

FRA_INH

13

FRB_INH14

CAN6_INH8

CAN7_INH8

CAN8_INH9

CAN9_INH9

SCH Title :

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FLEXRAY-02 & INH

BALA K SHAN TANU

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FLEXRAY-02 & INH

BALA K SHAN TANU

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Wednesday, November 20, 2019

FLEXRAY-02 & INH

BALA K SHAN TANU

R56 0E

D15 1N4148W-7-F

2

1

C18

0.1uF

C20

0.1uF

R31

10K

R40

10K

R29 100E

D12 1N4148W-7-F

2

1

C13

4.7uF

C23

4.7uF

D19 1N4148W-7-F

2

1

U4

TJA1081TS

INH

1

EN

2

VIO

3

TXD

4

TXEN

5

RXD

6

BGE

7

STBN

8

RXEN

9

ERRN

10

VBAT

11

WAKE

12

GND

13

BM

14

BP

15

VCC

16

L3 180nH

R54 0E

R76 20K

R52

0E

R35

10K

D13 1N4148W-7-F

2

1

C19

0.1uF

R53 0E

D1 1N4148W-7-F

2

1

R26 0E

R33

0E

D4 1N4148W-7-F

2

1

R20

4.7K_1%

DNI

R22

0E

DNI

D11 1N4148W-7-F

2

1

J8

HDR_1X3

1

2

3

D3 1N4148W-7-F

2 1

D20 1N4148W-7-F

2

1

L1

4000E

1

3

2

4

D17 1N4148W-7-F

2 1

P2B

CON_DSUB_9_MM

B1

B6

B2

B7

B3

B8

B4

B9

B5

SH3

SH4

R38

10K

D2

1N4148W-7-F

2 1

J73 HDR_1X2

1

2

R55 0E

R27 1M

R51 0E

D18 1N4148W-7-F

2

1

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 50

Figure C-13. CXPI, EEPROM & POT

5

4

3

2

1

D D

C C

B B

A A

Default Closed

Default closed Default closed

Default closed

CXPI_INTERFACE

Default Closed

EEPROM INTERFACE

Default closed

POTENTIOMETER

Default Open Default Open

Default Closed

CXPI_RXD_W

CXPI_TXD_W

CXPI_CLK_W

CXPI_NSLP_W

CXPI_SELMS_W

CXPI_CLK_W CXPI_NSLP_W

CXPI_SELMS_W

SPI0_CLK_W

SPI0_MOSI_W

SPI0_WP_n

SPI0_HOLD_n

SPI0_MISO_W

SPI0_SS_n_W

SPI0_WP_nSPI0_HOLD_n

SPI0_SS_n_W

CXPI_BUS

VDD_IO

VDD_IO VDD_IO

VDD_IO

ANALOG_VCC

VDD_IO ANALOG_VCC

VDD_IOVDD_IO

VDD_IO

CXPI_VS

VBAT

VDD_IO

CXPI_TXD

5,17

CXPI_RXD5,17

CXPI_CLK 5,18 CXPI_NSLP 5,17

CXPI_SELMS 5,17

SPI0_MOSI5,18

SPI0_CLK4,17

SPI0_MISO 5,18

SPI0_SS4,17

BB_ADC_POT

5,18

SPI0_HOLD5,18 SPI0_WP5,17

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Wednesday, November 20, 2019

CXPI, EEPROM & POT

BALA K SHANTANU

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CXPI, EEPROM & POT

BALA K SHANTANU

SCH Title :

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15 18

Wednesday, November 20, 2019

CXPI, EEPROM & POT

BALA K SHANTANU

J12

HDR_1X2

1 2

J45 HDR_1X2

1

2

C61

0.1uF

J47 HDR_1X2

1

2

R43 4.7K_1%

C41

0.1uF

J50 HDR_1X2

1

2

J48 HDR_1X2

1

2

+

C11 22uF_20V

J11 HDR_1X2

1

2

R80 10K

U9

25LC320A

CS

1

SO

2

WP

3

VSS

4

SI

5

SCK

6

HOLD

7

VCC

8

R82 10K

R115 1K

5% 0402

R24 1K

C65 33pF

R79 10K

DNI

R44 4.7K_1%

J14 HDR_1X2

1

2

C60

0.1uF

J13

HDR_1X2

1 2

R78 10K

DNI

J89 HDR_1X2

1

2

U2

S6BT112A01

RXD

1

NSLP

2

CLK

3

TXD

4

GND

5

BUS

6

BAT

7

SELMS

8

POT1 PTV09A-4015U-B103

1 3

2

SH1

SH2

D5

1N4002-T

21

J6 HDR_1X2

1

2

FL5

600E

1 2

R37

4.7K_1%

C64

0.1uF

R42

4.7K_1%

C16

0.1uF

J9

HDR_1X2

1 2

J49 HDR_1X2

1

2

D6 1N4148W-7-F

21

C17 220pF

R81 10K

C40

10uF

P1

CON_DSUB_9_M

9

8

7

6

5

4

3

2

1 10

11

J46 HDR_1X2

1

2

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 51

Figure C-14. USER_LED & PUSHBUTTON

5

4

3

2

1

D D

C C

B B

A A

Default Closed

USER_LED INTERFACE

USER_BUTTON INTERFACE

NOTE: 5-RED & 5-GREEN LED COLOR

BB_USER_LED0_W

BB_USER_LED1_W

BB_USER_LED2_W

BB_USER_LED3_W

BB_USER_LED8_W

BB_USER_LED9_W

BB_USER_BUTTON_1_W BB_USER_BUTTON_2_W BB_USER_BUTTON_3_W BB_USER_BUTTON_4_W BB_USER_BUTTON_5_W

BB_USER_LED4_W

BB_USER_LED5_W

BB_USER_LED6_W

BB_USER_LED7_W

VDD_IO

BB_USER_LED0

4,18

BB_USER_LED1

5,18

BB_USER_LED2

5,18

BB_USER_LED3

5,18

BB_USER_LED4

5,18

BB_USER_LED55,18

BB_USER_LED65,18

BB_USER_LED75,18

BB_USER_LED8

5,17

BB_USER_LED9

5,17

BB_USER_BUTTON_15,17 BB_USER_BUTTON_25,17 BB_USER_BUTTON_35,17 BB_USER_BUTTON_44,17 BB_USER_BUTTON_55,17

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USER_LED&PUSHBUTTON

BALA K SHAN TANU

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16 18

Wednesday, November 20, 2019

USER_LED&PUSHBUTTON

BALA K SHAN TANU

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16 18

Wednesday, November 20, 2019

USER_LED&PUSHBUTTON

BALA K SHAN TANU

R10 0E

LD7

LTST-C150GKT

2 1

C72

0.1uF SW5

7914J-1-000E

13

24

C76

0.1uF

C73

0.1uF

R17 0E

RA1

1K

1 2 3 4

5

6

7

8

LD10 LTST-C150GKT

2

1

C74

0.1uF

R123 10K

LD8 LTST-C150GKT

2

1

C75

0.1uF

R8

0E

LD11 LTST-C150GKT

2

1

R12 0E

LD3

LTST-C150GKT

2 1

R18 0E

RA3 1K

1 2 3 4

5

6

7

8

LD9 LTST-C150GKT

2 1

LD12 LTST-C150GKT

2

1

RA2 1K

1 2 3 45

6

7

8

R9

0E LD4

LTST-C150GKT

2 1

R14 0E

LD5 LTST-C150GKT

2 1

SW2

7914J-1-000E

13

24

R19 0E

J102

HDR_2X5

2 4 6 8 10

1 3 5 7 9

RA4 10K

123

4 5

678

R16 0E

SW3

7914J-1-000E

13

24

LD6

LTST-C150GKT

2 1

RA5 100E

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

9

SW4

7914J-1-000E

13

24

R15 0E

SW1

7914J-1-000E

13

24

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 52

Figure C-15. Pin Header Section-01

5

4

3

2

1

D D

C C

B B

A A

PIN HEADER SECTION -01

VCC_3V3 VCC_3V3

VCC_3V3

VCC_5V

BB_USER_BUTTON_44,16

LIN4_RXD

5,12

LIN3_WAKE

5,11

LIN3_RXD

5,11

LIN2_WAKE

5,11

LIN2_RXD

5,11

LIN4_TXD 5,12

LIN3_SLP 5,11

LIN3_TXD 5,11

LIN2_SLP 5,11

LIN2_TXD 5,11

BB_I2C1_SCL

5

BB_I2C1_SDA 5

LIN4_SLP 5,12

LIN4_WAKE

5,12

SPI0_WP

5,15

SUPPLY_INH 5,14

LIN0_RXD5,10

LIN0_TXD 5,10

LIN0_WAKE

5,10

LIN0_SLP 5,10

CXPI_RXD5,15 CXPI_TXD 5,15

LIN5_RXD5,12 LIN5_TXD 5,12 LIN5_WAKE5,12 LIN5_SLP 5,12 CXPI_SELMS

5,15

CXPI_NSLP 5,15 BB_HPMC_25 BB_HPMC_3 5 BB_HPMC_15 BB_HPMC_4 5

BB_PWM_24 BB_PWM_44 BB_PWM_64

BB_PWM_1 4 BB_PWM_3 4 BB_PWM_5 4 BB_PWM_7 4

BB_ADC_24 BB_ADC_4

4

BB_ADC_64 BB_ADC_8

4

BB_ADC_3 4 BB_ADC_5 4 BB_ADC_7 4

UART1_TX4

UART1_RX 4

UART1_CTS4

UART1_RTS 4

CAN2_RXD

4,6

CAN2_TXD 4,6

CAN_SPI1_SS14,8 CAN_ SPI1_SS0 4,8

CAN2_S4,6

CAN_SPI1_SS2 4,9

CAN4_S4,7

CAN3_S 4,6

CAN8_WAKE4,9

CAN5_S 4,7 CAN9_WAKE 4,9

CAN5_RXD4,7

CAN4_RXD

4,7

DEBUG_GPIO_34 DEBUG_GPIO_1

4 BB_USER_BUTTON_25,16 BB_USER_BUTTON_55,16

CAN5_TXD 4,7 CAN4_TXD 4,7 DEBUG_GPIO_4 4 DEBUG_GPIO_2 4

BB_USER_BUTTON_1 5,16 BB_USER_BUTTON_3 5,16

CAN6_WAKE 4,8

CAN7_WAKE4,8

SPI0_CLK

4,15

SPI0_SS 4,15

LIN1_SLP

5,10

LIN1_WAKE 5,10

CAN0_S

5,6

BB_USER_LED9 5,16

BB_USER_LED85,16

CAN1_RXD 5,6

CAN1_TXD

5,6

CAN1_S 5,6

CAN0_RXD5,6

CAN0_TXD 5,6

BB_ADC_9

5

LIN1_TXD 5,10

LIN1_RXD5,10

BB_ADC_10 5

BB_ADC_115

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PIN HEADER SECTION-01

BALA K SHAN TANU

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PIN HEADER SECTION-01

BALA K SHAN TANU

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PIN HEADER SECTION-01

BALA K SHAN TANU

JP9

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

JP6

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

JP1

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1

3

5

7

9 11 13 15 17 19

JP11

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

JP10

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

JP2

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 53

Figure C-16. Pin Header Section-02

5

4

3

2

1

D D

C C

B B

A A

PIN HEADER SECTION -02

VCC_3V3

VCC_5V VCC_3V3

VCC_5V

DEBUG_GPIO_55 DEBUG_GPIO_65 DEBUG_GPIO_75 DEBUG_GPIO_85 DEBUG_GPIO_95 DEBUG_GPIO_105 DEBUG_GPIO_115 DEBUG_GPIO_125

SPI2_MOSI 5 SPI2_CLK 5

SPI2_MISO 5

SPI2_SS 5 CAN3_TXD 5,6 CAN3_RXD 5,6

DEBUG_GPIO_205 DEBUG_GPIO_19 5 DEBUG_GPIO_185 DEBUG_GPIO_17 5 DEBUG_GPIO_165 DEBUG_GPIO_15 5 DEBUG_GPIO_145 DEBUG_GPIO_13 5 DEBUG_GPIO_275 DEBUG_GPIO_26 5

DEBUG_GPIO_25_W5 DEBUG_GPIO_24 5

DEBUG_GPIO_235 DEBUG_GPIO_22_W 5

DEBUG_GPIO_21_W5

BB_EXP2_GPIO_165 BB_EXP2_GPIO_145

BB_EXP2_GPIO_15 5

BB_EXP2_GPIO_13 5 BB_EXP2_GPIO_125 BB_EXP2_GPIO_11 5 BB_EXP2_GPIO_105 BB_EXP2_GPIO_9 5

BB_EXP2_GPIO_85 BB_EXP2_GPIO_65 BB_EXP2_GPIO_45

BB_EXP2_GPIO_7 5 BB_EXP2_GPIO_5 5 BB_EXP2_GPIO_3 5

BB_EXP2_GPIO_25 BB_EXP2_GPIO_1 5

BB_EXP1_GPIO_24 BB_EXP1_GPIO_44 BB_EXP1_GPIO_64

BB_EXP1_GPIO_84 BB_EXP1_GPIO_104 BB_EXP1_GPIO_124 BB_EXP1_GPIO_144 BB_EXP1_GPIO_16

4

BB_EXP1_GPIO_3 4 BB_EXP1_GPIO_5 4 BB_EXP1_GPIO_7 4 BB_EXP1_GPIO_9 4 BB_EXP1_GPIO_11 4 BB_EXP1_GPIO_13 4 BB_EXP1_GPIO_15 4

BB_EXP1_GPIO_1 4

BB_GPIO_495 BB_GPIO_515 BB_GPIO_535 BB_GPIO_555

BB_PWM_85

BB_PWM_105

BB_GPIO_48 5 BB_GPIO_50 5 BB_GPIO_52 5 BB_GPIO_54 5

BB_GPIO_56_RESET 5

BB_PWM_9 5

CAN_SP I1_MISO5,8,9 SPI0_HOLD 5,15

CAN_SPI1_SCK5,8,9 CAN_SPI1_MOSI 5,8,9

UART0_RX

5

UART0_CTS 5

UART0_RTS5 UART0_TX 5

BB_USER_LED7

5,16

BB_USER_LED5 5,16

BB_USER_LED35,16 BB_USER_LED1 5,16

BB_ADC_POT

5,15

BB_ADC_1 5 BB_USER_LED25,16 BB_USER_LED4 5,16 BB_USER_LED65,16

BB_GPIO_37 5

CXPI_CLK5,15

BB_USER_LED0 4,16

SPI0_MOSI 5,15 SPI0_MISO 5,15

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PIN HEADER SECTION-02

BALA K SHAN TANU

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PIN HEADER SECTION-02

BALA K SHAN TANU

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18 18

Wednesday, November 20, 2019

PIN HEADER SECTION-02

BALA K SHAN TANU

JP12

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

JP5

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

JP8

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

JP4

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

JP7

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

JP3

HDR_2X10

2 4 6 8 10 12 14 16 18 20

1 3 5 7

9 11 13 15 17 19

Schematics of Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 54

D. Component Assembly on Base Board

ART FILM - TASY

P2

P1

JP1

JP2

JP4JP3

R2

C1

C2

C3

J38

C4

C5

C6

J84

JP8

SW2

RA5

SW3 SW4 SW5 SW6

JP9

J64

SW1

JP10

JP11 JP12

C8

C9

C10

FL3

LD13

LD16

LD13 LD14LD15

LD17LD18 LD19

LD20

R21

FL2

FL1

LD1 LD2

TP2

TP3TP4

R3

JP5

J132

J133

J134

J7

R1

R4

R5

R6

R7

R11

P4

P5

P6

P7

P8

P9

J107

J119

J120

P10

J108

J8

J6

J11

J16

J23

J31

J32 J33 J34 J35

J39

J46

J45

J52

J59

J66

J70

J76

J81

J86

J97

J99

J94

J112

J117

J121

J114 J131

J125

J123

J122

J124

J118 J116 J115

J113 J111

J103

J106

J109 J110

J104 J105

J95

J100 J98

J96

J101

J91

J78

J83

R20

J89

RA4

P0T1

J102

J88

D4

D3

D2

D1

J93

J72J73

JP7

J80

TP9 TP10 TP11 TP12

TP6

TP5

TP7 TP8

R101 R102

J47J48

J54

J61

J68

J62

J63

J55

J49

J40

J53

J60

J67

J71

J77

J82

J87

J92

J56

J41 J42 J43

LD3

RA1 RA2 RA3

LD4

LD5

LD6

LD7

R15

R14

R12

R10

R9

R8

R19

R18

R17

R16

LD8

LD9

LD10

LD11

LD12

J50

J25J26

J18J19

J12

J17

J24

J20

J27

JP6

J13

J14

J9

P3

J10J11

J21J22J28J30

J36

J37

J44J51

J57

J58J65J69J75

J79J85J90

This appendix shows the top and bottom assembly of the PCB.

Figure D-1. Top Assembly of the PCB

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 55

Figure D-2. Bottom Assembly of the PCB

ART FILM - BASY

D5

C11

C16

C17

C13

C19

R26

R25

R51

R45

R52

R46

C23

C22

C18

C14

C15

C20

C21

L3

R27

R28

R29

R23

R22

R30

C12

R31

R32

R33R34

R35

R36 R39

R53

R54

R55

R56

R47

R48

R49

R50

R38

R40

R41

U2

R24

R37

R42

R44

R43

R59

R60

R64

D11

D12

D13

D15

D17

D18

D19

D20

R69

R74

R75

R85

R86

R90

R91

R78

R76

R80

R65R70

D6

L1

L2

U4

U3

U5

U6

D9

U7

D14

D10

C26

C27

C30

C33

C32

R67

R68

C31

C34

C35

C37

C36

C38

C39

R81

C40

C43

C42

D23

C41

U9

U10

C44

C47

C46

R87

D24

U11

C45

C48

D25

D26

C50

C51

C52

C53

C54

C55

C56

C57

C58C62

C63

R120

R124

R127

R126

R125

R137

R136

R140

R139

R129

R128

R130

R131

C79

C81

C83 C84 C85 C86

R133

R134

C82

U21

U20

R135

R138

R142

R144

R141

R13

U1

C7

R132

R122

R115

FL5

R123

C76

C75

C74

C73

C72

C65

C64

C61

C60

FL4

R143

C89

C90

C87

C88

C80

C77

C78

R121

C59

R96 R100 R106 R110 R114 R119

U12

U13

U14

U15

U16

U17

U18

U19

C66

C67

C68

C69

C70

C71

R93 R94 R95

R97 R98 R99

R103 R104 R105

R107 R108 R109

R111 R112 R113

R116 R117 R118

C49

R92

R89

R88

R82

R84

R83

R79

R77

D21

D22

R73

R72

D16

U8

R71

R63

R66

R62

C24

C29

C28

C25

R61

D8

D7

R57

R58

Component Assembly on Base Board

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 56

Revision History

Document Revision History

Document Title: CYTVII-B-E-1M-176-CPU Evaluation Board User Guide

Document Number: 002-22883

Revision ECN# Issue Date Description of Change

** 6186303 05/25/2018 New user guide for TVII CPU board.

Sunset Review

*A 6501207 03/05/2019

*B 6759586 12/23/2019

*C 6785957 01/24/2020

TVII-B-E-1M-176-CPU board user guide updated as per Rev C board designs.

1. Added 5 V and 3.3 V selectable power supply for CPU board using J23.

2.CPU board to base board pin connection are updated in Table 4-1.

Updated content in section 1. Introduction and 2. Overview.

Updated Figure 2-1 and Figure 3-1.

Updated A. Schematics of CPU Board, B. Component Assembly on CPU Board, C.

Schematics of Base Board, and D. Component Assembly on Base Board with text

searchable content.

Fixed Figure A-12.

Updated content in section 2. Overview.

CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C 57

Cypress CYTVII-B-E-1M-176-CPU User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

1. Introduction

1.1 Precautions and Warnings

2. Overview

2.1 Functional Overview

3. Operation

4. Connections and Settings

A. Schematics of CPU Board

B. Component Assembly on CPU Board

C. Schematics of Base Board

D. Component Assembly on Base Board

Revision History

Document Revision History