CYPRESS CYRF6936 User Manual

WirelessUSB™ LP 2.4 GHz Radio SoC

CYRF6936

Features

Data

Interface

and

Sequencer

DSSS

Baseband

& Framer

SPI

Synthesizer

GFSK

Demodulator

GFSK

Modulator

IRQ

SS

SCK
MISO
MOSI

RF

P

RF

N

XTAL

XOUT

Block Diagram

RSSI

Xtal Osc

Power Management

L/D

V

REG

V

BAT

V

DD

RF

BIAS

RST

V

IO

PACTL

V

CC

GND

CYRF6936 Simplified Block Diagram

Applications

• 2.4 GHz Direct Sequence Spread S p ectrum (DSSS) radio
transceiver

• Operates in the unlicensed worldwide Industrial, Scientific
and Medical (ISM) band (2.400 GHz–2.483 GHz)

• 21 mA operating current (Transmit @ –5 dBm)

• Transmit power up to +4 dBm

• Receive sensitivity up to –97 dBm

• Sleep Current <1 μA

• Operating range: 10m+

• DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps

• Low external component count

• Auto Transaction Sequencer (ATS) - no MCU intervention

• Framing, Length, CRC16, and Auto ACK

• Power Management Unit (PMU) for MCU/Sensor

• Fast Startup and Fast Channel Changes

• Separate 16-byte Transmit and Receive FIFOs

• AutoRate™ - dynamic data rate reception

• Receive Signal Strength Indication (RSSI)

• Serial Peripheral Interface (SPI) control while in sleep mode

• 4 MHz SPI microcontroller interface

• Battery Voltage Monitoring Circuitry

• Supports coin-cell operated applications

• Operating voltage from 1.8V to 3.6V

• Operating temperature from 0 to 70°C

• Space saving 40-pin QFN 6x6 mm package

• Wireless Keyboards and Mice

• Wireless Gamepads

• Remote Controls

•Toys

• VOIP and Wireless Headsets

• White Goods

• Consumer Electronics

• Home Automation

• Automatic Meter Readers

• Personal Health and Entertainment

Applications Support

See www.cypress.com for development tools, reference
designs, and application notes.

Functional Description

The CYRF6936 WirelessUSB™ LP radio is a second gene r­ation member of Cypress’s WirelessUSB Radio
System-On-Chip (SoC) family. The CYRF6936 is interop­erable with the first generation CYWUSB69xx devices. The
CYRF6936 IC adds a range of enhanced features, including
increased operating voltage range, reduced supply current in
all operating modes, higher data rate options, and reduced
crystal start up, synthesizer settling and link turnaround times.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-16015 Rev. *G Revised April 2, 2007

CYRF6936

Pin Descriptions

CYRF6936

40-lead QFN

RF

BIAS

NC

NC

V

BAT

V

CC

V

BAT

XTAL

V

CC

NC

NC

V

REG

NC

NC

V

BAT

L/D

NC

NC

V

IO

V

DD

RST

RFNNCNCVCCNCNCRESV

NC

GND

RF

P

NC

SS

SCK

IRQ / GPIO

MOSI / SDAT

MISO / GPIO

XOUT / GPIO

PACTL / GPIO

NC
NC

23

24

25

26

27

28

29

30

22
21

13141516171819

20

12

11

10

9

2

8

7

6

1

3

5

4

40

3932383736

31

333534

* E-PAD BOTTOM SIDE

CYRF6936

Top View*

Pin # Name Type Default Description

13 RF
11 RF
10 RF
30 PACTL I/O O Control signal for external PA, T/R switch, or GPIO
1 XTAL I I 12 MHz crystal
29 XOUT I/O O Buffered 0.75, 1. 5 , 3, 6 or 12 MHz clock, PACTL, or GPIO.

25 SCK I I SPI clock
28 MISO I/O Z SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).

27 MOSI I/O I
24 SS I I SPI enable, active LOW assertion. Enables and frames transfers
26 IRQ I/O O Interrupt output (configurable active HIGH or LOW), or GPIO
34 RST I I Device reset. Internal 10 kohm pull down resistor. Active HIGH, typically

37 L/D O PMU inductor/diode connection, when used. If not used, connect to GND
40 V
35 V

6, 8, 38 V
3, 7, 16 V
33 V

REG
DD

BAT
CC
IO

19 RESV I Must be connected to GND
2, 4, 5, 9, 14, 15, 18, 17, 20,

NC NC Connect to GND

21, 22, 23, 32, 36, 39, 31
12 GND GND Ground
E-PAD GND GND Ground

I/O I Differential RF signal to/from antenna

N

I/O I Differential RF signal to/from antenna

P

O O RF I/O 1.8V reference voltage

BIAS

Tri-states in sleep mode (configure as GPIO drive LOW)

Tri-states when SPI 3PIN = 0 and SS

is deasserted

SPI data input pin (Master Out Slave In), or SDAT

connect through a 0.47 μF capacitor to V
the first time power is applied to the radio. Otherwise the state of the radio

Must have RST = 1 event

BAT.

control registers is unknown

Pwr PMU boosted output voltage feedback
Pwr Decoupling pin for 1.8V logic regulator, connect through a 0.47 μF

capacitor to GND
Pwr V
Pwr VCC = 2.4V to 3.6V. Typically connected to V

= 1.8V to 3.6V. Main supply

BAT

REG

Pwr I/O interface voltage, 1.8–3.6V

Figure 1. CYRF6936, 40 QFN – Top View

Document #: 38-16015 Rev. *G Page 2 of 40

CYRF6936

Functional Overview

P SOP 1 SOP 2 Length CRC 16

Payload Data

Preamble

n x 16us

1st Framing

Sym bol*

2nd Framing

Sym bol*

Packet

length
1 Byte
Period

*Note:32 or 64us

The CYRF6936 IC provides a complete WirelessUSB SPI to
antenna wireless MODEMs. The SoC is designed to
implement wireless device links operating in the worldwide

2.4 GHz ISM frequency band. It is intended for systems
compliant with worldwide regulations covered by ETSI EN 301
489-1 V1.41, ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR
47 Part 15 (USA and Industry Canada) and TELEC
ARIB_T66_March, 2003 (Japan).

The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer, DSSS baseband
controller, Received Signal Strength Indication (RSSI), and
SPI interface for data transfer and device configuration.

The radio supports 98 discrete 1 MHz channels (regulations
may limit the use of some of these channels in certain jurisdic­tions).

The baseband performs DSSS spreading/despreading, Start
of Packet (SOP), End of Packet (EOP) detection, and CRC16
generation and checking. The baseband may also be
configured to automatically transmit Acknowledge (ACK)
handshake packets whenever a valid packet is received.

When in receive mode, with packet framing enabled, the
device is always ready to receive data transmitted at any of the
supported bit rates, enabling the implementation of mixed-rate
systems in which different devices use different data rates.
This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both, and change
to lower data rates at longer distances or in high interference
environments or both.

In addition, the CYRF6936 IC has a Power Management Unit
(PMU), which allows direct connection of the device to any
battery voltage in the r ange 1.8V t o 3.6V. The PMU conditions
the battery voltage to provide the supply voltages required by
the device, and may supply external devices.

Data Transmission Modes

The SoC supports four different data transmission modes:

• In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.

• In 8DR mode, eight bits are encoded in each derived code
symbol transmitted.

• In DDR mode, two bits are encoded in each derived code
symbol transmitted. (As in the CYWUSB6934 DDR mode).

• In SDR mode, one bit is encoded in each derived code
symbol transmitted. (As in the CYWUSB6934 standard
modes.)

Both 64 chip and 32 chip Pseudo Noise (PN) codes are
supported. The four data transmission modes apply to the data
after the SOP. In particular the length, data, and CRC16 are all
sent in the same mode. In general, lower data rates reduce
packet error rate in any given environment.

Link Layer Modes

The CYRF6936 IC device supports the following data packet
framing features:

SOP – Packets begin with a two-symbol Start of Packet
marker. This is required in GFSK and 8DR modes, but is
optional in DDR mode and is not supported in SDR mode ; if
framing is disabled then an SOP event is inferred whenever
two successive correlations are detected. The
SOP_CODE_ADR code used for the SOP is different from that
used for the “body” of the packet, and if desired may be a
different length. SOP must be configured to be the same
length on both sides of the link.

Length – There are two options for detecting the end of a
packet. If SOP is enabled, then the length field should be
enabled. GFSK and 8DR must enable the length field. This is
the first eight bits after the SOP symbol, and is transmitted at
the payload data rate. When the length field is enabled, an End
of Packet condition is inferred after reception of the number of
bytes defined in the length field, plus two bytes for the CRC16
(when enabled—see the following paragraph). The alternative
to using the length field is to infer an EOP condition from a
configurable number of successive noncorrelations; this
option is not available in GFSK mode and is only recom­mended when using SDR mode.

CRC16 – The device may be configured to append a 16 bit
CRC16 to each packet. The CRC16 uses the USB CRC
polynomial with the added programmability of the seed. If
enabled, the receiver verifies the calculated CRC16 for the
payload data against the received value in the CRC16 field.
The seed value for the CRC16 calculation is configurable, and
the CRC16 transmitted may be calculated using either the
loaded seed value or a zero seed; the received data CRC16
is checked against both the configured and zero CRC16
seeds.

CRC16 detects the following errors:

• Any one bit in error

• Any two bits in error (no matter how far apart, which column,
and so on)

• Any odd number of bits in error (no matter where they are)

• An error burst as wide as the checksum itself

Figure 2 shows an example packet with SOP, CRC16 and

lengths fields enabled, and Figure 3 on page 4 shows a
standard ACK packet.

Figure 2. Example Packet Format

Document #: 38-16015 Rev. *G Page 3 of 40

CYRF6936

Figure 3. Example ACK Packet Format

P SOP 1 SO P 2 CRC 16

Preamble

n x 16us

1st Fram ing

Sym bol*

2nd Framing

Sym bol*

CRC field from

received packet.

2 Byte periods

*Note:32 or 64us

Packet Buffers

All data transmission and reception uses the 16 byte packet
buffers—one for transmission and one for reception.

The transmit buffer allows a complete packet of up to 16 bytes
of payload data to be loaded in one burst SPI transaction, and
then transmitted with no further MCU intervention. Similarly,
the receive buffer allows an entire packet of payload data up
to 16 bytes to be received with no firmware intervention
required until packet reception is complete.

The CYRF6936 IC supports packets up to 255 bytes.
However, actual maximum packet length depends on the
accuracy of the clock on each end of the link and the data
mode; interrupts are provided to allow an MCU to use the
transmit and receive buffers as FIFOs. When transmitting a
packet longer than 16 bytes, the MCU can load 16 bytes
initially, and add further bytes to the transmit buffer as trans­mission of data creates space in the buffer. Similarly, when
receiving packets longer than 16 bytes, the MCU must fetch
received data from the FIFO periodically during packet
reception to prevent it from overflowing.

Auto Transaction Sequencer (ATS)

The CYRF6936 IC provides automated support for trans­mission and reception of acknowledged data packets.

When transmitting in transaction mode, the device automati­cally:

• Starts the crystal and synthesizer

• Enters transmit mode

• Transmits the packet in the transmit buffer

• Transitions to receive mode and waits for an ACK packet

• Transitions to the transaction end state when either an ACK
packet is received, or a timeout period expires

Similarly, when receiving in transaction mode, the device
automatically:

• Waits in receive mode for a valid packet to be received

• Transitions to transmit mode, transmits an ACK packet

• Transitions to the transaction end state (receive mode to
await the next packet, and so on.)

The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.

In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used); to transmit data the MCU simply must
load the data packet to be transmitted, set the length, and set
the TX GO bit. Similarly, when receiving pa ckets in transaction
mode, firmware simply must retrieve the fully received packet

in response to an interrupt request indicating reception of a
packet.

Backward Compatibility

The CYRF6936 IC is fully interoperable with the main modes
of the first generation devices. The 62.5 kbps mode is
supported by selecting 32 chip DDR mode. Similarly, the

15.675 kbps mode is supported by selecting 64 chip SDR
mode.

In this way, a suitab ly configured CYRF6936 IC device may
transmit data to or receive data from a first generation device,
or both. Backwards compatibility requires disabling the SOP,
length, and CRC16 fields.

Data Rates

By combining the PN code lengths and data transmission
modes described previously, the CYRF6936 IC supports the
following data rates:

• 1000 kbps (GFSK)

• 250 kbps (32 chip 8DR)

• 125 kbps (64 chip 8DR)

• 62.5 kbps (32 chip DDR)

• 31.25 kbps (64 chip DDR)

• 15.625 kbps (64 chip SDR)

Functional Block Overview

2.4 GHz Radio

The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in seven steps. The supply current of
the device is reduced as the RF output power is reduced.

Table 1. Internal PA Output Power Step Table

PA Setting Typical Output Power (dBm)

7+4
60
5–5
4 –13
3 –18
2 –24
1 –30
0 –35

Document #: 38-16015 Rev. *G Page 4 of 40

CYRF6936

Table 2. Typical Range Observed Table

Environment Typical Range (meters)

Outdoor 30

Office 20

Home 15

Note: Range observed with CY4636 WirelessUSB LP KBM v1.0 (Keyboard)

Frequency Synthesizer

Before transmission or reception may begin, the frequency
synthesizer must settle. The settling time varies depending on
channel; 25 fast channels are provided with a maximum
settling time of 100 μs.

The ‘fast channels’ (less than 100 μs settling time) are every
third channel, starting at 0 up to and including 72 (for example,
0, 3, 6, 9….69, 72).

Baseband and Framer

The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception and CRC16
generation and checking, as well as EOP detection and length
field.

Packet Buffers and Radio Configuration Registers

Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet (as in
the CYWUSB6934). Configuration registers allow configu­ration of DSSS PN codes, data rate, operating mode, interrupt
masks, interrupt status, and so on.

SPI Interface

The CYRF6936 IC has an SPI interface supporting communi­cations between an application MCU and one or more slave
devices (including the CYRF6936). The SPI interface supports
single-byte and multi-byte serial transfers using either 4-pin or
3-pin interfacing. The SPI communications interface consists
of Slave Select (SS
Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial
Data (SDA T).

The SPI communications are as follows:

• Command Direction (bit 7) = ‘1’ enables SPI write trans­action. A ‘0’ enables SPI read transactions.

• Command Increment (bit 6) = ‘1’ enables SPI auto address
increment. When set, the address field automatically incre­ments at the end of each data byte in a burst access,
otherwise the same address is accessed.

), Serial Clock (SCK), and Master

• Six bits of address.

• Eight bits of data.

The device receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI
pin. Data to the application MCU is shifted out on the MISO
pin. The active LOW Slave Select (SS
to initiate an SPI transfer.

The application MCU can initiate SPI data transfers using a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes as shown in

Figure 4 through Figure 7 on page 6.

The SPI communications interface has a burst mechanism,
where the first byte can be followed by as many data bytes as
desired. A burst transaction is terminated by deassertin g the
slave select (SS

The SPI communications interface single read and burst read
sequences are shown in Figure 5 and Figure 6, respectively.

The SPI communications interface single write and burst write
sequences are shown in Figure 7 and Figure 8, respectively.

This interface may optionally be operated in a 3-pin mode with
the MISO and MOSI functions combined in a single bidirec­tional data pin (SDA T). When using 3-pin mode, user firmware
should ensure that the MOSI pin on the MCU is in a high
impedance state except when MOSI is actively transmitting
data.

The device registers may be written to or read from one byte
at a time, or several sequential register locations may be
written/read in a single SPI transaction using incrementing
burst mode. In addition to single byte configuration registers,
the device includes register files; register files are FIFOs
written to and read from using nonincrementing burst SPI
transactions.

The IRQ pin function may optionally be multiplexed onto the
MOSI pin; when this option is enabled the IRQ function is not
available while the SS
ration, user firmware should ensure that the MOSI pin on the
MCU is in a high impedance state whenever the SS
HIGH.

The SPI interface is not dependent on the internal 12 MHz
clock. Registers may therefore be read from or written to while
the device is in sleep mode, and the 12 MHz oscillator
disabled.

The SPI interface and the IRQ and RST pins have a separate
voltage reference pin (V
directly to MCUs operating at voltages below the CYRF6936
IC supply voltage.

= 1).

pin is LOW. When using this configu-

), enabling the device to interface

IO

) pin must be asserted

pin is

Document #: 38-16015 Rev. *G Page 5 of 40

CYRF6936

Figure 4. SPI Transaction Format

Byte 1 Byte 1+N

Bit # 7 6 [5:0] [7:0]

Bit Name DIR INC Address Data

DIR

0

INCA5A4A3A2A1A0

D7 D6 D5 D4 D3 D2 D1 D0

SCK

MOSI

SS

MISO

cmd addr

data to mcu

DIR

0

INCA5A4A3A2A1A0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

data to mcu

1

cmd addr

data to mcu

1+N

SCK

MOSI

SS

MISO

DIR

1

INCA5A4A3A2A1A0

D7 D6 D5 D4 D3 D2 D1 D0

SCK

MOSI

SS

MISO

cmd addr data from mcu

DIR

1

INCA5A4A3A2A1A0

D7 D6 D5 D4 D3 D2 D1 D0

SCK

MOSI

SS

MISO

cmd addr data from mcu

1

D7 D6 D5 D4 D3 D2 D1 D0

data from mcu

1+N

Figure 5. SPI Single Read Sequence

Figure 6. SPI Incrementing Burst Read Sequence

Figure 7. SPI Single Write Sequence

Figure 8. SPI Incrementing Burst Write Sequence

Document #: 38-16015 Rev. *G Page 6 of 40

CYRF6936

Interrupts

The device provides an interrupt (IRQ) output, which is config­urable to indicate the occurrence of various different events.
The IRQ pin may be programmed to be either active HIGH or
active LOW, and be either a CMOS or open drain output. A full
description of all the available interrupts can be found in

“Register Descriptions” on page 12.

The CYRF6936 IC features three sets of interrupts: transmit,
receive, and system interrupts. These interrupts all share a
single pin (IRQ), but can be independently enabled/disa bled.
The contents of the enable registers are preserved when
switching between transmit and receive modes.

If more than one interrupt is enabled at any time, it is
necessary to read the relevant status register to determine
which event caused the IRQ pin to assert. Even when a given
interrupt source is disabled, the status of the condition that
would otherwise cause an interrupt can be determined by
reading the appropriate status register. It is therefore possible
to use the devices without the IRQ pin by polling the status
registers to wait for an event, rather than using the IRQ pin.

Clocks

A 12 MHz crystal (30 ppm or better) is directly connected
between XTAL and GND without the need for external capac­itors. A digital clock out function is provided, with selectable
output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output
may be used to clock an external microcontroller (MCU) or
ASIC. This output is enabled by default, but may be disabled.

Listed below are the requirements for the crystal to be directly
connected to XTAL pin and GND.

• Nominal Frequency: 12 MHz

• Operating Mode: Fundamental Mode

• Resonance Mode: Parallel Resonant

• Frequency Initial Stability: ±30 ppm

• Series Resistance: <

• Load Capacitance: 10 pF

• Drive Level: 10 µW–100 µW

Power Management

The operating voltage of the device is 1.8V to 3.6V DC, which
is applied to the V
fully static sleep mode by writing to the FRC END = 1 and END
STATE = 000 bits in the XACT_CFG_ADR register over the
SPI interface. The device enters sleep mode within 35 µs after
the last SCK positive edge at the end of this SPI transaction.
Alternatively, the device may be configured to automatically
enter sleep mode after completing packet transmission or
reception. When in sleep mode, the on-chip oscillator is
stopped, but the SPI interface remains functional. The device
wakes from sleep mode automatically when the device is

60 ohms

pin. The device can be shut down to a

BAT

commanded to enter transmit or receive mode. When
resuming from sleep mode, there is a short delay while the
oscillator restarts. The device can be configured to assert the
IRQ pin when the oscillator has stabilized.

The output voltage (V
(PMU) is configurable to several minimum values between

2.4V and 2.7V. V
(average load) to external devices. It is possible to disable the
PMU, and to provide an externally regulated DC supply
voltage to the device’s main supply in the range 2.4V to 3.6V.
The PMU also provides a regulated 1.8V supply to the logic.

The PMU is designed to provide high boost efficiency
(74–85% depending on input voltage, output voltage and load)
when using a Schottky diode and power inductor, eliminating
the need for an external boost converter in many systems
where other components require a boosted voltage. However,
reasonable efficiencies (69–82% depending on input voltage,
output voltage, and load) may be achieved when using low
cost components such as SOT23 diodes and 0805 inductors.

The PMU also provides a configurable low battery detection
function, which may be read over the SPI interface. One of
seven thresholds between 1.8V and 2.7V may be selected.
The interrupt pin may be configured to assert when the voltage
on the V
is not a latched event. Battery monitoring is disabled when the
device is in sleep mode.

Low Noise Amplifier and Received Signal Strength Indication

The gain of the receiver can be controlled directly by clearing
the AGC EN bit and writing to the Low Noise Amplifier (LNA)
bit of the RX_CFG_ADR register. Clearing the LNA bit reduces
the receiver gain approximately 20 dB, allowing accurate
reception of very strong received signals (for example when
operating a receiver very close to the transmitter). Approxi­mately 30 dB of receiver attenuation can be a dded b y se tting
the Attenuation (ATT) bit; this allows data reception to be
limited to devices at very short ranges. Disabling AGC and
enabling LNA is recommended unless receiving from a device
using external PA.

When the device is in receive mode the RSSI_ADR registe r
returns the relative signal strength of the on-channel signal
power.

When receiving, the device automatically measures and
stores the relative strength of the signal being received as a
five bit value. An RSSI reading is taken automatically when the
SOP is detected. In addition, a new RSSI reading is taken
every time the previous reading is read from the RSSI_ADR
register, allowing the background RF energy level on any
given channel to be easily measured when RSSI is read when
no signal is being received. A new reading can occur as fast
as once every 12 µs.

BAT

REG

pin falls below the configured threshold. LV IRQ

) of the Power Management Unit

REG

may be used to provide up to 15 mA

Document #: 38-16015 Rev. *G Page 7 of 40

CYRF6936

Application Examples

SDATA

ISSP

SCLK

XRES

BIND

Serial debug

header

Layout J3 and J2.1 in a

0.100" spacing

configuration

E-PAD must be soldered to ground.

Radio Decoupling Caps

RF VCO

and VCO

Buffer

Filter

The power supply decoupling shown for VBAT0

is a recommended cost effective

configuration:

C6=No Load R2= 1ohm C7=10uF ceramic.

For this configuration, it is required that

C18 be installed.

An alternate decoupling configuration is

the following:

C6=47uF ceramic R2=0ohm C7=.047uF.

For this configuration, it is not required

to load C18.

For reference design part numbers, please

refer to the Bill of Materials file

121-26504_A.xls.

A 2-pin jumper

installed from J3.1

to J2.1 enables the

radio to power the

processor. Jumper

removal is required

when programming U2

to disconnect the

radio from the

Miniprog 5V source.

R1 is a zero ohm

resistor that should

be installed for

production units

only, following

programming.

MISO

MOSI

P1_1

SCK

P1_0

MISO

nSS

IRQ

MOSI

CLKOUT

RST

SCK

COL16

COL10

COL17

COL9

COL13

P1_0

COL15

COL18

COL12

COL11

COL14

nSS

P1_1

COL5

COL3

COL2

COL8

COL1

COL6

COL7

COL4

ROW5

ROW4

ROW6

ROW2

ROW7

ROW1

ROW8

ROW3

IRQ

SW1

PACTL

EVCC

VCC

VBAT

VBAT

VCC

VBAT

VCC

EVCC

SOT23

D1

BAT400D

2 1

IND0402

L2

1.8 nH

U2

CY7C60123-PVXC

30

161718

292826

25

19

23

12

5

7

24

10

2043214222

6

34353637383940

41

131415

313233

2744

1198412346474845

P1_4 / SCLK

P0_7

P0_6 / TIO1

P0_5 / TIO0

P1_3 / SSEL

P1_2

P1_1

P1_0

P0_4 / INT2

P0_0 / CLKIN

P2_3

VDD1

P4_0

VSS1

P2_5

P0_3 / INT1

P4_3

P0_2 / INT0

P4_2

P0_1 / CLKOUT

P4_1

P3_0

P3_1

P3_2

P3_3

P3_4

P3_5

P3_6

P3_7

P2_2

P2_1

P2_0

P1_5 / SMOSI

P1_6 / SMISO

P1_7

VDD2VSS2

P2_4

P2_6

P2_7

NC4

NC1

NC2

NC3

NC6

NC7

NC8

NC5

S1

SW PUSHBUTTON

1A

2A

1B

2B

0402

C5

0.47 uFd

IND0603

L1

22 nH

0603

R1

NO LOAD

TV4

0402

C8

1 uFd 6.3V

0402

C11

0.047 uFd

0402

C17

0.47 uFd

0805

R2

1 1%

L3

10 uH

TV5

0805

C12

10 uFd 6.3V

0805

C7

10 uFd 6.3V

0402

C20

0.01 uFd

0402

C16

0.047 uFd

J3

1 PIN HDR

1

TV8

J2

5 PIN HDR

12345

J4

3 PIN HDR

123

0402

R3

47

TP2

TP1

0402

C13

0.047 uFd

U1

CYRF6936

36

4

8

1916202

252726

29

34

28

3

7

5

13

6

37

1

24

39

40

41

35

9

14

10

11

12

151718

21302233233132

38

NC15

NC2

VBAT2

RESV

VCC3

NC9NC1

SCK

MOSI

IRQ

XOUT

RST

MISO

VCC1

VCC2

NC3

RFn

VBAT1

L/D

XTAL

SS

NC16

VREG

E-PAD

VDD

NC4

NC5

RFbias

RFp

GND1

NC6

NC7

NC8

NC10

PACTL

NC11

VIO

NC12

NC13

NC14

VBAT0

0402

C3

2.0 pFd

0402

C1

15 pFd

+

E

C18

100 uFd 10v

0402

C15

0.047 uFd

TV7

TV6

ANT1

WIGGLE 63

1

2

0402

C4

1.5 pFd

Y1

12 MHz Crystal

TV2

1210

C6

No Load

0402

C10

0.047 uFd

TV1

TV3

0402

C19

0.01 uFd

0402

C9

0.047 uFd

Figure 9. Recommended Circuit for Systems Where V

May Fall Below 2.4V

BAT

Document #: 38-16015 Rev. *G Page 8 of 40

CYRF6936

Table 3. Recommended Bill of Materials for Systems Where V

May Fall Below 2.4V

BAT

Item Qty CY Part Number Reference Description Manufacturer Mfr Part Number

1 1 NA ANT1 2.5GHZ H-STUB WIGGLE ANTEN-

2 1 730-10012 C1 CAP 15PF 50V CERAMIC NPO 0402 Panasonic ECJ-0EC1H150J
3 1 730-11955 C3 CAP 2.0 PF 50V CERAMIC NPO

4 1 730-11398 C4 CAP 1.5PF 50V CERAMIC NPO

5 2 730R-13322 C5,C17 CAP CER 0.47UF 6.3V X5R 0402 Murata GRM155R60J474KE19D
6 2 730-13037 C12,C7 CAP CERAMIC 10UF 6.3V X5R 0805 Kemet C0805C106K9PACTU
7 1 730-13400 C8 CAP 1 uF 6.3V CERAMIC X5R 0402 Panasonic ECJ-0EB0J105M
8 6 730-13404 C9,C10,C11,

9 1 730-11952 C19 CAP 0.1 uF 50V CERAMIC X5R 0402 Kemet C0402C104K8PACTU
10 1 710-13201 C18 CAP 100UF 10V ELECT FC Panasonic - ECG EEU-FC1A101S
11 4 730-10794 C20,C23,C24,C25CAP 10000PF 16V CERAMIC 0402

12 3 730-13036 C26,C27,C28 CAP CERAMIC 1.0UF 10V X5R 0603 Kemet C0603C105K8PACTU
13 1 800-13248 D1 DIODE SCHOTTKY 20V 1A SMA Taiwan

14 1 420-11964 J1 HEADER 1 POS 0.230 HT MODII

15 1 420-11496 J3 CONN HDR BRKWA Y 5POS STR AU

16 1 800-13401 L1 INDUCTOR 22NH 2% FIXED 0603

17 1 800-11651 L2 INDUCTOR 1.8NH +-.3NH FIXED

18 1 800-13253 L3 COIL 10UH 1.23A UNSHIELDED

19 1 610-13402 R1 RES 47 OHM 1/16W 5% 0402 SMD Panasonic - ECG ERJ-2GEJ470X
20 1 620-10539 R2 RES 100K OHM 1/16W 5% 0603

21 3 tmp R6,R7,R8 RES CHIP 5.11 OHM 1/16W 1% 0603

22 1 630-11356 R9 RES 1.00 OHM 1/8W 1% 0805 SMD Yageo 9C08052A1R00FKHFT
23 1 CYRF6936-40LFC U1 IC, LP 2.4 GHz RADIO SoC QFN-40 Cypress Semiconductor CYRF6936 Rev A5
24 1 CY7C60323-PVXC U2 IC WIRELESS MICROCONTROL-

25 1 800-13259 Y1 CRYSTAL 12.00MHZ HC49 SMD eCERA GF-1200008
26 1 PDC-9302-*C PCB PRINTED CIRCUIT BOARD Cypress Semiconductor PDC-9302-*C
27 1 920-11206 LABEL1 Serial Number
28 1 920-30200 *C LABEL2 PCA # 121-30200 *C

C13,C15,C16

NA FOR 63MIL PCB

0402

0402 SMD

CAP 0.047 uF 50V CERAMIC X5R
0402

SMD

0.100CL

PCB

SMD

0402 SMD

SMD

SMD

SMD

LER SSOP28

NA NA

Kemet C0402C209C5GACTU

PANASONIC ECJ-0EC1H1R5C

AVX 0402YD473KAT2A

Panasonic - ECG ECJ-0EB1C103K

Semiconductor
AMP/Tyco 103185-1

AMP Division of TYCO 103185-5

Panasonic - ECG ELJ-RE22NGF2

Panasonic - ECG ELJ-RF1N8DF

Sumida CDH53100LC

Panasonic - ECG ERJ-3GEYJ104V

Yageo America 9C06031A5R11FGHFT

Cypress Semiconductor CY7C60323-PVXC

SS12

Document #: 38-16015 Rev. *G Page 9 of 40

CYRF6936

"BIND"

Power Supply

"CONNECT/ACTIVITY"

E-PAD must be soldered to ground.

DP

SW1

VBUS

DM

nSS

SCK

MISO

MOSI

IRQ

SW1

nLED1

nLED2

RST

nLED1

nLED2

IRQ

RST

MOSI

SCK

nSS

MISO

5V

5V

VCC

VCC

5V

VCC

VCC

5V

U1

CYRF6936

36

4

8

1916202

252726

29

34

28

3

7

5

13

6

37

1

24

39

40

41

35

9

14

10

11

12

151718

21302233233132

38

NC15

NC2

VBAT2

RESV

VCC3

NC9NC1

SCK

MOSI

IRQ

XOUT

RST

MISO

VCC1

VCC2

NC3

RFn

VBAT1

L/D

XTAL

SS

NC16

VREG

E-PAD

VDD

NC4

NC5

RFbias

RFp

GND1

NC6

NC7

NC8

NC10

PACTL

NC11

VIO

NC12

NC13

NC14

VBAT0

IND0402

L2

1.8 nH

0402

C9

0.047 uFd

J1

USB A SMT PLUG

12345

6

VBUS

DM

DP

GND

S1

S2

0402

C1

15 pFd

0402

R1

zero

D1

LED Green Red

1

2

3

4

GR

RD

C

C

0402

R2

620

ANT1

WIGGLE 32

1

2

0402

C12

1500 pFd

0402

C10

0.047 uFd

0402

C3

2.0 pFd

0402

C7

0.047 uFd

0805

C13

4.7 uFd

0805

C14

2.2 uFd

S1

SW RA PUSH

1A

1B

2A

2B

0402

C6

0.047 uFd

TV1 TV-20R Y1

12 MHz Crystal

0402

C11

0.047 uFd

0402

C4

1.5 pFd

0402

C8

0.047 uFd

U2

CY7C63803-SXC

7654321

16

15

8 11

1210

9

13

14

P0_0

P0_1

P0_2/INT0

P0_3/INT1

P0_4/INT2

P0_5/TIO0

P0_6/TIO1

MISO/P1_6

MOSI/P1_5

VSS VCC

VREGDM/P1_1

DP/P1_0

SSEL/P1_3

SCLK/P1_4

0402

C5

0.47 uFd

IND0603

L1

22 nH

Figure 10. Recommended Circuit for Systems Where V

is 2.4V to 3.6V (PMU disabled)

BAT

Document #: 38-16015 Rev. *G Page 10 of 40

CYRF6936

Table 4. Recommended Bill of Materials for Systems Where V

is 2.4V to 3.6V (PMU disabled)

BAT

Item Qty CY Part Number Reference Description Manufacturer Mfr Part Number

1 1 NA ANT1 2.5GHZ H-STUB WIGGLE ANTEN-

2 1 730-10012 C1 CAP 15PF 50V CERAMIC NPO 0402 Panasonic ECJ-0EC1H150J
3 1 730-11955 C3 CAP 2.0 PF 50V CERAMIC NPO

4 1 730-11398 C4 CAP 1.5PF 50V CERAMIC NPO

5 1 730-13322 C5 CAP 0.47 uF 6.3V CERAMIC X5R

6 6 730-13404 C6,C7,C8,C9,

7 1 730-11953 C12 CAP 1500PF 50V CERAMIC X7R

8 1 730-13040 C13 CAP CERAMIC 4.7UF 6.3V XR5

9 1 730-12003 C14 CAP CER 2.2UF 10V 10% X7R 0805 Murata Electronics

10 1 800-13333 D1 LED GREEN/RED BICOLOR 1210

11 1 420-13046 J1 CONN USB PLUG TYPE A PCB SMT ACON UAR72-4N5J10
12 1 800-13401 L1 INDUCTOR 22NH 2% FIXED 0603

13 1 800-11651 L2 INDUCTOR 1.8NH +-.3NH FIXED

14 1 610-10343 R1 RES ZERO OHM 1/16W 0402 SMD Panasonic - ECG ERJ-2GE0R00X
15 1 610-13472 R2 RES CHIP 620 OHM 1/16W 5% 0402

16 1 200-13471 S1 SWITCH LT 3.5MMX2.9MM 160GF

17 1 CYRF6936-40LFC U1 IC, LP 2.4 GHz RADIO SoC QFN-40 Cypress Semicondu ctor CYRF6936 Rev A5
18 1 CY7C63803-SXC U2 IC LOW-SPEED USB ENCORE II

19 1 800-13259 Y1 CRYSTAL 12.00MHZ HC49 SMD eCERA GF-1200008
20 1 PDC-9263-*B PCB PRINTED CIRCUIT BOARD Cypress Semiconductor PDC-9263-*B
21 1 LABEL1 Serial Number XXXXXX
22 1 LABEL2 PCA # 121-26305 **

C10,C11

NA FOR 32MIL PCB

0402

0402 SMD

0402
CAP 0.047 uF 16V CERAMIC X5R

0402

0402

0805

SMD

SMD

0402 SMD

SMD

SMD

CONTROLLER SOIC16

NA NA

Kemet C0402C209C5GACTU

PANASONIC ECJ-0EC1H1R5C

Murata GRM155R60J474KE19D

AVX 0402YD473KAT2A

Kemet C0402C152K5RACT U

Kemet C0805C475K9PACTU

North America
LITEON LTST-C155KGJRKT

Panasonic - ECG ELJ-RE22NGF2

Panasonic - ECG ELJ-RF1N8DF

Panasonic - ECG ERJ-2GEJ621X

Panasonic - ECG EVQ-P7J01K

Cypress Semiconductor CY7C63803-SXC

GRM21BR71A225KA01L

Document #: 38-16015 Rev. *G Page 11 of 40

CYRF6936

Register Descriptions

Notes

1. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined.

2. SOP_CODE_ADR default = 0x17FF9E213690C782.

3. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.

4. PREAMBLE_ADR default = 0x333302.

All registers are read and writable, except where noted. Registers may be written to or read from either individually or in sequential
groups.

Table 5. Register Map Summary

Address Mnemonic b7 b6 b5 b4 b3 b2 b1 b0 Default

0x00 CHANNEL_ADR Not Used Channel -1001000 -bbbbbbb
0x01 TX_LENGTH_ADR TX Length 00000000 bbbbbbbb

0x02 TX_CTRL_ADR TX GO TX CLR

0x03 TX_CFG_ADR Not Used Not Used

0x04 TX_IRQ_STATUS_ADR

0x05 RX_CTRL_ADR RX GO RSVD
0x06

0x07 RX_IRQ_STATUS_ADR
0x08 RX_STATUS_ADR RX ACK PKT ERR EOP ERR CRC0 Bad CRC RX Code RX Data Mode -------- rrrrrrrr
0x09 RX_COUNT_ADR RX Count 00000000 rrrrrrrr
0x0A RX_LENGTH_ADR RX Length 00000000 rrrrrrrr
0x0B PWR_CTRL_ADR PMU EN LVIRQ EN PMU Mode

0x0C XTAL_CTRL_ADR XOUT FN XSIRQ EN Not Used Not Used FREQ 000--100 bbb--bbb
0x0D IO_CFG_ADR IRQ OD IRQ POL MISO OD XOUT OD PACTL OD PACTL GPIO SPI 3PIN IRQ GPIO 00000000 bbbbbbbb
0x0E GPIO_CTRL_ADR XOUT OP MISO OP PACTL OP IRQ OP XOUT IP MISO IP PACTL IP IRQ IP 0000---- bbbbrrrr
0x0F XACT_CFG_ADR ACK EN Not Used FRC END END STATE ACK TO 1-000000 b-bbbbbb
0x10 FRAMING_CFG_ADR SOP EN SOP LEN LEN EN SOP TH 10100101 bbbbbbbb
0x11 DATA32_THOLD_A DR Not Used Not Used Not Used Not Used TH32 ----0100 ----bbbb
0x12 DATA64_THOLD_ADR Not Used Not Used Not Used TH64 ---01010 ---bbbbb
0x13 RSSI_ADR SOP Not Used LNA RSSI 0-100000 r-rrrrrr
0x14 EOP_CTRL_ADR HEN HINT EOP 10100100 bbbbbbbb
0x15 CRC_SEED_LSB_ADR CRC SEED LSB 00000000 bbbbbbbb
0x16 CRC_SEED_MSB_ADR CRC SEED MSB 00000000 bbbbbb bb
0x17 TX_CRC_LSB_ADR CRC LSB -------- rrrrrrrr
0x18 TX_CRC_MSB_ADR CRC MSB -------- rrrrrrrr
0x19 RX_CRC_LSB_ADR CRC LSB 11111111 rrrrrrrr
0x1A RX_CRC_MSB_ADR CRC MSB 11111111 rrrrrrrr
0x1B TX_OFFSET_LSB_ADR STRIM LSB 00000000 bbbbbbbb
0x1C TX_OFFSET_MSB_ADR Not Used Not Used Not Used Not Used STRIM MSB ----0000 ----bbbb
0x1D MODE_OVERRIDE_ADR RSVD RSVD FRC SE N FRC AWAKE Not Used Not Used RST 00000--0 wwwww--w

0x1E RX_OVERRIDE_ADR ACK RX RXTX DLY MAN RXACK

0x1F TX_OVERRIDE_ADR ACK TX FRC PRE RSVD
0x26 XTAL_CFG_ADR RSVD RSVD RSVD RSVD START DLY RSVD RSVD RSVD 00000000 wwwwwww

0x27 CLK_OVERRIDE_ADR RSVD RSVD RSVD RSVD RSVD RSVD RXF RSVD 00000000 wwwwwww

0x28 CLK_EN_ADR RSVD RSVD RSVD RSVD RSVD RSVD RXF RSVD 00000000 wwwwwww

0x29 RX_ABORT_ADR RSVD RSVD ABORT EN RSVD RSVD RSVD RSVD RSVD 000000 00 wwwwwww

0x32 AUTO_CAL_TIME_ADR AUTO_CAL_TIME 00000011 wwwwwww

0x35 AUTO_CAL_OFFSET_ADR AUTO_CAL_OFFSET 00000000 wwwwwww

0x39 ANALOG_CTRL_ADR RSVD R SVD RSVD RSVD RSVD RSVD RX INV ALL SLOW 000000 00 wwwwwww

Register Files
0x20 TX_BUFFER_ADR TX Buffer File -------- wwwwwww

0x21 RX_BUFFER_ADR RX Buffer File -------- rrrrrrrr
0x22 SOP_CODE_ADR SOP Code File Note 2 bbbbbbbb
0x23 DATA_CODE_ADR Data Code File Note 3 bbbbbbbb
0x24 PREAMBLE_ADR Preamble File Note 4 bbbbbbbb
0x25 MFG_ID_ADR MFG ID File NA rrrrrrrr

RX_CFG_ADR AGC EN LNA ATT HILO

OS

IRQ

RXOW

IRQ

LV

IRQ

SOPDET

IRQ

TXB15

IRQEN

DATA CODE

LENGTH DATA MODE PA SETTING

TXB15

IRQ

RXB16
IRQEN

RXB16

IRQ

Force

TXB8

IRQEN

TXB8

IRQ

RXB8

IRQEN

RXB8

IRQ

Not Used LVI TH PMU OUTV 10100000 bbb-bbbb

FRC

RXDR DIS CRC0 DIS RXCRC ACE Not Used

MAN

TXACK OVRD ACK DIS TXCRC RSVD TX INV

TXB0

IRQEN

TXB0

IRQ

RXB1

IRQEN

FAST TURN

EN Not Used RXOW EN VLD EN

RXB1

IRQ

TXBERR

IRQEN

TXBERR

IRQ

RXBERR

IRQEN

RXBERR

IRQ

TXC

IRQEN

TXC
IRQ

RXC

IRQEN

RXC

IRQ

TXE

IRQEN

TXE
IRQ

RXE

IRQEN

RXE
IRQ

[1]

Access

00000011 bbbbbbbb

--000101 --bbbbbb

-------- rrrrrrrr

00000111 bbbbbbbb

10010-10 bbbbb-bb

-------- brrrrrrr

0000000- bbbbbbb-

00000000 bbbbbbbb

w

w

w

w

w

w

w

w

[1]

Document #: 38-16015 Rev. *G Page 12 of 40