cypress CYRF6936 Service Manual

CYRF6936

WirelessUSB™ LP 2.4 GHz Radio SoC

Features

Logic Block Diagram

RF

BIAS

Data

Interface

and

Sequencer

DSSS

Baseband

& Framer

SPI

Synthesizer

GFSK

Demodulator

GFSK

Modulator

IRQ

SS

SCK
MISO
MOSI

RF

P

RF

N

XTAL XOUT

RSSI

Xtal Osc

Power Management

L/D V

DD

V

BAT

V

REG

RST

GND

V

CC

PACTL

■ 2.4 GHz Direct Sequence Spread Spectrum (DSSS) radio

transceiver

■ Operates in the unlicensed worldwide Industria l , Sci en ti f i c,

and Medical (ISM) band (2.400 GHz to 2.483 GHz)

■ 21 mA operating current (Transmit at –5 dBm)

■ Transmit power up to +4 dBm

■ Receive sensitivity up to –97 dBm

■ Sleep Current less than 1 μA

■ DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps

■ Low external component count

■ Auto Transaction Sequencer (ATS) - no MCU intervention

■ Framing, Length, CRC16, and Auto ACK

■ Power Management Unit (PMU) for MCU/Sensor

■ Fast Startup and Fast Channel Changes

■ Separate 16-byte Transmit and Receive FIFOs

■ AutoRate™ - dynamic data rate reception

■ Receive Signal Strength Indication (RSSI)

■ Serial Peripheral Interface (SPI) control while in sleep mode

■ 4 MHz SPI microcontroller interface

■ Battery Voltage Monitoring Circuitry

■ Supports coin-cell operated applications

■ Operating voltage from 1.8 V to 3.6 V

■ Operating temperature from 0 to 70°C

■ Space saving 40-pin QFN 6x6 mm package

Applications

■ Wireless Keyboards and Mice

■ Wireless Gamepads

■ Remote Controls

■ Toys

■ VOIP and Wireless Headsets

■ White Goods

■ Consumer Electronics

■ Home Automation

■ Automatic Meter Readers

■ Personal Health and Entertainment

Applications Support

See www.cypress.com for development tools, reference
designs, and application notes.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-16015 Rev. *J Revised April 18, 2011

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CYRF6936

Contents

Functional Description ...................................... ...............3

Functional Overview ........................................................4

Data Transmission Modes ...........................................4

Link Layer Modes ........................................................4

Packet Buffers .............................................................5

Auto Transaction Sequencer (ATS) ............................5

Data Rates ..................................................................6

Functional Block Overview ............................................. .6

2.4 GHz Radio ................................ ... ..........................6

Frequency Synthesizer ................................................6

Baseband and Framer ........................................ ... ......6

Packet Buffers and Radio Configuration Registers .....6

SPI Interface ................................................................6

Interrupts ..................................................................... 8

Clocks ..........................................................................8

Power Management ....................................................8

Low Noise Amplifier and Received

Signal Strength Indication ............................................8

Receive Spurious Response .......................................9

Application Examples ......................................................9

Registers .........................................................................14

Absolute Maximum Ratings ...........................................15

Operating Conditions .....................................................15

DC Characteristics ..........................................................15

AC Characteristics

RF Characteristics ..........................................................17

Typical Operating Characteristics .................................19

Ordering Information ................................ ... ...................22

Ordering Code Definitions .........................................22

Package Description ......................................................23

Acronyms ........................................................................25

Document Conventions .................................................25

Units of Measure .......................................................25

Document History Page .................................................26

Sales, Solutions, and Legal Information ......................28

Worldwide Sales and Design Support .......................28

Products ....................................................................28

PSoC Solutions .........................................................28

..........................................................16

Document #: 38-16015 Rev. *J Page 2 of 28

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CYRF6936

Functional Description

RF

BIAS

NC

NC

V

BAT2

V

CC

V

BAT1

XTAL

V

CC

NC

NC

V

REG

NC

NC

V

BAT0

L/D

NC

NC

V

I/O

V

DD

RST

RF

N

NCNCVCCNCNCRESV

NC

GND

RF

P

NC

SS

SCK

IRQ / GPIO

MOSI / SDAT

MISO / GPIO

XOUT / GPIO

PACTL / GPIO

NC
NC

* E-PAD Bottom Side

21

22

23

24

25

26

27

28

29

30

11

12131415161718

19

20

10

9

8

7

6

5

4

3

2

40

39383736353433

32

31

1

CYRF6936

WirelessUSB LP

40-Pin QFN

Corner

tabs

The CYRF6936 WirelessUSB™ LP radio is a second generation member of the Cypress WirelessUSB Radio System-On-Chip
(SoC) family. The CYRF6936 is interoperable with the first generation CYWUSB69xx devices. The CYRF6936 IC adds a range
of enhanced features, including increased operating voltage range, reduced supply current in all operating modes, higher data
rate options, reduced crystal start up, synthesizer settling, and link turnaround times.

Figure 1. Pin Diagram - CYRF6936 40 QFN

Table 1. Pin Description

Pin Number Name Type Default Description

1 XTAL I I 12 MHz crystal.
2, 4, 5, 9, 14, 15, 17, 18,

NC NC Connect to GND.
20, 21, 22, 23, 31, 32,
36, 39

3, 7, 16 V
6, 8, 38 V
10 RF
11 RF

CC
BAT(0-2)

BIAS
P

Pwr VCC = 2.4 V to 3.6 V. Typically connected to V
Pwr V

= 1.8 V to 3.6 V. Main supply.

BAT

O O RF I/O 1.8 V reference voltage.

I/O I Differential RF signal to and from antenna.

REG.

12 GND GND Ground.
13 RF

N

I/O I Differential RF signal to and from antenna.
19 RESV I Must be connected to GND.
24 SS I I SPI enable, active LOW assertion. Enables and frames transfers.
25 SCK I I SPI clock.
26 IRQ I/O O Interrupt output (configurable active HIGH or LOW), or GPIO.
27 MOSI I/O I
28 MISO I/O Z SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).

29 XOUT I/O O Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO.

Document #: 38-16015 Rev. *J Page 3 of 28

30 PACTL I/O O Control signal for external PA, T/R switch, or GPIO.
33 V

Pwr I/O interface voltage, 1.8–3.6 V.

I/O

SPI data input pin (Master Out Slave In), or SDAT.

Tri-states when SPI 3PIN = 0 and SS

is deasserted.

Tri-states in sleep mode (configure as GPIO drive LOW).

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CYRF6936

Table 1. Pin Description (continued)

Pin Number Name Type Default Description

34 RST I I Device reset. Internal 10 kohm pull down resistor. Active HIGH,

connect through a 0.47 μF capacitor to V
the first time power is applied to the radio. Otherwise the state of the
radio control registers is unknown.

35 V

37 L/D O PMU inductor/diode connection, when used. If not used, connect to

40 V
E-PAD GND GND Must be soldered to Ground.
Corner Tabs NC NC Do Not solder the tabs and keep other signal traces clear. All tabs are

DD

REG

Pwr Decoupling pin for 1.8 V logic regulator, connect through a 0.47 μF

capacitor to GND.

GND.

Pwr PMU boosted output voltage feedback.

common to the lead frame or paddle which is grounded after the pad
is grounded. While they are visible to the user, they do not extend to
the bottom.

Must have RST = 1 event

BAT.

Functional Overview

The CYRF6936 IC provides a complete WirelessUSB SPI to
antenna wireless MODEMs. The SoC is designed to implement
wireless device links operating in the worldwide 2.4 GHz ISM
frequency band. It is intended for systems compliant with
worldwide regulations covered by ETSI EN 301 489-1 V1.41,
ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA
and Industry Canada), and TELEC ARIB_T66_March, 2003
(Japan).

The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer , DSSS baseband controller,
Received Signal Strength Indication (RSSI), and SPI interface
for data transfer and device configuration.

The radio supports 98 discrete 1 MHz channels (regulations may
limit the use of some of these channels in certain jurisdictions).

The baseband performs DSSS spreading/despreading, Start of
Packet (SOP), End of Packet (EOP) detection, and CRC16
generation and checking. The baseband may also be configured
to automatically transmit Acknowledge (ACK) handshake
packets whenever a valid packet is received.

When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of the
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both. It changes to
lower data rates at longer distances or in high interference
environments or both.

In addition, the CYRF6936 IC has a Power Management Unit
(PMU), which enables direct connection of the device to any
battery voltage in the range 1.8 V to 3.6 V. The PMU conditions
the battery voltage to provide the supply voltages required by the
device, and may supply external devices.

Data Transmission Modes

The SoC supports four different data transmission modes:

■ In GFSK mode, data is transmitted at 1 Mbps, without any

DSSS.

■ In 8DR mode, eight bits are encoded in each derived code

symbol transmitted.

■ In DDR mode, two bits are encoded in each derived code

symbol transmitted (As in the CYWUSB6934 DDR mode).

■ In SDR mode, one bit is encoded in each derived code symbol

transmitted (As in the CYWUSB6934 standard modes).

Both 64 chip and 32 chip Pseudo Noise (PN) codes are
supported. The four data transmission modes apply to the data
after the SOP. In particular the length, data, and CRC16 are all
sent in the same mode. In general, lower data rates reduce
packet error rate in any given environment.

Link Layer Modes

The CYRF6936 IC device supports the following data packet
framing features:

SOP

Packets begin with a two-symbol SoP marker. This is required in
GFSK and 8DR modes, but is optional in DDR mode and is not
supported in SDR mode. If framing is disabled then an SOP
event is inferred whenever two successive correlations are
detected. The SOP_CODE_ADR code used for the SOP is
different from that used for the “body” of the packet, and if desired
may be a different length. SOP must be configured to be the
same length on both sides of the link.

Length

There are two options for detecting the end of a packet. If SOP
is enabled, then the length field must be enabled. GFSK and
8DR must enable the length field. This is the first eight bits after
the SOP symbol, and is transmitted at the payload data rate.
When the length field is enabled, an EoP condition is inferred
after reception of the number of bytes defined in the length field,
plus two bytes for the CRC16. The alternative to using the length

Document #: 38-16015 Rev. *J Page 4 of 28

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CYRF6936

field is to infer an EOP condition from a configurable number of

P SOP 1 SOP 2 Length CRC 16

Payload Data

Preamble

n x 16us

1st Framing

Sym bol*

2nd Framing

Sym bol*

Packet

length
1 Byte
Period

*Note:32 or 64us

P SOP 1 SOP 2 CRC 16

Preamble

n x 16us

1st Framing

Symbol*

2nd Framing

Sym bol*

CR C field from

received packet.

2 Byte periods

*Note:32 or 64us

successive noncorrelations; this option is not available in GFSK
mode and is only recommended when using SDR mode.

CRC16

The device may be configured to append a 16 bit CRC16 to each
packet. The CRC16 uses the USB CRC polynomial with the
added programmability of the seed. If enabled, the receiver
verifies the calculated CRC16 for the payload data against the
received value in the CRC16 field. The seed value for the CRC16
calculation is configurable, and the CRC16 transmitted may be
calculated using either the loaded seed value or a zero seed; the
received data CRC16 is checked against both the configured
and zero CRC16 seeds.

Figure 2. Example Packet Format

Figure 3. Example ACK Packet Format

CRC16 detects the following errors:

■ Any one bit in error.

■ Any two bits in error (irrespective of how far apart, which

column, and so on).

■ Any odd number of bits in error (irrespective of the location).

■ An error burst as wide as the checksum itself.

Figure 2 shows an example packet with SOP, CRC16, and

lengths fields enabled, and Figure 3 shows a standard ACK
packet.

Packet Buffers

All data transmission and reception use the 16 byte packet
buffers - one for transmission and one for reception.

The transmit buffer allows loading a complete packet of up to 16
bytes of payload data in one burst SPI transaction. This is then
transmitted with no further MCU intervention. Similarly, the
receive buffer allows receiving an entire packet of payload data
up to 16 bytes with no firmware intervention required until the
packet reception is complete.

The CYRF6936 IC supports packets up to 255 bytes. However,
the actual maximum packet length depends on the accuracy of
the clock on each end of the link and the data mode. Interrupts
are provided to allow an MCU to use the transmit and receive
buffers as FIFOs. When transmitting a packet longer than 16
bytes, the MCU can load 16 bytes initially, and add further bytes
to the transmit buffer as transmission of data creates space in
the buffer. Similarly, when receiving packets longer than 16
bytes, the MCU must fetch received data from the FIFO
periodically during packet reception to prevent it from
overflowing.

Auto Transaction Sequencer (ATS)

The CYRF6936 IC provides automated support for transmission
and reception of acknowledged data packets.

When transmitting in transaction mode, the device automatically:

■ starts the crystal and synthesizer

■ enters transmit mode

■ transmits the packet in the transmit buffer

■ transitions to receive mode and waits for an ACK packet

■ transitions to the transaction end state when an ACK packet is

received or a timeout period expires

Similarly, when receiving in transaction mode, the device
automatically:

■ waits in receive mode for a valid packet to be received

■ transitions to transmit mode, transmits an ACK packet

■ transitions to the transaction end state (receive mode to await

the next packet, and so on.)

The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.

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In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used). T o transmit data, the MCU must load the
data packet to be transmitted, set the length, and set the TX GO
bit. Similarly, when receiving packets in transaction mode,
firmware must retrieve the fully received packet in response to
an interrupt request indicating reception of a packet.

Data Rates

The CYRF6936 IC supports the following data rates by
combining the PN code lengths and data transmission modes
described in the previous sections:

■ 1000 kbps (GFSK)

■ 250 kbps (32 chip 8DR)

■ 125 kbps (64 chip 8DR)

■ 62.5 kbps (32 chip DDR)

■ 31.25 kbps (64 chip DDR)

■ 15.625 kbps (64 chip SDR)

Functional Block Overview

2.4 GHz Radio

The radio transceiver is a dual conversion low IF architecture
optimized for power, range, and robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in seven steps. The supply current of the
device is reduced as the RF output power is reduced.

Table 2. Internal PA Output Power Step Table

PA Setting Typical Output Power (dBm)

7+4
60
5–5
4–13
3–18
2–24
1–30
0–35

Frequency Synthesizer

Before transmission or reception may begin, the frequency
synthesizer must settle. The settling time varies depending on
channel; 25 fast channels are provided with a maximum settling
time of 100 μs.

The ‘fast channels’ (less than 100 μs settling time) are every third
channel, starting at 0 up to and including 72 (for example, 0, 3,
6, 9 …. 69, 72).

Baseband and Framer

The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception, CRC16
generation and checking, and EOP detection and length field.

Packet Buffers and Radio Configuration Registers

Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet (as in the
CYWUSB6934). Configuration registers allow configuration of
DSSS PN codes, data rate, operating mode, interrupt masks,
interrupt status, and so on.

SPI Interface

The CYRF6936 IC has an SPI interface supporting
communication between an application MCU and one or more
slave devices (including the CYRF6936). The SPI interface
supports single-byte and multi-byte serial transfers using either
4-pin or 3-pin interfacing. The SPI communications interface
consists of Slave Select (SS
Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data
(SDAT).

SPI communication may be described as the following:

■ Command Direction (bit 7) = ‘1’ enables SPI write transaction.

A ‘0’ enables SPI read transactions.

■ Command Increment (bit 6) = ‘1’ enables SPI auto address

increment. When set, the address field automatically
increments at the end of each data byte in a burst access.
Otherwise the same address is accessed.

■ Six bits of address

■ Eight bits of data

The device receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI pin.
Data to the application MCU is shifted out on the MISO pin. The
active LOW Slave Select (SS
SPI transfer.

The application MCU can initiate SPI data transfers using a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes shown in Table 3
through Figure 6 on page 7.

The SPI communications interface has a burst mechanism,
where the first byte can be followed by as many data bytes as
required. A burst transaction is terminated by deasserting the
slave select (SS

= 1).

The SPI communications interface single read and burst read
sequences are shown in Figure 4 and Figure 5 on page 7,
respectively.

The SPI communications interface single write and burst write
sequences are shown in Figure 6 and Figure 7 on page 7,
respectively.

This interface may be optionally operated in a 3-pin mode with
the MISO and MOSI functions combined in a single bidirectional
data pin (SDAT). When using 3-pin mode, user firmware must
ensure that the MOSI pin on the MCU is in a high impedance
state except when MOSI is actively transmitting data.

), Serial Clock (SCK), Master

) pin must be asserted to initiate an

Document #: 38-16015 Rev. *J Page 6 of 28

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CYRF6936

The device registers may be written to or read from one byte at

DIR

0

INCA5A4A3A2A1A0

D7 D6 D5 D4 D3 D2 D1 D0

SCK

MOSI

SS

MISO

cmd addr

data to mcu

DIR

0

INCA5A4A3A2A1A0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

data to mcu

1

cmd addr

data to mcu

1+N

SCK

MOSI

SS

MISO

DIR

1

INCA5A4A3A2A1A0

D7 D6 D5 D4 D3 D2 D1 D0

SCK

MOSI

SS

MISO

cmd addr data from mcu

DIR

1

INCA5A4A3A2A1A0

D7 D6 D5 D4 D3 D2 D1 D0

SCK

MOSI

SS

MISO

cmd addr data from mcu

1

D7 D6 D5 D4 D3 D2 D1 D0

data from mcu

1+N

a time, or several sequential register locations may be written or
read in a single SPI transaction using incrementing burst mode.
In addition to single byte configuration registers, the device
includes register files. Register files are FIFOs written to and
read from using nonincrementing burst SPI transactions.

The IRQ pin function may be optionally multiplexed onto the

The SPI interface is not dependent on the internal 12 MHz clock.
Registers may therefore be read from or written to when the
device is in sleep mode, and the 12 MHz oscillator disabled.

The SPI interface and the IRQ and RST pins have a separate
voltage reference pin (V
directly to MCUs operating at voltages below the CYRF6936 IC

). This enables the device to interface

I/O

supply voltage.
MOSI pin. When this option is enabled, the IRQ function is not
available while the SS pin is LOW. When using this configuration,
user firmware must ensure that the MOSI pin on the MCU is in a
high impedance state whenever the SS pin is HIGH.

Table 3. SPI Transaction Format

Parameter Byte 1 Byte 1+N

Bit # 7 6 [5:0] [7:0]

Bit Name DIR INC Address Data

Figure 4. SPI Single Read Sequence

Figure 5. SPI Incrementing Burst Read Sequence

Figure 6. SPI Single Write Sequence

Figure 7. SPI Incrementing Burst Write Sequence

Document #: 38-16015 Rev. *J Page 7 of 28

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CYRF6936

Interrupts

The device provides an interrupt (IRQ) output, which is
configurable to indicate the occurrence of various different
events. The IRQ pin may be programmed to be either active
HIGH or active LOW, and be either a CMOS or open drain output.
The available interrupts are described in the section Registers

on page 14.

The CYRF6936 IC features three sets of interrupts: transmit,
receive, and system interrupts. These interrupts all share a
single pin (IRQ), but can be independently enabled or disabled.
The contents of the enable registers are preserved when
switching between transmit and receive modes.

If more than one interrupt is enabled at any time, it is necessary
to read the relevant status register to determine which event
caused the IRQ pin to assert. Even when a given interrupt source
is disabled, the status of the condition that would otherwise
cause an interrupt can be determined by reading the appropriate
status register. It is therefore possible to use the devices without
the IRQ pin, by polling the status registers to wait for an event,
rather than using the IRQ pin.

Clocks

A 12 MHz crystal (30 ppm or better) is directly connected
between XTAL and GND without the need for external
capacitors. A digital clock out function is provided, with
selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This
output may be used to clock an external microcontroller (MCU)
or ASIC. This output is enabled by default, but may be disabled.

The requirements to directly connect the crystal to the XTAL pin
and GND are:

■ Nominal Frequency: 12 MHz

■ Operating Mode: Fundamental Mode

■ Resonance Mode: Parallel Resonant

■ Frequency Stability: ±30 ppm

■ Series Resistance: <60 ohms

■ Load Capacitance: 10 pF

■ Drive Level: 100 µW

Power Management

The operating voltage of the device is 1.8 V to 3.6 V DC, which
is applied to the V
static sleep mode by writing to the FRC END = 1 and
END STA TE = 000 bits in the XACT_CFG_ADR register over the
SPI interface. The device enters sleep mode within 35 µs after
the last SCK positive edge at the end of this SPI transaction.
Alternatively, the device may be configured to automatically
enter sleep mode after completing the packet transmission or
reception. When in sleep mode, the on-chip oscillator is stopped,
but the SPI interface remains functional. The device wakes from
sleep mode automatically when the device is commanded to
enter transmit or receive mode. When resuming from sleep
mode, there is a short delay while the oscillator restarts. The
device can be configured to assert the IRQ pin when the
oscillator has stabilized.

pin. The device can be shut down to a fully

BAT

The output voltage (V

(PMU) is configurable to several minimum values between 2.4 V

and 2.7 V. V

load) to external devices. It is possible to disable the PMU and

may be used to provide up to 15 mA (average

REG

) of the Power Management Unit

REG

provide an externally regulated DC supply voltage to the device’s

main supply in the range 2.4 V to 3.6 V. The PMU also provides

a regulated 1.8 V supply to the logic.

The PMU is designed to provide high boost efficiency (74–85%

depending on input voltage, output voltage, and load) when

using a Schottky diode and power inductor, eliminating the need

for an external boost converter in many systems where other

components require a boosted voltage. However, reasonable

efficiencies (69–82% depending on input voltage, output voltage,

and load) may be achieved when using low cost components

such as SOT23 diodes and 0805 inductors.

The current through the diode must stay within the linear

operating range of the diode. For some loads the SOT23 diode

is sufficient, but with higher loads it is not and an SS12 diode

must be used to stay within this linear range of operation. Along

with the diode, the inductor used must not saturate its core. In

higher loads, a lower resistance/higher saturation coil such as

the inductor from Sumida must be used.

The PMU also provides a configurable low battery detection

function, which may be read over the SPI interface. One of seven

thresholds between 1.8 V and 2.7 V may be selected. The

interrupt pin may be configured to assert when the voltage on the

V

pin falls below the configured threshold. LV IRQ is not a

BAT

latched event. Battery monitoring is disabled when the device is

in sleep mode.

Low Noise Amplifier and Received Signal Strength

Indication

The gain of the receiver can be controlled directly by clearing the

AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of

the RX_CFG_ADR register. Clearing the LNA bit reduces the

receiver gain approximately 20 dB, allowing accurate reception

of very strong received signals (for example, when operating a

receiver very close to the transmitter). Approximately 30 dB of

receiver attenuation can be added by setting the Attenuation

(ATT) bit. This limits data reception to devices at very short

ranges. Disabling AGC and enabling LNA is recommended,

unless receiving from a device using external PA.

When the device is in receive mode the RSSI_ADR register

returns the relative signal strength of the on-channel signal

power.

When receiving, the device automatically measures and stores

the relative strength of the signal being received as a five bit

value. An RSSI reading is taken automatically when the SoP is

detected. In addition, a new RSSI reading is taken every time the

previous reading is read from the RSSI_ADR register, allowing

the background RF energy level on any given channel to be

easily measured when RSSI is read while no signal is being

received. A new reading can occur as fast as once every 12 µs.

Document #: 38-16015 Rev. *J Page 8 of 28

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CYRF6936

Receive Spurious Response

Keyboard Interface

Power Supply

SDATA

ISSP

SCLK

"-"

XRES

"+"

BIND

Serial debug

header

Layout J3 and J2.1 in a

0.100" spacing

configuration

E-PAD must be soldered to ground.

Radio Decoupling Caps

RF VCO

and VCO

Buffer

Filter

The power supply decoupling shown for VBAT0

is a recommended cost effective

configuration:

C6=No Load R2= 1ohm C7=10uF ceramic.

For this configuration, it is required that

C18 be installed.

An alternate decoupling configuration is

the following:

C6=47uF ceramic R2=0ohm C7=.047uF.

For this configuration, it is not required

to load C18.

For reference design part numbers, please

refer to the Bill of Materials file

121-26504_A.xls.

A 2-pin jumper

installed from J3.1

to J2.1 enables the

radio to power the

processor. Jumper

removal is required

when programming U2

to disconnect the

radio from the

Miniprog 5V source.

R1 is a zero ohm

resistor that should

be installed for

production units

only, following

programming.

MISO

MOSI

P1_1

SCK

P1_0

MISO

nSS

IRQ

MOSI

CLKOUT

RST

SCK

COL16

COL10

COL17

COL9

COL13

P1_0

COL15

COL18

COL12

COL11

COL14

nSS

P1_1

COL5

COL3

COL2

COL8

COL1

COL6

COL7

COL4

ROW5

ROW4

ROW6

ROW2

ROW7

ROW1

ROW8

ROW3

COL7

COL11

ROW4

ROW2

COL1

COL3

COL8

COL10

COL14

ROW8

ROW3

COL2

COL6

ROW6

ROW5

COL18

ROW1

COL13

COL16

COL9

ROW7

COL5

COL4

COL12

COL15

COL17

IRQ

SW1

PACTL

EVCC

VCC

VBAT

VBAT

VCC

VBAT

VBAT

VCC

EVCC

SOT23

D1

BAT400D

2 1

IND0402

L2

1.8 nH

U2

CY7C60123-PVXC

30

161718

292826

25

19

23

12

5

7

24

10

2043214222

6

34353637383940

41

131415

313233

2744

1198412346474845

P1_4 / SCLK

P0_7

P0_6 / TIO1

P0_5 / TIO0

P1_3 / SSEL

P1_2

P1_1

P1_0

P0_4 / INT2

P0_0 / CLKIN

P2_3

VDD1

P4_0

VSS1

P2_5

P0_3 / INT1

P4_3

P0_2 / INT0

P4_2

P0_1 / CLKOUT

P4_1

P3_0

P3_1

P3_2

P3_3

P3_4

P3_5

P3_6

P3_7

P2_2

P2_1

P2_0

P1_5 / SMOSI

P1_6 / SMISO

P1_7

VDD2VSS2

P2_4

P2_6

P2_7

NC4

NC1

NC2

NC3

NC6

NC7

NC8

NC5

S1

SW PUSHBUTTON

1A

2A

1B

2B

0402

C5

0.47 uFd

IND0603

L1

22 nH

0603

R1

NO LOAD

J1

KB 26 Pin

12345678910111213141516171819202122232425

26

123456789

1011121314151617181920212223242526

TV4

0402

C8

1 uFd 6.3V

BH1

BATT CON 2xAA

123

POS

NEG1

NEG2

0402

C11

0.047 uFd

0402

C17

0.47 uFd

0805

R2

1 1%

L3

10 uH

TV5

0805

C12

10 uFd 6.3V

0805

C7

10 uFd 6.3V

0402

C20

0.01 uFd

0402

C16

0.047 uFd

J3

1 PIN HDR

1

TV8

J2

5 PIN HDR

12345

J4

3 PIN HDR

123

0402

R3

47

TP2

TP1

0402

C13

0.047 uFd

U1

CYRF6936

36

4

8

1916202

252726

29

34

28

3

7

5

13

6

37

1

24

39

40

41

35

9

14

10

11

12

151718

21302233233132

38

NC15

NC2

VBAT2

RESV

VCC3

NC9NC1

SCK

MOSI

IRQ

XOUT

RST

MISO

VCC1

VCC2

NC3

RFn

VBAT1

L/D

XTAL

SS

NC16

VREG

E-PAD

VDD

NC4

NC5

RFbias

RFp

GND1

NC6

NC7

NC8

NC10

PACTL

NC11

VIO

NC12

NC13

NC14

VBAT0

0402

C3

2.0 pFd

0402

C1

15 pFd

+

E

C18

100 uFd 10v

0402

C15

0.047 uFd

TV7

TV6

ANT1

WIGGLE 63

1

2

0402

C4

1.5 pFd

Y1

12 MHz Crystal

TV2

1210

C6

No Load

0402

C10

0.047 uFd

TV1

TV3

0402

C19

0.01 uFd

0402

C9

0.047 uFd

The transmitter may exhibit spurs around 50MHz offset at levels
approximately 50dB to 60dB below the carrier power. Receivers
operating at the transmit spur frequency may receive the spur if
the spur level power is greater than the receive sensitivity level.

Application Examples

The workaround for this is to program an additional byte in the

packet header which contains the transmitter channel number.

After the packet is received, the channel number can be

checked. If the channel number does not match the receive

channel then the packet is rejected.

Figure 8. Recommended Circuit for Systems where VBAT

≤ 2.4 V

Document #: 38-16015 Rev. *J Page 9 of 28

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