CYPRESS CYM1831 User Manual

31

CYM1831

64K x 32 Static RAM Module

Features

• High-density 2-Mbit SRAM module

• 32-bit standard footprint supports densities from 16K

x 32 through 1M x 32

• High-speed CMOS SRAMs
—Access time of 15 ns

• Low active power
—5.3W (max.)

• SMD technology

• TTL-compatible inputs and outputs

• Low profile
—Max. height of 0.50 in.

• Small PCB footprint
—1.2 sq. in.

Functional Description

The CYM1831 is a high -performance 2-Mbit stati c R AM mo d­ule organized as 64K words by 32 bits. This module is con-

on an epoxy laminate board with pins. F our chip s elects (C S

, CS3, and CS4) are used to independently en able the four

CS

2

bytes. Reading or wri tin g c an be executed on indivi dua l by te s
or any combination of multiple bytes through proper use of
selects.

Writing to each byte is accomplished when the appropriate
Chip Selects (CS
LOW. Data on the input/output pins (I/O

) and Write Enable (WE) inputs are both

N

memory location specified on the address pins (A

).

A

15

Reading the de vice is accompli shed by taking the Chip Select s

) LOW and Output Enable (OE) LOW while Write Enabl e

(CS

N

) remains HIGH. Under these conditions the contents of

(WE
the memory locatio n spe cified on th e addre ss pi ns wil l appe ar
on the data input/output pins (I/O

The data input/output pins stay in the high-impedance state
when Write Enable ( WE

) is LOW or the appropriate chip se-

lects are HIGH.
Two pins (PD

density in applications where alternate versions of the

and PD1) are used to identify module memory

0

JEDEC-standard modules can be interchanged.

structed from eight 64K x 4 SRAMs in SOJ packages mounte d

Logic Block Diagram Pin Configuration

PD0- OPEN

- GND

PD

A0–A

WE

CS

CS

CS

CS

OE

15

16

64K x 4

SRAM

1

64K x 4

SRAM

2

64K x 4

SRAM

3

64K x 4

SRAM

4

I/O0–I/O

I/O8–I/O

I/O16–I/O

I/O24–I/O

3

11

19

27

1

64K x 4

SRAM

64K x 4

SRAM

64K x 4

SRAM

64K x 4

SRAM

44

44

44

44

I/O4–I/O

I/O12–I/O

I/O20–I/O

I/O28–I/O

7

15

23

31

).

X

PD
I/O
I/O
I/O
I/O
V

CC

A
A
A

I/O
I/O
I/O
I/O

WE
A

CS
CS

NC

GND

I/O
I/O
I/O
I/O

A
A
A

A
I/O
I/O
I/O
I/O

GND

) is written into the

X

ZIP/SIMM

Top View

2

0
0

4
6

1

8

2

10

3

12
14

7

16

8

18

9

20

4

22

5

24

6

26

7

28
30

14

32

1

34

3

36
38

16

40
42

17

44

18

46

19

48

10

50

11

52

12

54

13

56

20

58

21

60

22

62

23

64

,

1

through

0

GND

1

PD

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31

33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63

I/O
I/O
I/O
I/O

A

0

A

1

A

2

I/O
I/O
I/O
I/O
GND
A

15

CS
CS

NC
OE
I/O
I/O
I/O
I/O
A

3

A

4

A

5

V

CC

A

6

I/O
I/O
I/O
I/O

1
8
9
10
11

12
13
14
15

2

4

24
25
26
27

28
29
30
31

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05270 Rev. ** Revised March 15, 2002

CYM1831

Selection Guide

1831-15 1831-20 1831-25 1831-30 1831-35 1831-45

Maximum Access Time (ns) 15 20 25 30 35 45 Maximum Operating Current (mA) 1120 960 720 720 720 720 Maximum Standby Current (mA) 160 160 160 160 160 160

Maximum Ratings

(Above which the useful life may be im pai red. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State...............................................–0.5V to +7.0V

DC Input Voltage............................................–0.5V to +7.0V

Output Current into Outputs (LOW).............................20 mA

Electrical Characteristics Ov er the Op erat ing Range

Parameter Description Test Conditions

V
V
V
V
I

IX

I

OZ

I

CC

I

SB1

I

SB2

OH
OL
IH
IL

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V Input HIGH Voltage 2.2 V Input LOW Voltage –0.5 0.8 –0.5 0.8 –0.5 0.8 V Input Load Current GND < VI < V Output Leakage

Current
VCC Operating

Supply Current
Automatic CS Pow-

er-Down Current
Automatic CS Pow-

er-Down Current

GND < VO < VCC,
Output Disabled

VCC = Max., I

< V

CS

N

VCC = Max., CSN > VIH,

[1]

Min. Duty Cycle = 100%
VCC = Max., CSN > VCC – 0.2V,

[1]

VIN > VCC – 0.2V or VIN < 0.2V

CC

= 0 mA,

OUT

IL

Operating Range

Range

Commercial 0°C to +70°C 5V ± 10%

1831-15 1831-20

CC

–20 +20 –20 +20 –20 +20 µA
–20 +20 –20 +20 –20 +20 µA

1120 960 720 mA

320 320 320 mA

160 160 160 mA

Ambient

Temperature V

1831-25, 3 0, 35,

45

2.2 V

CC

2.2 V

CC

CC

UnitMin. Max. Min. Max. Min. Max.

V

Capacitance

[2]

Parameter Description Test Conditions Max. Unit

C

INA

C

INB

C

OUT

Notes:

1. A pull-up resistor to V

2. Tested on a sample basis.

Input Capacitance (A0–A15, WE, OE) TA = 25°C, f = 1 MHz,

= 5.0V

V

Input Capacitance (CS) 15 pF

CC

80 pF

Output Capacitance 20 pF

on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.

CC

Document #: 38-05270 Rev. ** Page 2 of 8

AC Test Loads and Waveforms

CYM1831

Ω R1 481Ω

5V

OUTPUT

INCLUDING
JIG AND
SCOPE

Equivalent to: THÉ VENIN EQUIVALENT

OUTPUT

R1 481

R2
255

30 pF

Ω

(a) (b)

167Ω

5V

OUTPUT

INCLUDING
JIG AND
SCOPE

1.73V

5 pF

Switching Characteristics Over the Operating Range

[3]

R2
255

3.0V

GND

Ω

<5ns <5ns

ALL INPUT PULSES

90%

10%

90%

10%

1831-15 1831-20 1831-25 1831-30 1831-35 1831-45

Parameter Description

READ CYCLE

t

RC

t

AA

t

OHA

t

ACS

t

DOE

t

LZOE

t

HZOE

t

LZCS

t

HZCS

WRITE CYCLE

t

WC

t

SCS

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

Note:

3. T est conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I

OL/IOH

4. At any given temperature and voltage condition, t

5. t

HZCS

6. The internal write time of the memory is defined by the overlap of CS
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

Read Cycle T ime 15 20 25 30 35 45 ns
Address to Data Valid 15 20 25 30 35 45 ns
Data Hold from

3 3 3 3 3 3 ns

Address Change
CS LOW to Data Valid 15 20 25 30 35 45 ns
OE LOW to Data Valid 8 10 15 20 20 30 ns
OE LOW to Low Z 0 0 0 0 0 0 ns
OE LOW to High Z 8 10 15 15 20 20 ns
CS LOW to Low Z

[4]

0 3 3 3 3 ns

0

CS HIGH to High Z

[6]

[4, 5]

6 8 13 15 20 20 ns

Write Cycle Time 15 20 25 30 35 45 ns
CS LOW to Write End 10 15 20 25 30 40 ns
Address Set-Up to

10 15 20 25 30 40 ns

Write End
Address Hold from

2 2 2 2 2 2 ns

Write End
Address Set-Up to

2 2 2 2 2 2 ns

Write Start
WE Pulse Width 10 15 20 25 25 30 ns
Data Set-Up to Write

8 12 15 15 20 20 ns

End
Data Hold from Write

2 2 2 2 2 2 ns

End
WE HIGH to Low Z 3 3 3 3 3 3 ns
WE LOW to High Z

and 30-pF load capacitance.

and t

are specified with CL = 5 pF as in part (b) of AC T est Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.

HZWE

[5]

0 7 0 10 0 13 0 15 0 20 0 20 ns

HZCS

is less than t

for any given device. These parameters are guaranteed by design and not 100% tested.

LZCS

LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate

UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Document #: 38-05270 Rev. ** Page 3 of 8