The CYM1465 is a high-performance 4-megabit static RAM
module organized as 512K words by 8 bits. This module is
constructed using four 128K x 8 RAMs mounted on a substrate
with pins. A decoder is used to interpret the higher-order addresses (A
Writing to the module is accomplished when the chip select
) and write enable (WE) inputs are both LOW. Data on the
(CS
eight input/output pins (I/O
ten into the memory location specified o n the a ddress pins (A
through A18). Reading the device is accomplished by taking
chip select and output enable (OE
remains inactive or HIGH. Under these conditions, the contents of the memory location spec i fied o n the address pins (A
through A18) will appear on the eight appropriate data input/output pins (I/ O
The input/output pins remain in a high-impedance state unle ss
and A18) and to select one of the four RAMs.
17
through I/O7) of the device is writ-
0
) LOW while write enable
through I/O7).
0
the module is selected, outputs are enabled, and write enable
is HIGH.
Logic Block DiagramPin Configuration
DIP
0
1
2
Top View
1
S
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A0− A
16
WE
OE
A
A
CS
A
18
A
16
A
14
A
12
A
128K x 8
SRAM
17
18
1 OF 4
DECODER
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
A
A
A
A
A
A
A
I/O
I/O
I/O
GND
7
6
5
4
3
2
1
0
0
0
32
V
CC
31
A
15
A
30
17
29
WE
28
A
13
27
A
8
26
A
9
A
25
11
24
OE
A
23
10
22
CS
21
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
20
19
18
17
1465–2
1465–1
I/O − I/O
0
7
Selection G uide
1465-701465-851465-1001465-1201465-150
Maximum Access Time (ns)7085100120150
Maximum Operati ng Current (mA)110110110110110
Maximum Standby Current (mA)1212121212
Cypress Semiconductor Corporation•3901 North First Street•San Jose•CA 95134•408-943-2600
January 1991 – Revised January 1995
(a)
(b)
1465–31465–4
5V
90%
10%
3.0V
GND
90%
10%
OUTPUT
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
<10ns
1.847k Ω1.847k
Ω
OUTPUT
C
L
[2]
1kΩ1kΩ
Equiva le nt to:THÉ VENIN EQUIVALENT
<10ns
648Ω
1.76V
CYM1465
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature . ................................–55°C to +150°C
Ambient Temperature with
Power Applied...............................................–10°C to +85°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Input Voltage ................................. ............-0.5V to +7.0V
Operating Range
Ambient
Range
Commercial0°C to +70°C 5V ± 10%
Industrial–40°C to +85°C5V ± 10%
Temperature
V
CC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
1465
ParameterDescriptionTest ConditionsMin.Max.Unit
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Capacitance
C
IN
C
OUT
Output HIGH VoltageVCC = Min., IOH = –1.0 mA2.4V
Output LOW VoltageVCC = Min., IOL = 2.1 mA0.4V
Input HIGH Voltage2.2VCC + 0.3V
Input LOW Voltage–0.30.8V
Input Load CurrentGND < VI < V
Switching Characteristics Over the Operating Range
[2]
1465-701465-851465-1001465-1201465-150
ParameterDescriptionMi n. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
WRITE CYCLE
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time7085100120150ns
Address to Data Valid7085100120150ns
Data Hold from Address Change1010101010ns
CS LOW to Data Valid7085100120150ns
OE LOW to Data Valid3545506075ns
OE LOW to Low Z55555ns
OE HIGH to High Z
[3]
2530354555ns
CS LOW to Low Z1010101010ns
CS HIGH to High Z
[4]
[3]
3030354560ns
Write Cycle Time7085100120150ns
CS LOW to Write End657590100115ns
Address Set-Up to Write End657590100110ns
Address Hold from Write End05555ns
Address Set-Up to Write Start05555ns
WE Pulse Width5565758595ns
Data Set-Up to Write End3035404550ns
Data Hold from Write End00000ns
WE HIGH to Low Z55555ns
WE LOW to High Z
[3]
2530354045ns
Data Retention Characteristics Over the Operating Range (L Version Only)
2. Test conditions assume signal transition times of 10 ns or less, timing reference levels of 1.5V, input levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
3. CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
4. The internal write time of the memory is defined by the overlap of CS
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
5. Guaranteed, not tested.
VCC for Retention DataCS > VCC – 0.2V22V
Data Retention CurrentVDR = 3.0V,
CS
Chip Deselect to Data Retention Time00ns
Operation Recovery Time55ms
and 100-pF load capacitance for 85-, 100-, 120-, and 150-ns speeds. CL = 30 pF for 70-ns speed.
> VCC – 0.2V,
V
> VCC – 0.2V or
IN
V
< 0.2V
IN
LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
50150µA
Data Retention Waveform
3
Switching Waveforms
CYM1465
Read Cycle No. 1
ADDRESS
DATA OUT
Read Cycle No. 2
CS
OE
DATA OUT
[6,7]
t
RC
t
t
OHA
AA
PREVIOUS DATA VALIDDATA VALID
[6,8]
t
RC
t
ACS
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCS
DATA VALID
t
HZOE
t
HZCS
1465–6
HIGH
IMPEDANCE
1465–7
Write Cycle No. 1
(WE
Controlled)
ADDRESS
CS
WE
DATA IN
DATA
OUT
Notes:
6. WE
is HIGH for read cycle.
7. Device is co ntinuously selected, CS = VIL.
8. Address valid prior to or coincident with CS
[4]
t
SA
DATA UNDEFINED
transition LOW.
t
SCS
t
AW
t
WC
t
HZWE
t
PWE
t
SD
DATA VALID
t
HA
t
HD
t
LZWE
HIGH IMPEDANCE
1465–8
4
Switching Waveforms (continued)
CYM1465
Write Cycle No. 2 (CS Controlled)
[4,9]
ADDRESS
t
SA
CS
WE
DATA IN
DATA
Note:
9. If CS
OUT
goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
DATA UNDEFINED
Trut h Table
Inputs
CSWEOEOutputMode
HXXHigh ZDeselect/Power-Down
LHLData OutRead Word
LLXData InWrite Word
LHHHigh ZDeselect