Cypress CYDC064B08, CYDC064B16, CYDC128B16, CYDC256B16, CYDC128B08 User Manual
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
1.8V 4k/8k/16k x 16 and 8k/16k x 8
ConsuMoBL Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simultaneous access of the same memory location
• 4/8/16k × 16 and 8/16k × 8 organization
• High-speed access: 40 ns
• Ultra Low operating power
— Active: I
— Active: I
— Standby: I
• Port-independent 1.8V, 2.5V, and 3.0V I/Os
= 15 mA (typical) at 55 ns
CC
= 25 mA (typical) at 40 ns
CC
= 2 µA (typical)
SB3
Selection Guide for VCC = 1.8V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
Maximum Access Time 40 55 ns
Typical Operating Current 25 15 mA
Typical Standby Current for I
Typical Standby Current for I
SB1
SB3
CYDC064B08
-40
22µA
22µA
• Lead (Pb)-free 14 x 14 x 1.4 mm 100-pin TQFP Package
• Full asynchronous operation
• Pin select for Master or Slave
• Expandable data bus to 32 bits with Master/Slave chip
select when using more than one device
• On-chip arbitration logic
• On-chip semaphore logic
• Input Read Registers and Output Drive Registers
•INT
flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Commercial and industrial temperature ranges
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
UnitPort I/O Voltages (P1-P2) 1.8V-1.8V 1.8V-1.8V
Selection Guide for VCC = 2.5V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
Maximum Access Time 40 55 ns
Typical Operating Current 39 28 mA
Typical Standby Current for I
Typical Standby Current for I
SB1
SB3
CYDC064B08
-40
66µA
44µA
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
UnitPort I/O Voltages (P1-P2) 2.5V-2.5V 2.5V-2.5V
Selection Guide for VCC = 3.0V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
Maximum Access Time 40 55 ns
Typical Operating Current 49 42 mA
Typical Standby Current for I
Typical Standby Current for I
SB1
SB3
CYDC064B08
-40
77µA
66µA
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
UnitPort I/O Voltages (P1-P2) 3.0V-3.0V 3.0V-3.0V
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-01638 Rev. *E Revised January 25, 2007
[+] Feedback
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
I/O[15:0]
UB
LB
A[13:0]
CE
L
OE
L
R/W
SEM
BUSY
L
L
L
IO
Control
IO
Control
I/O[15:0]
UB
LB
R
R
R
16K X 16
Dual Ported Array
Address Decode
L
Interrupt
Arbitration
L
L
L
Semaphore
Address Decode
A [13:0]
CE
OE
R/W
SEM
BUSY
R
R
R
R
R
R
Notes:
1. A
0–A11
2. BUSY
CE
OE
R/W
MailboxesINT
L
L
L
L
IRR0 ,IRR
1
Figure 1. Top Level Block Diagram
for 4k devices; A0–A12 for 8k devices; A0–A13 for 16k devices.
is an output in master mode and an input in slave mode.
INT
M/S
R
Input Read
Register and
Output Drive
Register
SFEN
ODR0 - ODR
[1, 2]
CE
OE
R/W
4
R
R
R
Document #: 001-01638 Rev. *E Page 2 of 26
[+] Feedback
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Pin Configurations
A
4L
A
5L
A
6L
A
7L
A
8L
CE
L
SEM
L
INT
L
BUSY
L
A
9L
A
10L
V
SS
V
CC
A
11L
[3]
A
12L
[5]
IRR0
M/S
V
DDIOL
I/O
0L
I/O
1L
I/O
2L
V
SS
I/O
3L
I/O
4L
I/O
5L
[3, 4, 5, 6, 7]
A3LA2LA1LA0LUBLLB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100-Pin TQFP (Top View)
L
L
OE
R/WLV
SFEN
SS
ODR0
VSSODR2
ODR1
ODR3
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
CYDC064B16
CYDC128B16
CYDC256B16
34 35 36 424139 403837 43 44 45 5048 494746
3332313029282726
ODR4
R
VSSR/W
OERLBRUBRA0RA1RA2RA
3R
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
4R
A
5R
A
6R
A
7R
A
8R
CE
SEM
INT
BUSY
A
9R
A
10R
V
SS
V
CC
A
11R
A
12R
IRR1
NC
V
DDIOR
I/O
I/O
I/O
V
SS
I/O
I/O
I/O
R
R
R
R
[3]
[6]
[7]
15R
14R
13R
12R
11R
10R
6L
Notes:
3. A12L and A12R are NC pins for CYDC064B16.
4. IRR functionality is not supported for the CYDC256B16 device.
5. This pin is A13L for CYDC256B16 device.
6. This pin is A13R for CYDC256B16 device.
8L
I/O7LI/O
DDIOL
V
SS
10L
V
I/O9LI/O
I/O
12L
11L
13L
I/O
I/O
I/O
[7]
1R
2R
0R
15L
14L
NC
I/O
I/O
I/O
3R
I/O
I/O
I/O
5R
4R
SS
V
I/O
8R
I/O7RI/O6RI/O
I/O9RI/O
DDIOR
V
7. Leave this pin unconnected. No trace or power component can be connected to this pin.
Document #: 001-01638 Rev. *E Page 3 of 26
[+] Feedback
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Pin Configurations (continued)
A3LA2LA1LA0LUBLLB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SEM
INT
BUSY
A
A
A
IRR0
V
DDIOL
I/O
I/O
I/O
I/O
I/O
I/O
A
A
A
A
A
CE
A
V
V
M/S
V
10L
CC
11L
12L
4L
5L
6L
7L
8L
L
L
L
L
9L
SS
[9]
0L
1L
2L
SS
3L
4L
5L
[7, 8, 9, 10]
100-pin TQFP (Top View)
L
L
OE
R/WLV
SFEN
SS
ODR0
VSSODR2
ODR1
ODR3
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
CYDC064B08
CYDC128B08
34 35 36 424139 403837 43 44 45 5048 494746
3332313029282726
ODR4
R
VSSR/W
OERLBRUBRA0RA1RA2RA
3R
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
4R
A
5R
A
6R
A
7R
A
8R
CE
SEM
INT
BUSY
A
9R
A
10R
V
SS
V
CC
A
11R
A
12R
IRR1
NC
V
DDIOR
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
R
R
R
R
[10]
[11]
6L
Notes:
8. IRR functionality is not supported for the CYDC128B08 device.
9. This pin is A13L for CYDC128B08 devices.
SS
I/O7LI/O
DDIOL
V
VSSVSSVSSV
1R
2R
I/O
I/O
3R
I/O
0R
SS
VSSV
SS
SS
[11]
V
VSSV
NC
I/O
I/O
5R
4R
SS
V
SS
I/O7RI/O6RI/O
VSSV
DDIOR
V
10. This pin is A13R for CYDC128B08 devices.
Document #: 001-01638 Rev. *E Page 4 of 26
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Pin Definitions
Left Port Right Port Description
CE
L
R/W
L
OE
L
A
0L–A13L
–I/O
I/O
0L
15L
SEM
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A0R–A
13R
I/O0R–I/O
UB
LB
INT
BUSY
15R
R
R
R
R
R
IRR0, IRR1 Input Read Register for CYDC064B16, CYDC064B08, CYDC128B16.
ODR0-ODR4 Output Drive Register; These outputs are Open Drain.
SFEN
M/S
V
CC
GND Ground
V
DDIOL
V
DDIOR
NC No Connect. Leave this pin Unconnected.
Chip Enable
Read/Write Enable
Output Enable
Address (A0–A11 for 4k devices; A0–A12 for 8k devices; A0–A13 for 16k devices).
Data Bus Input/Output for x16 devices; I/O0–I/O7 for x8 devices.
Semaphore Enable
Upper Byte Select (I/O8–I/O15 for x16 devices; Not applicable for x8 devices).
Lower Byte Select (I/O0–I/O7 for x16 devices; Not applicable for x8 devices).
Interrupt Flag
Busy Flag
A13L, A13R for CYDC256B16 and CYDC128B08 devices.
Special Function Enable
Master or Slave Select
Core Power
Left Port I/O Voltage
Right Port I/O Voltage
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Functional Description
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 are low-power CMOS 4k,
8k,16k x 16, and 8/16k x 8 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations
when multiple processors access the same piece of data. Two
ports are provided, permitting independent, asynchronous
access for reads and writes to any location in memory. The
devices can be utilized as standalone 16-bit dual-port static
RAMs or multiple devices can be combined in order to function
as a 32-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE
Read or Write Enable (R/W
flags are provided on each port (BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT
) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Enable (CE
) pin.
), and Output Enable (OE). Two
and INT). BUSY
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 are available in 100-pin TQFP
packages.
Power Supply
The core voltage (VCC) can be 1.8V, 2.5V or 3.0V, as long as
it is lower than or equal to the I/O voltage.
Each port can operate on independent I/O voltages. This is
determined by what is connected to the V
pins. The supported I/O standards are 1.8V/2.5V LVCMOS
DDIOL
and 3.0V LVTTL.
Write Operation
Data must be set up for a duration of t
of R/W
in order to guarantee a valid write. A write operation is
controlled by either the R/W
waveform) or the CE
),
Required inputs for non-contention operations are summa-
pin (see Write Cycle No. 2 waveform).
pin (see Write Cycle No. 1
before the rising edge
SD
rized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
after the data is presented on the other port.
DDD
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
is asserted. If the user wishes to access a semaphore flag,
OE
after CE or t
ACE
and V
DOE
DDIOR
after
Document #: 001-01638 Rev. *E Page 5 of 26
[+] Feedback
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
then the SEM pin must be asserted instead of the CE pin, and
must also be asserted.
OE
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CYDC064B16, 1FFF for the CYDC128B16 and CYDC064B08,
3FFF for the CYDC256B16 and CYDC128B08) is the mailbox
for the right port and the second-highest memory location (FFE
for the CYDC064B16, 1FFE for the CYDC128B16 and
CYDC064B08, 3FFE for the CYDC256B16 and CYDC128B08)
is the mailbox for the left port. When one port writes to the
other port’s mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user-defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. On power up, an initialization program should be run
and the interrupts for both ports must be read to reset them.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ CE
within t
PS
port has access. If t
permission to the location, but it is not predictable which port
will get that permission. BUSY will be asserted t
address match or t
s are asserted and an address match occurs
of each other, the busy logic will determine which
is violated, one port will definitely gain
PS
after an
after CE is taken LOW.
BLC
BLA
Master/Slave
A M/S
pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S
device to be used as a master and, therefore, the BUSY
is an output. BUSY
can then be used to send the arbitration
input has settled (t
pin allows the
BLC
or t
BLA
line
outcome to a slave.
Input Read Register
The Input Read Register (IRR) captures the status of two
external input devices that are connected to the Input Read
pins.
The contents of the IRR read from address x0000 from either
port. During reads from the IRR, DQ0 and DQ1 are valid bits
and DQ<15:2> are don’t care. Writes to address x0000 are not
allowed from either port.
Address x0000 is not available for standard memory accesses
when SFEN
= VIL. When SFEN = VIH, address x0000 is
available for memory accesses.
The inputs will be 1.8V/2.5V LVCMOS or 3.0V LVTTL,
depending on the core voltage supply (V
for Input Read Register operation.
). Refer to Table 3
CC
IRR is not available in the CYDC256B16 and CYDC128B08,
as the IRR pins are used as extra address pins A
Output Drive Register
The Output Drive Register (ODR) determines the state of up
to five external binary state devices by providing a path to V
for the external circuit. These outputs are Open Drain.
The five external devices can operate at different voltages
(1.5V ≤ V
40 mA (8 mA max for each external device). The status of the
≤ 3.5V) but the combined current cannot exceed
DDIO
ODR bits are set using standard write accesses from either
port to address x0001 with a “1” corresponding to on and “0”
corresponding to off.
The status of the ODR bits can be read with a standard read
access to address x0001. When SFEN
= VIL, the ODR is active
and address x0001 is not available for memory accesses.
When SFEN = VIH, the ODR is inactive and address x0001 can
be used for standard accesses.
During reads and writes to ODR DQ<4:0> are valid and
DQ<15:5> are don’t care. Refer to Table 4 for Output Drive
Register operation.
Semaphore Operation
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 provide eight semaphore
latches, which are separate from the dual-port memory
locations. Semaphores are used to reserve resources that are
shared between the two ports. The state of the semaphore
indicates that a resource is in use. For example, if the left port
wants to request a given resource, it sets a latch by writing a
zero to a semaphore location. The left port then verifies its
success in setting the latch by reading it. After writing to the
semaphore, SEM
or OE must be deasserted for t
attempting to read the semaphore. The semaphore value will
be available t
semaphore write. If the left port was successful (reads a zero),
SWRD
+ t
after the rising edge of the
DOE
it assumes control of the shared resource, otherwise (reads a
one) it assumes the right port has control and continues to poll
the semaphore. When the right side has relinquished control
of the semaphore (by writing a one), the left side will succeed
in gaining control of the semaphore. If the left side no longer
),
requires the semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM
LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
semaphore address. OE
and R/W are used in the same
represents the
0–2
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
written to the left port of an available semaphore, a one will
is used. If a zero is
0
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 5 shows
sample semaphore operations.
13L
and A
SOP
13R
SS
before
.
Document #: 001-01638 Rev. *E Page 6 of 26
[+] Feedback
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
When reading a semaphore, all sixteen/eight data lines output
the semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within t
definitely be obtained by one side or the other, but there is no
of each other, the semaphore will
SPS
guarantee which side will control the semaphore. On
power-up, both ports should write “1” to all eight semaphores.
CYDC128B08 consist of an array of 8k and 16k words of 8
each of dual-port RAM cells, I/O and address lines, and control
signals (CE
, OE, R/W).These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two Interrupt (INT
for port-to-port communication. Two Semaphore (SEM
control pins are used for allocating shared resources. With the
M/S pin, the devices can function as a master (BUSY pins are
Architecture
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 consist of an array of 4k, 8k, or
16k words of 16 dual-port RAM cells, I/O and address lines,
and control signals (CE
, OE, R/W). The CYDC064B08 and
outputs) or as a slave (BUSY
pins are inputs). The devices
also have an automatic power-down feature controlled by CE
Each port is provided with its own output enable control (OE
which allows data to be read from the device.
Table 1. Non-Contending Read/Write
Inputs Outputs
[11]
15
I/O0–I/O
7
OperationCE R/W OE UB LB SEM I/O8–I/O
H X X X X H High Z High Z Deselected: Power-down
X X X H H H High Z High Z Deselected: Power-down
L L X L H H Data In High Z Write to Upper Byte Only
L L X H L H High Z Data In Write to Lower Byte Only
L L X L L H Data In Data In Write to Both Bytes
L H L L H H Data Out High Z Read Upper Byte Only
L H L H L H High Z Data Out Read Lower Byte Only
L H L L L H Data Out Data Out Read Both Bytes
X X H X X X High Z High Z Outputs Disabled
H H L X X L Data Out Data Out Read Data in Semaphore Flag
X H L H H L Data Out Data Out Read Data in Semaphore Flag
H X X X L Data In Data In Write D
into Semaphore Flag
IN0
) pins can be utilized
)
.
),
X X H H L Data In Data In Write D
into Semaphore Flag
IN0
LXXLXL Not Allowed
L X X X L L Not Allowed
Table 2. Interrupt Operation Example (Assumes BUSY
= BUSYR = HIGH)
L
[12]
Left Port Right Port
Function
Set Right INTR Flag L L X 3FFF
Reset Right INTR Flag X X X X X X L L 3FFF
Set Left INTL Flag X X X X L
Reset Left INT
Notes:
11. This column applies to x16 devices only.
12. See Interrupts Functional Description for specific highest memory locations by device.
13. If BUSY
14. If BUSY
15. See Functional Description for specific addresses by device.
Flag X L L 3FFE
L
= L, then no change.
R
= L, then no change.
L
R/WLCELOE
L
A
0L–13L
[15]
[15]
INTLR/WRCEROE
R
XXXX X L
[13]
H
[14]
LLX 3FFE
XXX X X
A
0R–13R
[15]
[15]
INT
[14]
H
X
R
[13]
Document #: 001-01638 Rev. *E Page 7 of 26
[+] Feedback
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
[21]
[16, 19]
[17]
L
[17]
VALID
[18]
[17]
L
x0000-Max VALID
[17]
[18]
[18]
VAL ID
15
[17]
Standard Memory Access
X IRR Read
15
[17]
Standard Memory Access
X ODR Write
X ODR Read
Mode
Mode
[20, 22]
[20]
Table 3. Input Read Register Operation
SFEN CE R/W OE UB LB ADDR I/O0–I/O1I/O2–I/O
HLHLLLx0000-MaxVALID
L L H L X L x0000 VALID
Table 4. Output Drive Register
[20]
SFEN CE R/W OE UB LB ADDR I/O0–I/O4I/O5–I/O
HLHX
LLLXXLx0001VALID
LLHLXLx0001VALID
Table 5. Semaphore Operation Example
Function I/O0–I/O
Left I/O0–I/O
15
Right Status
15
No action 1 1 Semaphore-free
Left port writes 0 to semaphore 0 1 Left Port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Notes:
= VIL for IRR reads.
16. SFEN
or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid.
17. UB
must be active (LB = VIL) for these bits to be valid.
18. LB
active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH.
19. SFEN
= VIL for ODR reads and writes.
20. SFEN
21. Output enable must be low (OE
22. During ODR writes data will also be written to the memory.
= VIL) during reads for valid data to be output.
Document #: 001-01638 Rev. *E Page 8 of 26
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