Cypress CY8CTMA120, CY8CTMG120, CY8CTST120 User Manual

CY8CTST120, CY8CTMG120, CY8CTMA120

Part Number

Ordering Information

CY8CTxx120

CY8CTST120-56LFXI

CY8CTST120-56LFXIT

CY8CTST120-00AXI

CY8CTMG120-56LFXI

CY8CTMG120-56LFXIT

CY8CTMG120-00AXI

CY8CTMA120-56LFXI

CY8CTMA120-56LFXIT

CY8CTMA120-00AXI

Items

Part Number

Silicon Revision

Fix Status

[1]. Internal Main Oscillator
(IMO) tolerance deviation at
temperature extremes

CY8CTxx120

A

Silicon fix is planned.

[2]. The DP line of the USB
interface may pulse low when
the PSoC device wakes from
sleep, causing an unexpected
wakeup of the host computer

CY8CTxx120

A

Use workaround.
[3]. Invalid Flash reads may

occur if Vdd is pulled to -0.5V
just before power on

CY8CTxx120

A

Use workaround.

[4]. PMA Index Register fails
to auto increment with
CPU_Clock set to SysClk/1
(24 MHz)

CY8CTxx120

A

Use workaround.

September 2008

Silicon Errata for CY8CTST120, CY8CTMG120, and CY8CTMA120

This document describes the errata for the TrueTouch™ devices CY8CTST120, CY8CTMA120, and
CY8CTMG120. Details include errata trigger conditions, scope of impact, available workarounds, and silicon
revision applicability. Compare this document to the device’s data sheet for a complete functional description.

Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Errata Summary

The following table defines the errata applicability to available CY8CTxx120 family devices.

September 25, 2008 Document No. 001-49038 Rev. ** 1

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CY8CTST120, CY8CTMG120, CY8CTMA120

1. Internal Main Oscillator (IMO) tolerance deviation at temperature extremes.

 PROBLEM DEFINITION

Asynchronous digital communication interfaces may fail framing beyond 0 to 70°C. This problem does not
affect end product usage between 0 and 70°C.

 PARAMETERS AFFECTED

The IMO frequency tolerance. The worst case deviation when operated below 0°C and above +70°C and
within the upper and lower data sheet temperature range is ±5%.

 TRIGGER CONDITION

The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit
of ±4% when operated beyond the temperature range of 0 to +70°C.

 SCOPE OF IMPACT

This problem may affect UART, IrDA, and FSK implementations.

 WORKAROUND

Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital
communications interface.

 FIX STATUS

The cause of this problem and its solution has been identified. Silicon fix is planned to correct the
deficiency in silicon.

2. The DP line of the USB interface may pulse low when the PSoC® device wakes from sleep causing an
unexpected wakeup of the host computer

 PROBLEM DEFINITION

When the device is operating at 4.75V to 5.25V and the 3.3V regulator is enabled, a short low pulse may
be created on the DP signal line during device wakeup. The 15 µs to 20 µs low pulse of the DP line may
be interpreted by the host computer as a de-attach or the beginning of a wakeup.

 PARAMETERS AFFECTED

The bandgap reference voltage used by the 3.3V regulator decreases during sleep due to leakage. Upon
device wakeup, the bandgap is re-enabled and after a delay for settling, the 3.3V regulator is enabled. On
some devices the 3.3V regulator that is used to generate the USB DP signal may be enabled before the
bandgap is fully stabilized. This can cause a low pulse on the regulator output and DP signal line until the
bandgap stabilizes. In applications where Vdd is 3.3V, the regulator is not used; therefore, the DP low
pulse is not generated.

 WORKAROUND

To prevent the DP signal from pulsing low, keep the bandgap enabled during sleep. The most efficient
method is to set the No Buzz bit in the OSC_CR0 register. The No Buzz bit keeps the bandgap powered
and output stable during sleep. Setting the No Buzz bit results in a nominal 100 µA increase to sleep
current. Leaving the analog reference block enabled during sleep also resolves this issue because it
forces the bandgap to remain enabled. An example to disable the No Buzz bit is as follows.

Assembly

M8C_SetBank1
or reg[OSC_CR0], 0x20
M8C_SetBank0

C

OSC_CR0 |= 0x20;

September 25, 2008 Document No. 001-49038 Rev. ** 2

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