Cypress CY8CNP102B, CY8CNP102E User Manual

PRELIMINARY

CY8CNP102B, CY8CNP102E

Nonvolatile Programmable System-on-Chip

(

PSoC® NV)

Overview

The Cypress nonvolatile Programmable System-on-Chip

®

(PSoC

NV) processor combines a versatile Programmable
System-on-Chip™ (PSoC) core with an infinite endurance
nvSRAM in a single package. The PSoC NV combines an 8-bit
MCU core (M8C), configurable analog and digital functions, a
uniquely flexible IO interface, and a high density nvSRAM. This
creates versatile data logging solutions that provide value
through component integration and programmability. The flexible
core and a powerful development environment work to reduce
design complexity, component count, and development time.

Features

■ Powerful Harvard Architecture Processor

❐ M8C processor speeds

• Up to 12 MHz for 3.3V operation

• Up to 24 MHz for 5V operation

❐ Two 8x8 multiply, 32 bit accumulate
❐ Low power at high speed

■ Operating Voltage

❐ 3.3V (CY8CNP102B)
❐ 5V (CY8CNP102E)

■ Advanced Peripherals

❐ 12 Rail-to-Rail Analog PSoC blocks provide:

• Up to 14 bit ADCs

• Up to 9 bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

• 8 Analog channels for simultaneous sampling

• Up to 820 SPS for each channel with 8 channel sampling
and logging

❐ 16 Digital PSoC Blocks provide:

• 8 to 32 bit timers, counters, and PWMs

• CRC and PRS Modules

• Up to 4 Full Duplex UARTs

• Multiple SPI™ Masters and Slaves

❐ Complex Peripherals by Combining Blocks

■ Precision, Programmable Clocking
❐ Internal ±2.5% 24 and 48 MHz Oscillator

❐ 24 and 48 MHz with optional 32.768 kHz Crystal
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep

■ Flexible On-Chip Memory
❐ 32K Bytes Flash Program Storage

❐ 2K Bytes SRAM Data Storage
❐ 256K Bytes secure store nvSRAM with data throughput be-

tween 100 KBPS and 1 MBPS

❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations
❐ 33 GPIOs
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive

Modes on all GPIO

❐ Up to 12 Analog Inputs on GPIOs
❐ Analog Outputs with 40 mA on 4 GPIOs
❐ Configurable Interrupt on all GPIOs

■ Additional System Resources

2

❐ I

C Slave, Master, and MultiMaster to 100 Kbps

and 400 Kbps

❐ Watchdog and Sleep Timers
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference

■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)

❐ Full Featured, In Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ C Compilers, Assembler, and Linker

■ Temperature and Packaging
❐ Industrial Temperature Range: -40°C to +85°C
❐ Packaging: 100-pin TQFP

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-43991 Rev. *D Revised October 20, 2008

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Logic Block Diagram

Document #: 001-43991 Rev. *D Page 2 of 38

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Pinouts

Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm)

Table 1. Pin Definitions - 100-Pin TQFP

Pin Number Pin Name

1 P0_5 IO IO Analog Column Mux Input and Column Output

2 P0_3 IO IO Analog Column Mux Input and Column Output

3 P0_1 IO I Analog Column Mux Input, GPIO

4P2_7IO GPIO

5P2_5IO GPIO

6 P2_3 IO I Direct Switched Capacitor Block Input

7 P2_1 IO I Direct Switched Capacitor Block Input

8 Vcc Power Supply Voltage

9 DNU Reserved for test modes - Do Not Use

10 DNU Reserved for test modes - Do Not Use

11 DNU Reserved for test modes - Do Not Use

12 DNU Reserved for test modes - Do Not Use

13 DNU Reserved for test modes - Do Not Use

14 NC

15 P3_5 IO GPIO

16 EN_W Connect to Pin 26 (EN_W to NV_W)

17 P3_1 IO GPIO

Digital Analog

Typ e

Pin Definition

Not connected on the die

Document #: 001-43991 Rev. *D Page 3 of 38

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Table 1. Pin Definitions - 100-Pin TQFP (continued)

Pin Number Pin Name

18 P5_7 IO GPIO

19 P5_5 IO GPIO

20 P5_3 IO GPIO

21 P5_1 IO GPIO

22 P1_7 IO I2C Serial Clock (SCL), GPIO

23 P1_5 IO I2C Serial Data (SDA), GPIO

24 P1_3 IO GPIO

25 P1_1 IO Serial Clock (SCL), Crystal (XTALin), GPIO

26 NV_W Connect to pin 16 (NV_W to EN_W)

27 - 34 NC

35 - 39 Vss Power Ground

40 - 47 NC

48 DNU Reserved for test modes - Do Not Use

49 NV_A1 Connect to pin 58 (NV_A1 to EN_A1)

50 NV_A2 Connect to pin 59 (NV_A2 to EN_A2)

51 P1_0 IO Serial Data (SDA), Crystal (XTALout), GPIO

52 P1_2 IO GPIO

53 P1_6 IO GPIO

54 P5_0 IO GPIO

55 P5_2 IO GPIO

56 P5_4 IO GPIO

57 P5_6 IO GPIO

58 EN_A1 Connect to Pin 49 (EN_A1 to NV_A1)

59 EN_A2 Connect to Pin 50 (EN_A2 to NV_A2)

60 EN_O Connect to Pin 76 (EN_O to NV_O)

61 EN_C Connect to Pin 99 (EN_C to NV_C)

62 XRES Input Active high external reset (Internal Pull down)

63 VCAP Power External Capacitor connection for nvSRAM

64 Vcc Power Supply Voltage

65 P2_0 IO I Direct Switched Capacitor Block Input, GPIO

66 P2_2 IO I Direct Switched Capacitor Block Input, GPIO

67 P2_4 IO External Analog GND, GPIO

68 P2_6 IO External Voltage Ref, GPIO

69 P0_0 IO I Analog Column Mux Input, GPIO

70 P0_2 IO IO Analog Column Mux Input and Column Output

71 P0_4 IO IO Analog Column Mux Input and Column Output

72-73 NC

74 P0_6 IO I Analog Column Mux Input, GPIO

75 Vcc Power Supply Voltage

76 NV_O Connect to Pin 60 (NV_O to EN_O)

77 DNU Reserved for test modes - Do Not Use

78 NC

Digital Analog

Typ e

Pin Definition

Not connected on the die

Not connected on the die

Not connected on the die

Not connected on the die

Document #: 001-43991 Rev. *D Page 4 of 38

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Table 1. Pin Definitions - 100-Pin TQFP (continued)

Pin Number Pin Name

79 HSB# Weak Pull up. Connect 10kΩ to Vcc.

80 Vcc Power Supply Voltage

81 - 85 NC

86 - 90 Vss Power Ground

91 - 98 NC

99 NV_C Connect to Pin 61 (NV_C to EN_C).Weak Pull up. Connect 10kΩ to Vcc.

100 P0_7 IO I Analog Column Mux Input, GPIO

Digital Analog

Typ e

Pin Definition

Not connected on the die

Not connected on the die

PSoC NV Functional Overview

The PSoC NV provides a versatile microcontroller core (M8C),
Flash program memory, nvSRAM data memory, and
configurable analog and digital peripheral blocks in a single
package. The flexible digital and analog IOs and routing matrix
create a powerful embedded and flexible mixed signal
System-on-Chip (SoC).

The device incorporates configurable analog and digital blocks,
interconnect circuitry around an MCU subsystem, and an infinite
endurance nvSRAM. This enables high level integration in
consumer, industrial, and automotive applications, where
preventing data loss under all conditions is vital.

PSoC NV Core

The PSoC NV core is a powerful PSoC engine that supports a
rich feature set. The core includes a M8C CPU, memory, clocks,
and configurable GPIO (General Purpose IO). The M8C CPU
core is a powerful processor with speeds up to 24 MHz, providing
a four MIPS 8-bit Harvard architecture microprocessor. The CPU
uses an interrupt controller with 25 vectors, to simplify
programming of real time embedded events. Program execution
is timed and protected using the included Sleep and Watch Dog
Timers (WDT).

On-chip memory encompasses 32 KB Flash for program
storage, 2 KB SRAM for data storage, 256 KB nvSRAM for data
logging, and up to 2 KB EEPROM emulated using Flash.
Program Flash uses four protection levels on blocks of 64 bytes,
allowing customized software IP protection. The nvSRAM
combines a static RAM cell and a SONOS cell to provide an
infinite endurance nonvolatile memory block. The memory is
random access and is accessed using a user module provided
with the device.

The device incorporates flexible internal clock generators,
including a 24 MHz Internal Main Oscillator (IMO) accurate to 2.5
percent over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz Internal Low speed Oscillator (ILO) is provided for the
Sleep timer and WDT. The clocks, together with programmable
clock dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC NV
device.

GPIOs provide connection to the CPU, and digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external

interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.

nvSRAM Data Memory

The nvSRAM memory block is byte addressable fast static RAM
with a nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap® technology
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, when independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down, and
data is restored to the SRAM (the RECALL operation) from the
nonvolatile memory on power up. All cells store and recall data
in parallel.

Both the STORE and RECALL operations may be initiated under
software control. The PSoC NV user module embedded in the
PSoC Designer Tool provides all necessary APIs to initiate
software STORE and RECALL function from the user program.

nvSRAM Operation

The nvSRAM is made up of an SRAM memory cell, and a
nonvolatile QuantumTrap cell paired in the same physical cell.
The SRAM memory cell operates as a standard fast static, and
all READ and WRITE takes place from the SRAM during normal
operation.

During the STORE and RECALL operations, SRAM READ and
WRITE operations are inhibited, and internal operations transfer
data between the SRAM and nonvolatile cells. The nvSRAM
provides infinite RECALL operations from the nonvolatile cells
and up to 200,000 STORE operations.

CAP

SWITCH

®

is ignored

pin. This

, the part

To reduce unnecessary nonvolatile stores, AutoStore
unless at least one WRITE operation is complete after the most
recent STORE or RECALL cycle. Software initiated STORE
cycles are performed regardless of whether a WRITE operation
has taken place. Embedded APIs provide a seamless interface
to the nvSRAM.

During normal operation, the embedded nvSRAM draws current
from Vcc to charge a capacitor connected to the V
stored charge is used by the chip to perform a STORE operation.
If the voltage on the Vcc pin drops below V
automatically disconnects the V
operation is initiated.

pin from Vcc and STORE

CAP

Document #: 001-43991 Rev. *D Page 5 of 38

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Programmable Digital System

The digital system contains 16 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references. The digital peripheral configurations
are:

■ PWMs (8 to 32 bit)

■ PWMs with dead band (8 to 32 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity (up to 4)

■ SPI master and slave (up to 4 each)

2

■ I

C slave and multimaster (1 available as a System Resource)

■ Cyclical Redundancy Checker and Generator (8 to 32 bit)

■ IrDA (up to 4)

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks connect to any GPIO through a series of global
buses that route any signal to any pin. The buses also enable
signal multiplexing and performing logic operations. This
configurability frees your designs from the constraints of a fixed
peripheral controller.

Digital blocks are provided in rows of four, where the number of
blocks varies with PSoC device family. This gives you the
optimum choice of system resources for your application.

Programmable Analog System

■ Peak Detectors

■ Other possible topologies

■ Analog blocks are provided in columns of three, which includes

one CT (Continuous Time) and two SC (Switched Capacitor)
blocks.

Additional System Resources

System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. The merits of
each system resource are:

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.

■ Multiply Accumulate (MAC) provides fast 8-bit multiplier with

32-bit accumulate, to assist in general math and digital filters.

■ The decimator provides a custom hardware filter for digital

signal, and processing applications including the creation of
Delta Sigma ADCs.

2

■ The I

■ Low Voltage Detection (LVD) interrupts can signal the

C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi master modes are all
supported.

application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.

The analog system consists 12 configurable blocks, each having
an opamp circuit enabling the creation of complex analog signal
flows. Analog peripherals are very flexible and may be
customized to support specific application requirements. Some
of the more common analog functions (most available as user
modules) are:

■ Analog-to-digital converters (up to 4, with 6 to 14 bit resolution,

selectable as Incremental, Delta Sigma, and SAR)

■ Filters (2, 4, 6, or 8 pole band pass, low pass, and notch)

■ Amplifiers (up to 4, with selectable gain to 48x)

■ Instrumentation amplifiers (up to 2, with selectable gain to 93x)

■ Comparators (up to 4, with 16 selectable thresholds)

■ DACs (up to 4, with 6 to 9 bit resolution)

■ Multiplying DACs (up to 4, with 6 to 9 bit resolution)

■ High current output drivers (four with 40 mA drive as a Core

Resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

Document #: 001-43991 Rev. *D Page 6 of 38

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Development Tools

Commands

Results

PSoC

Designer

Core

Engine

PSoC

Configuration

Sheet

Manufacturing

Info rm atio n

File

Device

Database

Importable

Design

Database

Device

Programmer

Graphical Designer

Inter face

Context

Se nsitive

Help

Emulation

Pod

In-C irc uit
Emulator

Project

Database

Ap plic atio n

Database

User

Modules

Library

PSoC

Designer

PSoC Designer Software Subsystems

PSoC Designer is a Microsoft® Windows based, integrated
development environment for Programmable System-on-Chip
(PSoC) devices. The PSoC Designer IDE and application run on
Windows NT 4.0, Windows 2000, Windows Millennium (Me),
Microsoft Vista, and Windows XP.

PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.

PSoC Designer also supports a high level C language compiler
developed specifically for the devices in this family.

Figure 2. PSoC Designer Subsystem

Device Editor

The Device Editor subsystem enables the user to select different
onboard analog and digital components called user modules,
using the PSoC blocks. Examples of user modules are ADCs,
DACs, nvSRAM, Amplifiers, and Filters.

The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration enables changing configurations at run time.

PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components. Also, if the project uses more
than one operating configuration, the framework contains
routines to switch between different sets of PSoC block
configurations at run time. PSoC Designer can print out a
configuration sheet for a given project configuration, for use
during application programming in conjunction with the Device
Data Sheet. After the framework is generated, the user can add
application specific code to flesh out the framework. It is also
possible to change the selected components and regenerate the
framework.

Design Browser

The Design Browser enables users to select and import
preconfigured designs into their project. Users can easily browse
a catalog of preconfigured designs to facilitate time to design.
Examples provided in the tools include a 300 baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.

Application Editor

In the Application Editor you can edit C language and Assembly
language source code. You can also assemble, compile, link,
and build.

Assembler. The macro assembler seamlessly merges the
assembly code with C code. The link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.

C Language Compiler. A C language compiler that supports
Cypress PSoC family devices is available. Even if you have
never worked in the C language before, the product quickly
enables you to create complete C programs for the PSoC family
devices.

The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It is complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.

Debugger

The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, which enables the designer to test the
program in a physical system while providing an internal view of
the PSoC device. Debugger commands enable the designer to
read and program, read and write data memory, read and write
IO registers, read and write CPU registers, set and clear
breakpoints, and provide program run, halt, and step control. The
debugger also enables the designer to create a trace buffer of
registers and memory locations of interest.

Document #: 001-43991 Rev. *D Page 7 of 38

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Online Help System

Debugger

Int erfac e

to ICE

Application Editor

Device Editor

Project

Manager

Source

Code

Editor

Storage

Inspector

User

Module

Selection

Placement

and

Parameter

-ization

Generate
Application

Build
All

Event &

Breakpoint

Manager

Build

Manager

Source

Code

Generator

The online help system displays online, context sensitive help for
the user. Designed for procedural and quick reference, each
functional subsystem has its own context sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.

The emulator consists of a base unit that connects to the PC
through the USB port. The base unit is universal and operates
with all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed
(24 MHz) operation.

Designing with User Modules

The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that manages specification change during
development and lowers inventory costs. These configurable
resources, called PSoC Blocks, implement a wide variety of
user-selectable functions. Each block has several registers that
determine its function and connectivity to other blocks,
multiplexers, buses, and to the IO pins. Iterative development
cycles permit you to adapt the hardware and the software. This
substantially lowers the risk of selecting a different part to meet
the final design requirements.

The development process starts when you open a new project
and bring up the Device Editor, which is a graphical user
interface (GUI) for configuring the hardware. Pick the user
modules required for your project and map them onto the PSoC
blocks with point and click simplicity. Next, build signal chains by
interconnecting user modules to each other and to the IO pins.
At this stage, configure the clock source connections and enter
parameter values directly or by selecting values from drop down
menus. When you are ready to test the hardware configuration
or develop code for the project, perform the “Generate
Application” step. PSoC Designer generates source code that
automatically configures the device to your specification and
provides high level user module API functions.

User Module and Source Code Development Flows

The next step is to write the main program, and any subroutine
using PSoC Designer’s Application Editor subsystem. The
Application Editor includes a Project Manager that enables you
to open the project source code files (including all generated
code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for C and
assembly language. File search capabilities include simple string
searches and recursive “grep-style” patterns. A single mouse
click invokes the Build Manager.

It employs a professional strength “makefile” system to
automatically analyze all file dependencies and run the compiler
and assembler as necessary. Project level options control
optimization strategies used by the compiler and linker. Syntax
errors are displayed in a console window. Double clicking the
error message takes you directly to the offending line of source
code. After correction, the linker builds a HEX file image suitable
for programming.

Figure 3. User Module and Source Code Development Flows

To speed the development process, the PSoC Designer IDE
provides a library of prebuilt, pretested hardware peripheral
functions, called “User Modules.” User modules simplify
selecting and implementing peripheral devices, and come in
analog, digital, and mixed signal varieties. The standard User
Module library contains over 50 peripherals such as ADCs,
DACs, Timers, Counters, UARTs, nvSRAM, DTMF Generators,
and Bi-Quad analog filter sections.

Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
enable you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module Application Programming Interface (API) provides high
level functions to control and respond to hardware events at run
time. The API also provides optional interrupt service routines
that you can adapt as needed.

The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.

Document #: 001-43991 Rev. *D Page 8 of 38

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The last step in the development process takes place inside the

5.25

4.75

3.00

93 kHz 12 MHz 24 MHz

CPU Frequency

Vdd Voltage

5.25

4.75

3.00

93 kHz 12 MHz 24 MHz

IMO Frequency

Vdd Voltage

3.60

6 MHz

SLIMO Mode = 0

SLIMO

Mode=0

SLIMO

Mode=1

R

e

g

i

o

n

SLIMO

Mode=1

SLIMO

Mode=0

3.60

Operating Region

(CY8CNP102E)

Operating Region

(CY8CNP102B)

PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. The Debugger capabilities rival those of
systems costing much more. In addition to traditional single step,
run to breakpoint, and watch variable features, the Debugger
provides a large trace buffer enabling you to define complex
breakpoint events that include monitoring address and data bus
values, memory locations, and external signals.

Cypress nvSRAM user Module

The nvSRAM user module is integrated with the PSoC Designer
tool and contains APIs that facilitate nvSRAM access and
control. The user module provides high level access to the
nvSRAM without user developed code. The user module API
also provides the ability to read and write arbitrary data struc­tures to or from the nvSRAM, and initiate nvSRAM Store or
Recall operations.

Electrical Specifications

This section lists the PSoC NV device DC and AC electrical specifications.

Specifications are valid for -40

Refer Table 14 on page 17 for electrical specifications on the Internal Main Oscillator (IMO) using SLIMO mode.

Figure 4. Voltage versus CPU Frequency Figure 5. IMO Frequency Trim Options

o

C ≤ TA ≤ 85oC, and TJ ≤ 100oC, except where noted.

The following table lists the units of measure that are used in this data sheet.

Table 2. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

o

C degree Celsius μW microwatts

dB decibels mA milli-ampere

fF femto farad ms milli-second

Hz hertz mV milli-volts

KB 1024 bytes nA nanoampere

Kbit 1024 bits ns nanosecond

kHz kilohertz nV nanovolts

kΩ kilohm Ω ohm

MHz megahertz pA picoampere

MΩ megaohm pF picofarad

μA microampere pp peak-to-peak

μF microfarad ppm parts per million

μH microhenry ps picosecond

μs microsecond sps samples per second

μV microvolts σ sigma: one standard deviation

μVrms microvolts root-mean-square V volts

Document #: 001-43991 Rev. *D Page 9 of 38

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3.3V Operation

Absolute Maximum Ratings

Table 3. 3.3V Absolute Maximum Ratings (CY8CNP102B)

Symbol Description Min Ty p Max Units Notes

T

T

STG

A

Storage Temperature -55 25 +100

Ambient Temperature with Power Applied -40 – +85

Vcc Supply Voltage on Vcc Relative to Vss -0.5 – +4.1 V

V

IO

V

IOZ

I

MIO

I

MAIO

DC Input Voltage Vss - 0.5 – Vcc + 0.5 V

DC Voltage Applied to Tri-state Vss - 0.5 – Vcc + 0.5 V

Maximum Current into any Port Pin -25 – +50 mA

Maximum Current into any Port Pin

-50 – +50 mA

Configured as Analog Driver

ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.

LU Latch-up Current – – 200 mA

Operating Temperature

o

C Higher storage temperatures

reduce data retention time.
Recommended storage
temperature is ± 25

o

C.
Extended duration storage
temperatures above 65oC
degrade reliability.

o

C

Table 4. 3.3V Operating Temperature (CY8CNP102B)

Symbol Description Min Typ Max Units Notes

T

A

T

J

Ambient Temperature -40 – +85

Junction Temperature -40 – +100

o

C

o

C

Document #: 001-43991 Rev. *D Page 10 of 38

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DC Electrical Characteristics

The following DC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature
range: 3.0V to 3.6V over the Temperature range of -40°C ≤ T
guidance only.

DC Chip Level Specifications

Table 5. 3.3V DC Chip Level Specifications (CY8CNP102B)

Symbol Description Min Typ Max Units Notes

Vcc Supply Voltage 3.00 – 3.6 V

I

DD

I

DDP

I

SB

Supply Current – 36 40 mA TA = 25 oC, CPU = 3 MHz,

Supply current when IMO = 6 MHz
using SLIMO mode.

Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.

V

V

REF

cap

Reference Voltage (Bandgap) 1.28 1.3 1.32 V Trimmed for appropriate Vcc.

Storage Capacitor between Vcap and
Vss

≤ 85°C. Typical parameters apply to 3.3V at 25°C and are for design

A

SYSCLK doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 0.366 kHz, continuous
nvSRAM access

– 27 28 mA TA = 25 oC, CPU = 0.75 MHz,

SYSCLK doubler disabled,
VC1=0.375 MHz, VC2=23.44 kHz,
VC3 = 0.09 kHz, continuous
nvSRAM access

– – 5 mA nvSRAM in standby.

61 68 82 uF 5V rated (minimum)

DC General Purpose IO Specifications

Table 6. 3.3V DC GPIO Specifications (CY8CNP102B)

Symbol Description Min Typ Max Units Notes

R

PU

R

PD

V

OH

Pull up Resistor 4 5.6 8 KΩ

Pull down Resistor 4 5.6 8 KΩ

High Output Level Vcc - 1.0 – – V IOH = 10 mA, Vcc = 3.0 to 3.6V. 8

total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd
port pins (for example, P0[3],
P1[5]). 80 mA maximum combined
IOH budget.

V

OL

Low Output Level – – 0.75 V IOL = 25 mA, Vcc = 3.0 to 3.6V

8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3],
P1[5]). 150 mA maximum
combined IOL budget.

V

V

V

I

C

C

IL

IH

H

IL

IN

OUT

Input Low Level – – 0.8 V Vcc = 3.0 to 3.6

Input High Level 1.6 – V Vcc = 3.0 to 3.6

Input Hysterisis – 60 – mV

Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA.

Capacitive Load on Pins as Input – 3.5 10 pF Pin dependent.

Tem p = 2 5

Capacitive Load on Pins as Output – 3.5 10 pF Pin dependent.

Tem p = 2 5

o

C.

o

C.

Document #: 001-43991 Rev. *D Page 11 of 38

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PRELIMINARY CY8CNP102B, CY8CNP102E

DC Operational Amplifier Specifications

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.

Table 7. 3.3V DC Operational Amplifier Specifications (CY8CNP102B)

Symbol Description Min Typ Max Units Notes

V

OSOA

Input Offset Voltage (absolute value) High Power is 5 Volts Only

Power = Low, Opamp Bias = High – 1.65 10 mV

Power = Medium, Opamp Bias = High – 1.32 8 mV

TCV

OSOA

I

EBOA

C

INOA

V

CMOA

CMRR

G

OLOA

V

OHIGHOA

V

OLOWOA

I

SOA

Average Input Offset Voltage Drift – 7.0 35.0 μV/oC

Input Leakage Current (Port 0 Analog

– 200 – pA Gross tested to 1 μA.

Pins)

Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Pin dependent. Temp = 25 oC.

Common Mode Voltage Range 0 – Vcc V

Common Mode Rejection Ratio 60 – – dB

OA

Open Loop Gain 80 – – dB

High Output Voltage Swing (internal

Vcc - 0.01 – – V

signals)

Low Output Voltage Swing (internal

– – 0.01 V

signals)

Supply Current
(including associated AGND buffer)

Power = Low, Opamp Bias = Low – 150 200 μA

Power = Low, Opamp Bias = High – 300 400 μA

Power = Medium, Opamp Bias = Low – 600 800 μA

Power = Medium, Opamp Bias = High – 1200 1600 μA

Power = High, Opamp Bias = Low – 2400 3200 μA

Power = High, Opamp Bias = High – – – μA Not Allowed for 3.3V operation

PSRR

Supply Voltage Rejection Ratio 54 80 – dB Vss ≤ VIN ≤ (Vcc - 2.25) or

OA

(Vcc - 1.25V) ≤ VIN ≤ Vcc

DC Low Power Comparator Specifications

Table 8. 3.3V DC Low Power Comparator Specifications (CY8CNP102B)

Symbol Description Min Ty p Max Units

V

REFLPC

I

SLPC

V

OSLPC

Low power comparator (LPC) reference voltage range 0.2 – Vcc - 1.0 V

LPC supply current – 10 40 μA

LPC voltage offset – 2.5 30 mV

Document #: 001-43991 Rev. *D Page 12 of 38

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