CYPRESS CY8CLED04 User Manual

Features

CY8CLED04

EZ-Color™ HB LED Controller

■ HB LED Controller

❐ Configurable Dimmers Support up to 4

Independent LED Channels

❐ 8-32 Bits of Resolution per Channel
❐ Dynamic Reconfiguration Enables LED

Controller plus other Features; CapSense, Battery Charging,
Motor Control…

■ Visual Embedded Design, PSoC Express

❐ LED Based Express Drivers

• Binning Compensation

• Temperature Feedback

•DMX512

■ PrISM Modulation Technology
❐ Reduces Radiated EMI

❐ Reduces Low Frequency Blinking

■ Advanced Peripherals (PSoC Blocks)
❐ 4 Digital PSoC Blocks Provide:

• 8 to 32-Bit Timers, Counters, and PWMs

• Up to 2 Full-Duplex UART

• Multiple SPI™ Masters or Slaves

• Connectable to all GPIO Pins

❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs

• Up to 9-Bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

❐ Complex Peripherals by Combining Blocks
❐ Capacitive Sensing Application Capability

■ Complete Development Tools

❐ Free Development Software

• PSoC Designer™

• PSoC Express™

❐ Full-Featured, In-Circuit Emulator and

Programmer

❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KBytes Trace Memory

■ Programmable Pin Configurations

❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive

Modes on all GPIO

❐ Up to 12 Analog Inputs on GPIO
❐ Four 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO

■ Flexible On-Chip Memory

❐ 16K Flash Program Storage 50,000 Erase/Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash

■ Full-Speed USB (12 Mbps)

❐ Four Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-13108 Rev. ** Revised June 13, 2007

Overview

Block Diagram

CY8CLED04

Port 7

s

u
B

m

e

t

s

y

Global Digital Interconnect

S

SRAM

1K

Interrupt

Controller

DIGITAL SYSTEM

Digital

Block
Array

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

Global Analog Interconnect

PSoC CORE

SROM Flash 16K

Sleep and

CPU Core (M8C)

Watchdog

Clock Sources

(Includes IMO and ILO)

ANALOG SYSTEM

Analog

Ref.

Analog

Block
Array

Analog
Drivers

Digital

Clocks

2

MACs

Decimator

Type 2

POR and LVD

I2C USB

System Resets

Internal
Voltage

Ref.

Analog

Input

Muxing

SYSTEM RESOURCES

Document Number: 001-13108 Rev. ** Page 2 of 33

CY8CLED04

EZ-Color Functional Overview

Cypress' EZ-Color family of devices offers the ideal control
solution for High Brightness LED applications requiring intel­ligent dimming control. EZ-Color devices combine the power and
flexibility of PSoC (Programmable System-on-Chip™); with
Cypress' PrISM (precise illumination signal modulation)
modulation technology providing lighting designers a fully
customizable and integrated lighting solution platform.

The EZ-Color family support up to 16 independent LED channels
with up to 32 bits of resolution per channel, enabling lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Express software, with lighting specific drivers,
can significantly cut development time and simp lify implemen­tation of fixed color points through temperature and LED binning
compensation. EZ-Color's virtually limitless analog and digital
customization allow for simple integration of features in addition
to intelligent lighting, such as CapSense, Battery Charging,
Image Stabilization, and Motor Control during the development
process. These features, along with Cypress' best-in-class
quality and design support, make EZ-Color the ideal choice for
intelligent HB LED control applications.

Target Applications

■ LCD Backlight

■ Large Signs

■ General Lighting

■ Architectural Lighting

■ Camera/Cell Phone Flash

■ Flashlights

The PSoC Core

The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory , clocks, and configurable
GPIO (General Purpose IO).

The M8C CPU core is a powerful processor with speeds up to 68
MHz, providing a four MIPS 8-bit Harvard architecture micropro­cessor. The CPU utilizes an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).

Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash utilizes four protection levels on
blocks of 64 bytes, allowing customized software IP protection.

The EZ-Color family incorporates flexible internal clock gener­ators, including a 24 MHz IMO (internal main oscillator) accurate
to 8% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. The clocks, together with programmable
clock dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the EZ-Color
device. In USB systems, the IMO will self-tune to ± 0.25%
accuracy for USB communication.

EZ-Color GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.

The Digital System

The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.

Digital peripheral configurations include those listed below.

■ PrISM (8 to 32 bit)

■ Full-Speed USB (12 Mbps)

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 24 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity

■ SPI master and slave

■ I2C slave and multi-master

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA

■ Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device Charac­teristics.

Document Number: 001-13108 Rev. ** Page 3 of 33

CY8CLED04

Figure 1. Digital System Block Diagram

Port 2

Port 1

To Analog

System

4

4

GOE[7:0]

GOO[7:0]

Configuration

Port 0

Row Output

8

88

Port 7

D

Port 5

i

g

i

t

a

l

C

l

o

c

k

s

F

r

o

m

C

o

r

e

Port 3

Port 4

To System Bus

DIGITAL SYSTEM

Digital PSoC Block Array

8

DBB00 DBB01 DCB02 DCB03

Row Input

Configuration

GIE[7:0]

GIO[7:0]

Row 0

Global Digital

Interconnect

The Analog System

The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.

■ Analog-to-digital converters (up to 2, with 6- to 14-bit resolution,

selectable as Incremental, Delta Sigma, and SAR)

■ Filters (2 and 4 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 2, with selectable gain to 48x)

■ Instrumentation amplifiers (1 with selectable gain to 93x)

■ Comparators (up to 2, with 16 selectable thresholds)

■ DACs (up to 2, with 6- to 9-bit resolution)

■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)

■ High current output drivers (two with 30 mA drive as a PSoC

Core Resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

■ Peak Detectors

■ Many other topologies possible

Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.

Figure 2. Analog System Block Diagram

All IO

(Except Port 7)

P0[7]

P0[5]

P0[3]
P0[1]

P2[3]

P2[1]

Interface to

Digital System

ACI0[1:0]

Array Input

Configura tio n

Block
Array

M8C Interface (Address Bus, Data Bus, Etc.)

ACB00 ACB01

ASC10

ASD20

RefHi
RefLo

AGND

Analog

Mux Bus

RefIn

AGNDIn

ACI1[1:0]

ASD11

ASC21

Analog Reference

Reference

Generators

P0[6]

P0[4]

P0[2]
P0[0]

P2[6]

P2[4]

P2[2]
P2[0]

AGNDIn
RefIn
Bandgap

Document Number: 001-13108 Rev. ** Page 4 of 33

CY8CLED04

The Analog Multiplexer System

The Analog Mux Bus can connect to every GPIO pin in ports 0-5.
Pins can be connected to the bus individually or in any combi­nation. The bus also connects to the analog system for analysis
with comparators and analog-t o-digit al converters. It ca n be split
into two sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.

Switch control logic enables selected pins to precharge continu­ously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:

■ Track pad, finger sensing.

■ Chip-wide mux that allows analog input from up to 48 IO pins.

■ Crosspoint connection between any IO pin combinatio ns.

When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under http://www.cypress.com >>
DESIGN RESOURCES >> Application Notes. In general, and
unless otherwise noted in the relevant Application Notes, the
minimum signal-to-noise ratio (SNR) for CapSense applications
is 5:1.

Additional System Resources

System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief state­ments describing the merits of each resource follow.

■ Full-Speed USB (12 Mbps) with 5 configurable endpoints and

256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (-10°C to +85°C).

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.

■ Two multiply accumulates (MACs) provide fast 8-bit multipliers

with 32-bit accumulate, to assist in both general math as well
as digital filters.

■ Decimator provides a custom hardware filter for digital signal

processing apps. including creation of Delta Sigma ADCs.

■ The I2C module provides 100 and 400 kHz communication over

two wires. Slave, master, multi-master are supported.

■ Low Voltage Detection (LVD) interrupts signal the application

of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

■ Versatile analog multiplexer system.

EZ-Color Device Characteristics

Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table

Table 1. EZ-Color Device Characteristics

PSoC Part

Number

CY8CLED04 4 56 1 4 48 2 2 6 1K 16K Yes

CY8CLED08 8 44 2 8 12 4 4 12 256 Bytes 16K No
CY8CLED16 16

LED

Channels

IO

Digital

64 4 16 12 4 4 12 2K 32K No

Rows

Digital

Digital

Blocks

Analog

Inputs

Analog

Analog

Outputs

Columns

Analog

Blocks

Size

SRAM

Flash

Size

CapSense

Document Number: 001-13108 Rev. ** Page 5 of 33

CY8CLED04

Getting Started

The quickest path to understanding the EZ-Color silicon is by
reading this data sheet and using the PSoC Express Integrated
Development Environment (IDE). This data sheet is an overview
of the EZ-Color integrated circuit and presents specific pin,
register, and electrical specifications.

For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest device data sheets on the web
at http://www.cypress.com/ez-color.

Development Kits

Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at

http://www.cypress.com, click the Online Store shopping cart

icon at the bottom of the web page, and click EZ-Color to view
a current list of available items.

Technical Training Modules

Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced analog and CapSense. Go to

http://www.cypress.com/techtrain.

Development Tools

PSoC Express is a high-level design tool for creating embedded
systems using Cypress's PSoC mixed-signal technology. With
PSoC Express you create a complete embedded solution
including all necessary on-chip peripherals, block configuratio n,
interrupt handling and application software without writing a
single line of assembly or C code.

PSoC Express solves design problems the way you think about
the system:

■ Select input and output devices based upon system require-

ments.

■ Add a communications interface and define its interface to

system (using registers).

■ Define when and how an output device changes state based

upon any and all other system devices.

Based upon the design, automatically select one or more PSoC Mixed-Signal Controllers that match system requirements.

Figure 3. PSoC Express

Consultants

Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. T o contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.

Technical Support

PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.

Application Notes

A long list of application notes will assist you in every aspect of
your design effort. To view the PSoC application notes, go to the

http://www.cypress.com web site and select Application Notes

under the Design Resources list located in the center of the web
page. Application notes are listed by date as default.

PSoC Express Subsystems

Express Editor

The Express Editor allows you to create designs visually by
dragging and dropping inputs, outputs, communication inter­faces, and other design elements, and then describing the logic
that controls them.

Project Manager

The Project Manager allows you to work with your applications
and projects in PSoC Express. A PSoC Express application is a
top level container for projects and their associated files. Each
project contains a design that uses a single PSoC device. An
application can contain multiple projects so if you are creating an
application that uses multiple PSoC devices you can keep all of
the projects together in a single application.

Most of the files associated with a project are automatically
generated by PSoC Express during the build process, but you
can make changes directly to the custom.c and custom.h files

Document Number: 001-13108 Rev. ** Page 6 of 33

CY8CLED04

and also add your own custom code to the project in the Project
Manager.

Application Editor

The Application Editor allows you to edit custom.c and custom.h
as well as any C or assembly language source code that you add
to your project. With PSoC Express you can create application
software without writing a single line of assembly or C code, but
you have a full featured application editor at your finger tips if you
want it.

Build Manager

The Build Manager gives you the ability to build the application
software, assign pins, and generate the data sheet, schematic,
and BOM for your project.

Board Monitor

The Board Monitor is a debugging tool designed to be used
while attached to a prototype board through a communication
interface that allows you to monitor changes in the various
design elements in real time.

2

The default communication for the board monitor is I

2

the CY3240-I2USB I

C to USB Bridge Debugging/Communica-

C. It uses

tion Kit.

Tuners

A Tuner is a visual interface for the Board Monitor that allows you
to view the performance of the HB LED drivers on your test board
while your program is running, and manually override values and
see the results.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.

The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and will operate
with all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.

Document Conventions

Units of Measure

A units of measure table is located in the Electrical Specifications
section. Table6 on page 12 lists all the abbreviations used to
measure the PSoC devices.

Numeric Naming

Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.

Acronyms Used

The following table lists the acronyms that are used in this
document.

Table 2. Acronyms

Acronym Description

AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC® Programmable System-on-Chip™
PWM pulse width modulator
SC switched capacitor
SRAM static random access memory

Document Number: 001-13108 Rev. ** Page 7 of 33

CY8CLED04

Pin Information

68-Pin Part Pinout

This Section describes, lists, and illustrates the CY8CLED04 EZ-Color device pins and pinout configuration. The CY8CLED04 device
is available in the following package. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are
not capable of Digital IO.

Table 3. 68-Pin Part Pinout (QFN**)

Pin
No.

1 IO M P4[7]
2 IO M P4[5]
3 IO MP4[3]
4 IO MP4[1]
5 NC No connection.
6 NC No connection.
7 Power Vss Ground connection.
8 IO M P3[7]
9 IO M P3[5]

10 IO MP3[3]
11 IO MP3[1]
12 IO M P5[7]
13 IO M P5[5]
14 IO MP5[3]
15 IO MP5[1]
16 IO M P1[7] I2C Serial Clock (SCL).
17 IO M P1[5] I2C Serial Data (SDA).
18 IO M P1[3]
19 IO M P1[1] I2C Serial Clock (SCL) ISSP SCLK*.
20 Power Vss Ground connection.
21 USB D+
22 USB D­23 Power Vdd Supply voltage.
24 IO P7[7]
25 IO P7[6]
26 IO P7[5]
27 IO P7[4]
28 IO P7[3]
29 IO P7[2]

30 IO P7[1] Digital Analog
31 IO P7[0] 50 IO M P4[6]
32 IO M P1[0] I2C Serial Data (SDA), ISSP SDATA*. 51 IO I,M P2[0] Direct switched capacitor block input.
33 IO M P1[2] 52 IO I,M P2[2] Direct switched capacitor block input.
34 IO M P1[4] Optional External Clock Input (EXT-

35 IO M P1[6] 54 IO M P2[6] External Voltage Reference (VREF) input.
36 IO M P5[0] 55 IO I,M P0[0] Analog column mux input.
37 IO M P5[2] 56 IO I,M P0[2] Analog column mux input and column output.
38 IO M P5[4] 57 IO I,M P0[4] Analog column mux input and column output.
39 IO M P5[6] 58 IO I,M P0[6] Analog column mux input.
40 IO M P3[0] 59 Power Vdd Supply voltage.
41 IO M P3[2] 60 Power Vss Ground connection.
42 IO M P3[4] 61 IO I,M P0[7] Analog column mux input, integration input #1
43 IO M P3[6] 62 IO IO,M P0[5] Analog column mux input and column output, integra-

44
45
46

Type

Digital Analog

Name Description

CLK).

NC No connection. 63 IO IO,M P0[3] Analog column mux input and column output.
NC No connection. 64 IO I,M P0[1] Analog column mux input.

Input XRES Active high pin reset with internal pull

down.

68-Pin Device

P2[1], M, AI

P2[3], M, AI

P2[5], M

P2[7], M

P0[1], M, AI

P0[3], M, AIO

P0[5], M, AIO

P0[7], M, AI

Vss

Vdd

P0[6], M, AI

P0[4], M, AI

P0[2], M, AI

P0[0], M, AI

P2[6], M, Ext. VREF

P2[4], M, Ext. AGND

P2[2], M, AI

676665646362616059585756555453

68

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

1819202122232425262728293031323334

Vss

M, P1[3]

I2C SCL, M, P1[1]

D +

D -

Vdd

QFN

(Top View)

P7[7]

P7[5]

P7[6]

P7[4]

P7[3]

P7[2]

P7[1]

Name Description

I2C SCL, M, P1 [7 ]
I2C SDA, M, P1 [5 ]

Pin
No.

M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]

M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]

Type

NC
NC

Vss

53 IO M P2[4] External Analog Ground (AGND) input.

tion input #2.

65 IO M P2[7]

52

P7[0]

M, P1[2]

M, P1[4]

I2C SDA, M, P1[0]

51
50

49
48
47
46

45
44

43
42
41
40
39
38
37
36
35

P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M

Document Number: 001-13108 Rev. ** Page 8 of 33

CY8CLED04

Table 3. 68-Pin Part Pinout (QFN**) (continued)

47 IO M P4[0] 66 IO M P2[5]
48 IO M P4[2] 67 IO I,M P2[3] Direct switched capacitor block input.
49

IO M P4[4] 68 IO I,M P2[1] Direct switched capacitor block input.

LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR.

** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.

Register Conventions

This section lists the registers of the CY8CLED04 EZ-Color device.

Abbreviations Used

The register conventions specific to this section are listed in the following table.

Convention Description

R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific

Register Mapping Tables

The device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks.
The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are Reserved and should not be accessed.

Table 4. Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access

PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2

Blank fields are Reserved an d should not be accessed. # Access is bit specific.

00 RW PMA0_DR 40 RW
01 RW PMA1_DR 41 RW
02 RW PMA2_DR 42 RW
03 RW PMA3_DR 43 RW
04 RW PMA4_DR 44 RW
05 RW PMA5_DR 45 RW
06 RW PMA6_DR 46 RW
07 RW PMA7_DR 47 RW
08 RW USB_SOF0 48 R 88 C8
09 RW USB_SOF1 49 R 89 C9
0A RW USB_CR0 4A RW 8A CA
0B RW USBIO_CR0 4B # 8B CB
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18 EP0_DR0 58 RW 98
19 EP0_DR1 59 RW 99

RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

USBIO_CR1 4C RW 8C CC

4D 8D CD
EP1_CNT1 4E # 8E CE
EP1_CNT 4F RW 8F CF
EP2_CNT1 50 #
EP2_CNT 51 RW
EP3_CNT1 52 #
EP3_CNT 53 RW
EP4_CNT1 54 #
EP4_CNT 55 RW
EP0_CR 56 #
EP0_CNT 57 #

ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3

ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3

80
81
82
83
84
85
86
87

90
91
92
93
94
95
96
97

RW
RW
RW
RW
RW
RW
RW
RW

RW CUR_PP
RW STK_PP
RW
RW IDX_PP
RW MVR_PP
RW MVW_PP
RW I2C_CFG
RW I2C_SCR

I2C_DR
I2C_MSCR

C0
C1
C2
C3
C4
C5
C6
C7

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

RW
RW

RW
RW
RW
RW
#
RW
#

Document Number: 001-13108 Rev. ** Page 9 of 33

CY8CLED04

Table 4. Register Map Bank 0 Table: User Space (continued)

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access

PRT7DR
PRT7IE
PRT7GS
PRT7DM2
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0

Blank fields are Reserved an d should not be accessed. # Access is bit specific.

1A EP0_DR2 5A RW 9A
1B EP0_DR3 5B RW 9B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD
3E 7E BE
3F 7F BF

RW
RW
RW
RW
# AMX_IN
W AMUXCFG
RW
# ARF_CR
# CMP_CR0
W ASY_CR
RW CMP_CR1
#
#
W
RW
#
# TMP_DR0
W TMP_DR1
RW TMP_DR2
# TMP_DR3

EP0_DR4 5C RW 9C
EP0_DR5 5D RW 9D
EP0_DR6 5E RW 9E
EP0_DR7 5F RW 9F

ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2

60

61

62 A2

63

64

65

66

67 A7

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

RW
RW

RW
#
#
RW

MUL1_X
MUL1_Y
MUL1_DH

MUL1_DL
RW ACC1_DR1
RW ACC1_DR0
RW ACC1_DR3
RW ACC1_DR2
RW RDI0RI
RW RDI0SYN
RW RDI0IS
RW RDI0LT0
RW RDI0LT1
RW RDI0RO0
RW RDI0RO1
RW

A0
A1

A3
A4
A5
A6

A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7

W MUL0_X
W MUL0_Y
R MUL0_DH
R MUL0_DL
RW ACC0_DR1
RW ACC0_DR0
RW ACC0_DR3
RW ACC0_DR2
RW
RW
RW
RW
RW
RW
RW

INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1

CPU_F

DAC_D
CPU_SCR1
CPU_SCR0

DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7

FD
FE
FF

RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW

RL

RW
#
#

Table 5. Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access

PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
Blank fields are Reserved an d should not be accessed. # Access is bit specific.

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14

RW PMA0_WA
RW PMA1_WA
RW PMA2_WA
RW PMA3_WA
RW PMA4_WA
RW PMA5_WA
RW PMA6_WA
RW PMA7_WA
RW
RW
RW
RW
RW
RW
RW
RW
RW PMA0_RA
RW PMA1_RA
RW PMA2_RA
RW PMA3_RA
RW PMA4_RA

Document Number: 001-13108 Rev. ** Page 10 of 33

40
41
42
43
44
45
46
47
48 88 C8
49 89 C9
4A 8A CA
4B 8B CB
4C 8C CC
4D 8D CD
4E 8E CE
4F 8F CF
50
51
52
53
54

RW
RW ASC10CR1
RW ASC10CR2
RW ASC10CR3
RW ASD11CR0
RW ASD11CR1
RW
RW

RW
RW ASD20CR1
RW ASD20CR2
RW ASD20CR3
RW ASC21CR0

ASC10CR0

ASD11CR2
ASD11CR3

80
81
82
83
84
85
86
87

90
91
92
93
94

RW
RW
RW
RW
RW
RW
RW
RW

RW GDI_E_IN
RW GDI_O_OU
RW GDI_E_OU
RW

USBIO_CR2 C0 RW
USB_CR1 C1 #

EP1_CR0 C4 #
EP2_CR0 C5 #
EP3_CR0 C6 #
EP4_CR0 C7 #

GDI_O_IN

D0
D1
D2
D3
D4

RW
RW
RW
RW