Datasheet CY8CLED04 Datasheet (CYPRESS)

Features

CY8CLED04

EZ-Color™ HB LED Controller

■ HB LED Controller

❐ Configurable Dimmers Support up to 4

Independent LED Channels

❐ 8-32 Bits of Resolution per Channel
❐ Dynamic Reconfiguration Enables LED

Controller plus other Features; CapSense, Battery Charging,
Motor Control…

■ Visual Embedded Design, PSoC Express

❐ LED Based Express Drivers

• Binning Compensation

• Temperature Feedback

•DMX512

■ PrISM Modulation Technology
❐ Reduces Radiated EMI

❐ Reduces Low Frequency Blinking

■ Advanced Peripherals (PSoC Blocks)
❐ 4 Digital PSoC Blocks Provide:

• 8 to 32-Bit Timers, Counters, and PWMs

• Up to 2 Full-Duplex UART

• Multiple SPI™ Masters or Slaves

• Connectable to all GPIO Pins

❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs

• Up to 9-Bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

❐ Complex Peripherals by Combining Blocks
❐ Capacitive Sensing Application Capability

■ Complete Development Tools

❐ Free Development Software

• PSoC Designer™

• PSoC Express™

❐ Full-Featured, In-Circuit Emulator and

Programmer

❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KBytes Trace Memory

■ Programmable Pin Configurations

❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive

Modes on all GPIO

❐ Up to 12 Analog Inputs on GPIO
❐ Four 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO

■ Flexible On-Chip Memory

❐ 16K Flash Program Storage 50,000 Erase/Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash

■ Full-Speed USB (12 Mbps)

❐ Four Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-13108 Rev. ** Revised June 13, 2007

Overview

Block Diagram

CY8CLED04

Port 7

s

u
B

m

e

t

s

y

Global Digital Interconnect

S

SRAM

1K

Interrupt

Controller

DIGITAL SYSTEM

Digital

Block
Array

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

Global Analog Interconnect

PSoC CORE

SROM Flash 16K

Sleep and

CPU Core (M8C)

Watchdog

Clock Sources

(Includes IMO and ILO)

ANALOG SYSTEM

Analog

Ref.

Analog

Block
Array

Analog
Drivers

Digital

Clocks

2

MACs

Decimator

Type 2

POR and LVD

I2C USB

System Resets

Internal
Voltage

Ref.

Analog

Input

Muxing

SYSTEM RESOURCES

Document Number: 001-13108 Rev. ** Page 2 of 33

CY8CLED04

EZ-Color Functional Overview

Cypress' EZ-Color family of devices offers the ideal control
solution for High Brightness LED applications requiring intel­ligent dimming control. EZ-Color devices combine the power and
flexibility of PSoC (Programmable System-on-Chip™); with
Cypress' PrISM (precise illumination signal modulation)
modulation technology providing lighting designers a fully
customizable and integrated lighting solution platform.

The EZ-Color family support up to 16 independent LED channels
with up to 32 bits of resolution per channel, enabling lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Express software, with lighting specific drivers,
can significantly cut development time and simp lify implemen­tation of fixed color points through temperature and LED binning
compensation. EZ-Color's virtually limitless analog and digital
customization allow for simple integration of features in addition
to intelligent lighting, such as CapSense, Battery Charging,
Image Stabilization, and Motor Control during the development
process. These features, along with Cypress' best-in-class
quality and design support, make EZ-Color the ideal choice for
intelligent HB LED control applications.

Target Applications

■ LCD Backlight

■ Large Signs

■ General Lighting

■ Architectural Lighting

■ Camera/Cell Phone Flash

■ Flashlights

The PSoC Core

The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory , clocks, and configurable
GPIO (General Purpose IO).

The M8C CPU core is a powerful processor with speeds up to 68
MHz, providing a four MIPS 8-bit Harvard architecture micropro­cessor. The CPU utilizes an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).

Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash utilizes four protection levels on
blocks of 64 bytes, allowing customized software IP protection.

The EZ-Color family incorporates flexible internal clock gener­ators, including a 24 MHz IMO (internal main oscillator) accurate
to 8% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. The clocks, together with programmable
clock dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the EZ-Color
device. In USB systems, the IMO will self-tune to ± 0.25%
accuracy for USB communication.

EZ-Color GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.

The Digital System

The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.

Digital peripheral configurations include those listed below.

■ PrISM (8 to 32 bit)

■ Full-Speed USB (12 Mbps)

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 24 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity

■ SPI master and slave

■ I2C slave and multi-master

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA

■ Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device Charac­teristics.

Document Number: 001-13108 Rev. ** Page 3 of 33

CY8CLED04

Figure 1. Digital System Block Diagram

Port 2

Port 1

To Analog

System

4

4

GOE[7:0]

GOO[7:0]

Configuration

Port 0

Row Output

8

88

Port 7

D

Port 5

i

g

i

t

a

l

C

l

o

c

k

s

F

r

o

m

C

o

r

e

Port 3

Port 4

To System Bus

DIGITAL SYSTEM

Digital PSoC Block Array

8

DBB00 DBB01 DCB02 DCB03

Row Input

Configuration

GIE[7:0]

GIO[7:0]

Row 0

Global Digital

Interconnect

The Analog System

The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.

■ Analog-to-digital converters (up to 2, with 6- to 14-bit resolution,

selectable as Incremental, Delta Sigma, and SAR)

■ Filters (2 and 4 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 2, with selectable gain to 48x)

■ Instrumentation amplifiers (1 with selectable gain to 93x)

■ Comparators (up to 2, with 16 selectable thresholds)

■ DACs (up to 2, with 6- to 9-bit resolution)

■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)

■ High current output drivers (two with 30 mA drive as a PSoC

Core Resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

■ Peak Detectors

■ Many other topologies possible

Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.

Figure 2. Analog System Block Diagram

All IO

(Except Port 7)

P0[7]

P0[5]

P0[3]
P0[1]

P2[3]

P2[1]

Interface to

Digital System

ACI0[1:0]

Array Input

Configura tio n

Block
Array

M8C Interface (Address Bus, Data Bus, Etc.)

ACB00 ACB01

ASC10

ASD20

RefHi
RefLo

AGND

Analog

Mux Bus

RefIn

AGNDIn

ACI1[1:0]

ASD11

ASC21

Analog Reference

Reference

Generators

P0[6]

P0[4]

P0[2]
P0[0]

P2[6]

P2[4]

P2[2]
P2[0]

AGNDIn
RefIn
Bandgap

Document Number: 001-13108 Rev. ** Page 4 of 33

CY8CLED04

The Analog Multiplexer System

The Analog Mux Bus can connect to every GPIO pin in ports 0-5.
Pins can be connected to the bus individually or in any combi­nation. The bus also connects to the analog system for analysis
with comparators and analog-t o-digit al converters. It ca n be split
into two sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.

Switch control logic enables selected pins to precharge continu­ously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:

■ Track pad, finger sensing.

■ Chip-wide mux that allows analog input from up to 48 IO pins.

■ Crosspoint connection between any IO pin combinatio ns.

When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under http://www.cypress.com >>
DESIGN RESOURCES >> Application Notes. In general, and
unless otherwise noted in the relevant Application Notes, the
minimum signal-to-noise ratio (SNR) for CapSense applications
is 5:1.

Additional System Resources

System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief state­ments describing the merits of each resource follow.

■ Full-Speed USB (12 Mbps) with 5 configurable endpoints and

256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (-10°C to +85°C).

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.

■ Two multiply accumulates (MACs) provide fast 8-bit multipliers

with 32-bit accumulate, to assist in both general math as well
as digital filters.

■ Decimator provides a custom hardware filter for digital signal

processing apps. including creation of Delta Sigma ADCs.

■ The I2C module provides 100 and 400 kHz communication over

two wires. Slave, master, multi-master are supported.

■ Low Voltage Detection (LVD) interrupts signal the application

of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

■ Versatile analog multiplexer system.

EZ-Color Device Characteristics

Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table

Table 1. EZ-Color Device Characteristics

PSoC Part

Number

CY8CLED04 4 56 1 4 48 2 2 6 1K 16K Yes

CY8CLED08 8 44 2 8 12 4 4 12 256 Bytes 16K No
CY8CLED16 16

LED

Channels

IO

Digital

64 4 16 12 4 4 12 2K 32K No

Rows

Digital

Digital

Blocks

Analog

Inputs

Analog

Analog

Outputs

Columns

Analog

Blocks

Size

SRAM

Flash

Size

CapSense

Document Number: 001-13108 Rev. ** Page 5 of 33

CY8CLED04

Getting Started

The quickest path to understanding the EZ-Color silicon is by
reading this data sheet and using the PSoC Express Integrated
Development Environment (IDE). This data sheet is an overview
of the EZ-Color integrated circuit and presents specific pin,
register, and electrical specifications.

For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest device data sheets on the web
at http://www.cypress.com/ez-color.

Development Kits

Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at

http://www.cypress.com, click the Online Store shopping cart

icon at the bottom of the web page, and click EZ-Color to view
a current list of available items.

Technical Training Modules

Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced analog and CapSense. Go to

http://www.cypress.com/techtrain.

Development Tools

PSoC Express is a high-level design tool for creating embedded
systems using Cypress's PSoC mixed-signal technology. With
PSoC Express you create a complete embedded solution
including all necessary on-chip peripherals, block configuratio n,
interrupt handling and application software without writing a
single line of assembly or C code.

PSoC Express solves design problems the way you think about
the system:

■ Select input and output devices based upon system require-

ments.

■ Add a communications interface and define its interface to

system (using registers).

■ Define when and how an output device changes state based

upon any and all other system devices.

Based upon the design, automatically select one or more PSoC Mixed-Signal Controllers that match system requirements.

Figure 3. PSoC Express

Consultants

Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. T o contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.

Technical Support

PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.

Application Notes

A long list of application notes will assist you in every aspect of
your design effort. To view the PSoC application notes, go to the

http://www.cypress.com web site and select Application Notes

under the Design Resources list located in the center of the web
page. Application notes are listed by date as default.

PSoC Express Subsystems

Express Editor

The Express Editor allows you to create designs visually by
dragging and dropping inputs, outputs, communication inter­faces, and other design elements, and then describing the logic
that controls them.

Project Manager

The Project Manager allows you to work with your applications
and projects in PSoC Express. A PSoC Express application is a
top level container for projects and their associated files. Each
project contains a design that uses a single PSoC device. An
application can contain multiple projects so if you are creating an
application that uses multiple PSoC devices you can keep all of
the projects together in a single application.

Most of the files associated with a project are automatically
generated by PSoC Express during the build process, but you
can make changes directly to the custom.c and custom.h files

Document Number: 001-13108 Rev. ** Page 6 of 33

CY8CLED04

and also add your own custom code to the project in the Project
Manager.

Application Editor

The Application Editor allows you to edit custom.c and custom.h
as well as any C or assembly language source code that you add
to your project. With PSoC Express you can create application
software without writing a single line of assembly or C code, but
you have a full featured application editor at your finger tips if you
want it.

Build Manager

The Build Manager gives you the ability to build the application
software, assign pins, and generate the data sheet, schematic,
and BOM for your project.

Board Monitor

The Board Monitor is a debugging tool designed to be used
while attached to a prototype board through a communication
interface that allows you to monitor changes in the various
design elements in real time.

2

The default communication for the board monitor is I

2

the CY3240-I2USB I

C to USB Bridge Debugging/Communica-

C. It uses

tion Kit.

Tuners

A Tuner is a visual interface for the Board Monitor that allows you
to view the performance of the HB LED drivers on your test board
while your program is running, and manually override values and
see the results.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.

The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and will operate
with all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.

Document Conventions

Units of Measure

A units of measure table is located in the Electrical Specifications
section. Table6 on page 12 lists all the abbreviations used to
measure the PSoC devices.

Numeric Naming

Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.

Acronyms Used

The following table lists the acronyms that are used in this
document.

Table 2. Acronyms

Acronym Description

AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC® Programmable System-on-Chip™
PWM pulse width modulator
SC switched capacitor
SRAM static random access memory

Document Number: 001-13108 Rev. ** Page 7 of 33

CY8CLED04

Pin Information

68-Pin Part Pinout

This Section describes, lists, and illustrates the CY8CLED04 EZ-Color device pins and pinout configuration. The CY8CLED04 device
is available in the following package. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are
not capable of Digital IO.

Table 3. 68-Pin Part Pinout (QFN**)

Pin
No.

1 IO M P4[7]
2 IO M P4[5]
3 IO MP4[3]
4 IO MP4[1]
5 NC No connection.
6 NC No connection.
7 Power Vss Ground connection.
8 IO M P3[7]
9 IO M P3[5]

10 IO MP3[3]
11 IO MP3[1]
12 IO M P5[7]
13 IO M P5[5]
14 IO MP5[3]
15 IO MP5[1]
16 IO M P1[7] I2C Serial Clock (SCL).
17 IO M P1[5] I2C Serial Data (SDA).
18 IO M P1[3]
19 IO M P1[1] I2C Serial Clock (SCL) ISSP SCLK*.
20 Power Vss Ground connection.
21 USB D+
22 USB D­23 Power Vdd Supply voltage.
24 IO P7[7]
25 IO P7[6]
26 IO P7[5]
27 IO P7[4]
28 IO P7[3]
29 IO P7[2]

30 IO P7[1] Digital Analog
31 IO P7[0] 50 IO M P4[6]
32 IO M P1[0] I2C Serial Data (SDA), ISSP SDATA*. 51 IO I,M P2[0] Direct switched capacitor block input.
33 IO M P1[2] 52 IO I,M P2[2] Direct switched capacitor block input.
34 IO M P1[4] Optional External Clock Input (EXT-

35 IO M P1[6] 54 IO M P2[6] External Voltage Reference (VREF) input.
36 IO M P5[0] 55 IO I,M P0[0] Analog column mux input.
37 IO M P5[2] 56 IO I,M P0[2] Analog column mux input and column output.
38 IO M P5[4] 57 IO I,M P0[4] Analog column mux input and column output.
39 IO M P5[6] 58 IO I,M P0[6] Analog column mux input.
40 IO M P3[0] 59 Power Vdd Supply voltage.
41 IO M P3[2] 60 Power Vss Ground connection.
42 IO M P3[4] 61 IO I,M P0[7] Analog column mux input, integration input #1
43 IO M P3[6] 62 IO IO,M P0[5] Analog column mux input and column output, integra-

44
45
46

Type

Digital Analog

Name Description

CLK).

NC No connection. 63 IO IO,M P0[3] Analog column mux input and column output.
NC No connection. 64 IO I,M P0[1] Analog column mux input.

Input XRES Active high pin reset with internal pull

down.

68-Pin Device

P2[1], M, AI

P2[3], M, AI

P2[5], M

P2[7], M

P0[1], M, AI

P0[3], M, AIO

P0[5], M, AIO

P0[7], M, AI

Vss

Vdd

P0[6], M, AI

P0[4], M, AI

P0[2], M, AI

P0[0], M, AI

P2[6], M, Ext. VREF

P2[4], M, Ext. AGND

P2[2], M, AI

676665646362616059585756555453

68

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

1819202122232425262728293031323334

Vss

M, P1[3]

I2C SCL, M, P1[1]

D +

D -

Vdd

QFN

(Top View)

P7[7]

P7[5]

P7[6]

P7[4]

P7[3]

P7[2]

P7[1]

Name Description

I2C SCL, M, P1 [7 ]
I2C SDA, M, P1 [5 ]

Pin
No.

M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]

M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]

Type

NC
NC

Vss

53 IO M P2[4] External Analog Ground (AGND) input.

tion input #2.

65 IO M P2[7]

52

P7[0]

M, P1[2]

M, P1[4]

I2C SDA, M, P1[0]

51
50

49
48
47
46

45
44

43
42
41
40
39
38
37
36
35

P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M

Document Number: 001-13108 Rev. ** Page 8 of 33

CY8CLED04

Table 3. 68-Pin Part Pinout (QFN**) (continued)

47 IO M P4[0] 66 IO M P2[5]
48 IO M P4[2] 67 IO I,M P2[3] Direct switched capacitor block input.
49

IO M P4[4] 68 IO I,M P2[1] Direct switched capacitor block input.

LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR.

** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.

Register Conventions

This section lists the registers of the CY8CLED04 EZ-Color device.

Abbreviations Used

The register conventions specific to this section are listed in the following table.

Convention Description

R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific

Register Mapping Tables

The device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks.
The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are Reserved and should not be accessed.

Table 4. Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access

PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2

Blank fields are Reserved an d should not be accessed. # Access is bit specific.

00 RW PMA0_DR 40 RW
01 RW PMA1_DR 41 RW
02 RW PMA2_DR 42 RW
03 RW PMA3_DR 43 RW
04 RW PMA4_DR 44 RW
05 RW PMA5_DR 45 RW
06 RW PMA6_DR 46 RW
07 RW PMA7_DR 47 RW
08 RW USB_SOF0 48 R 88 C8
09 RW USB_SOF1 49 R 89 C9
0A RW USB_CR0 4A RW 8A CA
0B RW USBIO_CR0 4B # 8B CB
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18 EP0_DR0 58 RW 98
19 EP0_DR1 59 RW 99

RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

USBIO_CR1 4C RW 8C CC

4D 8D CD
EP1_CNT1 4E # 8E CE
EP1_CNT 4F RW 8F CF
EP2_CNT1 50 #
EP2_CNT 51 RW
EP3_CNT1 52 #
EP3_CNT 53 RW
EP4_CNT1 54 #
EP4_CNT 55 RW
EP0_CR 56 #
EP0_CNT 57 #

ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3

ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3

80
81
82
83
84
85
86
87

90
91
92
93
94
95
96
97

RW
RW
RW
RW
RW
RW
RW
RW

RW CUR_PP
RW STK_PP
RW
RW IDX_PP
RW MVR_PP
RW MVW_PP
RW I2C_CFG
RW I2C_SCR

I2C_DR
I2C_MSCR

C0
C1
C2
C3
C4
C5
C6
C7

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

RW
RW

RW
RW
RW
RW
#
RW
#

Document Number: 001-13108 Rev. ** Page 9 of 33

CY8CLED04

Table 4. Register Map Bank 0 Table: User Space (continued)

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access

PRT7DR
PRT7IE
PRT7GS
PRT7DM2
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0

Blank fields are Reserved an d should not be accessed. # Access is bit specific.

1A EP0_DR2 5A RW 9A
1B EP0_DR3 5B RW 9B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD
3E 7E BE
3F 7F BF

RW
RW
RW
RW
# AMX_IN
W AMUXCFG
RW
# ARF_CR
# CMP_CR0
W ASY_CR
RW CMP_CR1
#
#
W
RW
#
# TMP_DR0
W TMP_DR1
RW TMP_DR2
# TMP_DR3

EP0_DR4 5C RW 9C
EP0_DR5 5D RW 9D
EP0_DR6 5E RW 9E
EP0_DR7 5F RW 9F

ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2

60

61

62 A2

63

64

65

66

67 A7

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

RW
RW

RW
#
#
RW

MUL1_X
MUL1_Y
MUL1_DH

MUL1_DL
RW ACC1_DR1
RW ACC1_DR0
RW ACC1_DR3
RW ACC1_DR2
RW RDI0RI
RW RDI0SYN
RW RDI0IS
RW RDI0LT0
RW RDI0LT1
RW RDI0RO0
RW RDI0RO1
RW

A0
A1

A3
A4
A5
A6

A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7

W MUL0_X
W MUL0_Y
R MUL0_DH
R MUL0_DL
RW ACC0_DR1
RW ACC0_DR0
RW ACC0_DR3
RW ACC0_DR2
RW
RW
RW
RW
RW
RW
RW

INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1

CPU_F

DAC_D
CPU_SCR1
CPU_SCR0

DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7

FD
FE
FF

RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW

RL

RW
#
#

Table 5. Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access

PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
Blank fields are Reserved an d should not be accessed. # Access is bit specific.

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14

RW PMA0_WA
RW PMA1_WA
RW PMA2_WA
RW PMA3_WA
RW PMA4_WA
RW PMA5_WA
RW PMA6_WA
RW PMA7_WA
RW
RW
RW
RW
RW
RW
RW
RW
RW PMA0_RA
RW PMA1_RA
RW PMA2_RA
RW PMA3_RA
RW PMA4_RA

Document Number: 001-13108 Rev. ** Page 10 of 33

40
41
42
43
44
45
46
47
48 88 C8
49 89 C9
4A 8A CA
4B 8B CB
4C 8C CC
4D 8D CD
4E 8E CE
4F 8F CF
50
51
52
53
54

RW
RW ASC10CR1
RW ASC10CR2
RW ASC10CR3
RW ASD11CR0
RW ASD11CR1
RW
RW

RW
RW ASD20CR1
RW ASD20CR2
RW ASD20CR3
RW ASC21CR0

ASC10CR0

ASD11CR2
ASD11CR3

80
81
82
83
84
85
86
87

90
91
92
93
94

RW
RW
RW
RW
RW
RW
RW
RW

RW GDI_E_IN
RW GDI_O_OU
RW GDI_E_OU
RW

USBIO_CR2 C0 RW
USB_CR1 C1 #

EP1_CR0 C4 #
EP2_CR0 C5 #
EP3_CR0 C6 #
EP4_CR0 C7 #

GDI_O_IN

D0
D1
D2
D3
D4

RW
RW
RW
RW

CY8CLED04

Table 5. Register Map Bank 1 Table: Configuration Space (continued)

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access

PRT5DM1
PRT5IC0
PRT5IC1

PRT7DM0
PRT7DM1
PRT7IC0
PRT7IC1
DBB00FN
DBB00IN
DBB00OU

DBB01FN
DBB01IN
DBB01OU

DCB02FN
DCB02IN
DCB02OU

DCB03FN
DCB03IN
DCB03OU

Blank fields are Reserved an d should not be accessed. # Access is bit specific.

15
16
17
18 58 98
19 59 99
1A 5A 9A
1B 5B 9B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B 6B AB
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D
3E
3F 7F BF CPU_SCR0 FF #

RW PMA5_RA
RW PMA6_RA
RW

RW
RW
RW
RW
RW CLK_CR0
RW CLK_CR1
RW

RW CMP_GO_EN
RW CMP_GO_EN1
RW AMD_CR1

RW
RW
RW

RW TMP_DR0
RW TMP_DR1
RW TMP_DR2

PMA7_RA

ABF_CR0
AMD_CR0

ALT_CR0

TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2

55
56
57

5C 9C DC
5D 9D
5E 9E
5F 9F
60
61
62
63
64
65
66
67
68 A8
69 A9
6A AA

6C
6D
6E
6F
70
71
72
73
74
75
76
77

7D BD
7E BE

RW
RW ASC21CR2
RW

RW
RW
RW
RW
RW
RW
RW
RW

RW
RW
RW
RW
RW RDI0RI
RW RDI0SYN
RW RDI0IS
RW RDI0LT0
RW RDI0LT1
RW RDI0RO0
RW RDI0RO1
RW

ASC21CR1

ASC21CR3

95
96
97

A0
A1
A2
A3
A4
A5 E5
A6 E6
A7 E7

AC
AD
AE EE
AF EF
B0
B1
B2
B3
B4
B5
B6
B7

RW
RW
RW

MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3

OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP

IMO_TR
ILO_TR
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5

RW
RW
RW
RW
RW
RW
RW

CPU_F

DAC_CR
CPU_SCR1

D5
D6
D7
D8
D9
DA
DB

DD
DE
DF
E0
E1
E2
E3
E4

E8
E9
EA
EB
EC
ED

F0
F1
F2
F3
F4
F5
F6
F7

FD
FE

RW
RW
RW
RW

RW
RW
RW
RW
RW
RW
RW
R

W
W
RW
W
RW
RW

RL

RW
#

Document Number: 001-13108 Rev. ** Page 11 of 33

Electrical Specifications

CY8CLED04

This section presents the DC and AC electrical specifications of
the CY8CLED04 EZ-Color device. For the most up to date
electrical specifications, confirm that you have the most recent
data sheet by going to the web at

http://www.cypress.com/ez-color.

Specifications are valid for -40

o

C ≤ TA ≤ 85oC and TJ ≤ 100oC,
except where noted. Specifications for devices running at greater
than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.

Figure 4. Voltage versus CPU Frequency

5.25

4.75

Vdd Voltage

3.00

93 kHz 12 MHz 24 MHz

O

V

p

a

e

l

R

CPU Frequency

i

d

r

a

e

t

g

i

n

i

o

g

n

The following table lists the units of measure that are used in this
chapter.

Table 6. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

o

degree Celsius μW microwatts

C

dB decibels mA milli-ampere

fF femto farad ms milli-second

Hz hertz mV milli-volts

KB 1024 bytes nA nanoampere
Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts

kΩ kilohm Ω ohm

MHz megahertz pA picoampere

MΩ megaohm pF picofarad

μA microampere pp peak-to-peak
μF microfarad ppm parts per million

μH microhenry ps picosecond

μs microsecond sps samples per second
μV microvolts σ sigma: one standard

μVrms microvolts

root-mean-square

deviation

V volts

Document Number: 001-13108 Rev. ** Page 12 of 33

Absolute Maximum Ratings

Table 7. Absolute Maximum Ratings

Symbol Description Min Typ Max Units Notes

T

STG

T

A

Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V
V

IO

V

IO2

I

MIO

I

MAIO

ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.
LU Latch-up Current – – 200 mA

Storage Temperature -55 25 +100

Ambient Temperature with Power Applied -40 – +85

DC Input Voltage Vss - 0.5 – Vdd + 0.5 V
DC Voltage Applied to Tri-state Vss - 0.5 – Vdd + 0.5 V
Maximum Current into any Port Pin -25 – +50 mA
Maximum Current into any Port Pin Configured as Analog

Driver

-50 – +50 mA

o

C

o

C

Higher storage temperatures will reduce data
retention time. Recommended storage temper-

ature is +25
age temperatures above 65

reliability.

o

C ± 25oC. Extended duration stor-

Operating Temperature

Table 8. Operating Temperature

Symbol Description Min Typ Max Units Notes

T
T
T

A
AUSB
J

Ambient Temperature -40 – +85
Ambient Temperature using USB -10 – +85
Junction Temperature -40 – +100

o

C

o

C

o

C

The temperature rise from ambient to junction
is package specific. See “Thermal Impedance”
on page 30. The user must limit the power con­sumption to comply with this requirement.

CY8CLED04

o

C will degrade

DC Electrical Characteristics

DC Chip-Level Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only.

Table 9. DC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

Vdd Supply Voltage 3.0 – 5.25 V See DC POR and LVD specifications, Table 20

I

DD5

I

DD3

I

SB

I

SBH

a. Standby current includes all functions (POR , LVD, WDT, Sleep Time) needed for reliable system operation. This should be compa re d with de vices t hat hav e s imilar functions

enabled.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

A

on page 20.

Supply Current, IMO = 24 MHz (5V) – 14 27 mA

Supply Current, IMO = 24 MHz (3.3V) – 8 14 mA

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

a

WDT.

Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT at high temperature.

a

– 3 6.5 μA Conditions are with internal slow speed oscilla-

– 4 25 μA Conditions are with internal slow speed oscilla-

Conditions are Vdd = 5.0V , TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5

MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, ana­log power = off.

Conditions are Vdd = 3.3V , TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5

MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, ana­log power = off.

tor, Vdd = 3.3V , -40
power = off.

tor, Vdd = 3.3V, 55
power = off.

o

C ≤ TA ≤ 55 oC, analog

o

C < TA ≤ 85 oC, analog

Document Number: 001-13108 Rev. ** Page 13 of 33

CY8CLED04

DC General Purpose IO Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 10. DC GPIO Specifications

Symbol Description Min Typ Max Units Notes

R

PU

R

PD

V

OH

V

OL

V

IL

V

IH

V

H

I

IL

C

IN

C

OUT

Pull-Up Resistor 4 5.6 8 kΩ
Pull-Down Resistor 4 5.6 8 kΩ
High Output Level Vdd - 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total

Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total

Input Low Level – – 0.8 V Vdd = 3.0 to 5.25.
Input High Level 2.1 – V Vdd = 3.0 to 5.25.
Input Hysterisis – 60 – mV
Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA.
Capacitive Load on Pins as Input – 3.5 10 pF
Capacitive Load on Pins as Output – 3.5 10 pF

loads, 4 on even port pins (for example, P0[2],
P1[4]), 4 on odd port pins (for example, P0[3],
P1[5])). 80 mA maximum combined IOH bud­get.

loads, 4 on even port pins (for example, P0[2],
P1[4]), 4 on odd port pins (for example, P0[3],
P1[5])). 200 mA maximum combined IOL bud­get.

Package and pin dependent. Temp = 25oC.
Package and pin dependent. Temp = 25oC.

DC Full-Speed USB Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -10°C ≤ T
are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

A

Table 11. DC Full-Speed (12 Mbps) USB Specifications

Symbol Description Min Typ Max Units Notes

USB Interface

V
V
V
C
I
R
V
V
V
Z
V

DI
CM
SE
IN

IO

EXT
UOH
UOHI
UOL

O

CRS

Differential Input Sensitivity 0.2 – – V | (D+) - (D-) |
Differential Input Common Mode Range 0.8 – 2.5 V
Single Ended Receiver Threshold 0.8 – 2.0 V
Transceiver Capacitance – – 20 pF
High-Z State Data Line Leakage -10 – 10 μA0V < V
External USB Series Resistor 23 – 25 Ω In series with each USB pin.
Static Outpu t High, Driven 2.8 – 3.6 V 15 kΩ ± 5% to Ground. Internal pull-up enabled.
Static Output High, Idle 2.7 – 3.6 V 15 kΩ ± 5% to Ground. Internal pull-up enabled.
Static Output Low – – 0.3 V 15 kΩ ± 5% to Ground. Internal pull-up enabled.
USB Driver Output Impedance 28 – 44 Ω Including R
D+/D- Crossover Voltage 1.3 – 2.0 V

< 3.3V.

IN

EXT

Resistor.

Document Number: 001-13108 Rev. ** Page 14 of 33

CY8CLED04

DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.

Table 12. 5V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

V

OSOA

TCV
I

EBOA

C

INOA

V

CMOA

G

OLOA

V

OHIGHOA

V

OLOWOA

I

SOA

PSRR

OSOA

Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Average Input Offset Voltage Drift – 7.0 35.0

Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 μA.
Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF
Common Mode Voltage Range

Common Mode Voltage Range (high po we r or high
opamp bias)

Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
High Output Voltag e Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Low Output Voltage Swing (int ernal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio 65 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN

OA

–1.6
–
–

0.0 – Vdd

0.5 –

60
60
80

Vdd - 0.2
Vdd - 0.2
Vdd - 0.5

–
–
–

–
–
–
–
–
–

1.3

1.2

––dB

–
–
–

–
–
–

400
500
800
1200
2400
4600

10
8

7.5

Vdd - 0.5

–
–
–

0.2

0.2

0.5

800
900
1000
1600
3200
6400

mV
mV
mV

o

μV/

C

Package and pin dependent. Temp = 25

V The common-mode input voltage range is mea-

V
V
V

V
V
V

μA
μA
μA
μA
μA
μA

sured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.

≤ Vdd.

o

C.

Document Number: 001-13108 Rev. ** Page 15 of 33

Table 13. 3.3V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

V

OSOA

TCV
I

EBOA

C

INOA

V

CMOA

G

OLOA

V

OHIGHOA

V

OLOWOA

I

SOA

PSRR

OSOA

Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
Average Input Offset Voltage Drift – 7.0 35.0

Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 μA.
Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF
Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage range is mea-

Open Loop Gain
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
High Output Voltag e Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
Low Output Voltage Swing (int ernal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio 65 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN

OA

–
–

60
60
80

Vdd - 0.2
Vdd - 0.2
Vdd - 0.2

–
–
–

–
–
–
–
–
–

1.65

1.32

––dB

–
–
–

–
–
–

400
500
800
1200
2400
4600

10
8

–
–
–

0.2

0.2

0.2

800
900
1000
1600
3200
6400

mV
mV

μV/

V
V
V

V
V
V

μA
μA
μA
μA
μA
μA

o

C

Package and pin dependent. Temp = 25

sured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.

≤ Vdd.

CY8CLED04

o

C.

DC Low Power Comparator Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T
apply to 5V at 25°C and are for design guidance only.

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

A

Table 14. DC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

V

REFLPC

I

SLPC

V

OSLPC

Low power comparator (LPC) reference voltage range 0.2 – Vdd - 1 V
LPC supply current – 10 40 μA
LPC voltage offset – 2.5 30 mV

Document Number: 001-13108 Rev. ** Page 16 of 33

CY8CLED04

DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 15. 5V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

V

OSOB

TCV
V

CMOB

R

OUTOB

V

OHIGHOB

V

OLOWOB

I

SOB

PSRR

OSOB

Input Offset Voltage (Absolute Value) – 3 12 mV
Average Input Offset Voltage Drift – +6 – μV/°C
Common-Mode Input Volt age Range 0.5 – Vdd - 1.0 V
Output Resistance

Power = Low
Power = High
High Output Voltage Swing (Load = 32 ohms to Vdd/2)

Power = Low
Power = High

Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High

Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio 53 64 – dB (0.5 x Vdd - 1.3) ≤ V

OB

–
–

0.5 x Vdd
+ 1.1

0.5 x Vdd
+ 1.1

–
–

–
–

0.6

0.6

–
–

–
–

–
–

Ω

Ω

V
V

–
–

1.1

2.6

0.5 x Vdd

- 1.3

0.5 x Vdd

- 1.3

5.1

8.8

V
V

mA
mA

≤ (Vdd - 2.3).

OUT

Table 16. 3.3V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

V

OSOB

TCV
V

CMOB

R

OUTOB

V

OHIGHOB

V

OLOWOB

I

SOB

PSRR

OSOB

Input Offset Voltage (Absolute Value) – 3 12 mV
Average Input Offset Voltage Drift – +6 – μV/°C
Common-Mode Input Volt age Range 0.5 - Vdd - 1.0 V
Output Resistance

Power = Low
Power = High
High Output Voltage Swing (Load = 1K ohms to Vdd/2)
Power = Low
Power = High

Low Output Voltage Swing (Load = 1K ohms to Vdd/2)
Power = Low
Power = High

Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio 34 64 – dB (0.5 x Vdd - 1.0) ≤ V

OB

–
–

0.5 x Vdd
+ 1.0

0.5 x Vdd
+ 1.0

–
–

–

1
1

–
–

–
–

–
–

Ω

Ω

V
V

–
–

0.8

2.0

0.5 x Vdd

- 1.0

0.5 x Vdd

- 1.0

2.0

4.3

V
V

mA
mA

≤ (0.5 x Vdd + 0.9).

OUT

Document Number: 001-13108 Rev. ** Page 17 of 33

CY8CLED04

DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.

Table 17. 5V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.28 1.30 1.32 V
–

–

–

–

–

–
– RefHi = Vdd/2 + BandGap

– RefHi = 3 x BandGap 3 x BG -

– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG +

– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] +

– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] +

– RefHi = 3.2 x BandGap 3.2 x BG

– RefLo = Vdd/2 – BandGap

– RefLo = BandGap BG - 0.06 BG BG +

– RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG -

– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] -

– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] -

AGND = Vdd/2

AGND = 2 x BandGap

AGND = P2[4] (P2[4] = Vdd/2)

AGND = BandGap

AGND = 1.6 x BandGap

AGND Block to Block Variation (AGND = Vdd/2)

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

a

a

a

a

a

a

Vdd/2 -

0.04
2 x BG -

0.048
P2[4] -

0.011
BG -

0.009

1.6 x BG

- 0.022

-0.034 0.000 0.034 V

Vdd/2 +

BG - 0.10

0.06

P2[6] -

0.113

BG -

0.130

P2[6] -

0.133

- 0.112

Vdd/2 -

BG - 0.04

P2[6] -

0.084

BG -

0.056

P2[6] -

0.057

Vdd/2 -

0.01
2 x BG -

0.030
P2[4] P2[4] +

BG +

0.008

1.6 x BG

- 0.010

Vdd/2 +

0.007
2 x BG +

0.024

0.011
BG +

0.016

1.6 x BG
+ 0.018

Vdd/2 + BGVdd/2 +

BG +

0.10

3 x BG 3 x BG +

2 x BG +
P2[6] -

0.018
P2[4] +

BG -

0.016
P2[4] +

P2[6] -

0.016

3.2 x BG 3.2 x BG

Vdd/2 -

BG

0.024

2 x BG ­P2[6] +

0.025
P2[4] -

BG +

0.026
P2[4] -

P2[6] +

0.026

0.06
2 x BG +

P2[6] +

0.077
P2[4] +

BG +

0.098
P2[4] +

P2[6]+

0.100

+ 0.076

Vdd/2 -

BG +

+

0.04

0.06
2 x BG -

P2[6] +

0.134
P2[4] -

BG +

0.107
P2[4] -

P2[6] +

0.110

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Document Number: 001-13108 Rev. ** Page 18 of 33

Table 18. 3.3V DC Analog Reference Specifications

Symbol Description Min Typ Max Units Notes

BG Bandgap Voltage Reference 1.28 1.30 1.32 V
–

–
– AGND = P2[4] (P2[4] = Vdd/2) P2[4] -

–

–

–
– RefHi = Vdd/2 + BandGap

– RefHi = 3 x BandGap
– RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
– RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] +

– RefHi = 3.2 x BandGap
– RefLo = Vdd/2 - BandGap
– RefLo = BandGap
– RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
– RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4 ] -

AGND = Vdd/2

AGND = 2 x BandGap

AGND = BandGap

AGND = 1.6 x BandGap

AGND Column to Column Variation (AGND = Vdd/2)

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

a

a

a

a

Vdd/2 -

0.03
Not Allowed

0.008
BG -

0.009

1.6 x BG

- 0.027

a

-0.034 0.000 0.034 V
Not Allowed
Not Allowed
Not Allowed
Not Allowed

P2[6] -

0.075
Not Allowed

Not Allowed
Not Allowed
Not Allowed
Not Allowed

P2[6] -

0.048

Vdd/2 -

0.01

P2[4] +

0.001
BG +

0.005

1.6 x BG

- 0.010

P2[4] +
P2[6] -

0.009

P2[4]­P2[6] +

0.022

Vdd/2 +

0.005

P2[4] +

0.009
BG +

0.015

1.6 x BG
+ 0.018

P2[4] +
P2[6] +

0.057

P2[4] ­P2[6] +

0.092

V

V

V

V

V

V

CY8CLED04

DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

A

Table 19. DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Units Notes

R

CT

C

SC

Resistor Unit Value (Continuo us Time) – 12.2 – kΩ
Capacitor Unit Value (Switched Capacitor) – 80 – fF

DC POR and LVD Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T
for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters apply to 5V or 3.3V at 25°C and are

A

Document Number: 001-13108 Rev. ** Page 19 of 33

Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register.
Table 20. DC POR and LVD Specifications

Symbol Description Min Typ Max Units Notes

V

PPOR0R

V

PPOR1R

V

PPOR2R

V

PPOR0

V

PPOR1

V

PPOR2

V

PH0

V

PH1

V

PH2

V

LVD0

V

LVD1

V

LVD2

V

LVD3

V

LVD4

V

LVD5

V

LVD6

V

LVD7

a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b

Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b

PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b

Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b

–

–

–
–
–

2.86

2.96

3.07

3.92

4.39

4.55

4.63

4.72

2.91

4.39

4.55

2.82

4.39

4.55

92
0
0

2.92

3.02

3.13

4.00

4.48

4.64

4.73

4.81

–

–

–
–
–

2.98

3.08

3.20

4.08

4.57

4.74

4.82

4.91

V
V
V

V
V
V

mV
mV
mV

a

V
V
V
V

V
V

b

V
V
V

CY8CLED04

DC Programming Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 21. DC Programming Specifications

Symbol Description Min Typ Max Units Notes

I

DDP

V

ILP

V

IHP

I

ILP

I

IHP

V

OLV

V

OHV

Flash
Flash

Flash

a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of

Supply Current During Programming or Verify – 15 30 mA
Input Low Voltage During Programming or Verify – – 0.8 V
Input High Voltage During Programming or Verify 2.1 – – V
Input Current when Applying Vilp to P1[0] or P1[1] Dur-

ing Programming or Verify
Input Current when Applying Vihp to P1[0] or P1[1] Dur-

ing Programming or Verify
Output Low Volta ge During Programming or Verify – – Vss +

– – 0.2 mA Driving internal pull-down resistor.

– – 1.5 mA Driving internal pull-down resistor.

V

0.75

Output High Voltage During Programming or Verify Vdd - 1.0 – Vdd V
Flash Endurance (per block) 50,000 – – – Erase/write cycles per block.

ENPB
ENT

Flash Endurance (total)

Flash Data Retention 10 – – Years

DR

a

1,800,000– – – Erase/write cycles.

25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than
50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the tempera ture argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

Document Number: 001-13108 Rev. ** Page 20 of 33

CY8CLED04

AC Electrical Characteristics

AC Chip-Level Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only.

Table 22. AC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

F

IMO245V

F

IMO243V

F

IMOUSB5V

F

IMOUSB3V

F

CPU1

F

CPU2

F

BLK5

F

BLK3

F

32K1

Jitter32k 32 kHz Period Jitter – 100 ns
Step24M 24 MHz Trim Step Size – 50 – kHz
Fout48M 48 MHz Output Frequency 46.08 48.0

Jitter24M1 24 MHz Period Jitter (IMO) Peak-to-Peak – 300 ps
F

MAX

T

RAMP

a. 4.75V < Vdd < 5.25V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. 3.0V < Vdd < 3.6V. See Application Not e AN2012 “Adjusting PSoC Micro controller Trims for Dual V oltage-Range Op eration” for inf ormation on trimmin g for operat ion at 3.3V.
d. See the individual user module data sheets for information on maximum frequencies for user modules.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

A

Internal Main Oscillator Frequency for 24 MHz (5V) 23.04 24

Internal Main Oscillator Frequency for 24 MHz (3.3V) 22.08 24

Internal Main Oscillator Frequency with USB (5V)
Frequency locking enabled and USB traffic present.

Internal Main Oscillator Frequency with USB (3.3V)
Frequency locking enabled and USB traffic present.

CPU Frequency (5V Nominal) 0.93 24
CPU Frequency (3.3V Nominal) 0.93 12
Digital PSoC Block Frequency (5V Nominal) 0 48
Digital PSoC Block Frequency (3.3V Nominal) 0 24
Internal Low Speed Oscillator Frequency 15 32 64 kHz

Maximum frequency of signal on row input or row outp ut. – – 12.96 MHz
Supply Ramp Time 0 – – μs

23.94 24

23.94 24

24.96

25.92

24.06

24.06

24.96

12.96

49.92

25.92

49.92

a,b

MHz Trimmed for 5V operation using factory trim

b,c

MHz Trimmed for 3.3V operation using factory trim

b

MHz -10°C ≤ TA ≤ 85°C

b

MHz -0°C ≤ TA ≤ 70°C

a,b

MHz

b,c

MHz

a,b,d

MHz Refer to the AC Digital Block Specifications.

b, d

MHz

a,c

MHz Trimmed. Utilizing factory trim values.

values.

values.

4.35 ≤ Vdd ≤ 5.15

3.15 ≤ Vdd ≤ 3.45

Figure 5. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

F

24M

AC General Purpose IO Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

A

Table 23. AC GPIO Specifications

Symbol Description Min Typ Max Units Notes

F

GPIO

TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90%
TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS Ri se Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90%
TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10 % - 90%

GPIO Operating Frequency 0 – 12 MHz Normal Strong Mode

Document Number: 001-13108 Rev. ** Page 21 of 33

GPIO

Pin

Output

Voltage

CY8CLED04

Figure 6. GPIO Timing Diagram

90%

10%

TRiseF
TRiseS

TFallF
TFallS

AC Full-Speed USB Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -10°C ≤ T
are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

A

Table 24. AC Full-Speed (12 Mbps) USB Specifications

Symbol Description Min Typ Max Units Notes

T

RFS

T

FSS

T

RFMFS

T

DRATEFS

Transition Rise Time 4 – 20 ns For 50 pF load.
Transition Fall Time 4 – 20 ns For 50 pF load.
Rise/Fall Time Matching: (TR/TF)90– 111 % For 50 pF load.
Full-Speed Data Rate 12 -

0.25%

12 12 +

0.25%

Mbps

AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

A

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V

.

Table 25. 5V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

T

T

SR

SR

ROA

SOA

ROA

FOA

Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)

Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10

pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High

–
–
–

–
–
–

0.15

1.7

6.5

0.01

0.5

4.0

–
–
–

–
–
–

–
–
–

–
–
–

3.9

0.72

0.62

5.9

0.92

0.72

–
–
–

–
–
–

μs
μs
μs

μs
μs
μs

V/μs
V/μs
V/μs

V/μs
V/μs
V/μs

Document Number: 001-13108 Rev. ** Page 22 of 33

Table 25. 5V AC Operational Amplifier Specifications (continued)

Symbol Description Min Typ Max Units Notes

BW

E

OA

NOA

Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

0.75

3.1

5.4

–
–
–

–
–
–

MHz
MHz
MHz

Table 26. 3.3V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

T

T

SR

SR

BW

E

ROA

SOA

ROA

FOA

OA

NOA

Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)

Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10

pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

–
–

–
–

0.31

2.7

0.24

1.8

0.67

2.8

–
–

–
–

–
–

–
–

–
–

3.92

0.72

5.41

0.72

–
–

–
–

–
–

μs
μs

μs
μs

V/μs
V/μs

V/μs
V/μs

MHz
MHz

CY8CLED04

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 7. Typical AGND Noise with P2[4] Bypass

dBV/rtHz
10000

0

0.01

0.1

1.0
10

1000

100

0.001 0.01 0.1 1 10 100Freq (kHz)

Document Number: 001-13108 Rev. ** Page 23 of 33

CY8CLED04

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.

Figure 8. Typical Opamp Noise

nV/rtHz
10000

PH_BH
PH_BL
PM_BL
PL_BL

1000

100

10

0.001 0.01 0.1 1 10 100

Freq (kHz)

AC Low Power Comparator Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T
apply to 5V at 25°C and are for design guidance only.

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

A

Table 27. AC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

T

RLPC

LPC response time – – 50 μs ≥ 50 mV overdrive comparator reference set

within V

REFLPC

.

Document Number: 001-13108 Rev. ** Page 24 of 33

CY8CLED04

AC Digital Block Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 28. AC Digital Block Specifications

Function Description Min Typ Max Units Notes

Timer Capture Pulse Width

Maximum Frequency, No Capture – – 49.92 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, With Capture – – 25.92 MHz

Counter Enable Pulse Width

Maximum Frequency, No Enable Input – – 49.92 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input – – 25.92 MHz

Dead Band Kill Pulse Width:

Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode

Disable Mode

Maximum Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.

CRCPRS
(PRS Mode)

CRCPRS
(CRC Mode)

SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to 2 x over

SPIS Maximum Input Clock Frequency – – 4.1 MHz

Transmitter Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over

Receiver Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over

Maximum Input Clock Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.

Maximum Input Clock Frequency – – 24.6 MHz

Width of SS_ Negated Between Transmissions

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

a

50

50

50
50

50

– – ns

a

– – ns

a

– – ns

a

– – ns

a

– – ns

clocking.

clocking.

clocking.

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

A

Table 29. AC External Clock Specifications

Symbol Description Min Typ Max Units Notes

F

OSCEXT

– Duty Cycle 47
– Power up to IMO Switch 150

Frequency for USB Applications 23.94 24 24.06 MHz

50 53 %
– – μs

Document Number: 001-13108 Rev. ** Page 25 of 33

CY8CLED04

AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 30. 5V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

T

T

SR

SR

BW

BW

ROB

SOB

Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load

ROB

Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

FOB

Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load

OBSS

Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load

OBLS

Power = Low
Power = High

–
–

–
–

0.65

0.65

0.65

0.65

0.8

0.8

300
300

–
–

–
–

–
–

–
–

–
–

–
–

2.5

2.5

2.2

2.2

–
–

–
–

–
–

–
–

μs
μs

μs
μs

V/μs
V/μs

V/μs
V/μs

MHz
MHz

kHz
kHz

Table 31. 3.3V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

T

T

SR

SR

BW

BW

ROB

SOB

Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load

ROB

Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

FOB

Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load

OBSS

Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load

OBLS

Power = Low
Power = High

–
–

–
–

0.5

0.5

0.5

0.5

0.7

0.7

200
200

–
–

–
–

–
–

–
–

–
–

–
–

3.8

3.8

2.6

2.6

–
–

–
–

–
–

–
–

μs
μs

μs
μs

V/μs
V/μs

V/μs
V/μs

MHz
MHz

kHz
kHz

Document Number: 001-13108 Rev. ** Page 26 of 33

CY8CLED04

AC Programming Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 32. AC Programming Specifications

Symbol Description Min Typ Max Units Notes

T

RSCLK

T

FSCLK

T

SSCLK

T

HSCLK

F

SCLK

T

ERASEB

T

WRITE

T

DSCLK

T

DSCLK3

AC I

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only.

Rise Time of SCLK 1 – 20 ns
Fall Time of SCLK 1 – 20 ns
Data Set up Time to Falling Edge of SCLK 40 – – ns
Data Hold Time from Falling Edge of SCLK 40 – – ns
Frequency of SCLK 0 – 8 MHz
Flash Erase Time (Block) – 10 – ms
Flash Block Write Time – 30 – ms
Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6
Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6

2

C Specifications

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

A

Table 33. AC Characteristics of the I2C SDA and SCL Pins for Vdd

Standard Mode Fast Mode

Symbol Description

F

SCLI2C

T

HDSTAI2C

T

LOWI2C

T

HIGHI2C

T

SUSTAI2C

T

HDDATI2C

T

SUDATI2C

T

SUSTOI2C

T

BUFI2C

T

SPI2C

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

SCL Clock Frequency 0 100 0 400 kHz
Hold Time (repeated) START Condition. After this

period, the first clock pulse is generated.
LOW Period of the SCL Clock 4.7 –1.3– μs

HIGH Period of the SCL Clock 4.0 –0.6– μs
Set-up Time for a Repeated START Condition 4.7 –0.6– μs
Data Hold Time 0 –0– μs
Data Set-up Time 250 –
Set-up Time for STOP Condition 4.0 –0.6– μs
Bus Free Time Between a STOP and START Condition 4.7 –1.3– μs
Pulse Width of spikes are suppressed by the input filter. – – 0 50 ns

the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL sign al, it must output the next data bit to the SDA line

+ t

t

rmax

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

SU;DAT

4.0 –0.6– μs

a

100

–ns

≥ 250 ns must then be met. This will automatically be the case if

SU;DAT

Units NotesMin Max Min Max

Document Number: 001-13108 Rev. ** Page 27 of 33

Figure 9. Definition for Timing for Fast/Standard Mode on the I

2

C Bus

CY8CLED04

SDA

SCL

S

T

LOWI2C

T

HDSTAI2C

T

HDDATI2C

T

SUDATI2C

T

HIGHI2C

T

SUSTAI2C

T

T

HDSTAI2C

Sr SP

SPI2C

T

SUSTOI2C

T

BUFI2C

Document Number: 001-13108 Rev. ** Page 28 of 33

CY8CLED04

Packaging Information

Packaging Dimensions

This section illustrates the package specification for the CY8CLED04 EZ-Color device, along with the thermal impedance for the
package and solder reflow peak temperatures.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a de tailed descripti on of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

Figure 10. 68-Lead (8x8 mm x 0.89 mm) QFN

51-85214 *C

Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.

Document Number: 001-13108 Rev. ** Page 29 of 33

CY8CLED04

Thermal Impedance

Table 34. Thermal Impedance for the Package

Package

68 QFN**

* TJ = TA + POWER x θ

JA

Typical θ

13.05 oC/W

JA

*

** To achieve the thermal impedance specified for the QFN
package, the center thermal pad should be soldered to the PCB
ground plane.

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to
achieve good solderability.

Table 35. Solder Reflow Peak Temperature

Package

68 QFN

*Higher temperatures may be required based on the solder melting
point. Typical temperatures f or solder are 220 ± 5

o

C with Sn-Ag-Cu paste. Refer to the solder manufacturer

245 ± 5
specifications.

Minimum Peak

Temperature*

240oC 260oC

Maximum Peak

Temperature

o

C with Sn-Pb or

Development Tools

Software

This section presents the development tools available for all
current PSoC device families including the CY8CLED04
EZ-Color.

PSoC Express

As the newest addition to the PSoC development software suite,
PSoC Express is the first visual embedded system design tool
that allows a user to create an entire PSoC project and generate
a schematic, BOM, and data sheet without writing a single line
of code. Users work directly with application objects such as
LEDs, switches, sensors, and fans. PSoC Express is available
free of charge at http://www.cypress.com/psocexpress.

PSoC Designer

At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at

http://www.cypress.com under DESIGN RESOURCES >>

Software and Drivers.

™

™

PSoC Programmer

Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free ofcharge at http://www.cypress.com/psocpro-

grammer.

CY3202-C iMAGEcraft C Compiler

CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.

Evaluation Tools

All evaluation tools can be purchased from the Cypress Online
Store.

CY3261A-RGB EZ-Color RGB Kit

The CY3261A-RGB board is a preprogrammed HB LED color
mix board with seven pre-set colors using the CY8CLED16
EZ-Color HB LED Controller. The board is accompanied by a
CD containing the color selector software application, PSoC
Express 3.0 Beta 2, PSoC Programmer, and a suite of
documents, schematics, and firmware examples. The color
selector software application can be installed on a host PC and
is used to control the EZ-Color HB LED controller using the
included USB cable. The application enables you to select colors
via a CIE 1931 chart or by entering coordinates. The kit includes:

■ Training Board (CY8CLED16)

■ One mini-A to mini-B USB Cable

■ PSoC Express CD-ROM

■ Design Files and Application Installation CD-ROM

T o program and tune this kit via PSoC Express 3.0 you must use
a Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit.

CY3210-MiniProg1

The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

Document Number: 001-13108 Rev. ** Page 30 of 33

CY8CLED04

CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread­boarding space to meet all of your evaluation needs. The kit
includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

Device Programmers

All device programmers can be purchased from the Cypress
Online Store.

CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:

■ Modular Programmer Base

■ 3 Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

3rd-Party Tools

Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during devel­opment and production. Specific details for each of these tools
can be found at http://www.cypress.com under DESIGN
RESOURCES >> Evaluation Boards.

Build a PSoC Emulator into Your Board

For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323” at

http://www.cypress.com/an2323.

The following table lists the CY8CLED04 EZ-Color device key
package features and ordering codes.

Document Number: 001-13108 Rev. ** Page 31 of 33

Ordering Information

Key Device Features

Table 36. Device Key Features and Ordering Information

CY8CLED04

Package

68 Pin (8x8 mm) QFN CY8CLED04-68LFXI 16K 1K -40C to +85C 4 6 56 48 2 Yes
68 Pin (8x8 mm) QFN

(Tape and Reel)

CY8CLED04-68LFXIT 16K 1K -40C to +85C 4 6 56 48 2 Yes

Code

Ordering

Flash

(Bytes)

SRAM

(Bytes)

Temperature

Range

Digital Blocks

Analog Blocks

Digital IO Pins

Analog Inputs

Analog Outputs

Ordering Code Definitions

CY 8 C LED xx - xx xxxx

Package Type: Thermal Rating:

PX = PDIP Pb-Free C = Commercial
SX = SOIC Pb-Free I = Industrial
PVX = SSOP Pb-Free E = Extended
LFX/LKX = QFN Pb-Free

AX = TQFP Pb-Free
Pin Count
Part Number
LED Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress

XRES Pin

Document Number: 001-13108 Rev. ** Page 32 of 33

Revision History

Table 37. CY8CLED04 Data Sheet Revision History

Document Title: CY8CLED04 EZ-Color HB LED Controller
Document Number: 001-13108

Revision ECN # Issue Date Origin of Change Description of Change

** 1148504 See ECN SFVTMP3 New document (revision **).

Distribution: External/Public Posting: None

CY8CLED04

© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than c ir cuit ry em bo di ed in a Cyp re ss pr od uct . No r do es it c onv ey or im ply an y lice n se u n der pat ent or ot he r rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress doe s n ot a uth or ize its pr od ucts for
use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injur y to the user . The inclusion of Cypress products i n life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress S emiconductor Corp. A ll other trademar ks or registered
trademarks referenced herein are property of the respective corporations.

Any Source Code (software an d/or firm ware) is o wned by C ypres s Semi cond uctor Corpo rati on (C ypress) a nd i s pro tected by an d s ubje ct to wo rldwide p a tent p rotec tion (Un ited States and foreign),
United States copy r ight la w s and international treaty provisions. Cypre ss he re by g r ants to licensee a personal, non-exclu si ve, n on-t ransfera ble lice nse to copy, use, modify, create derivative works
of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in c onj unc tio n wit h
a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is
prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARR ANTY OF ANY KIND, EXPRESS OR IM PLIED, WITH REGARD TO THIS MATERIAL, INCLUDING , BUT NOT LIMITED T O, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any pro duct or circuit described herein. Cypress d oes not authorize its products for use as critical components in life-support systems
where a malfunction or failure ma y reasonably be expecte d to result in significant injury to the user . The inclusion of Cypress ' product in a life-support systems application implies th at the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-13108 Rev. ** Page 33 of 33