CYPRESS CY8C27143 User Manual
PSoC™ Mixed Signal Array Final Data Sheet
Features
CY8C27143, CY8C27243,
CY8C27443, CY8C27543, and CY8C27643
■ Powerful Harvard Architecture Processor
■ Advanced Peripherals (PSoC Blocks)
❐ M8C Processor Speeds to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0 to 5.25 V Operating Voltage
❐ Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐ 8 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 2 Full-Duplex UARTs
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
Port 4 Port 3 Port 2 Port 1 Port 0
Port 5
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Interrupt
Controller
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
(2 Rows,
8 Blocks)
SROM Flash 16K
CPU Core (M8C)
Global Analog Interconnect
ANALOG SYSTEM
Analog
Block
Array
(4 Columns,
12 Blocks)
■ Precision, Programmable Clocking
❐ Internal 2.5% 24/48 MHz Oscillator
❐ 24/48 MHz with Optional 32 kHz Crystal
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 16K Bytes Flash Program Storage 50,000
Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP ™)
❐ Partial Flash Updat es
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐ Up to 12 Analog Inputs on GPIO
❐ Four 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
Analog
Drivers
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
Sleep and
Watchdog
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of convenient pinouts and packages.
The PSoC architecture, as illustrated on the left, is com pri se d of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
Analog
Ref
the device r esources to be c ombined into a compl ete custom
system. The PSoC CY8C27x43 family can have up to five IO
ports that connec t to the gl obal di git al and a nalog i ntercon ne cts ,
Analog
Input
Muxing
providing access to 8 digital blocks and 12 analog blocks.
The PSoC Core
■ Additional System Resources
2
❐ I
C™ Slave, Master, and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software
(PSoC™ Designer)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
The PSoC Core is a powerful engine that supports a rich feature set. Th e co re in cl ud es a C PU , memo r y, clocks, and c on fig -
Digital
Clocks
Multiply
Accum.
POR and LVD
Decimator
I C
2
System Resets
SYSTEM RESOURCES
Internal
Voltage
Ref.
Switch
Mode
Pump
urable GPIO (General Purpose IO).
The M8C C PU core is a powerfu l proce ssor wit h spee ds up t o
24 MHz, providing a four MI PS 8-bit Harvar d archit ecture m icro-
August 3, 2004 © Cypress MicroSystems, Inc. 2002 – 2004 — Document No. 38-12012 Rev. *I 1
CY8C27x43 Final Data Sheet PSoC™ Overview
processor. The CPU utilizes an interrupt controller with 17 vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompas s es 16 KB of Flash for program s tora ge, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software
IP protection.
The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real Time Cloc k (RT C) and can opti onally genera te a crys tal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide conne ct ion t o the CP U, di gital and analog
resources of the devi ce. Each pin’ s dri ve mod e may b e selec te d
from eight options, allowing great flexibility in external interfacing. Every pin also has the c apa bility to gen erate a syste m inte rrupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 8 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to fo rm 8, 16 , 24, and 32-bit p eriphe rals, wh ich
are called user module references.
Port 4 Port 3 Port 2 Port 1 Port 0Port 5
To System Bus
s
k
c
C
o
l
l
a
t
i
g
i
D
e
r
o
C
m
F
o
r
DIGITAL SYSTEM
Digital PSoC Bl ock Array
Row 0
DBB00 DBB01 DCB02 DCB03
Row Input
8
Configuration
Row 1
DBB10 DBB11 DCB12 DCB13
Row Input
Configuration
To Analog
System
4
4
4
4
Configuration
Row Output
8
Configuration
Row Output
88
Digital peripheral configurations include those listed below.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity (up to 2)
■ SPI master and slave (up to 2)
■ I2C slave and master (1 available as a System Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA (up to 2)
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This co nfig ura bil ity free s y our d e si gn s fro m th e co nstraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Charac-
teristics” on page 3.
The Analog System
The Analog System is composed of 12 configurable blocks,
each comprised of an opamp circuit allowing the creation of
complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application
requiremen ts. Some of the more comm on PSoC analog fun ctions (most available as user modules) are listed below.
■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolu-
tion, selectable as Incr emental, Delta Sigma, and SAR)
■ Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)
■ Amplifiers (up to 4, with selectable gain to 48x)
■ Instrumentation amplifiers (up to 2, with selectable gain to
93x)
■ Comparators (up to 4, with 16 selectable thresholds)
■ DACs (up to 4, with 6- to 9-bit resolution)
■ Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■ High current output drivers (four with 30 mA drive as a Core
Resource)
■ 1.3V refer ence (as a System Resource)
■ DTMF dialer
■ Modulators
■ Correlators
■ Peak detectors
■ Many other topologies possible
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital System Block Diagram
August 3, 2004 Document No. 38-12012 Rev. *I 2
CY8C27x43 Final Data Sheet PSoC™ Overview
p
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Array Input Configuration
ACI0[1:0] ACI3[1:0]
ACB00 ACB01
ACI1[1:0] ACI2[1:0]
Block Array
ACB02 ACB03
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
RefIn
P2[4]
AGNDIn
P2[2]
P2[0]
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below.
■ Digital clock dividers provide three customizable clock fre-
quencies for use in applic ations . The clo cks c an be route d to
both the digital a nd analog systems. Additiona l clocks c an be
generated using digital PSoC blocks as clock dividers.
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumula te, to assi st in both genera l math as well
as digital filters.
■ The decimator provides a custom hardware filter for digital
signal processing applications inc lud in g t he c r eati on of D e lta
Sigma ADCs.
■ The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of f alling voltage levels, w hile the adv anced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■ An internal 1.3V refe rence provides an absolute reference fo r
the analog system, including ADCs and DACs.
■ An integrated switch mode pump (S MP) gene rate s norm al
operating volt ages f rom a single 1.2V batt ery cel l, providin g a
low cost boost converter.
ASC10
Interface to
Digital System
M8C Interface (Address Bus, Data Bus, Etc.)
ASD11
ASC21
AGND
RefHi
RefLo
ASC12 ASD13
ASD22 ASC23ASD20
Analog Reference
Analog System Block Diagram
Reference
Generators
AGNDIn
RefIn
Bandga
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is shown in the second row of the
table.
PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
CY8C27x43
CY8C24x23
CY8C24x23A
CY8C22x13
Digital
up to
64
up to
44
up to
24
up to
24
up to
16
IO
Rows
Digital
Digital
4 16 12 4 4 12
2 8 12 4 4 12
1 4 12 2 2 6
1 4 12 2 2 6
1 4 8 1 1 3
Inputs
Blocks
Analog
Analog
Outputs
Analog
Analog
Columns
Blocks
August 3, 2004 Document No. 38-12012 Rev. *I 3
CY8C27x43 Final Data Sheet PSoC™ Overview
Getting Started
The quickest path to understanding th e PSoC s ili co n is by rea ding this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed Signal Array Technical Reference Manual.
For up-to-date Ordering, Packag ing, an d Electri cal Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at http://www.onfulfillment.com/cypressstore/ contains develop-
ment kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view
a current list of available items.
Tele-Training
Free PSoC "Tele-training" is available for beginners and taught
by a live marketing or appli ca tio n eng in eer ov er th e pho ne . F ive
training cl asses are availabl e to accelerate th e learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the
tele-training, see http://www.cypress.com/support/training.cfm.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to complete d PSoC d esign s. To contact or be come a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Development Tools
The Cypress MicroSystems PSoC Designer is a Microsoft
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
TM
PSoC
Designer
Importable
Design
Database
Device
Database
Application
Database
Project
Database
Graphical Designer
Interface
Results
Commands
TM
PSoC
Designer
Core
Engine
Context
Sensitive
Help
PSoC
Configuration
Sheet
Manufacturing
Information
File
®
Technical Support
PSoC application engineers take pride in fast and accurate
User
Modules
Library
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
A long list of application notes will assist you in every aspect of
Emulation
Pod
In-Circuit
Emulator
your design effort. To locate the PSoC application notes, go to
http://www.cypress.com/design/results.cfm.
PSoC Designer Subsystems
August 3, 2004 Document No. 38-12012 Rev. *I 4
Device
Programmer
CY8C27x43 Final Data Sheet PSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
The Device Edi tor su bsys tem al lows the use r to se lect differ ent
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an ap pli cat ion f ram ewor k. The fram ew ork con tains soft ware
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PS o C De s ig ne r c a n pri nt ou t a co n f ig ur at io n s he et fo r
a given project configuration for use during application programming in conj unc tion with the Devi ce Da ta Shee t. On ce t he
framework is generated, t he user can add a pplication-spe cific
code to flesh out the framework. It’s also possible to change the
selected component s and rege nera te the fram ew or k.
Design Browser
The Design Bro wser allows users to select an d import prec onfigured desi g ns int o th e u se r’s project. Us er s ca n ea s il y bro w se
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tool s i ncl ud e a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, compile, link, and build.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical s ystem while pr ovidi ng an i nter nal vie w of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting st arte d.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consist s of a bas e unit th at conne ct s to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulati on pods for each
device family ar e ava ilabl e sep arate ly. The emulation pod t akes
the place of the PSoC device in the targ et board and performs
full speed (24 MHz) operation.
Assembler. T he macro assembler all ows the assembly code
to be merged seamlessly with C code. The link libraries automatically use abso lut e addre ssing or ca n be co mpil ed in re lat ive
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
August 3, 2004 Document No. 38-12012 Rev. *I 5
CY8C27x43 Final Data Sheet PSoC™ Overview
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and d igital hard ware blocks give the PS oC archite cture
a unique flexibility that p ays d ivide nds in mana gi ng specifi catio n
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses, and to the IO
pins. Iterative devel op men t cy cl es perm it y ou to ada pt th e hardware as well as the software. This substantially lowers the risk
that you will have to select a different part to meet the final
design requirements.
To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user mod ule establishes the basi c register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
applicati on. For exam ple, a Puls e Width Modula tor User Module configures one or more digital PSoC blocks, one for each 8
bits of reso lution. The user mod ule parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides highlevel functions to control and respond to hardware events at
run-time. The API als o provides o ptional int errupt serv ice routines that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSo C D esi gn er IDE. Th es e data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and- cli ck si mplic ity. Next, you b uil d si gnal chain s by int erconnecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to develo ping co de for the proj ect, yo u
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
Device Editor
User
Module
Selection
Placement
and
Parameter
-ization
Source
Code
Generator
Generate
Application
Application Editor
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open t he project sourc e code files (i ncluding all gene rated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the devel opm en t proc es s t ak es pla ce insi de the
PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events tha t inc lu de m oni tori ng ad dres s and da t a bu s
values, memory locations and external signals.
August 3, 2004 Document No. 38-12012 Rev. *I 6
CY8C27x43 Final Data Sheet PSoC™ Overview
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-t o-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC™ Programmable System-on-Chip™
PWM pulse width modulator
RAM random access memory
SC switched capacitor
SLIMO slow IMO
SMP switch mode pump
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 17 lists all the abbreviations
used to measure the PSoC devices.
Numeric Naming
Table of Contents
For an in depth discussion and more information on your PSoC
device, obtain the
ence Manual
into the following chapters and sections.
1. Pin Information .............................. ..... ...... .................... 8
1.1 Pinouts ................................................................... 8
1.1.1 8-Pin Part Pinout ................................ ............. ....8
1.1.2 20-Pin Part Pinout ........................ .... .... ........... ....9
1.1.3 28-Pin Part Pinout ........................ .... .... ........... ..10
1.1.4 44-Pin Part Pinout ........................ .... .... ........... ..11
1.1.5 48-Pin Part Pinouts ...........................................12
2. Register Reference ..................................................... 14
2.1 Register Conventions ...........................................14
2.2 Register Mapping Tables ..................................... 14
3. Electrical Specifications ............................................ 17
3.1 Absolute Maximum Ratings .............. ..... ...... ...... .18
3.2 Operating Temperature .......................................18
3.3 DC Electrical Characteristics ................................ 19
3.3.1 DC Chip-Level Specifications .............................19
3.3.2 DC General Purpose IO Specifications ..............19
3.3.3 DC Operational Amplifier Specifications ............20
3.3.4 DC Analog Output Buffer Specifications ............22
3.3.5 DC Switch Mode Pump Specifications ...............23
3.3.6 DC Analog Reference Specifications .................24
3.3.7 DC Analog PSoC Block Specifications ...............26
3.3.8 DC POR and LVD Specifications .......................26
3.3.9 DC Programming Specifications ........................27
3.4 AC Electrical Characteristics ................................28
3.4.1 AC Chip-Level Spec ifications .............................28
3.4.2 AC General Purpose IO Specifications ..............30
3.4.3 AC Operational Amplifier Specifications .............31
3.4.4 AC Digital Block Specifications ..........................32
3.4.5 AC Analog Output Buffer Specifications .............33
3.4.6 AC External Clock Specifications .......................34
3.4.7 AC Programmi n g Spe c ifications .........................34
3.4.8 AC I2C Specifications ................ .............. ...........35
4. Packaging Information ............................................... 36
4.1 Packaging Dimensions .........................................36
4.2 Thermal Impedances .......................................... 41
4.3 Capacitance on Crystal Pins ............................... 41
5. Ordering Information .................................................. 42
5.1 Ordering Code Definitions ...................................43
6. Sales and Service Information .................................. 44
6.1 Revision History ...................................................44
6.2 Copyrights and Code Protection .......................... 44
PSoC Mixed Signal Array Technical Refer-
. This document encompasses and is organized
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexi d ec im al nu mb ers ma y al so be rep r es en ted by a ‘0 x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
August 3, 2004 Document No. 38-12012 Rev. *I 7
1. Pin Information
A
This chapter describes, lists, and illustrates the CY8C27x43 PSoC device pins and pinout configurations.
1.1 Pinouts
The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.1 8-Pin Part Pinout
Table 1-1. 8-Pin Part Pinout (PDIP)
Pin
No.
1 IO IO P0[5] Analog column mux input and column output.
2 IO IO P0[3] Analog column mux input and column output.
3 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
4 Power Vss Ground c onnection.
5 IO P1[0] Crystal Output (XTALout), I2C Serial Data
6 IO IO P0[2] Analog column mux input and column output.
7 IO IO P0[4] Analog column mux input and column output.
8 Power Vdd Supply voltage.
Type
Digital Analog
Pin
Name
Description
(SDA)
CY8C27143 8-Pin PSoC Device
AIO, P0[5]
AIO, P0[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
PDIP
3
4
Vdd
8
P0[4], AIO
7
P0[2], AIO
6
P1[0], XTALout , I2 C SD
5
LEGEND: A = Analog, I = Input, and O = Output.
August 3, 2004 Document No. 38-12012 Rev. *I 8
CY8C27x43 Final Data Sheet 1. Pin Information
A
1.1.2 20-Pin Part Pinout
Table 1-2. 20-Pin Part Pinout (SSOP, SOIC)
Pin
No.
1 IO I P0[7] Analog column mux input.
2 IO IO P0[5] Analog column mux input and colum n outp ut.
3 IO IO P0[3] Analog column mux input and colum n outp ut.
4 IO I P0[1] Analog column mux input.
5 Power SMP Switch Mode Pump (SMP) connection to
6 IO P1[7] I2C Serial Clock (SCL)
7 IO P1[5] I2C Serial Data (SDA)
8 IO P1[3]
9 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
10 Power Vss Ground connection.
11 IO P1[0] Crystal Output (XTALout), I2C Serial Data
12 IO P1[2]
13 IO P1[4] Optional External Clock Input (EXTCLK)
14 IO P1[6]
15 Input XRES Active high external reset with internal pull
16 IO I P 0[0] Analog column mux input.
17 IO IO P0[2] Analog column mux input and column output.
18 IO IO P0[4] Analog column mux input and column output.
19 IO I P 0[6] Analog column mux input.
20 Power Vdd Supply voltage.
Type
Digital Analog
Pin
Name
external components requi red .
(SDA)
down.
Description
I2C SCL, XTALin, P1[1]
CY8C27243 20-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
Vss
10
1
2
3
4
5
6
7
8
9
SSOP
SOIC
20
19
18
17
16
15
14
13
12
11
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SD
LEGEND: A = Analog, I = Input, and O = Output.
August 3, 2004 Document No. 38-12012 Rev. *I 9
CY8C27x43 Final Data Sheet 1. Pin Information
A
1.1.3 28-Pin Part Pinout
Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
1 IO I P0[7] Analog column mux input.
2 IO IO P0[5] Analog column mux input and column output.
3 IO IO P0[3] Analog column mux input and column output.
4 IO I P0[1] Analog column mux input.
5 IO P2[7]
6 IO P2[5]
7 IO I P2[3] Direct switched capacitor block input.
8 IO I P2[1] Direct switched capacitor block input.
9 Power SMP Switch Mode Pump (SMP) connection to
10 IO P1[7] I2C Serial Clock (SCL)
11 IO P1[5] I2C Serial Data (SDA)
12 IO P1[3]
13 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
14 Power Vss Ground connection.
15 IO P1[0] Crystal Output (XTALout), I2C Serial Data
16 IO P1[2]
17 IO P1 [4] Optio na l Exter nal Clock Inpu t (EXT CLK)
18 IO P1[6]
19 Input XRES Active high external reset with internal pull
20 IO I P2[0] Direct switched capacitor block input.
21 IO I P2[2] Direct switched capacitor block input.
22 IO P2[4] External Analog Ground (AGND)
23 IO P2[6] External Voltage Reference (VRef)
24 IO I P0[0] Analog column mux input.
25 IO IO P0[2] Analog column mux input and column output.
26 IO IO P0[4] Analog column mux input and column output.
27 IO I P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
Type
Digital Analog
Pin
Name
external components required.
(SDA)
down.
Description
I2C SCL, XTALin, P1[1]
CY8C27443 28-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
Vss
10
11
12
13
14
1
2
3
4
5
6
7
8
9
PDIP
SSOP
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SD
LEGEND: A = Analog, I = Input, and O = Output.
August 3, 2004 Document No. 38-12012 Rev. *I 10
CY8C27x43 Final Data Sheet 1. Pin Information
D
A
A
f
1.1.4 44-Pin Part Pinout
Table 1-4. 44-Pin Part Pinout (TQFP)
Pin
No.
1 IO P2[5]
2 IO I P2[3] Direct switched capacitor block input.
3 IO I P2[1] Direct switched capacitor block input.
4 IO P4[7]
5 IO P4[5]
6 IO P4[3]
7 IO P4[1]
8 Power SMP Switch Mode Pump (SMP) connection to
9 IO P3[7]
10 IO P3[5]
11 IO P3[3]
12 IO P3[1]
13 IO P1[7] I2C Serial Clock (SCL)
14 IO P1[5] I2C Serial Data (SDA)
15 IO P1[3]
16 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
17 Power Vss Ground connection.
18 IO P1[0] Crystal Output (XTALout), I2C Serial Data
19 IO P1[2]
20 IO P1[4] Optional External Clock Input (EXTCLK)
21 IO P1[6]
22 IO P3[0]
23 IO P3[2]
24 IO P3[4]
25 IO P3[6]
26 Input XRES Active high external reset with internal pull
27 IO P4[0]
28 IO P4[2]
29 IO P4[4]
30 IO P4[6]
31 IO I P2[0] Direct switched capacitor block input.
32 IO I P2[2] Direct switched capacitor block input.
33 IO P2[4] External Analog Ground (AGND)
34 IO P2[6] External V oltage Re ference (VR ef)
35 IO I P0[0] Analog column mux input.
36 IO IO P0[2] Analog colum n mux input and column output.
37 IO IO P0[4] Analog colum n mux input and column output.
38 IO I P0[6] Analog column mux input.
39 Power Vdd Supply voltage.
40 IO I P0[7] Analog column mux input.
41 IO IO P0[5] Analog colum n mux input and column output.
42 IO IO P0[3] Analog colum n mux input and column output.
43 IO I P0[1] Analog column mux input.
44 IO P2[7]
Type
Digital Analog
Pin
Name
external components requi re d.
(SDA)
down.
Description
CY8C27543 44-Pin PSoC Device
P2[7]
P0[1], AI
P0[3], AIO
P0[5], AIO
P0[7], AI
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6 ], Extern al VRe
14
I2C SDA, P1[5]
TQFP
16
15
P1[3]
I2C SCL, X TALin , P1[1]
39
17
Vss
38
18
I2C SDA, XTALout, P1[0]
36
37
192021
P1[2]
EXTCLK, P1[4]
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P1[6]
P3[0]
P2[5]
I, P2[3]
I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP XRES
P3[7]
P3[5] P3[4]
P3[3]
4443424140
1
2
3
4
5
6
7
8
9
10
11
12
13
P3[1]
I2C SCL, P1[7]
P2[4], External AGN
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
P3[6]
P3[2]
LEGEND: A = Analog, I = Input, and O = Output.
August 3, 2004 Document No. 38-12012 Rev. *I 11
CY8C27x43 Final Data Sheet 1. Pin Information
I
A
1.1.5 48-Pin Part Pinouts
Table 1-5. 48-Pin Part Pinout (SSOP)
Pin
No.
1 IO I P0[7] Analog column mux input.
2 IO IO P0[5] Analog column mux input and column output.
3 IO IO P0[3] Analog column mux input and column output.
4 IO I P0[1] Analog column mux input.
5 IO P2[7]
6 IO P2[5]
7 IO I P2[3] Direct switched capacitor block input.
8 IO I P2[1] Direct switched capacitor block input.
9 IO P4[7]
10 IO P4[5]
11 IO P4[3]
12 IO P4[1]
13 Power SMP Switch Mode Pump (SMP) connection to
14 IO P3[7]
15 IO P3[5]
16 IO P3[3]
17 IO P3[1]
18 IO P5[3]
19 IO P5[1]
20 IO P1[7] I2C Serial Clock (SCL)
21 IO P1[5] I2C Serial Data (SDA)
22 IO P1[3]
23 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
24 Power Vss Ground connecti on.
25 IO P1[0] Crystal Output (XTALout), I2C Serial Data
26 IO P1[2]
27 IO P1[4] Optional External Clock Input (EXTCLK)
28 IO P1[6]
29 IO P5[0]
30 IO P5[2]
31 IO P3[0]
32 IO P3[2]
33 IO P3[4]
34 IO P3[6]
35 Input XRES Active high external reset with internal pull
36 IO P4[0]
37 IO P4[2]
38 IO P4[4]
39 IO P4[6]
40 IO I P2[0] Direct switched capacitor block input.
41 IO I P2[2] Direct switched capacitor block input.
42 IO P2[4] External Analog Ground (AGND)
43 IO P2[6] External Voltage Reference (VRef)
44 IO I P0[0] Analog column mux input.
45 IO IO P0[2] Analog column mux input and column output.
46 IO IO P0[4] Analog column mux input and column output.
47 IO I P0[6] Analog column mux input.
48 Power Vdd Supply voltage.
Type
Digital Analog
Pin
Name
external co mponents required.
(SDA)
down.
Description
2C SCL, XTALin, P1[1]
CY8C27643 48-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
SSOP
13
14
15
16
17
18
19
20
21
22
23
24
Vdd
48
P0[6], AI
47
P0[2], AIO
46
P0[4], AIO
45
P0[0], AI
44
P2[6], External VRef
43
P2[4], External AGND
42
P2[2], AI
41
P2[0], AI
40
P4[6]
39
P4[4]
38
P4[2]
37
P4[0]
36
XRES
35
P3[6]
34
P3[4]
33
P3[2]
32
P3[0]
31
P5[2]
30
P5[0]
29
P1[6]
28
P1[4], EXTCLK
27
P1[2]
26
P1[0], XTALout, I2C SD
25
LEGEND: A = Analog, I = Input, and O = Output.
August 3, 2004 Document No. 38-12012 Rev. *I 12
CY8C27x43 Final Data Sheet 1. Pin Information
f
A
A
D
Table 1-6. 48-Pin Part Pinout (MLF*)
Pin
No.
1 IO I P2[3] Direct switched capacitor block input.
2 IO I P2[1] Direct switched capacitor block input.
3 IO P4[7]
4 IO P4[5]
5 IO P4[3]
6 IO P4[1]
7 Power SMP Switch Mode Pump (SMP) connection to
8 IO P3[7]
9 IO P3[5]
10 IO P3[3]
11 IO P3[1]
12 IO P5[3]
13 IO P5[1]
14 IO P1[7] I2C Serial Clock (SCL)
15 IO P1[5] I2C Serial Data (SDA)
16 IO P1[3]
17 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
18 Power Vss Ground connection.
19 IO P1[0] Crystal Output (XTALout), I2C Serial Data
20 IO P1[2]
21 IO P1[4] Optional External Clock Input (EXTCLK)
22 IO P1[6]
23 IO P5[0]
24 IO P5[2]
25 IO P3[0]
26 IO P3[2]
27 IO P3[4]
28 IO P3[6]
29 Input XRES Active high external reset with internal pull
30 IO P4[0]
31 IO P4[2]
32 IO P4[4]
33 IO P4[6]
34 IO I P2[0] Direct switched capacitor block input.
35 IO I P2[2] Direct switched capacitor block input.
36 IO P2[4] External Analog Ground (AGND)
37 IO P2[6] External Voltage Reference (VRef)
38 IO I P0[0] Analog column mux input.
39 IO IO P0[2] Analog col umn mux input and column output.
40 IO IO P0[4] Analog col umn mux input and column output.
41 IO I P0[6] Analog column mux input.
42 Power Vdd Su pply vol tage .
43 IO I P0[7] Analog column mux input.
44 IO IO P0[5] Analog col umn mux input and column output.
45 IO IO P0[3] Analog col umn mux input and column output.
46 IO I P0[1] Analog column mux input.
47 IO P2[7]
48 IO P2[5]
Type
Digital Analog
Pin
Name
external components required.
(SDA)
down.
Description
I, P2[3]
I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
CY8C27643 48-Pin PSoC Device
P2[5]
P2[7]
P0[1], AI
P0[3], AIO
P0[5], AIO
P0[7], AI
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], Extern al VRe
4847464544
1
2
3
4
5
6
7
8
9
10
11
12
131415161718192021
P5[1]
I2C SCL, P1[7]
43424140393837
MLF
(Top View)
Vss
P1[3]
I2C SDA, P1[5]
I2C SCL , X T ALin, P1 [1 ]
P1[2]
I2C SDA, XTALout, P1[0]
36
35
34
33
32
31
30
29
28
27
26
25
22
23
24
P1[6]
P5[0]
P5[2]
EXTC L K , P 1 [4 ]
P2[4], External AGN
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to ground (Vss).
August 3, 2004 Document No. 38-12012 Rev. *I 13
2. Register Reference
This chapter lists the registers of the CY8C27x43 PSoC device. For detailed register information, reference the PSoC™ Mixed Sig-
nal Array Technical Reference Manual
.
2.1 Register Conventions
The register conventions specific to this section are listed in the
following table.
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical regi ster or bit(s)
C Clearable register or bit(s)
# Access is bit specific
2.2 Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag regist er (CPU_F)
determines which bank the user is currently in. When the XOI
bit is set the user is in bank 1.
Note In the foll owing reg ister mappi ng tables, blank fiel ds are
reserved and should not be accessed.
August 3, 2004 © Cypress MicroSystems, Inc. 2003 — Document No. 38-12012 Rev. *I 14
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