CYPRESS CY8C27143 User Manual

PSoC™ Mixed Signal Array Final Data Sheet

Features

CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643

■ Powerful Harvard Architecture Processor

■ Advanced Peripherals (PSoC Blocks)

❐ M8C Processor Speeds to 24 MHz ❐ 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3.0 to 5.25 V Operating Voltage ❐ Operating Voltages Down to 1.0V Using On-

Chip Switch Mode Pump (SMP)

❐ Industrial Temperature Range: -40°C to +85°C

❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:

- Up to 14-Bit ADCs

- Up to 9-Bit DACs

- Programmable Gain Amplifiers

- Programmable Filters and Comparators

❐ 8 Digital PSoC Blocks Provide:

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Up to 2 Full-Duplex UARTs

- Multiple SPI™ Masters or Slaves

- Connectable to all GPIO Pins

❐ Complex Peripherals by Combining Blocks

Port 4 Port 3 Port 2 Port 1 Port 0

Port 5

PSoC

CORE

System Bus

Global Digital Interconnect

SRAM

256 Bytes

Interrupt

Controller

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

DIGITAL SYSTEM

Digital

Block Array

(2 Rows,

8 Blocks)

SROM Flash 16K

CPU Core (M8C)

Global Analog Interconnect

ANALOG SYSTEM

Analog

Block Array

(4 Columns,

12 Blocks)

■ Precision, Programmable Clocking ❐ Internal 2.5% 24/48 MHz Oscillator ❐ 24/48 MHz with Optional 32 kHz Crystal ❐ Optional External Oscillator, up to 24 MHz ❐ Internal Oscillator for Watchdog and Sleep

■ Flexible On-Chip Memory ❐ 16K Bytes Flash Program Storage 50,000

Erase/Write Cycles

❐ 256 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP ™) ❐ Partial Flash Updat es ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations ❐ 25 mA Sink on all GPIO ❐ Pull up, Pull down, High Z, Strong, or Open

Drain Drive Modes on all GPIO

❐ Up to 12 Analog Inputs on GPIO ❐ Four 30 mA Analog Outputs on GPIO ❐ Configurable Interrupt on all GPIO

Analog Drivers

PSoC™ Functional Overview

The PSoC™ family consists of many Mixed Signal Array with On-Chip Controller devices. These devices are designed to

replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations

Sleep and Watchdog

that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages.

The PSoC architecture, as illustrated on the left, is com pri se d of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all

Analog

Ref

the device r esources to be c ombined into a compl ete custom system. The PSoC CY8C27x43 family can have up to five IO ports that connec t to the gl obal di git al and a nalog i ntercon ne cts ,

Analog

Input

Muxing

providing access to 8 digital blocks and 12 analog blocks.

The PSoC Core

■ Additional System Resources

❐ I

C™ Slave, Master, and Multi-Master to

400 kHz

❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference

■ Complete Development Tools ❐ Free Development Software

(PSoC™ Designer)

❐ Full-Featured, In-Circuit Emulator and

Programmer

❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Bytes Trace Memory

The PSoC Core is a powerful engine that supports a rich feature set. Th e co re in cl ud es a C PU , memo r y, clocks, and c on fig -

Digital Clocks

Multiply Accum.

POR and LVD

Decimator

I C

System Resets

SYSTEM RESOURCES

Internal Voltage

Ref.

Switch

Mode Pump

urable GPIO (General Purpose IO). The M8C C PU core is a powerfu l proce ssor wit h spee ds up t o

24 MHz, providing a four MI PS 8-bit Harvar d archit ecture m icro-

August 3, 2004 © Cypress MicroSystems, Inc. 2002 – 2004 — Document No. 38-12012 Rev. *I 1

CY8C27x43 Final Data Sheet PSoC™ Overview

processor. The CPU utilizes an interrupt controller with 17 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT).

Memory encompas s es 16 KB of Flash for program s tora ge, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection.

The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Cloc k (RT C) and can opti onally genera te a crys tal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device.

PSoC GPIOs provide conne ct ion t o the CP U, di gital and analog resources of the devi ce. Each pin’ s dri ve mod e may b e selec te d from eight options, allowing great flexibility in external interfacing. Every pin also has the c apa bility to gen erate a syste m inte rrupt on high level, low level, and change from last read.

The Digital System

The Digital System is composed of 8 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to fo rm 8, 16 , 24, and 32-bit p eriphe rals, wh ich are called user module references.

Port 4 Port 3 Port 2 Port 1 Port 0Port 5

To System Bus

DIGITAL SYSTEM

Digital PSoC Bl ock Array

Row 0

DBB00 DBB01 DCB02 DCB03

Row Input

Configuration

Row 1

DBB10 DBB11 DCB12 DCB13

Row Input

Configuration

To Analog

System

Configuration

Row Output

Configuration

Row Output

Digital peripheral configurations include those listed below.

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 32 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity (up to 2)

■ SPI master and slave (up to 2)

■ I2C slave and master (1 available as a System Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA (up to 2)

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This co nfig ura bil ity free s y our d e si gn s fro m th e co nstraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled “PSoC Device Charac-

teristics” on page 3.

The Analog System

The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requiremen ts. Some of the more comm on PSoC analog fun ctions (most available as user modules) are listed below.

■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolu-

tion, selectable as Incr emental, Delta Sigma, and SAR)

■ Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 4, with selectable gain to 48x)

■ Instrumentation amplifiers (up to 2, with selectable gain to

93x)

■ Comparators (up to 4, with 16 selectable thresholds)

■ DACs (up to 4, with 6- to 9-bit resolution)

■ Multiplying DACs (up to 4, with 6- to 9-bit resolution)

■ High current output drivers (four with 30 mA drive as a Core

Resource)

■ 1.3V refer ence (as a System Resource)

■ DTMF dialer

■ Modulators

■ Correlators

■ Peak detectors

■ Many other topologies possible

GIE[7:0]

GIO[7:0]

Global Digital

Interconnect

GOE[7:0]

GOO[7:0]

Digital System Block Diagram

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CY8C27x43 Final Data Sheet PSoC™ Overview

Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below.

P0[7]

P0[5]

P0[3] P0[1]

P2[3]

P2[1]

Array Input Configuration

ACI0[1:0] ACI3[1:0]

ACB00 ACB01

ACI1[1:0] ACI2[1:0]

Block Array

ACB02 ACB03

P0[6]

P0[4]

P0[2] P0[0]

P2[6]

RefIn

P2[4]

AGNDIn

P2[2] P2[0]

Additional System Resources

System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below.

■ Digital clock dividers provide three customizable clock fre-

quencies for use in applic ations . The clo cks c an be route d to both the digital a nd analog systems. Additiona l clocks c an be generated using digital PSoC blocks as clock dividers.

■ A multiply accumulate (MAC) provides a fast 8-bit multiplier

with 32-bit accumula te, to assi st in both genera l math as well as digital filters.

■ The decimator provides a custom hardware filter for digital

signal processing applications inc lud in g t he c r eati on of D e lta Sigma ADCs.

■ The I2C module provides 100 and 400 kHz communication

over two wires. Slave, master, and multi-master modes are all supported.

■ Low Voltage Detection (LVD) interrupts can signal the appli-

cation of f alling voltage levels, w hile the adv anced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V refe rence provides an absolute reference fo r

the analog system, including ADCs and DACs.

■ An integrated switch mode pump (S MP) gene rate s norm al

operating volt ages f rom a single 1.2V batt ery cel l, providin g a low cost boost converter.

ASC10

Interface to

Digital System

M8C Interface (Address Bus, Data Bus, Etc.)

ASD11

ASC21

AGND

RefHi RefLo

ASC12 ASD13

ASD22 ASC23ASD20

Analog Reference

Analog System Block Diagram

Reference

Generators

AGNDIn RefIn Bandga

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is shown in the second row of the table.

PSoC Device Characteristics

PSoC Part

Number

CY8C29x66

CY8C27x43

CY8C24x23

CY8C24x23A

CY8C22x13

Digital

up to

Rows

Digital

4 16 12 4 4 12

2 8 12 4 4 12

1 4 12 2 2 6

1 4 8 1 1 3

Inputs

Blocks

Analog

Outputs

Analog

Columns

Blocks

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CY8C27x43 Final Data Sheet PSoC™ Overview

Getting Started

The quickest path to understanding th e PSoC s ili co n is by rea ding this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC™ Mixed Signal Array Technical Reference Manual.

For up-to-date Ordering, Packag ing, an d Electri cal Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com/psoc.

Development Kits

Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at http://www.onfulfillment.com/cypressstore/ contains develop- ment kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view a current list of available items.

Tele-Training

Free PSoC "Tele-training" is available for beginners and taught by a live marketing or appli ca tio n eng in eer ov er th e pho ne . F ive training cl asses are availabl e to accelerate th e learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the tele-training, see http://www.cypress.com/support/training.cfm.

Consultants

Certified PSoC Consultants offer everything from technical assistance to complete d PSoC d esign s. To contact or be come a PSoC Consultant, go to the following Cypress support web site:

http://www.cypress.com/support/cypros.cfm.

Development Tools

The Cypress MicroSystems PSoC Designer is a Microsoft Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)

PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs.

PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.

PSoC

Designer

Importable

Design

Database

Device

Database

Application

Database

Project

Database

Graphical Designer

Interface

Results

Commands

PSoC

Designer

Core

Engine

Context

Sensitive

Help

PSoC

Configuration

Sheet

Manufacturing

Information

File

Technical Support

PSoC application engineers take pride in fast and accurate

User

Modules

Library

response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.

Application Notes

A long list of application notes will assist you in every aspect of

Emulation

Pod

In-Circuit Emulator

your design effort. To locate the PSoC application notes, go to

http://www.cypress.com/design/results.cfm.

PSoC Designer Subsystems

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Device

Programmer

CY8C27x43 Final Data Sheet PSoC™ Overview

PSoC Designer Software Subsystems

Device Editor

The Device Edi tor su bsys tem al lows the use r to se lect differ ent onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.

PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an ap pli cat ion f ram ewor k. The fram ew ork con tains soft ware to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PS o C De s ig ne r c a n pri nt ou t a co n f ig ur at io n s he et fo r a given project configuration for use during application programming in conj unc tion with the Devi ce Da ta Shee t. On ce t he framework is generated, t he user can add a pplication-spe cific code to flesh out the framework. It’s also possible to change the selected component s and rege nera te the fram ew or k.

Design Browser

The Design Bro wser allows users to select an d import prec onfigured desi g ns int o th e u se r’s project. Us er s ca n ea s il y bro w se a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tool s i ncl ud e a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader.

Application Editor

In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build.

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical s ystem while pr ovidi ng an i nter nal vie w of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting st arte d.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consist s of a bas e unit th at conne ct s to the PC by way of the parallel or USB port. The base unit is universal and will operate with all PSoC devices. Emulati on pods for each device family ar e ava ilabl e sep arate ly. The emulation pod t akes the place of the PSoC device in the targ et board and performs full speed (24 MHz) operation.

Assembler. T he macro assembler all ows the assembly code

to be merged seamlessly with C code. The link libraries automatically use abso lut e addre ssing or ca n be co mpil ed in re lat ive mode, and linked with other software modules to get absolute addressing.

C Language Compiler. A C language compiler is available

that supports Cypress MicroSystems’ PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices.

The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

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CY8C27x43 Final Data Sheet PSoC™ Overview

Designing with User Modules

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and d igital hard ware blocks give the PS oC archite cture a unique flexibility that p ays d ivide nds in mana gi ng specifi catio n change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses, and to the IO pins. Iterative devel op men t cy cl es perm it y ou to ada pt th e hardware as well as the software. This substantially lowers the risk that you will have to select a different part to meet the final design requirements.

To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections.

Each user mod ule establishes the basi c register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular applicati on. For exam ple, a Puls e Width Modula tor User Module configures one or more digital PSoC blocks, one for each 8 bits of reso lution. The user mod ule parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run-time. The API als o provides o ptional int errupt serv ice routines that you can adapt as needed.

The API functions are documented in user module data sheets that are viewed directly in the PSo C D esi gn er IDE. Th es e data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module.

The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and- cli ck si mplic ity. Next, you b uil d si gnal chain s by int erconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to develo ping co de for the proj ect, yo u perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.

Device Editor

User

Module

Selection

Placement

and

Parameter

-ization

Source

Code

Generator

Generate Application

Application Editor

Project

Manager

Source

Code

Editor

Build

Manager

Build All

Debugger

Interface

to ICE

Storage

Inspector

Event &

Breakpoint

Manager

User Module and Source Code Development Flows

The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open t he project sourc e code files (i ncluding all gene rated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming.

The last step in the devel opm en t proc es s t ak es pla ce insi de the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events tha t inc lu de m oni tori ng ad dres s and da t a bu s values, memory locations and external signals.

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CY8C27x43 Final Data Sheet PSoC™ Overview

Document Conventions

Acronyms Used

The following table lists the acronyms that are used in this document.

Acronym Description

AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT continuous time DAC digital-t o-analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory FSR full scale range GPIO general purpose IO GUI graphical user interface HBM human body model ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input/output IPOR imprecise power on reset LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoC™ Programmable System-on-Chip™ PWM pulse width modulator RAM random access memory SC switched capacitor SLIMO slow IMO SMP switch mode pump

Units of Measure

A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 17 lists all the abbreviations used to measure the PSoC devices.

Numeric Naming

Table of Contents

For an in depth discussion and more information on your PSoC device, obtain the

ence Manual

into the following chapters and sections.

1. Pin Information .............................. ..... ...... .................... 8

1.1 Pinouts ................................................................... 8

1.1.1 8-Pin Part Pinout ................................ ............. ....8

1.1.2 20-Pin Part Pinout ........................ .... .... ........... ....9

1.1.3 28-Pin Part Pinout ........................ .... .... ........... ..10

1.1.4 44-Pin Part Pinout ........................ .... .... ........... ..11

1.1.5 48-Pin Part Pinouts ...........................................12

2. Register Reference ..................................................... 14

2.1 Register Conventions ...........................................14

2.2 Register Mapping Tables ..................................... 14

3. Electrical Specifications ............................................ 17

3.1 Absolute Maximum Ratings .............. ..... ...... ...... .18

3.2 Operating Temperature .......................................18

3.3 DC Electrical Characteristics ................................ 19

3.3.1 DC Chip-Level Specifications .............................19

3.3.2 DC General Purpose IO Specifications ..............19

3.3.3 DC Operational Amplifier Specifications ............20

3.3.4 DC Analog Output Buffer Specifications ............22

3.3.5 DC Switch Mode Pump Specifications ...............23

3.3.6 DC Analog Reference Specifications .................24

3.3.7 DC Analog PSoC Block Specifications ...............26

3.3.8 DC POR and LVD Specifications .......................26

3.3.9 DC Programming Specifications ........................27

3.4 AC Electrical Characteristics ................................28

3.4.1 AC Chip-Level Spec ifications .............................28

3.4.2 AC General Purpose IO Specifications ..............30

3.4.3 AC Operational Amplifier Specifications .............31

3.4.4 AC Digital Block Specifications ..........................32

3.4.5 AC Analog Output Buffer Specifications .............33

3.4.6 AC External Clock Specifications .......................34

3.4.7 AC Programmi n g Spe c ifications .........................34

3.4.8 AC I2C Specifications ................ .............. ...........35

4. Packaging Information ............................................... 36

4.1 Packaging Dimensions .........................................36

4.2 Thermal Impedances .......................................... 41

4.3 Capacitance on Crystal Pins ............................... 41

5. Ordering Information .................................................. 42

5.1 Ordering Code Definitions ...................................43

6. Sales and Service Information .................................. 44

6.1 Revision History ...................................................44

6.2 Copyrights and Code Protection .......................... 44

PSoC Mixed Signal Array Technical Refer-

. This document encompasses and is organized

Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexi d ec im al nu mb ers ma y al so be rep r es en ted by a ‘0 x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.

August 3, 2004 Document No. 38-12012 Rev. *I 7

1. Pin Information

This chapter describes, lists, and illustrates the CY8C27x43 PSoC device pins and pinout configurations.

1.1 Pinouts

The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.

1.1.1 8-Pin Part Pinout

Table 1-1. 8-Pin Part Pinout (PDIP)

Pin No.

1 IO IO P0[5] Analog column mux input and column output. 2 IO IO P0[3] Analog column mux input and column output. 3 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) 4 Power Vss Ground c onnection. 5 IO P1[0] Crystal Output (XTALout), I2C Serial Data

6 IO IO P0[2] Analog column mux input and column output. 7 IO IO P0[4] Analog column mux input and column output. 8 Power Vdd Supply voltage.

Type

Digital Analog

Name

Description

(SDA)

CY8C27143 8-Pin PSoC Device

AIO, P0[5]

AIO, P0[3]

I2C SCL, XTALin, P1[1]

Vss

1 2

PDIP

3 4

Vdd

P0[4], AIO

P0[2], AIO

P1[0], XTALout , I2 C SD

LEGEND: A = Analog, I = Input, and O = Output.

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CY8C27x43 Final Data Sheet 1. Pin Information

1.1.2 20-Pin Part Pinout

Table 1-2. 20-Pin Part Pinout (SSOP, SOIC)

Pin No.

6 IO P1[7] I2C Serial Clock (SCL) 7 IO P1[5] I2C Serial Data (SDA) 8 IO P1[3] 9 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) 10 Power Vss Ground connection. 11 IO P1[0] Crystal Output (XTALout), I2C Serial Data

12 IO P1[2] 13 IO P1[4] Optional External Clock Input (EXTCLK)

14 IO P1[6] 15 Input XRES Active high external reset with internal pull

16 IO I P 0[0] Analog column mux input. 17 IO IO P0[2] Analog column mux input and column output. 18 IO IO P0[4] Analog column mux input and column output. 19 IO I P 0[6] Analog column mux input. 20 Power Vdd Supply voltage.

Type

Digital Analog

Name

external components requi red .

(SDA)

down.

Description

I2C SCL, XTALin, P1[1]

CY8C27243 20-Pin PSoC Device

AI, P0[7] AIO, P0[5] AIO, P0[3]

AI, P0[1]

SMP

I2C SCL, P1[7]

I2C SDA, P1[5]

P1[3]

Vss

1 2 3 4 5 6 7 8 9

SSOP

SOIC

20 19 18 17 16 15 14 13 12 11

Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SD

LEGEND: A = Analog, I = Input, and O = Output.

August 3, 2004 Document No. 38-12012 Rev. *I 9

CY8C27x43 Final Data Sheet 1. Pin Information

1.1.3 28-Pin Part Pinout

Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC)

Pin No.

1 IO I P0[7] Analog column mux input. 2 IO IO P0[5] Analog column mux input and column output. 3 IO IO P0[3] Analog column mux input and column output. 4 IO I P0[1] Analog column mux input. 5 IO P2[7] 6 IO P2[5] 7 IO I P2[3] Direct switched capacitor block input. 8 IO I P2[1] Direct switched capacitor block input. 9 Power SMP Switch Mode Pump (SMP) connection to

10 IO P1[7] I2C Serial Clock (SCL) 11 IO P1[5] I2C Serial Data (SDA) 12 IO P1[3] 13 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) 14 Power Vss Ground connection. 15 IO P1[0] Crystal Output (XTALout), I2C Serial Data

16 IO P1[2] 17 IO P1 [4] Optio na l Exter nal Clock Inpu t (EXT CLK) 18 IO P1[6] 19 Input XRES Active high external reset with internal pull

20 IO I P2[0] Direct switched capacitor block input. 21 IO I P2[2] Direct switched capacitor block input. 22 IO P2[4] External Analog Ground (AGND) 23 IO P2[6] External Voltage Reference (VRef) 24 IO I P0[0] Analog column mux input. 25 IO IO P0[2] Analog column mux input and column output. 26 IO IO P0[4] Analog column mux input and column output. 27 IO I P0[6] Analog column mux input. 28 Power Vdd Supply voltage.

Type

Digital Analog

Name

external components required.

(SDA)

down.

Description

I2C SCL, XTALin, P1[1]

CY8C27443 28-Pin PSoC Device

AI, P0[7] AIO, P0[5] AIO, P0[3]

AI, P0[1]

P2[7] P2[5]

AI, P2[3]

AI, P2[1]

SMP I2C SCL, P1[7] I2C SDA, P1[5]

P1[3]

Vss

10 11 12 13 14

1 2 3 4 5 6 7 8 9

PDIP

SSOP

SOIC

28 27 26 25 24 23 22 21 20 19 18 17 16 15

Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SD

LEGEND: A = Analog, I = Input, and O = Output.

August 3, 2004 Document No. 38-12012 Rev. *I 10

CY8C27x43 Final Data Sheet 1. Pin Information

D A A

1.1.4 44-Pin Part Pinout

Table 1-4. 44-Pin Part Pinout (TQFP)

Pin No.

1 IO P2[5] 2 IO I P2[3] Direct switched capacitor block input. 3 IO I P2[1] Direct switched capacitor block input. 4 IO P4[7] 5 IO P4[5] 6 IO P4[3] 7 IO P4[1] 8 Power SMP Switch Mode Pump (SMP) connection to

9 IO P3[7] 10 IO P3[5] 11 IO P3[3] 12 IO P3[1] 13 IO P1[7] I2C Serial Clock (SCL) 14 IO P1[5] I2C Serial Data (SDA) 15 IO P1[3] 16 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) 17 Power Vss Ground connection. 18 IO P1[0] Crystal Output (XTALout), I2C Serial Data

19 IO P1[2] 20 IO P1[4] Optional External Clock Input (EXTCLK)

21 IO P1[6] 22 IO P3[0] 23 IO P3[2] 24 IO P3[4] 25 IO P3[6] 26 Input XRES Active high external reset with internal pull

27 IO P4[0] 28 IO P4[2] 29 IO P4[4] 30 IO P4[6] 31 IO I P2[0] Direct switched capacitor block input. 32 IO I P2[2] Direct switched capacitor block input. 33 IO P2[4] External Analog Ground (AGND) 34 IO P2[6] External V oltage Re ference (VR ef) 35 IO I P0[0] Analog column mux input. 36 IO IO P0[2] Analog colum n mux input and column output. 37 IO IO P0[4] Analog colum n mux input and column output. 38 IO I P0[6] Analog column mux input. 39 Power Vdd Supply voltage. 40 IO I P0[7] Analog column mux input. 41 IO IO P0[5] Analog colum n mux input and column output. 42 IO IO P0[3] Analog colum n mux input and column output. 43 IO I P0[1] Analog column mux input. 44 IO P2[7]

Type

Digital Analog

Name

external components requi re d.

(SDA)

down.

Description

CY8C27543 44-Pin PSoC Device

P2[7]

P0[1], AI

P0[3], AIO

P0[5], AIO

P0[7], AI

Vdd

P0[6], AI

P0[4], AIO

P0[2], AIO

P0[0], AI

P2[6 ], Extern al VRe

I2C SDA, P1[5]

TQFP

P1[3]

I2C SCL, X TALin , P1[1]

Vss

I2C SDA, XTALout, P1[0]

192021

P1[2]

EXTCLK, P1[4]

33 32 31 30 29 28 27 26

25 24 23

P1[6]

P3[0]

P2[5] I, P2[3] I, P2[1]

P4[7]

P4[5]

P4[3]

P4[1]

SMP XRES P3[7] P3[5] P3[4]

P3[3]

4443424140

1 2 3 4 5 6 7 8 9

10 11

P3[1]

I2C SCL, P1[7]

P2[4], External AGN P2[2], AI P2[0], AI P4[6] P4[4] P4[2] P4[0]

P3[6]

P3[2]

LEGEND: A = Analog, I = Input, and O = Output.

August 3, 2004 Document No. 38-12012 Rev. *I 11

CY8C27x43 Final Data Sheet 1. Pin Information

1.1.5 48-Pin Part Pinouts

Table 1-5. 48-Pin Part Pinout (SSOP)

Pin No.

14 IO P3[7] 15 IO P3[5] 16 IO P3[3] 17 IO P3[1] 18 IO P5[3] 19 IO P5[1] 20 IO P1[7] I2C Serial Clock (SCL) 21 IO P1[5] I2C Serial Data (SDA) 22 IO P1[3] 23 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) 24 Power Vss Ground connecti on. 25 IO P1[0] Crystal Output (XTALout), I2C Serial Data

26 IO P1[2] 27 IO P1[4] Optional External Clock Input (EXTCLK) 28 IO P1[6] 29 IO P5[0] 30 IO P5[2] 31 IO P3[0] 32 IO P3[2] 33 IO P3[4] 34 IO P3[6] 35 Input XRES Active high external reset with internal pull

36 IO P4[0] 37 IO P4[2] 38 IO P4[4] 39 IO P4[6] 40 IO I P2[0] Direct switched capacitor block input. 41 IO I P2[2] Direct switched capacitor block input. 42 IO P2[4] External Analog Ground (AGND) 43 IO P2[6] External Voltage Reference (VRef) 44 IO I P0[0] Analog column mux input. 45 IO IO P0[2] Analog column mux input and column output. 46 IO IO P0[4] Analog column mux input and column output. 47 IO I P0[6] Analog column mux input. 48 Power Vdd Supply voltage.

Type

Digital Analog

Name

external co mponents required.

(SDA)

down.

Description

2C SCL, XTALin, P1[1]

CY8C27643 48-Pin PSoC Device

AI, P0[7] AIO, P0[5] AIO, P0[3]

AI, P0[1]

P2[7]

P2[5] AI, P2[3] AI, P2[1]

P4[7]

P4[5]

P4[3]

P4[1]

SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1]

I2C SCL, P1[7]

I2C SDA, P1[5]

P1[3]

Vss

1 2 3 4 5 6 7 8 9

10 11 12

SSOP

13 14 15 16 17 18 19 20 21 22 23 24

Vdd

P0[6], AI

P0[2], AIO

P0[4], AIO

P0[0], AI

P2[6], External VRef

P2[4], External AGND

P2[2], AI

P2[0], AI

P4[6]

P4[4]

P4[2]

P4[0]

XRES

P3[6]

P3[4]

P3[2]

P3[0]

P5[2]

P5[0]

P1[6]

P1[4], EXTCLK

P1[2]

P1[0], XTALout, I2C SD

LEGEND: A = Analog, I = Input, and O = Output.

August 3, 2004 Document No. 38-12012 Rev. *I 12

CY8C27x43 Final Data Sheet 1. Pin Information

A A

Table 1-6. 48-Pin Part Pinout (MLF*)

Pin No.

1 IO I P2[3] Direct switched capacitor block input. 2 IO I P2[1] Direct switched capacitor block input. 3 IO P4[7] 4 IO P4[5] 5 IO P4[3] 6 IO P4[1] 7 Power SMP Switch Mode Pump (SMP) connection to

8 IO P3[7] 9 IO P3[5] 10 IO P3[3] 11 IO P3[1] 12 IO P5[3] 13 IO P5[1] 14 IO P1[7] I2C Serial Clock (SCL) 15 IO P1[5] I2C Serial Data (SDA) 16 IO P1[3] 17 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) 18 Power Vss Ground connection. 19 IO P1[0] Crystal Output (XTALout), I2C Serial Data

20 IO P1[2] 21 IO P1[4] Optional External Clock Input (EXTCLK) 22 IO P1[6] 23 IO P5[0] 24 IO P5[2] 25 IO P3[0] 26 IO P3[2] 27 IO P3[4] 28 IO P3[6] 29 Input XRES Active high external reset with internal pull

30 IO P4[0] 31 IO P4[2] 32 IO P4[4] 33 IO P4[6] 34 IO I P2[0] Direct switched capacitor block input. 35 IO I P2[2] Direct switched capacitor block input. 36 IO P2[4] External Analog Ground (AGND) 37 IO P2[6] External Voltage Reference (VRef) 38 IO I P0[0] Analog column mux input. 39 IO IO P0[2] Analog col umn mux input and column output. 40 IO IO P0[4] Analog col umn mux input and column output. 41 IO I P0[6] Analog column mux input. 42 Power Vdd Su pply vol tage . 43 IO I P0[7] Analog column mux input. 44 IO IO P0[5] Analog col umn mux input and column output. 45 IO IO P0[3] Analog col umn mux input and column output. 46 IO I P0[1] Analog column mux input. 47 IO P2[7] 48 IO P2[5]

Type

Digital Analog

Name

external components required.

(SDA)

down.

Description

I, P2[3] I, P2[1]

P4[7] P4[5] P4[3] P4[1]

SMP P3[7] P3[5] P3[3] P3[1] P5[3]

CY8C27643 48-Pin PSoC Device

P2[5]

P2[7]

P0[1], AI

P0[3], AIO

P0[5], AIO

P0[7], AI

Vdd

P0[6], AI

P0[4], AIO

P0[2], AIO

P0[0], AI

P2[6], Extern al VRe

4847464544

1 2 3 4 5 6 7 8 9

10 11

131415161718192021

P5[1]

I2C SCL, P1[7]

43424140393837

MLF

(Top View)

Vss

P1[3]

I2C SDA, P1[5]

I2C SCL , X T ALin, P1 [1 ]

P1[2]

I2C SDA, XTALout, P1[0]

36 35 34 33 32 31 30 29 28 27 26

P1[6]

P5[0]

P5[2]

EXTC L K , P 1 [4 ]

P2[4], External AGN P2[2], AI P2[0], AI

P4[6] P4[4] P4[2] P4[0] XRES

P3[6] P3[4]

P3[2] P3[0]

LEGEND: A = Analog, I = Input, and O = Output.

* The MLF package has a center pad that must be connected to ground (Vss).

August 3, 2004 Document No. 38-12012 Rev. *I 13

2. Register Reference

This chapter lists the registers of the CY8C27x43 PSoC device. For detailed register information, reference the PSoC™ Mixed Sig-

nal Array Technical Reference Manual

2.1 Register Conventions

The register conventions specific to this section are listed in the following table.

Convention Description

R Read register or bit(s) W Write register or bit(s) L Logical regi ster or bit(s) C Clearable register or bit(s) # Access is bit specific

2.2 Register Mapping Tables

The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag regist er (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in bank 1.

Note In the foll owing reg ister mappi ng tables, blank fiel ds are

reserved and should not be accessed.

August 3, 2004 © Cypress MicroSystems, Inc. 2003 — Document No. 38-12012 Rev. *I 14

CY8C27x43 Final Data Sheet 2. Register Reference

Access

Name

PRT0DR 00 RW 40 ASC10CR0 80 RW C0 PRT0IE 01 RW 41 ASC10CR1 81 RW C1 PRT0GS 02 RW 42 ASC10CR2 82 RW C2 PRT0DM2 03 RW 43 ASC10CR3 83 RW C3 PRT1DR 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 PRT2DR 08 RW 48 ASC12CR0 88 RW C8 PRT2IE 09 RW 49 ASC12CR1 89 RW C9 PRT2GS 0A RW 4A ASC12CR2 8A RW CA PRT2DM2 0B RW 4B ASC12CR3 8B RW CB PRT3DR 0C RW 4C ASD13CR0 8C RW CC PRT3IE 0D RW 4D ASD13CR1 8D RW CD PRT3GS 0E RW 4E ASD13CR2 8E RW CE PRT3DM2 0F RW 4F ASD13CR3 8F RW CF PRT4DR 10 RW 50 ASD20CR0 90 RW D0 PRT4IE 11 RW 51 ASD20CR1 91 RW D1 PRT4GS 12 RW 52 ASD20CR2 92 RW D2 PRT4DM2 13 RW 53 ASD20CR3 93 RW D3 PRT5DR 14 RW 54 ASC21CR0 94 RW D4 PRT5IE 15 RW 55 ASC21CR1 95 RW D5 PRT5GS 16 RW 56 ASC21CR2 96 RW I2C_CFG D6 RW PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C_SCR D7 #

DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW DCB02DR0 28 # 68 A8 MUL_X E8 W DCB02DR1 29 W 69 A9 MUL_Y E9 W DCB02DR2 2A RW 6A AA MUL_DH EA R DCB02CR0 2B # 6B AB MUL_DL EB R DCB03DR0 2C # 6C AC ACC_DR1 EC RW DCB03DR1 2D W 6D AD ACC_DR0 ED RW DCB03DR2 2E RW 6E AE ACC_DR3 EE RW DCB03CR0 2F # 6F AF ACC_DR2 EF RW DBB10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0 DBB10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1 DBB10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2 DBB10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3 DBB11DR0 34 # ACB01CR3 74 RW RDIOLT1 B4 RW F4 DBB11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBB11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6 DBB11CR0 37 # ACB01CR2 77 RW B7 CPU_F F7 RL DCB12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8 DCB12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9 DCB12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA DCB12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB DCB13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW FC DCB13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW FD DCB13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE # DCB13CR0 3F # ACB03CR2 7F RW BF CPU_SCR0 FF #

Blank fields are Reserved and should not be accessed. # Access is bit specific.

(0,Hex)

Addr

18 58 ASD22CR0 98 RW I2C_DR D8 RW 19 59 ASD22CR1 99 RW I2C_MSCR D9 # 1A 5A ASD22CR2 9A RW INT_CLR0 DA RW 1B 5B ASD22CR3 9B RW INT_CLR1 DB RW 1C 5C ASC23CR0 9C RW DC 1D 5D ASC23CR1 9D RW INT_CLR3 DD RW 1E 5E ASC23CR2 9E RW INT_MSK3 DE RW 1F 5F ASC23CR3 9F RW DF

Name

Access

(0,Hex)

Addr

Name

Access

(0,Hex)

Addr

Name

Access

(0,Hex)

Addr

August 3, 2004 Document No. 38-12012 Rev. *I 15

CY8C27x43 Final Data Sheet 2. Register Reference

Access

Name

PRT0DM0 00 RW 40 ASC10CR0 80 RW C0 PRT0DM1 01 RW 41 ASC10CR1 81 RW C1 PRT0IC0 02 RW 42 ASC10CR2 82 RW C2 PRT0IC1 03 RW 43 ASC10CR3 83 RW C3 PRT1DM0 04 RW 44 ASD11CR0 84 RW C4 PRT1DM1 05 RW 45 ASD11CR1 85 RW C5 PRT1IC0 06 RW 46 ASD11CR2 86 RW C6 PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 PRT2DM0 08 RW 48 ASC12CR0 88 RW C8 PRT2DM1 09 RW 49 ASC12CR1 89 RW C9 PRT2IC0 0A RW 4A ASC12CR2 8A RW CA PRT2IC1 0B RW 4B ASC12CR3 8B RW CB PRT3DM0 0C RW 4C ASD13CR0 8C RW CC PRT3DM1 0D RW 4D ASD13CR1 8D RW CD PRT3IC0 0E RW 4E ASD13CR2 8E RW CE PRT3IC1 0F RW 4F ASD13CR3 8F RW CF PRT4DM0 10 RW 50 ASD20CR0 90 RW GDI_O_IN D0 RW PRT4DM1 11 RW 51 ASD20CR1 91 RW GDI_E_IN D1 RW PRT4IC0 12 RW 52 ASD20CR2 92 RW GDI_O_OU D2 RW PRT4IC1 13 RW 53 ASD20CR3 93 RW GDI_E_OU D3 RW PRT5DM0 14 RW 54 ASC21CR0 94 RW D4 PRT5DM1 15 RW 55 ASC21CR1 95 RW D5 PRT5IC0 16 RW 56 ASC21CR2 96 RW D6 PRT5IC1 17 RW 57 ASC21CR3 97 RW D7

DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

DBB01FN 24 RW 64 A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 E5 DBB01OU 26 RW AMD_CR1 66 RW A6 E6

DCB02FN 28 RW ALT_CR1 68 RW A8 IMO_TR E8 W DCB02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 W DCB02OU 2A RW 6A AA BDG_TR EA RW

DCB03FN 2C RW 6C AC EC DCB03IN 2D RW 6D AD ED DCB03OU 2E RW 6E AE EE

DBB10FN 30 RW ACB00CR3 70 RW RDI0RI B0 RW F0 DBB10IN 31 RW ACB00CR0 71 RW RDI0SYN B1 RW F1 DBB10OU 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2

DBB11FN 34 RW ACB01CR3 74 RW RDIOLT1 B4 RW F4 DBB11IN 35 RW ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBB11OU 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6

DCB12FN 38 RW ACB02CR3 78 RW RDI1RI B8 RW F8 DCB12IN 39 RW ACB02CR0 79 RW RDI1SYN B9 RW F9 DCB12OU 3A RW ACB02CR1 7A RW RDI1IS BA RW FA

DCB13FN 3C RW ACB03CR3 7C RW RDI1LT1 BC RW FC DCB13IN 3D RW ACB03CR0 7D RW RDI1RO0 BD RW FD DCB13OU 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #

Blank fields are Reserved and should not be accessed. # Access is bit specific.

(1,Hex)

Addr

18 58 ASD22CR0 98 RW D8 19 59 ASD22CR1 99 RW D9 1A 5A ASD22CR2 9A RW DA 1B 5B ASD22CR3 9B RW DB 1C 5C ASC23CR0 9C RW DC 1D 5D ASC23CR1 9D RW OSC_GO_EN DD RW 1E 5E ASC23CR2 9E RW OSC_CR4 DE RW 1F 5F ASC23CR3 9F RW OSC_CR3 DF RW

23 AMD_CR0 63 RW A3 VLT_CR E3 RW

27 ALT_CR0 67 RW A7 E7

2B 6B AB ECO_TR EB W

2F 6F AF EF

33 ACB00CR2 73 RW RDI0LT0 B3 RW F3

37 ACB01CR2 77 RW B7 CPU_F F7 RL

3B ACB02CR2 7B RW RDI1LT0 BB RW FB

3F ACB03CR2 7F RW BF CPU_SCR0 FF #

Name

Access

(1,Hex)

Addr

Name

Access

(1,Hex)

Addr

Name

Access

(1,Hex)

Addr

August 3, 2004 Document No. 38-12012 Rev. *I 16

3. Electrical S pecifications

This chapter presents the DC and AC electrical specifications of the CY8C27x43 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40 than 12 MHz are valid for -40

5.25

4.75

Vdd Voltage

C ≤ TA ≤ 85oC and TJ ≤ 100oC, except w here not ed. Specificat ions for devices r unning a t greater

C ≤ TA ≤ 70oC and TJ ≤ 82oC.

3.00

93 kHz 12 MHz 24 MHz

CPU Frequency

Figure 3-1. Voltage versus CPU Frequency

The following table lists the units of measure that are used in this chapter.

Table 3-1: Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

dB decibels mA milli-ampere

fF femto farad ms milli-second Hz hertz mV milli-volts KB 1024 bytes nA nano ampere

Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts

kΩ kilohm Ω ohm

MHz megahertz pA pico ampere

MΩ megaohm pF pico farad

µA micro ampere pp peak-to-peak µF micro farad ppm parts per million µH micro henry ps picosecond µs microsecond sps samples per second µV micro volts σ sigma: one standard deviation

µVrms micro volts root-mean-square V volts

degree Cels i us µW micro watts

August 3, 2004 Document No. 38-12012 Rev. *I 17

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.1 Ab solute Maximum Ratings

Table 3-2. Absolute Maximum Ratings

Symbol Description Min Typ Max Units Notes

STG

Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V V

– DC Voltage Applied to Tri-state Vss - 0.5 – Vdd + 0.5 V I

MIO

MAIO

ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD – Latch-up Current – – 200 mA

Storag e Temperature -55 – +100

Ambient Temperature with Power Applied -40 – +85

DC Input Voltage Vss- 0.5 – Vdd + 0.5 V

Maximum Current into any Port Pin -25 – +50 mA Maximum Current into any Port Pin Configured as Analog

Driver

-50 – +50 mA

Higher storage temperatures will reduce data retention time.

3.2 Operating Temperature

Table 3-3. Operating Temperature

Symbol Description Min Typ Max Units Notes

Ambient Temperature -40 – +85 Junction Temperature -40 – +100

The temperature rise from ambient to junction is package specific. See “Thermal Impedances”

on page 41. The user must limit the power con-

sumption to comply with this requirement.

August 3, 2004 Document No. 38-12012 Rev. *I 18

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.3 DC Electrical Characteristics

3.3.1 DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

°C ≤ T

are for design guidance only.

Table 3-4. DC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

Vdd Supply Voltage 3.00 – 5.25 V I

DD3

SBH

SBXTL

SBXTLH

REF

a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devi c e s t ha t ha ve si m i la r fu n cti o ns

enabled.

b. Refer to the Order ing Info rm atio n chapter on page 4 2.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, re sp ect i ve ly. Typical paramete r s app ly t o 5 V an d 3 .3V at 2 5°C and

Supply Current – 5 8 mA

Supply Current – 3.3 6.0 mA

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

WDT. Sleep (Mode) Current with POR, LVD, Sleep Timer, and

WDT at high temperature. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,

and external crystal.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.

Reference Voltage (Bandgap) for Silicon A Reference Voltage (Bandgap) for Silicon B

b b

– 3 6.5 µA Conditions are with internal slow speed oscilla-

– 4 25 µA Conditions are with internal slow speed oscilla-

– 4 7.5 µA Conditions are with pr operly loaded , 1 µW max,

– 5 26 µA Conditions are with prope rl y loaded, 1 µW max,

1.275 1.300 1.325 V Trimmed for appropriate Vdd.

1.280 1.300 1.320 V Trimmed for appropriate Vdd.

Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, 48 MHz = Disabled. VC1 = 1.5 MHz, VC2

= 93.75 kHz, VC3 = 93.75 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3

MHz, 48 MHz = Disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz.

tor, Vdd = 3.3V, -40

tor, Vdd = 3.3V, 55

32.768 kHz crystal. V dd = 3.3V, -40

32.768 kHz crystal. Vdd = 3.3V, 55

C ≤ TA ≤ 55 oC.

C < TA ≤ 85 oC.

C ≤ TA ≤

C < TA ≤ 85

3.3.2 DC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

°C ≤ T

are for design guidance only.

Table 3-5. DC GPIO Specifications

Symbol Description Min Typ Max Units Notes

OUT

August 3, 2004 Document No. 38-12012 Rev. *I 19

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, re sp ect i ve ly. Typical paramete r s app ly t o 5 V an d 3 .3V at 2 5°C and

Pull up Resistor 4 5.6 8 kΩ Pull down Resistor 4 5.6 8 kΩ High Output Level Vdd - 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,

Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 tot al load s,

Input Low Level – – 0.8 V Vdd = 3.0 to 5.25 Input High Level 2.1 – V Vdd = 3.0 to 5.25 Input Hysterisis – 60 – mV Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 µA. Capacitive Load on Pins as Input – 3.5 10 pF Capacitive Load on Pins as Output – 3.5 10 pF

4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pi ns (for exam pl e, P0[3], P1[ 5])).

Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC.

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.3.3 DC Operational Amplifier Specifications

The follo wing tabl es l is t gua ran tee d ma xim um an d mi nim um sp eci fic ati ons for the volta ge a nd temp erat ur e ra nge s: 4.75V to 5. 25V and -40

°C ≤ T

are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC

blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at

°C and are for design guidance only.

T able 3-6. 5V DC Operatio nal A mpli fier Sp ecifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV

OSOA

EBOA

INOA

CMOA

CMRR

OLOA

OHIGHOA

OLOWOA

SOA

PSRR

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, re sp ect i ve ly. Typical paramete r s app ly t o 5 V an d 3 .3V at 2 5°C and

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Average Input Offset Voltage Drift – 7.0 35.0

Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 µA. Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Common Mode Voltage Range

Common Mode Voltage Range (high power or high opamp bias)

Common Mode Rejection Ratio Power = Low Power = Medium Power = High Open Loop Gain Power = Low Power = Medium Power = High High Output Voltage Swing (in ternal signal s) Power = Low Power = Medium Power = High Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High Supply Current (including associated AGND buff er) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejectio n Ra tio 60 – – dB 0V ≤ VIN ≤ (Vdd - 2.25 ) or

–1.6 – –

0.0 – Vdd

0.5 –

60 60 60

60 60 80

Vdd - 0.2 Vdd - 0.2 Vdd - 0.5

– – –

– – – – – –

1.3

1.2

– – dB Specification is applicable at high power. For all

– – –

150 300 600 1200 2400 4600

10 8

7.5

Vdd - 0.5

– – –

0.2

0.5

200 400 800 1600 3200 6400

mV mV mV

µV/

Package and pin dependent. Temp = 25

V The common-mode input voltage range is mea-

V V V

µA µA µA µA µA µA

sured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.

other bias modes (except high power, high opamp bias), minimum is 60 dB.

≤ V

(Vdd - 1.25V)

≤ Vdd.

August 3, 2004 Document No. 38-12012 Rev. *I 20

CY8C27x43 Final Data Sheet 3. Electrical Specifications

Table 3-7. 3.3V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV

OSOA

EBOA

INOA

CMOA

CMRR

OLOA

OHIGHOA

OLOWOA

SOA

PSRR

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High

– –

1.65

1.32

10 8

mV High Power is 5 Volt s On ly Average Input Offset Voltage Drift – 7.0 35.0

µV/

Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 µA. Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage range is

Package and pin dependent. Temp = 25

measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.

Common Mode Rejection Ratio

Power = Low Power = Medium Power = High Open Loop Gain Power = Low Power = Medium Power = High

50 50 50

60 60 80

– – dB Specification is applicable at high power. For

all other bias modes (except high power, high opamp bias), minimum is 60 dB.

– – dB Specification is applicable at high power. For

all other bias modes (except high power, high opamp bias), minimum is 60 dB.

High Output Voltage Swing (in ternal signal s) Power = Low Power = Medium Power = High is 5V only

Vdd - 0.2 Vdd - 0.2 Vdd - 0.2

– – –

V Low Output Voltage Swing (internal signals) Power = Low Power = Medium

Power = High

– – –

0.2

V Supply Current (including associated AGND buff er) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio 50 – – dB 0V ≤ VIN ≤ (Vdd - 2.25) or

– – – – – –

150 300 600 1200 2400 4600

200 400 800 1600 3200 6400

µA

(Vdd - 1.25V)

≤ V

≤ Vdd.

August 3, 2004 Document No. 38-12012 Rev. *I 21

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.3.4 DC Analog Output Buffer Specifications

The follo wing tabl es l is t gua ran tee d ma xim um an d mi nim um sp eci fic ati ons for the volta ge a nd temp erat ur e ra nge s: 4.75V to 5. 25V and -40

°C ≤ T

are for design guidance only.

Table 3-8. 5V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

OSOB

TCV

OSOB

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, re sp ect i ve ly. Typical paramete r s app ly t o 5 V an d 3 .3V at 2 5°C and

Input Off set Voltage (Absolute Value) – 3 12 mV Average I nput Offset Voltage Drift – +6 – µV/°C Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V Output Resistance

Power = Low Power = High High Output Voltage Swing (Load = 32 ohms to Vdd/2)

Power = Low Power = High

Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High

Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio 60 – – dB

– –

0.5 x Vdd + 1.3

0.5 x Vdd

– –

+ 1.3

1 1

– –

1.1

2.6

– –

0.5 x Vdd - 1.3

0.5 x Vdd

5.1

8.8

- 1.3

Ω

V V

mA mA

Table 3-9. 3.3V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

OSOB

TCV

OSOB

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV Average Input Offset Voltage Drift – +6 – µV/°C Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V Output Resistance

Power = Low Power = High High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High

Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High

Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rej ectio n Ra tio 60 – – dB

– –

0.5 x Vdd + 1.0

0.5 x Vdd

– –

–

+ 1.0

1 1

– –

0.8

2.0

– –

0.5 x Vdd - 1.0

0.5 x Vdd

2.0

4.3

- 1.0

Ω

V V

mA mA

August 3, 2004 Document No. 38-12012 Rev. *I 22

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.3.5 DC Switch Mode Pump Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

°C ≤ T

are for design guidance only.

Table 3-10. DC Switch Mode Pump (SMP) Specifications

Symbol Description Min Typ Max Units Notes

5V 5V Output Voltage 4.75 5.0 5.25 V

PUMP

3V 3V Output Voltage 3.00 3.25 3.60 V

PUMP

5V Input Voltage Range from Battery 1.8 – 5.0 V

BAT

3V Input Voltage Range from Battery 1.0 – 3.3 V

BAT

BATSTART

∆V

PUMP_Line

∆V

PUMP_Load

∆V

PUMP_Ripple

PUMP

a. L1 = 2 µH inductor, C1 = 10 µF capacitor, D1 = Schottky diode. See Figure3-2.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, re sp ect i ve ly. Typical paramete r s app ly t o 5 V an d 3 .3V at 2 5°C and

Configura tion of f ootnot e

. Average, neglecting

ripple. SMP trip voltage is set to 5.0V .

Configura tion of f ootnot e

. Average, neglecting

ripple. SMP trip voltage is set to 3.25V. Available Output Curren t V V

BAT BAT

= 1.5V, V = 1.8V, V

PUMP PUMP

= 3.25V = 5.0V

8 5

– –

mA mA

SMP trip voltage is set to 3.25V.

SMP trip voltage is set to 5.0V.

Configura tion of footnote

. SMP trip voltage is

set to 5.0V.

Configura tion of footnote

. SMP trip voltage is

set to 3.25V. Minimum Input Voltage from Battery to Start Pump 1.1 – – V

Line Regulation (over V

range) – 5 – %V

BAT

Configura tion of footnote

Configura tion of footnote a. VO is the “Vdd

Value for PUMP Trip” specified by the VM[2:0]

setting in the DC POR and LVD Specification,

Table 3-16 on page 26.

Load Regulation – 5 –

Configura tion of footnote a. VO is the “Vdd

Value for PUMP Trip” specified by the VM[2:0]

setting in the DC POR and LVD Specification,

Table 3-16 on page 26.

Output Voltage Ripple (depends on capacitor/load) – 100 – mVpp Efficiency 35 50 – %

Configura tion of footnote

Configuration of footnote

. Load is 5mA.

. Load is 5 mA. SMP

trip voltage is set to 3.25V. Switching Frequency – 1.3 – MHz

Switching Duty Cycle – 50 – %

BAT

Vdd

Battery

SMP

PSoC

PUM

Vss

Figure 3-2. Basic Switch Mode Pump Circuit

August 3, 2004 Document No. 38-12012 Rev. *I 23

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.3.6 DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only. The guaranteed specific ations are measure d throug h the Anal og Con tinuou s T ime PSo C block s. The powe r level s for AGND refer to

the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high.

Table 3-11. Silicon Revision A – 5V DC Analog Reference Specifications

°C ≤ T

Symbol Description Min Typ Max Units

BG B a ndgap Voltage Reference 1.274 1.30 1.326 V –

– – – – – – RefHi = Vdd/2 + BandGap – RefHi = 3 x Ba ndGap 3 x BG - 0.112 3 x BG - 0.018 3 x BG + 0.076 V

– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077 V – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 V – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6] + 0.100 V – RefHi = 3.2 x BandGap 3.2 x BG - 0.112 3.2 x BG 3.2 x BG + 0.076 V – RefLo = Vdd/2 – BandGap – RefLo = Band Gap BG - 0.082 BG + 0.023 BG + 0.129 V – RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134 V – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110 V

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

AGND = Vdd/2 AGND = 2 x BandGap AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Block to Block Variation (AGND = Vdd/2)

Vdd/2 - 0.030 Vdd/2 - 0.004 Vdd/2 + 0.003 V 2 x BG - 0.043 2 x BG - 0.010 2 x BG + 0.024 V P2[4] - 0.013 P2[4] P2[4] + 0.014 V BG - 0.009 BG BG + 0.009 V

1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V

-0.034 0.000 0.034 V

Vdd/2 + BG - 0.140 Vdd/2 + BG - 0.018 Vdd/2 + BG + 0.103

Vdd/2 - BG - 0.051 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.098

a. AGND tolerance includes the offsets of the local buffer in the PSoC block.

Table 3-12. Silicon Revision B – 5V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG B a ndgap Voltage Reference 1.28 1.30 1.32 V –

– – – – – – RefHi = Vdd/2 + BandGap – RefHi = 3 x Ba ndGap 3 x BG - 0.06 3 x BG - 0.01 3 x BG + 0.06 V

– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.06 2 x BG + P2[6] - 0.01 2 x BG + P2[6] + 0.06 V – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.06 P2[4] + BG - 0.01 P2[4] + BG + 0.06 V – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.06 P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.06 V – RefHi = 3.2 x BandGap 3.2 x BG - 0.06 3.2 x BG - 0.01 3.2 x BG + 0.06 V – RefLo = Vdd/2 – BandGap – RefLo = Band Gap BG - 0.06 BG + 0.01 BG + 0.06 V – RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.04 2 x BG - P2[6] + 0.01 2 x BG - P2[6] + 0.04 V – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.01 P2[4] - BG + 0.056 V – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.056 P2[4] - P2[6] + 0.01 P2[4] - P2[6] + 0.056 V

AGND = Vdd/2 AGND = 2 x BandGap AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Block to Block Variation (AGND = Vdd/2)

Vdd/2 - 0.030 Vdd/2 Vdd/2 + 0.007 V 2 x BG - 0.043 2 x BG 2 x BG + 0.024 V P2[4] - 0.011 P2[4] P2[4] + 0.011 V BG - 0.009 BG BG + 0.009 V

1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V

-0.034 0.000 0.034 V

Vdd/2 + BG - 0.1 Vdd/2 + BG - 0.01 Vdd/2 + BG + 0.1

Vdd/2 - BG - 0.051 Vdd/2 - BG + 0.01 Vdd/2 - BG + 0.06

a. AGND tolerance includes the offsets of the local buffer in the PSoC block.

August 3, 2004 Document No. 38-12012 Rev. *I 24

CY8C27x43 Final Data Sheet 3. Electrical Specifications

Table 3-13. Silicon Revision A – 3.3V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.274 1.30 1.326 V –

–

AGND = Vdd/2

AGND = 2 x BandGap – AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.008 P2[4] + 0.001 P2[4] + 0.009 V –

– –

AGND = BandGap

AGND = 1.6 x BandGap

AGND Block to Block Variation (AGND = Vdd/2) – RefHi = Vdd/2 + BandGap Not Allowed – RefHi = 3 x BandGap Not Allowed – RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V – RefHi = 3.2 x BandGap Not Allowed – RefLo = Vdd/2 - BandGap Not Allowed – RefLo = BandGap Not Allowed – RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048 P2[4] - P2[6] + 0.022 P2[4] - P2[6] + 0.092 V

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.

Vdd/2 - 0.027 Vdd/2 - 0.003 Vdd/2 + 0.002 V Not Allowed

BG - 0.009 BG BG + 0.009 V

1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V

-0.034 0.000 0.034 mV

Table 3-14. Silicon Revision B – 3.3V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.28 1.30 1.32 V –

–

AGND = Vdd/2

AGND = 2 x BandGap – AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.008 P2[4] P2[4] + 0.009 V –

– –

AGND = BandGap

AGND = 1.6 x BandGap

AGND Block to Block Variation (AGND = Vdd/2) – RefHi = Vdd/2 + BandGap Not Allowed – RefHi = 3 x BandGap Not Allowed – RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.06 P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.057 V – RefHi = 3.2 x BandGap Not Allowed – RefLo = Vdd/2 - BandGap Not Allowed – RefLo = BandGap Not Allowed – RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048 P2[4] - P2[6] + 0.01 P2[4] - P2[6] + 0.048 V

Vdd/2 - 0.027 Vdd/2 Vdd/2 + 0.005 V Not Allowed

BG - 0.009 BG BG + 0.009 V

1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V

-0.034 0.000 0.034 mV

August 3, 2004 Document No. 38-12012 Rev. *I 25

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.3.7 DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

°C ≤ T

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-15. DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Units Notes

Resistor Unit Value (Continuous Time) – 12.2 – kΩ Capacitor Unit Value (Switch Cap) – 80 – fF

3.3.8 DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the

Reference Manual

Table 3-16. DC POR and LVD Specifications

°C ≤ T

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

PSoC Mixed Signal Array Technical

for more information on the VLT_CR register.

Symbol Description Min Typ Max Units Notes

PPOR0R

PPOR1R

PPOR2R

PPOR0

PPOR1

PPOR2

PH0

PH1

PH2

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

PUMP0

PUMP1

PUMP2

PUMP3

PUMP4

PUMP5

PUMP6

PUMP7

a. Always greater th an 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater th an 50 mV above PPOR (PORLEV = 10) for falling supply.

Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b

Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b

–

– – –

2.86

2.96

3.07

3.92

4.39

4.55

4.63

4.72

2.96

3.03

3.18

4.11

4.55

4.63

4.72

4.90

2.91

4.39

4.55

2.82

4.39

4.55

92 0 0

2.92

3.02

3.13

4.00

4.48

4.64

4.73

4.81

3.02

3.10

3.25

4.19

4.64

4.73

4.82

5.00

–

– – –

2.98

3.08

3.20

4.08

4.57

4.74

4.82

4.91

3.08

3.16

3.32

4.28

4.74

4.82

4.91

5.10

V V V

mV mV mV

V V

V V V V

V V V

V V V V V V V V V

August 3, 2004 Document No. 38-12012 Rev. *I 26

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.3.9 DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only.

Table 3-17. DC Programming Specifications

°C ≤ T

Symbol Description Min Typ Max Units Notes

DDP

ILP

IHP

ILP

IHP

OLV

OHV

Flash

ENPB

Flash

ENT

Flash

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Supply Current During Programming or Verify – 5 25 mA Input Low Voltage During Programming or Verify – – 0.8 V Input High Voltage During Programming or Verify 2.2 – – V Input Current when Applying Vilp to P1[0] or P1[1] During

Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During

Programming or Verify Output Low Voltage During Programming or Veri fy – – Vss + 0.75 V

Output High Voltage During Programming or Verify Vdd - 1.0 – Vdd V Flash Endurance (per block) 50,000 – – – Erase/write cycles per block. Flash Endurance (total)

Flash Data Retention 10 – – Years

– – 0.2 mA Driving internal pull-down resistor.

– – 1.5 mA Driving internal pull-down resistor.

1,800,000 – – – Erase/write cycles.

a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of

25,000 maxi mu m c yc les ea c h, or 36 x4 bl oc k s o f 12 , 500 max i mu m cyc l e s ea c h ( to lim i t t he to t al nu mb er of cy c l es to 36 x5 0, 0 00 an d that no single block ever sees more than 50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

August 3, 2004 Document No. 38-12012 Rev. *I 27

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.4 AC Electrical Characteristics

3.4.1 AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only.

Table 3-18. AC Chip-Level Specifications

°C ≤ T

Symbol Description Min Typ Max Units Notes

IMO

CPU1

CPU2

48M

24M

32K1

32K2

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Internal Main Oscillator Frequency 23.4 24 CPU Frequency (5V Nominal) 0.93 24 CPU Frequency (3.3V Nominal) 0.93 12 Digital PSoC Block Frequency 0 48

Digital PSoC Block Frequency 0 24 Internal Low Speed Oscillator Fr eq uency 15 32 64 kHz External Crystal Oscillator – 32.768 – kHz

24.6

12.3

49.2

24.6

MHz Trimmed. Utilizing factory trim values.

a,b

MHz Trimmed. Utilizing factory trim values.

b,c

MHz Trimmed. Utilizing factory trim values.

a,b,d

MHz Refer to the AC Digital Block Specifications

b, d

MHz

below.

Accuracy is capacitor and crystal dependent. 50% duty cycle.

PLL

Jitter24M2 24 MHz Period Jitter (PLL) – – 600 ps T

PLLSLEW

PLLSLEWS-

LOW

OSACC

Jitter32k 32 kHz Period Jitter – 100 ns T

XRST

DC24M 24 MHz Duty Cycle 40 50 60 % Step24M 24 MHz Trim Step Size – 50 – kHz Fout48M 48 MHz Output Frequency 46.8 48.0

Jitter24M1 24 MHz Period Jitter (IMO) – 600 ps F

MAX

RAMP

PLL Frequency – 23.986 – MHz

PLL Lock Time 0.5 – 10 ms PLL Lock Time for Low Gain Setting 0.5 – 50 ms

External Crystal Oscillator Startup to 1% – 1700 External Crystal Oscillator Startup to 100 ppm – 2800 3800 ms The crystal oscilla tor fr eque nc y i s wi th in 100 pp m of its

External Reset Pulse Width 10 – – µs

Maximum frequency of signal on row input or row output. – – 12.3 MHz Supply Ramp Time 0 – – µs

2620

49.2

a,c

MHz Trimmed. Utilizing factory trim values.

Multiple (x732) of crystal frequency.

final value by the end of the T operation assum es a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5. 5V, -40

C ≤ TA ≤ 85 oC.

period. Correct

osacc

a. 4.75V < Vdd < 5.25V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V. d. See the individual user module data sheets for information on maximum frequencies for user modules.

PLL nable

PLL

Gain

PLLSLEW

24 MHz

Figure 3-3. PLL Lock Timing Diagram

August 3, 2004 Document No. 38-12012 Rev. *I 28

CY8C27x43 Final Data Sheet 3. Electrical Specifications

PLL nable

PLLSLEWLOW

PLL

24 MHz

PLL

Gain

Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram

32K

elect

32K2

Figure 3-5. External Crystal Oscillator Startup Timing Diagram

Jitter24M1

24M

Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram

32 kHz

Jitter32k

32K2

Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram

August 3, 2004 Document No. 38-12012 Rev. *I 29

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.4.2 AC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only.

Table 3-19. AC GPIO Specifications

°C ≤ T

Symbol Description Min Typ Max Units Notes

GPIO

TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90% TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%

90%

GPIO

Output

oltage

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

GPIO Operating Frequ ency 0 – 12 MHz

10%

TRiseF TRiseS

Figure 3-8. GPIO Timing Diagram

TFallF TFallS

August 3, 2004 Document No. 38-12012 Rev. *I 30

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.4.3 AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only. Settling times, slew rates, and gain bandw idth are based on the Analog Continuous Time PSoC block.

°C ≤ T

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Power = High and Opamp Bias = High is not supported at 3.3V.

Table 3-20. 5V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

ROA

SOA

ROA

FOA

NOA

Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

– – –

0.15

1.7

6.5

0.01

0.5

4.0

0.75

3.1

5.4

– – –

3.9

0.72

0.62

5.9

0.92

0.72

– – –

µs µs µs

µs µs

V/ V/

µs

V/ V/

µs

MHz MHz MHz

Table 3-21. 3.3V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

ROA

SOA

ROA

FOA

NOA

Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

– –

0.31

2.7

0.24

1.8

0.67

2.8

– –

3.92

0.72

5.41

0.72

– –

µs µs

µs

MHz MHz

August 3, 2004 Document No. 38-12012 Rev. *I 31

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.4.4 AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only.

Table 3-22. AC Digital Block Specifications

°C ≤ T

Function Description Min Typ Max Units Notes

All Functions

Timer Capture Pulse Width

Counter Enable Pulse Width

Dead Band Kill Pulse Width:

CRCPRS (PRS Mode)

CRCPRS (CRC Mode)

SPIM Maximum Input C l ock Frequency – – 8.2 MHz Maximum data r ate at 4.1 MHz du e to 2 x over

SPIS Maximum Input Clock Frequency – – 4.1 ns

Transmitter

Receiver

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Maximum Block Clocking Frequency (> 4.75V) 49.2 4.75V < Vdd < 5.25V. Maximum Block Clocking Frequency (< 4.75V) 24.6 3.0V < Vdd < 4.75V.

50 Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V. Maximum Frequency, With Capture – – 24.6 MHz

50 Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V. Maximum Frequency, Enable Input – – 24.6 MHz

Asynchronous Restart Mode 20 – – ns Synchronous Restart Mode

Disable Mode

Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.2 5V . Maximum Input C l oc k Frequency – – 49.2 MHz 4.75V < Vdd < 5.2 5V .

Maximum Input C l oc k Frequency – – 24.6 MHz

Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency

Silicon A

Silicon B

Maximum Input Clock Frequency Silicon A

Silicon B

–

– – ns

–

16.4

24.6

16.4

24.6

MHz

clocking.

Maximum data rate at 2.05 MHz due to 8 x over clocking.

Maximum data rate at 3.08 MHz due to 8 x over clocking.

Maximum data rate at 2.05 MHz due to 8 x over clocking.

Maximum data rate at 3.08 MHz due to 8 x over clocking.

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). b. Refer to the Order ing Info rm atio n chapter on page 4 2.

August 3, 2004 Document No. 38-12012 Rev. *I 32

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.4.5 AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only.

Table 3-23. 5V AC Analog Output Buffer Specifications

°C ≤ T

Symbol Description Min Typ Max Units Notes

ROB

SOB

ROB

FOB

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load

Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load

Power = Low Power = High

–

0.65

0.8

300

– –

2.5

2.2

– –

µs µs

V/µs V/

MHz MHz

kHz kHz

µs

Table 3-24. 3.3V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

ROB

SOB

ROB

Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

FOB

Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load

Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load

Power = Low Power = High

–

0.5

0.7

200

– –

3.8

2.6

– –

µs µs

V/µs V/

µs

V/µs V/

µs

MHz MHz

kHz kHz

August 3, 2004 Document No. 38-12012 Rev. *I 33

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.4.6 AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only.

Table 3-25. 5V AC External Clock Specifications

Table 3-26. 3.3V AC Ex ternal Clock Specifications

°C ≤ T

Symbol Description Min Typ Max Units Notes

OSCEXT

– High Period 20.6 – Low Period 20.6 – Power Up IMO to Switch 150

Symbol Description Min Typ Max Units Notes

OSCEXT

– High Period with CPU Cl ock divide by 1 41.7 – Low Period with CPU Clock divide by 1 41.7 – Power Up IMO to Switch 150

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Frequency 0.093 –24.6MHz

– 5300 ns – –ns – – µs

Frequency with CPU Clock divide by 1 Frequency with CPU Clock divide by 2 or greater

0.093 –12.3MHz

0.186 –24.6MHz – 5300 ns

– –ns – – µs

a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-

cent duty cycle requi rement is met.

3.4.7 AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only.

Table 3-27. AC Programming Specifications

°C ≤ T

Symbol Description Min Typ Max Units Notes

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

ERASEB

WRITE

DSCLK

DSCLK3

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Rise Time of SCLK 1 – 20 ns Fall Time of SCLK 1 – 20 ns Data Set up Time to Falling Edge of SCLK 40 – – ns Data Hold Time from Fa llin g Edge of SCLK 40 – – ns Frequency of SCLK 0 – 8 MHz Flash Erase Time (Block) – 10 – ms Flash Block Write Time – 10 – ms Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6

August 3, 2004 Document No. 38-12012 Rev. *I 34

CY8C27x43 Final Data Sheet 3. Electrical Specifications

3.4.8 AC I2C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

are for design guidance only.

Table 3-28. AC Characteristics of the I

°C ≤ T

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

SPI2C

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t

rmax

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

C SDA and SCL Pins

Standard Mode Fast Mode

Units NotesMin Max Min Max

SCL Clock Frequency 0 100 0 400 kHz Hold Time (repeated) START Condition. After this period, the

first clock pulse is generated. LOW Period of the SCL Clock 4.7 –1.3– µs

HIGH Period of the SCL Clock 4.0 –0.6– µs Set-up Time for a Repeated START Condition 4.7 –0.6– µs Data Hold Time 0 –0– µs Data Set-up Time 250 – Set-up Time for STOP Condition 4.0 –0.6– µs Bus Free Time Between a STOP and START Condition 4.7 –1.3– µs Pulse Width of spikes are suppressed by the input filter. – – 0 50 ns

+ t

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

SU;DAT

4.0 –0.6– µs

100

SU;DAT

–ns

≥ 250 ns must then be met. This will automatically be the case if

SCL

LOWI2C

HDSTAI2C

HDDATI2C

SUDATI2C

HIGHI2C

SUSTAI2C

Sr SP

Figure 3-9. Definition for Timing for Fast/Standard Mode on the I

SPI2C

SUSTOI2C

C Bus

BUFI2C

August 3, 2004 Document No. 38-12012 Rev. *I 35

4. Packaging Information

This chapter illustrates the packaging specifications for the CY8C27x43 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled

http://www.cypress.com/support/link.cfm?mr=poddim.

4.1 Packaging Dimensions

PSoC Emulator Pod Dimensions at

51-85075 - *A

Figure 4-1. 8-Lead (300-Mil) PDIP

CY8C27x43 Final Data Sheet 4. Packaging Information

Figure 4-2. 20-Lead (210-Mil) SSOP

51-85077 - *C

51-85024 - *B

Figure 4-3. 20-Lead (300-Mil) Molded SOIC

August 3, 2004 Document No. 38-12012 Rev. *I 37

CY8C27x43 Final Data Sheet 4. Packaging Information

Figure 4-4. 28-Lead (300-Mil) Molded DIP

51-85014 - *D

51-85079 - *C

Figure 4-5. 28-Lead (210-Mil) SSOP

August 3, 2004 Document No. 38-12012 Rev. *I 38

CY8C27x43 Final Data Sheet 4. Packaging Information

51-85026 - *C

Figure 4-6. 28-Lead (300-Mil) Molded SOIC

51-85064-B

51-85064 - *B

Figure 4-7. 44-Lead TQFP

August 3, 2004 Document No. 38-12012 Rev. *I 39

CY8C27x43 Final Data Sheet 4. Packaging Information

51-85061-C

51-85061 - *C

Figure 4-8. 48-Lead (300-Mil) SSOP

0.80 DIA.

6.90

7.10

6.70

6.80

TOP VIEW

DIMENSIONS IN mm MIN.

MAX.

0.08

0.05 MAX.

0.20 REF.

6.70

6.80

6.90

7.10

1.00 MAX.

0.80 MAX.

0°-12°

SIDE VIEW

Figure 4-9. 48-Lead (7x7 mm) MLF

SEATING PLANE

0.30-0.45

E-PAD SIZE PADDLE SIZE

(X, Y MAX.)

0.23±0.05

E-PAD

5.45

5.55

BOTTOM VIEW

0.50

PIN1 ID

0.20 R.

51-85152 - *B

0.45

0.42±0.18

(4X)

5.45

5.55

August 3, 2004 Document No. 38-12012 Rev. *I 40

CY8C27x43 Final Data Sheet 4. Packaging Information

4.2 Thermal Impeda nces

Table 4-1. Thermal Impedances per Package

Package Typical θ

8 PDIP

20 SSOP

20 SOIC 28 PDIP

28 SSOP

28 SOIC 44 TQFP 48 SSOP

48 MLF

* TJ = TA + POWER x θ

120 oC/W

95 oC/W 79 oC/W 67 oC/W 95 oC/W 71 oC/W 58 oC/W 69 oC/W 18 oC/W

4.3 Capacitance on Crystal Pins

Table 4-2: Typical Package Capacitance on Crystal Pins

Package Package Capacitance

8 PDIP 2.8 pF

20 SSOP 2.6 pF

20 SOIC 2.5 pF

28 PDIP 3.5 pF 28 SSOP 2.8 pF

28 SOIC 2.7 pF 44 TQFP 2.6 pF 48 SSOP 3.3 pF

48 MLF 2.3 pF

August 3, 2004 Document No. 38-12012 Rev. *I 41

5. Ordering Information

The following table lists the CY8C27x43 PSoC device family’s key package features and ordering codes.

Table 5-1. CY8C27x43 PSoC Device Family Key Features and Ordering Information

Package

CY8C27x43 Silicon B – These parts are lead free and offer the following improvements. The DEC_CR1 register selections are enhanced to allow

any digital block to be the decimator clock source, the ECO EX and ECO EXW bits in the CPU_SCR1 register are readable, and the accuracy of the analog reference is enhanced (see the Electrical Specifications chapter). All silicon A errata are fixed in silicon B.

8 Pin (300 Mil) DIP CY8C27143-24PXI 16 256 No -40C to +85C 8 12 6 4 4 No 20 Pin (210 Mil) SSOP CY8C27243-24PVXI 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin (210 Mil) SSOP

(Tape and Reel) 20 Pin (300 Mil) SOIC CY8C27243-24SXI 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin 300 Mil) SOIC

(Tape and Reel) 28 Pin (300 Mil) DIP CY8C27443-24PXI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (210 Mil) SSOP CY8C27443-24PVXI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (210 Mil) SSOP

(Tape and Reel) 28 Pin (300 Mil) SOIC CY8C27443-24SXI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (300 Mil) SOIC

(Tape and Reel) 44 Pin TQFP CY8C27543- 24AXI 16 256 Yes -40C to +85C 8 12 40 12 4 Yes 44 Pin TQFP

(Tape and Reel) 48 Pin (300 Mil) SSOP CY8C27643-24PVXI 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (300 Mil) SSOP

(Tape and Reel) 48 Pin (7x7) MLF CY8C27643-24LFXI 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (7x7) MLF

(Tape and Reel)

CY8C27x43 Silicon A – Silicon A is not recommended for new designs.

8 Pin (300 Mil) DIP CY8C27143-24PI 16 256 No -40C to +85C 8 12 6 4 4 No 20 Pin (210 Mil) SSOP CY8C27243-24PVI 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin (210 Mil) SSOP

(Tape and Reel) 20 Pin (300 Mil) SOIC CY8C27243-24SI 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin 300 Mil) SOIC

(Tape and Reel) 28 Pin (300 Mil) DIP CY8C27443-24PI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (210 Mil) SSOP CY8C27443-24PVI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes

Ordering

Code

CY8C27243-24PVXIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes

CY8C27243-24SXIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes

CY8C27443-24PVXIT 16 256 Yes -40C to +85C 8 12 24 12 4 Yes

CY8C27443-24SXIT 16 256 Yes -40C to +85C 8 12 24 12 4 Yes

CY8C27543-24AXIT 16 256 Yes -40C to +85C 8 12 40 12 4 Yes

CY8C27643-24PVXIT 16 256 Yes -40C to +85C 8 12 44 12 4 Yes

CY8C27643-24LFXIT 16 256 Yes -40C to +85C 8 12 44 12 4 Yes

CY8C27243-24PVIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes

CY8C27243-24SIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes

Flash

(Kbytes)

RAM

(Bytes)

Switch Mode

Pump

Range

Temperature

(Rows of 4)

Digital Blocks

Analog Blocks

(Columns of 3)

Digital IO

Pins

Inputs

Analog

Outputs

XRES Pin

August 3, 2004 Document No. 38-12012 Rev. *I 42

CY8C27x43 Final Data Sheet 5. Ordering Information

Table 5-1. CY8C27x43 PSoC Device Family Key Features and Ordering Information (continued)

Package

28 Pin (210 Mil) SSOP (Tape and Reel)

28 Pin (300 Mil) SOIC CY8C27443-24SI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (300 Mil) SOIC

(Tape and Reel) 44 Pin TQFP CY8C27543- 24AI 16 256 Yes -40C to +85C 8 12 40 12 4 Yes 44 Pin TQFP

(Tape and Reel) 48 Pin (300 Mil) SSOP CY8C27643-24PVI 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (300 Mil) SSOP

(Tape and Reel) 48 Pin (7x7) MLF CY8C27643-24LFI 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (7x7) MLF

(Tape and Reel)

Ordering

Code

CY8C27443-24PVIT 16 256 Yes -40C to +85C 8 12 24 12 4 Yes

CY8C27443-24SIT 16 256 Yes -40C to +85C 8 12 24 12 4 Yes

CY8C27543-24AIT 16 256 Yes -40C to +85C 8 12 40 12 4 Yes

CY8C27643-24PVIT 16 256 Yes -40C to +85C 8 12 44 12 4 Yes

CY8C27643-24LFIT 16 256 Yes -40C to +85C 8 12 44 12 4 Yes

RAM

Flash

(Kbytes)

(Bytes)

Switch Mode

Pump

Range

Temperature

(Rows of 4)

Digital Blocks

Analog Blocks

(Columns of 3)

Digital IO

Pins

Inputs

Analog

Outputs

5.1 Ordering Code Definitions

Y 8 C 27 xxx-SPxx

XRES Pin

Package Type: Thermal Rating:

P = PDIP PX = PDIP Pb Free C = Commercial S = SOIC SX = SOIC Pb Free I = Industrial PV = SSOP PVX = SSOP Pb Free E = Extended LF = MLF LFX = MLF Pb Free

A = TQFP AX = TQFP Pb Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress MicroSystems Company ID: CY = Cypress

August 3, 2004 Document No. 38-12012 Rev. *I 43

6. Sales and Service Information

To obtain information about Cypre ss Micro Sys tems or PSoC sales and tec hnical s upport, referenc e the fol lowing i nforma tion or go to the section titled “Getting Started” on page 4 in this document.

Cypress MicroSystems

2700 162nd Street SW Building D Lynnwood, WA 98037 Phone: 800.669.0557 Facsimile: 425.787.4641

Web Sites: Company Information – http://www.cypress.com

Sales – http://www.cypress.com/aboutus/sales_locations.cfm

Technical Support – http://www.cypress.com/support/login.cfm

6.1 Revision History

Table 6-1. CY8C27x43 Data Sheet Revision History

Document Title: CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 PSoC Mixed Signal Array Final Data Sheet Document Number: 38-12012

Revision ECN # Issue Date Origin of Change Description of Change

** 127087 7/01/2003 New Silicon. New document (Revision **). *A 128780 7/29/2003 Engineering and

*B 128992 8/14/2003 NWJ Interrupt controller table fixed, refinements to Electrical Spec section and Register chapter. *C 129283 8/28/2003 NWJ Significant changes to the Electrical Specifications section. *D 129442 9/09/2003 NWJ Changes made to Electrical Spec section. Added 20/28-Lead SOIC packages and pinouts. *E 130129 10/13/2003 NWJ Revised document for Silicon Revision A. *F 130651 10/28/2003 NWJ Refinements to Electrical Specification section and I2C chapter. *G 131298 11/18/2003 NWJ Revisions to GDI, RDI, and Digital Block chapters. Revisions to AC Digital Block Spec and miscella-

*H 229416 See ECN SFV New data sheet format and organization. Reference the PSoC Mixed Signal Array Technical Refer-

*I 247529 See ECN SFV Added Silicon B information to this data sheet.

Distribution: External Public Posting: None

NWJ.

New electrical spec additions, fix of Core Architecture links, corrections to some text, tables, drawings, and format.

neous register changes.

ence Manual

for additional inform ati o n. Title change .

6.2 Copyrights and Code Protection

Copyrights

© Cypress MicroSystems, Inc. 2000 – 2004. All rights reserved. PSoC™, PSoC Designer™, and Programmable System-on-Chip™ are trademarks of Cypress MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circ uitry embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does n o t au t hori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress MicroSystems products in li fe-support systems application impl ies that the manufacturer assumes all ri sk of such use and in doing so indemnifie s Cypress MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess MicroSystems.

Flash Code Protection

Note the following details of the Flash code protection features on Cypress MicroSystems devices. Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of

products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress MicroSystems, that can breach the code protect ion featu res. Any of th ese methods , to our kno wledge, wo uld be dish onest and po ssibly il legal. Neither Cypre ss MicroSystems nor an y other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress MicroSystems are committed to continuously improving the code protection features of our products.

This datasheet has been downloaded from:

www.DatasheetCatalog.com

Datasheets for electronic components.

CYPRESS CY8C27143 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

PSoC™ Functional Overview

Getting Started

Development Tools

Designing with User Modules

Document Conventions

1. Pin Information

1.1 Pinouts

1.1.1 8-Pin Part Pinout

1.1.2 20-Pin Part Pinout

1.1.3 28-Pin Part Pinout

1.1.4 44-Pin Part Pinout

1.1.5 48-Pin Part Pinouts

2. Register Reference

2.1 Register Conventions

2.2 Register Mapping Tables

3. Electrical S pecifications

3.1 Ab solute Maximum Ratings

3.2 Operating Temperature

3.3 DC Electrical Characteristics

3.3.1 DC Chip-Level Specifications

3.3.2 DC General Purpose IO Specifications

3.3.3 DC Operational Amplifier Specifications

3.3.4 DC Analog Output Buffer Specifications

3.3.5 DC Switch Mode Pump Specifications

3.3.6 DC Analog Reference Specifications

3.3.7 DC Analog PSoC Block Specifications

3.3.8 DC POR and LVD Specifications

3.3.9 DC Programming Specifications

3.4 AC Electrical Characteristics

3.4.1 AC Chip-Level Specifications

3.4.2 AC General Purpose IO Specifications

3.4.3 AC Operational Amplifier Specifications

3.4.4 AC Digital Block Specifications

3.4.5 AC Analog Output Buffer Specifications

3.4.6 AC External Clock Specifications

3.4.7 AC Programming Specifications

3.4.8 AC I2C Specifications

4. Packaging Information

4.1 Packaging Dimensions

4.2 Thermal Impeda nces

4.3 Capacitance on Crystal Pins

5. Ordering Information

5.1 Ordering Code Definitions

6. Sales and Service Information

6.1 Revision History

6.2 Copyrights and Code Protection