Cypress CY8C24223A, CY8C24423A User Manual
CY8C24223A, CY8C24423A
PSoC® Programmable System-on-Chip™
Features
DIGITAL SYSTEM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Incl udes IM O, I LO, PLL, and E CO)
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
CPU Core (M8C)
SROM Flash 4K
Digital
Bloc k A rray
Multiply
Accum .
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Res ets
Decimator
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref
An a l o g
Input
Muxi n g
I2C
(1 Row,
4 Blocks)
Por t 2 Por t 1 Por t 0
Analog
Drivers
System Bus
Analog
Block
Array
(2 Colum ns ,
6 Blocks)
Logic Block Diagram
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 12 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 4.75V to 5.25V Operating Voltage
❐ Extended Temperature Range: -40°C to +125°C
■ Advanced Peripherals (PSoC Blocks)
❐ Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking
❐ Internal ± 4% 24 MHz Oscillator
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 4K Bytes Flash Program Storage 100 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
■ Programmable Pin Configurations
❐ 25 mA Sink on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to Ten Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO
■ Additional System Resources
2
❐ I
C™ Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 3-12029 Rev. *E Revised December 11, 2008
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PSoC® Functional Overview
DIGITAL SYSTEM
To System Bus
D
i
g
i
t
a
l
C
l
o
c
k
s
F
r
o
m
C
o
r
e
Digital PSoC Block Array
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 2
Port 1
Port 0
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one, low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, and
Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user module references.
Figure 1. Digital System Block Diagram
programmable interconnects. This architecture allows the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts and
packages.
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, is comprised of four main areas: PSoC Core, Digital
System, Analog System, and System Resources. Configurable
global busing allows all the device resources to be combined into
a complete custom system. The PSoC automotive CY8C24x23A
group can have up to three IO ports that connect to the global
digital and analog interconnects, providing access to 4 digital
blocks and 6 analog blocks.
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory , clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
12 MHz, providing a two MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 11
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory includes 4 KB of Flash for program storage and 256
bytes of SRAM for data storage. Program Flash uses four
protection levels on blocks of 64 bytes, allowing customized
software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 4%
over temperature and voltage. A low power 32 kHz ILO (internal
low speed oscillator) is provided for the Sleep timer and WDT. If
crystal accuracy is desired, the ECO (32.768 kHz external crystal
oscillator) is available for use as a Real Time Clock (RTC) and
can optionally generate a crystal-accurate 24 MHz system clock
using a PLL. The clocks, together with programmable clock
dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
Digital peripheral configurations include:
■ PWMs (8 to 32 bit)
■ PWMs with Dead Band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity
■ SPI Master and Slave
■ I2C Slave and Multi-Master (one available as a System
Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in the table PSoC Device Characteristics
on page 4.
Document Number: 3-12029 Rev. *E Page 2 of 31
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Analog System
ACB00 ACB01
Block Array
Arra y Input Configur at ion
ACI1[1:0]
ASD20
ACI0[1:0]
P0[ 6]
P0[ 4]
P0[ 2]
P0[ 0]
P2[ 2]
P2[ 0]
P2[ 6]
P2[ 4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Refe re nce
Gene rators
AGNDIn
Ref In
Bandgap
Ref Hi
Ref Lo
AGND
ASD11
ASC21
ASC10
Inte rface t o
Digital System
M 8 C Int e rf ac e ( Addr e s s Bus , Da t a Bus , Et c .)
Analog Refe renc e
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
■ Analog-to-digital converters (up to two, with 6 to 14-bit
resolution, selectable as Incremental, Delta Sigma, and SAR)
■ Filters (two and four pole band-pass, low-pass, and notch)
■ Amplifiers (up to two, with selectable gain to 48x)
■ Instrumentation amplifiers (one with selectable gain to 93x)
■ Comparators (up to two, with 16 selectable thresholds)
■ DACs (up to two, with 6 to 9-bit resolution)
■ Multiplying DACs (up to two, with 6 to 9-bit resolution)
■ High current output drivers (two with 30 mA drive as a PSoC
Core resource)
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
■ Modulators
■ Correlators
■ Peak Detectors
■ Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 2.
Figure 2. Analog System Block Diagram
Document Number: 3-12029 Rev. *E Page 3 of 31
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Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief
statements describing the merits of each system resource follow:
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
■ The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■ The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups. The PSoC device covered by
this data sheet is highlighted.
Table 1. PSoC Device Characteristics
Getting Started
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, refer the PSoC Programmable Sytem-on-Chip Technical Reference Manual.
For up-to-date Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets on the web
at http://www.cypress.com/psoc.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click PSoC (Program-
mable System-on-Chip) to view a current list of available items.
Technical Training
Free PSoC technical training is available for beginners and is
taught by a marketing or application engineer over the phone.
PSoC training classes cover designing, debugging, advanced
analog, and application-specific classes covering topics, such as
PSoC and the LIN bus. Go to http://www.cypress.com, click on
Design Support located on the left side of the web page, and
select Technical Training for more details.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
PSoC Part
Number
CY8C29x66 up to 644 16 12 4 4 12 2K 32K
CY8C27x43
CY8C24x94 49 1 4 48 2 2 6 1K 16K
CY8C24x23
CY8C24x23A up t o 241 4 12 2 2 6 256
CY8C21x34 up to 281 4 28 0 2 4
CY8C21x23 16 1 4 8 0 2 4
a. Limited analog functionality.
IO
Digital
Rows
Digital
up to 442 8 12 4 4 12 256
up to 241 4 12 2 2 6 256
Inputs
Digital
Blocks
Analog
Analog
Outputs
Blocks
Analog
Analog
Columns
Bytes
Bytes
Bytes
a
512
Bytes
a
256
Bytes
Size
SRAM
Flash
16K
4K
4K
8K
4K
Technical Support
Size
PSoC application engineers take pride in fast and accurate
response. They can be reached with a four-hour guaranteed
response at http://www.cypress.com/support.
Application Notes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are listed by date as default.
Document Number: 3-12029 Rev. *E Page 4 of 31
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Development Tools
Commands
Results
PSoC
Designer
Core
Engine
PSoC
Configuration
Sheet
Manufacturing
Information
File
Device
Database
Importable
Design
Database
Device
Programmer
Graphical Designer
Interface
Context
Sensitive
Help
Emulation
Pod
In-Circuit
Emulator
Project
Database
Application
Database
User
Modules
Library
PSoC
Designer
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP (refer Figure 3).
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
Design Browser
The Design Browser allows users to select and import
preconfigured designs into the user’s project. Users can easily
browse a catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler. The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available that
supports Cypress MicroSystems’ PSoC family devices. Even if
you have never worked in the C language before, the product
quickly allows you to create complete C programs for the PSoC
family devices.
The embedded, optimizing C compiler provides all th e features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Document Number: 3-12029 Rev. *E Page 5 of 31
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Debugger
Debugger
Interface
to ICE
Application Editor
Device Editor
Project
Manager
Source
Code
Editor
Storage
Inspector
User
Module
Se lectio n
Placement
and
Parameter
-ization
Generate
A p p licatio n
Build
All
Event &
Breakpoint
Manager
Build
Manager
Source
Code
Generator
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
operates with all PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (12 MHz) operation.
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run-time. The API also provides optional interrupt service
routines that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by
interconnecting user modules to each other and the IO pins. At
this stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
Figure 4. User Module and Source Code Development Flow s
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware as well as the software. This substantially lowers the
risk of having to select a different part to meet the final design
requirements.
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
Document Number: 3-12029 Rev. *E Page 6 of 31
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The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (includ ing
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrical ly erasable programmable read-only
memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
Table 2. Acronyms (continued)
Acronym Description
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision po wer on reset
®
PSoC
PWM pulse width modulator
SC switched capacitor
SRAM static random access memory
Programmable System-on-Chip™
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 5 on page 10 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Document Number: 3-12029 Rev. *E Page 7 of 31
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Pinouts
A, I, P 0[7]
A, IO, P 0[5]
A, IO, P 0[3]
A, I, P 0[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
SSOP
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Vss
The CY8C24x23A automotive PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
20-Pin Part Pinout
Table 3. 20-Pin Part Pinout (SSOP)
Pin
No.
Type
Digital Analog
Pin
Name
Description
1 IO I P0[7] Analog column mux input
2 IO IO P0[5] Analog column mux input and column
output
3 IO IO P0[3] Analog column mux input and column
output
4 IO I P0[1] Analog column mux input
5 Power Vss Ground connection
6 IO P1[7] I2C Serial Clock (SCL)
7 IO P1[5] I2C Serial Data (SDA)
8 IO P1[3]
9 IO P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
10 Power Vss Ground connection
11 IO P1[0] C rystal Output (XT ALout), I2C Serial Data
(SDA), ISSP-SDATA*
12 IO P1[2]
13 IO P1[4] Optional External Clock Input (EXTCLK)
14 IO P1[6]
15 Input XRES Active high external reset with internal pull
down
16 IO I P0[0] Analog column mux input
17 IO I P0[2] Analog column mux input
18 IO I P0[4] Analog column mux input
19 IO I P0[6] Analog column mux input
20 Power Vdd Supply voltage
Figure 5. CY8C24223A 20-Pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 3-12029 Rev. *E Page 8 of 31
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28-Pin Part Pinout
A, I, P0[7]
A, IO, P 0[5]
A, IO, P 0[3]
A, I, P 0[1]
P2[7]
P2[5]
A, I, P 2[3]
A, I, P2[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P2[6], Ex ternal VRef
P2[4], Ex ternal AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
Table 4. 28-Pin Part Pinout (SSOP)
Pi
n
No
.
1 IO I P0[7] Analog column mux input
2 IO IO P0[5] Analog column mux input and column
3 IO IO P0[3] Analog column mux input and column
4 IO I P0[1] Analog column mux input
5 IO P2[7]
6 IO P2[5]
7 IO I P2[3] Direct switched capacitor block input
8 IO I P2[1] Direct switched capacitor block input
9 Power Vss Ground connection
10 IO P1[7] I2C Serial Clock (SCL)
11 IO P1[5] I2C Serial Data (SDA)
12 IO P1[3]
13 IO P1[1] Crystal Input (XTALin), I2C Serial Clock
14 Power Vss Ground connection
15 IO P1[0] Crystal Output (XTALout), I2C Serial Data
16 IO P1[2]
17 IO P1[4] Optional External Clock Input (EXTCLK)
18 IO P1[6]
19 Input XRES Active high external reset with internal pull
20 IO I P2[0] Direct switched capacitor block input
21 IO I P2[2] Direct switched capacitor block input
22 IO P2[4] External Analog Ground (AGND)
23 IO P2[6] External Voltage Reference (VRef)
24 IO I P0[0] Analog column mux input
25 IO I P0[2] Analog column mux input
26 IO I P0[4] Analog column mux input
27 IO I P0[6] Analog column mux input
28 Power Vdd Supply voltage
Digi-
tal
Type
Ana-
log
Pin
Name
Description
output
output
(SCL), ISSP-SCLK*
(SDA), ISSP-SDATA*
down
Figure 6. CY8C24423A 28-Pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 3-12029 Rev. *E Page 9 of 31
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CY8C24223A, CY8C24423A
Register Reference
This section lists the registers of the CY8C24x23A automotive
PSoC device. For detailed register information, refer the PSoC
Programmable System-on-Chip Technical Reference Manual.
Register Conventions
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Table 5. Abbreviations
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Document Number: 3-12029 Rev. *E Page 10 of 31
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