Cypress CY8C24223A, CY8C24423A User Manual

CY8C24223A, CY8C24423A

PSoC® Programmable System-on-Chip™

Features

DIGITAL SYSTEM

SRAM

256 Bytes

Interrupt

Controller

Sleep and
Watchdog

Multiple Clock Sources

(Incl udes IM O, I LO, PLL, and E CO)

Global Digital Interconnect

Global Analog Interconnect

PSoC CORE

CPU Core (M8C)

SROM Flash 4K

Digital

Bloc k A rray

Multiply
Accum .

Internal
Voltage

Ref.

Digital
Clocks

POR and LVD

System Res ets

Decimator

SYSTEM RESOURCES

ANALOG SYSTEM

Analog

Ref

An a l o g

Input

Muxi n g

I2C

(1 Row,

4 Blocks)

Por t 2 Por t 1 Por t 0

Analog
Drivers

System Bus

Analog

Block
Array

(2 Colum ns ,

6 Blocks)

Logic Block Diagram

■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 12 MHz
❐ 8x8 Multiply, 32-Bit Accumulate

❐ Low Power at High Speed
❐ 4.75V to 5.25V Operating Voltage
❐ Extended Temperature Range: -40°C to +125°C

■ Advanced Peripherals (PSoC Blocks)
❐ Six Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs

• Up to 9-Bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

❐ Four Digital PSoC Blocks Provide:

• 8 to 32-Bit Timers, Counters, and PWMs

• CRC and PRS Modules

• Full-Duplex UART

• Multiple SPI™ Masters or Slaves

• Connectable to all GPIO Pins

❐ Complex Peripherals by Combining Blocks

■ Precision, Programmable Clocking
❐ Internal ± 4% 24 MHz Oscillator
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL

❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep

■ Flexible On-Chip Memory
❐ 4K Bytes Flash Program Storage 100 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage

❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes

■ Programmable Pin Configurations
❐ 25 mA Sink on All GPIO

❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive

Modes on All GPIO

❐ Up to Ten Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO

■ Additional System Resources

2

❐ I

C™ Slave, Master, and Multi-Master to 400 kHz

❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference

■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)

❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 3-12029 Rev. *E Revised December 11, 2008

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PSoC® Functional Overview

DIGITAL SYSTEM

To System Bus

D

i

g

i

t

a

l

C

l

o

c

k

s

F

r

o

m

C

o

r

e

Digital PSoC Block Array

To Analog

System

8

Row Input

Configuration

Row Output

Configuration

88

8

Row 0

DBB00 DBB01 DCB02 DCB03

4

4

GIE[7:0]
GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Port 2

Port 1

Port 0

The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one, low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, and

Digital System

The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user module references.

Figure 1. Digital System Block Diagram

programmable interconnects. This architecture allows the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts and
packages.

The PSoC architecture, as shown in the Logic Block Diagram on
page 1, is comprised of four main areas: PSoC Core, Digital
System, Analog System, and System Resources. Configurable
global busing allows all the device resources to be combined into
a complete custom system. The PSoC automotive CY8C24x23A
group can have up to three IO ports that connect to the global
digital and analog interconnects, providing access to 4 digital
blocks and 6 analog blocks.

PSoC Core

The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory , clocks, and configurable
GPIO (General Purpose IO).

The M8C CPU core is a powerful processor with speeds up to
12 MHz, providing a two MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 11
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).

Memory includes 4 KB of Flash for program storage and 256
bytes of SRAM for data storage. Program Flash uses four
protection levels on blocks of 64 bytes, allowing customized
software IP protection.

The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 4%
over temperature and voltage. A low power 32 kHz ILO (internal
low speed oscillator) is provided for the Sleep timer and WDT. If
crystal accuracy is desired, the ECO (32.768 kHz external crystal
oscillator) is available for use as a Real Time Clock (RTC) and
can optionally generate a crystal-accurate 24 MHz system clock
using a PLL. The clocks, together with programmable clock
dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC device.

PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external inter­facing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.

Digital peripheral configurations include:

■ PWMs (8 to 32 bit)

■ PWMs with Dead Band (8 to 32 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity

■ SPI Master and Slave

■ I2C Slave and Multi-Master (one available as a System

Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in the table PSoC Device Characteristics
on page 4.

Document Number: 3-12029 Rev. *E Page 2 of 31

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Analog System

ACB00 ACB01

Block Array

Arra y Input Configur at ion

ACI1[1:0]

ASD20

ACI0[1:0]

P0[ 6]

P0[ 4]

P0[ 2]
P0[ 0]

P2[ 2]
P2[ 0]

P2[ 6]

P2[ 4]

RefIn

AGNDIn

P0[7]

P0[5]

P0[3]
P0[1]

P2[3]

P2[1]

Refe re nce

Gene rators

AGNDIn
Ref In
Bandgap

Ref Hi
Ref Lo
AGND

ASD11

ASC21

ASC10

Inte rface t o

Digital System

M 8 C Int e rf ac e ( Addr e s s Bus , Da t a Bus , Et c .)

Analog Refe renc e

The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:

■ Analog-to-digital converters (up to two, with 6 to 14-bit

resolution, selectable as Incremental, Delta Sigma, and SAR)

■ Filters (two and four pole band-pass, low-pass, and notch)

■ Amplifiers (up to two, with selectable gain to 48x)

■ Instrumentation amplifiers (one with selectable gain to 93x)

■ Comparators (up to two, with 16 selectable thresholds)

■ DACs (up to two, with 6 to 9-bit resolution)

■ Multiplying DACs (up to two, with 6 to 9-bit resolution)

■ High current output drivers (two with 30 mA drive as a PSoC

Core resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

■ Peak Detectors

■ Many other topologies possible

Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 2.

Figure 2. Analog System Block Diagram

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Additional System Resources

System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief
statements describing the merits of each system resource follow:

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.

■ A multiply accumulate (MAC) provides a fast 8-bit multiplier

with 32-bit accumulate, to assist in both general math as well
as digital filters.

■ The decimator provides a custom hardware filter for digital

signal processing applications including the creation of Delta
Sigma ADCs.

■ The I2C module provides 100 and 400 kHz communication over

two wires. Slave, master, and multi-master modes are all
supported.

■ Low Voltage Detection (LVD) interrupts can signal the

application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups. The PSoC device covered by
this data sheet is highlighted.

Table 1. PSoC Device Characteristics

Getting Started

The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, refer the PSoC Program­mable Sytem-on-Chip Technical Reference Manual.

For up-to-date Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets on the web
at http://www.cypress.com/psoc.

Development Kits

Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at

http://www.cypress.com, click the Online Store shopping cart

icon at the bottom of the web page, and click PSoC (Program-
mable System-on-Chip) to view a current list of available items.

Technical Training

Free PSoC technical training is available for beginners and is
taught by a marketing or application engineer over the phone.
PSoC training classes cover designing, debugging, advanced
analog, and application-specific classes covering topics, such as
PSoC and the LIN bus. Go to http://www.cypress.com, click on
Design Support located on the left side of the web page, and
select Technical Training for more details.

Consultants

Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.

PSoC Part

Number

CY8C29x66 up to 644 16 12 4 4 12 2K 32K

CY8C27x43

CY8C24x94 49 1 4 48 2 2 6 1K 16K
CY8C24x23

CY8C24x23A up t o 241 4 12 2 2 6 256

CY8C21x34 up to 281 4 28 0 2 4

CY8C21x23 16 1 4 8 0 2 4

a. Limited analog functionality.

IO

Digital

Rows

Digital

up to 442 8 12 4 4 12 256

up to 241 4 12 2 2 6 256

Inputs

Digital

Blocks

Analog

Analog

Outputs

Blocks

Analog

Analog

Columns

Bytes

Bytes

Bytes

a

512
Bytes

a

256
Bytes

Size

SRAM

Flash

16K

4K

4K

8K

4K

Technical Support

Size

PSoC application engineers take pride in fast and accurate
response. They can be reached with a four-hour guaranteed
response at http://www.cypress.com/support.

Application Notes

A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to the

http://www.cypress.com web site and select Application Notes

under the Design Resources list located in the center of the web
page. Application notes are listed by date as default.

Document Number: 3-12029 Rev. *E Page 4 of 31

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Development Tools

Commands

Results

PSoC

Designer

Core

Engine

PSoC

Configuration

Sheet

Manufacturing

Information

File

Device

Database

Importable

Design

Database

Device

Programmer

Graphical Designer

Interface

Context

Sensitive

Help

Emulation

Pod

In-Circuit

Emulator

Project

Database

Application

Database

User

Modules

Library

PSoC

Designer

PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP (refer Figure 3).

PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.

PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.

Figure 3. PSoC Designer Subsystems

PSoC Designer Software Subsystems

Device Editor

The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.

The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.

PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.

Design Browser

The Design Browser allows users to select and import
preconfigured designs into the user’s project. Users can easily
browse a catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.

Application Editor

In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.

Assembler. The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries automati­cally use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.

C Language Compiler. A C language compiler is available that
supports Cypress MicroSystems’ PSoC family devices. Even if
you have never worked in the C language before, the product
quickly allows you to create complete C programs for the PSoC
family devices.

The embedded, optimizing C compiler provides all th e features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.

Document Number: 3-12029 Rev. *E Page 5 of 31

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Debugger

Debugger

Interface

to ICE

Application Editor

Device Editor

Project

Manager

Source

Code

Editor

Storage

Inspector

User

Module

Se lectio n

Placement

and

Parameter

-ization

Generate
A p p licatio n

Build
All

Event &

Breakpoint

Manager

Build

Manager

Source

Code

Generator

The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break­points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.

The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
operates with all PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (12 MHz) operation.

of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run-time. The API also provides optional interrupt service
routines that you can adapt as needed.

The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.

The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by
interconnecting user modules to each other and the IO pins. At
this stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.

Figure 4. User Module and Source Code Development Flow s

Designing with User Modules

The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware as well as the software. This substantially lowers the
risk of having to select a different part to meet the final design
requirements.

To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.

Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits

Document Number: 3-12029 Rev. *E Page 6 of 31

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The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (includ ing
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.

The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.

Document Conventions

Acronyms Used

The following table lists the acronyms that are used in this
document.

Table 2. Acronyms

Acronym Description

AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrical ly erasable programmable read-only

memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset

Table 2. Acronyms (continued)

Acronym Description

LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision po wer on reset

®

PSoC
PWM pulse width modulator
SC switched capacitor
SRAM static random access memory

Programmable System-on-Chip™

Units of Measure

A units of measure table is located in the Electrical Specifications
section. Table 5 on page 10 lists all the abbreviations used to
measure the PSoC devices.

Numeric Naming

Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.

Document Number: 3-12029 Rev. *E Page 7 of 31

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Pinouts

A, I, P 0[7]
A, IO, P 0[5]
A, IO, P 0[3]

A, I, P 0[1]

I2C SCL, P1[7]

I2C SDA, P1[5]

P1[3]

I2C SCL, XTALin, P1[1]

Vss

SSOP

20
19
18
17
16
15
14
13
12
11

1
2
3
4
5
6
7
8
9

10

Vdd
P0[6], A, I
P0[4], A, I

P0[2], A, I
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA

Vss

The CY8C24x23A automotive PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.

20-Pin Part Pinout

Table 3. 20-Pin Part Pinout (SSOP)

Pin
No.

Type

Digital Analog

Pin

Name

Description

1 IO I P0[7] Analog column mux input
2 IO IO P0[5] Analog column mux input and column

output

3 IO IO P0[3] Analog column mux input and column

output
4 IO I P0[1] Analog column mux input
5 Power Vss Ground connection
6 IO P1[7] I2C Serial Clock (SCL)
7 IO P1[5] I2C Serial Data (SDA)
8 IO P1[3]
9 IO P1[1] Crystal Input (XTALin), I2C Serial Clock

(SCL), ISSP-SCLK*
10 Power Vss Ground connection
11 IO P1[0] C rystal Output (XT ALout), I2C Serial Data

(SDA), ISSP-SDATA*
12 IO P1[2]
13 IO P1[4] Optional External Clock Input (EXTCLK)
14 IO P1[6]
15 Input XRES Active high external reset with internal pull

down
16 IO I P0[0] Analog column mux input
17 IO I P0[2] Analog column mux input
18 IO I P0[4] Analog column mux input
19 IO I P0[6] Analog column mux input
20 Power Vdd Supply voltage

Figure 5. CY8C24223A 20-Pin PSoC Device

LEGEND: A = Analog, I = Input, and O = Output.

* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

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28-Pin Part Pinout

A, I, P0[7]
A, IO, P 0[5]
A, IO, P 0[3]

A, I, P 0[1]

P2[7]
P2[5]

A, I, P 2[3]

A, I, P2[1]

I2C SCL, P1[7]

I2C SDA, P1[5]

P1[3]

I2C SCL, XTALin, P1[1]

Vss

Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P2[6], Ex ternal VRef
P2[4], Ex ternal AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA

SSOP

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Vss

Table 4. 28-Pin Part Pinout (SSOP)

Pi

n

No

.

1 IO I P0[7] Analog column mux input
2 IO IO P0[5] Analog column mux input and column

3 IO IO P0[3] Analog column mux input and column

4 IO I P0[1] Analog column mux input
5 IO P2[7]
6 IO P2[5]
7 IO I P2[3] Direct switched capacitor block input
8 IO I P2[1] Direct switched capacitor block input
9 Power Vss Ground connection
10 IO P1[7] I2C Serial Clock (SCL)
11 IO P1[5] I2C Serial Data (SDA)
12 IO P1[3]
13 IO P1[1] Crystal Input (XTALin), I2C Serial Clock

14 Power Vss Ground connection
15 IO P1[0] Crystal Output (XTALout), I2C Serial Data

16 IO P1[2]
17 IO P1[4] Optional External Clock Input (EXTCLK)
18 IO P1[6]
19 Input XRES Active high external reset with internal pull

20 IO I P2[0] Direct switched capacitor block input
21 IO I P2[2] Direct switched capacitor block input
22 IO P2[4] External Analog Ground (AGND)
23 IO P2[6] External Voltage Reference (VRef)
24 IO I P0[0] Analog column mux input
25 IO I P0[2] Analog column mux input
26 IO I P0[4] Analog column mux input
27 IO I P0[6] Analog column mux input
28 Power Vdd Supply voltage

Digi-

tal

Type

Ana-

log

Pin

Name

Description

output

output

(SCL), ISSP-SCLK*

(SDA), ISSP-SDATA*

down

Figure 6. CY8C24423A 28-Pin PSoC Device

LEGEND: A = Analog, I = Input, and O = Output.

* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

Document Number: 3-12029 Rev. *E Page 9 of 31

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CY8C24223A, CY8C24423A

Register Reference

This section lists the registers of the CY8C24x23A automotive
PSoC device. For detailed register information, refer the PSoC
Programmable System-on-Chip Technical Reference Manual.

Register Conventions

Abbreviations Used

The register conventions specific to this section are listed in the
following table.

Table 5. Abbreviations

Convention Description

R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific

Register Mapping Tables

The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.

Document Number: 3-12029 Rev. *E Page 10 of 31

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Table 6. Register Map Bank 0 Table: User Space

Name

PRT0DR 00 RW 40 ASC10CR0 80 RW C0
PRT0IE 01 RW 41 ASC10CR1 81 RW C1
PRT0GS 02 RW 42 ASC10CR2 82 RW C2
PRT0DM2 03 RW 43 ASC10CR3 83 RW C3
PRT1DR 04 RW 44 ASD11CR0 84 RW C4
PRT1IE 05 RW 45 ASD11CR1 85 RW C5
PRT1GS 06 RW 46 ASD11CR2 86 RW C6
PRT1DM2 07 RW 47 ASD11CR3 87 RW C7
PRT2DR 08 RW 48 88 C8
PRT2IE 09 RW 49 89 C9
PRT2GS 0A RW 4A 8A CA
PRT2DM2 0B RW 4B 8B CB

DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW
DBB00DR2 22 RW 62 A2 INT_VC E2 RC
DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC
DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC
DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW
DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW
DCB02DR0 28 # 68 A8 MUL_X E8 W
DCB02DR1 29 W 69 A9 MUL_Y E9 W
DCB02DR2 2A RW 6A AA MUL_DH EA R
DCB02CR0 2B # 6B AB MUL_DL EB R
DCB03DR0 2C # 6C AC ACC_DR1 EC RW
DCB03DR1 2D W 6D AD ACC_DR0 ED RW

Blank fields are Reserved and must not be accessed. # Access is bit specific.

Addr

(0,Hex)

Access

0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 ASD20CR0 90 RW D0
11 51 ASD20CR1 91 RW D1
12 52 ASD20CR2 92 RW D2
13 53 ASD20CR3 93 RW D3
14 54 ASC21CR0 94 RW D4
15 55 ASC21CR1 95 RW D5
16 56 ASC21CR2 96 RW I2C_CFG D6 RW
17 57 ASC21CR3 97 RW I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 I2C_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C DC
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F DF

Name

Addr

(0,Hex)

Access

Name

Addr

(0,Hex)

Access

Name

Addr

(0,Hex)

Access

Document Number: 3-12029 Rev. *E Page 11 of 31

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Table 6. Register Map Bank 0 Table: User Space (continued)

Name

DCB03DR2 2E RW 6E AE ACC_DR3 EE RW
DCB03CR0 2F # 6F AF ACC_DR2 EF RW

Blank fields are Reserved and must not be accessed. # Access is bit specific.

Addr

(0,Hex)

Access

30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #

Name

Addr

(0,Hex)

Access

Name

Addr

(0,Hex)

Access

Name

Addr

(0,Hex)

Table 7. Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0 00 RW 40 ASC10CR0 80 RW C0
PRT0DM1 01 RW 41 ASC10CR1 81 RW C1
PRT0IC0 02 RW 42 ASC10CR2 82 RW C2
PRT0IC1 03 RW 43 ASC10CR3 83 RW C3
PRT1DM0 04 RW 44 ASD11CR0 84 RW C4
PRT1DM1 05 RW 45 ASD11CR1 85 RW C5
PRT1IC0 06 RW 46 ASD11CR2 86 RW C6
PRT1IC1 07 RW 47 ASD11CR3 87 RW C7
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 89 C9
PRT2IC0 0A RW 4A 8A CA
PRT2IC1 0B RW 4B 8B CB

Blank fields are Reserved and must not be accessed. # Access is bit specific.

Addr

(1,Hex)

Access

0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 ASD20CR0 90 RW GDI_O_IN D0 RW
11 51 ASD20CR1 91 RW GDI_E_IN D1 RW
12 52 ASD20CR2 92 RW GDI_O_OU D2 RW
13 53 ASD20CR3 93 RW GDI_E_OU D3 RW
14 54 ASC21CR0 94 RW D4
15 55 ASC21CR1 95 RW D5
16 56 ASC21CR2 96 RW D6

Name

Addr

(1,Hex)

Access

Name

Addr

(1,Hex)

Access

Name

Addr

(1,Hex)

Access

Access

Document Number: 3-12029 Rev. *E Page 12 of 31

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Table 7. Register Map Bank 1 Table: Configuration Space (continued)

Name

DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

DBB01FN 24 RW 64 A4 VLT_CMP E4 R
DBB01IN 25 RW 65 A5 E5
DBB01OU 26 RW AMD_CR1 66 RW A6 E6

DCB02FN 28 RW 68 A8 IMO_TR E8 W
DCB02IN 29 RW 69 A9 ILO_TR E9 W
DCB02OU 2A RW 6A AA BDG_TR EA RW

DCB03FN 2C RW 6C AC EC
DCB03IN 2D RW 6D AD ED
DCB03OU 2E RW 6E AE EE

Blank fields are Reserved and must not be accessed. # Access is bit specific.

Addr

(1,Hex)

17 57 ASC21CR3 97 RW D7
18 58 98 D8
19 59 99 D9
1A 5A 9A DA
1B 5B 9B DB
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW

23 AMD_CR0 63 RW A3 VLT_CR E3 RW

27 ALT_CR0 67 RW A7 E7

2B 6B AB ECO_TR EB W

2F 6F AF EF
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #

Access

Name

Addr

(1,Hex)

Access

Name

Addr

(1,Hex)

Access

Name

Addr

(1,Hex)

Access

Document Number: 3-12029 Rev. *E Page 13 of 31

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Electrical Specifications

5.25

4.75

3.00

93 kHz 12 MHz 24 MHz

CPU Frequency

Vdd Voltage

Valid

Operating

Region

This section presents the DC and AC electrical speci ficati ons of the CY 8C24 x23A auto motive PSoC device. For the l atest electrical
specifications, visit http://www.cypress.com/psoc.

o

Specifications are valid for -40

C ≤ TA ≤ 125oC and TJ ≤ 135oC, except where noted.

Figure 7. Voltage versus CPU Frequency

The following table lists the units of measure that are used in this section.

Table 8. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

o

C degree Celsius μW microwatts
dB decibels mA milli-ampere
fF femto farad ms milli-second
Hz hertz mV milli-volts
KB 1024 bytes nA nanoampere
Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts
kΩ kilohm W ohm
MHz megahertz pA picoampere
MΩ megaohm pF picofarad

μA microampere pp peak-to-peak
μF microfarad ppm parts per million
μH microhenry ps picosecond
μs microsecond sps samples per second
μV microvolts s sigma: one standard deviation
μVrms microvolts root-mean-square V volts

Document Number: 3-12029 Rev. *E Page 14 of 31

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Absolute Maximum Ratings

Table 9. Absolute Maximum Ratings

Symbol Description Min Typ Max Units Notes

T

STG

Storage Temperature -55 +25 +125

o

C Higher storage temperature s

reduce data retention time.
Recommended storage temper­ature is +25°C ± 25°C. Storage
temperatures above 65
degrades reliability. Maximum
combined storage and operational
time at +125°C is 7000 hours.

T

A

Ambient Temperature with Power Applied -40 – +125

o

C
Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +5.75 V
V
V
I

MIO

IO
IOZ

DC Input Voltage Vss - 0.5 – Vdd + 0.5 V
DC Voltage Applied to Tri-state Vss - 0.5 – Vdd + 0.5 V

Maximum Current into any Port Pin -25 – +25 mA
ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.
LU Latch-up Current – – 200 mA

Operating Temperature

Table 10. Operating Temperature

Symbol Description Min Typ Max Units Notes

T

A

T

J

Ambient Temperature -40 – +125

Junction Temperature -40 – +135

o

C

o

C The temperature rise from ambient

to junction is package specific. See

Thermal Impedances per Package

on page 29. The user must limit the
power consumption to comply with
this requirement.

o

C

Document Number: 3-12029 Rev. *E Page 15 of 31

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DC Electrical Characteristics

DC Chip-Level Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 11. DC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

Vdd Supply Voltage 4.75 – 5.25 V
I

DD

Supply Current – 5 8 mA Conditions are Vdd = 5.25V , -40 oC ≤ TA

≤ 125 oC, CPU = 3 MHz, SYSCLK
doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off.

I

SB

I

SBH

I

SBXTL

Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.

Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature.

Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal.

a

a

a

– 4 13 μA Conditions are with internal slow speed

oscillator, Vdd = 5.25V, -40

o

55

C. Analog power = off.

o

C ≤ TA ≤

– 4 100 μA Conditions are with internal slow speed

oscillator, Vdd = 5.25V, 55 oC < TA ≤

o

C. Analog power = off.

125

– 6 15 μA Conditions are with properly loaded, 1

μW max, 32.768 kHz crystal.
Vdd = 5.25V, -40

o

C ≤ TA ≤ 55 oC.

Analog power = off.

I

SBXTLH

Sleep (Mode) Current with POR, LVD, Sleep
Timer , WDT, and external crystal at high temper-

a

ature.

– 6 100 μA Conditions are with properly loaded,

1μW max, 32.768 kHz crystal.
Vdd = 5.25V, 55

o

C < TA ≤ 125oC.

Analog power = off.

V

REF

a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar

Reference Voltage (Bandgap) 1.25 1.3 1.35 V Trimmed for appropriate Vdd.

functions enabled.

DC General Purpose IO Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

Table 12. DC GPIO Specifications

Symbol Description Min Typ Max Units Notes

R

PU

R

PD

V

OH

V

OL

V

IL

V

IH

V

H

I

IL

C

IN

C

OUT

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance.

A

Pull up Resistor 4 5.6 8 kΩ
Pull down Resistor 4 5.6 8 kΩ
High Output Level 3.5 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 tot al

loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).

Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total

loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])). T otal I OL budget

of 150 mA.
Input Low Level – – 0.8 V Vdd = 4.75 to 5.25
Input High Level 2.2 – V Vdd = 4.75 to 5.25
Input Hysterisis – 60 – mV
Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA
Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent.

Temp = 25
Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent.

Temp = 25

o

C

o

C

Document Number: 3-12029 Rev. *E Page 16 of 31

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DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switch ed Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.

Table 13. DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

V

OSOA

TCV
I

EBOA

C

INOA

V

CMOA

Input Offset Voltage (absolute value) Low Power
Input Offset Voltage (absolute value) Mid Power
Input Offset Voltage (absolute value) High Power

Input Offset Voltage Drift – 7.0 35.0 μV/oC

OSOA

Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA
Input Capacitance (Port 0 Analog Pins) – 4.5 10 pF Package and pin

Common Mode Voltage Range
Common Mode Voltage Range (high power or high
opamp bias)

–1.6
–
–

1.3

1.2

11

9
9

0.0 – Vdd

0.5 –

Vdd - 0.5

mV
mV
mV

dependent. T emp = 25

V The common-mode input

voltage range is
measured through an

o

C.

analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the
analog output buffer.

G

OLOA

Open Loop Gain
Power = Low
Power = Medium
Power = High

–
–
–

80
80
80

Specification is applicable

dB

at high power . For all other

dB

bias modes (except high

dB

power, high opamp bias),
minimum is 60 dB.

V

OHIGHOA

V

OLOWOA

I

SOA

PSRR

High Output Voltage Swing (worst case internal load)
Power = Low
Power = Medium
Power = High

Vdd - 0.2
Vdd - 0.2
Vdd - 0.5

–
–
–

–
–
–

V
V
V

Low Output Voltage Swing (worst case internal load)
Power = Low
Power = Medium
Power = High

–
–
–

–
–
–

0.2

0.2

0.5

V
V
V

Supply Current (including associated AGND buffer)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
Power = High, Opamp Bias = High

Supply Voltage Rejection Ratio – 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or

OA

–
–
–
–
–
–

150
300

600
1200
2400
4600

200
400

800
1600
3200
6400

μA
μA
μA
μA
μA
μA

(Vdd - 1.25V) ≤ VIN ≤ Vdd

Document Number: 3-12029 Rev. *E Page 17 of 31

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DC Low Power Comparator Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 14. DC Low Power Comparator Specifications

Symbol Description Min Typ Max Units

V

REFLPC

I

SLPC

V

OSLPC

Low power comparator (LPC) reference voltage range 0.2 – Vdd - 1 V
LPC supply current – 10 40 μA
LPC voltage offset – 2.5 30 mV

DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 15. DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units

V

OSOB

TCV

OSOB

V

CMOB

R

OUTOB

V

OHIGHOB

V

OLOWOB

I

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 18 mV
Input Offset Voltage Drift – +6 – μV/°C
Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V
Output Resistance – 1 – W
High Output Voltage Swing (Load = 32 ohms to Vdd/2) 0.5 x Vdd + 1.1 – – V
Low Output Voltage Swing (Load = 32 ohms to Vdd/2) – – 0.5 x Vdd - 1.3 V
Supply Current Including Bias Cell (No Load)

Power = Low
Power = High

Supply Voltage Rejection Ratio – 64 – dB

OB

–
–

1.1

2.6

5.1

8.8

mA
mA

Document Number: 3-12029 Rev. *E Page 18 of 31

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DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.

Note Avoid using P2[4] for digital signaling when using an analog resource that depen ds on the Analog Reference. Some coup ling
of the digital signal may appear on the AGND.

Table 16. DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.25 1.30 1.35 V
– AGND = Vdd/2

CT Block Power = High

– AGND = 2 x BandGap

a

Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V

a

CT Block Power = High 2.4 2.6 2.8 V

– AGND = P2[4] (P2[4] = Vdd/2)

a

CT Block Power = High P2[4] - 0.02 P2[4] P2[4] + 0.02 V

– AGND = BandGap

a

CT Block Power = High 1.23 1.30 1.37 V

– AGND = 1.6 x BandGap

a

CT Block Power = High 1.98 2.08 2.14 V

– AGND Column to Column Variation (AGND =

Vdd/2)

a

-0.035 0.000 0.035 V

CT Block Power = High

– RefHi = Vdd/2 + BandGap

Ref Control Power = High

Vdd/2 + 1.15 Vdd/2 +1.30 Vdd/2 +1.45 V

– RefHi = 3 x BandGap

Ref Control Power = High

3.65 3.9 4.15 V

– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

Ref Control Power = High

P2[6] + 2.4 P2[6] + 2.6 P2[6] + 2.8 V

– RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

Ref Control Power = High

P2[4] + 1.24 P2[4] +1.30 P2[4] + 1.36 V

– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

Ref Control Power = High

P2[4] + P2[6] - 0.1 P2[4] + P2[6] P2[4] + P2[6] + 0.1 V

– RefHi = 3.2 x BandGap

Ref Control Power = High

3.9 4.16 4.42 V

– RefLo = Vdd/2 – BandGap

Ref Control Power = High

Vdd/2 - 1.45 Vdd/2 - 1.3 1.15 V

– RefLo = BandGap

Ref Control Power = High

1.15 1.3 1.45 V

– RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

Ref Control Power = High

2.4 - P2[6] 2.6 - P2[6] 2.8 - P2[6] V

– RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

Ref Control Power = High

P2[4] - 1.45 1.3 P2[4] - 1.15 V

– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

Ref Control Power = High

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.05V.

P2[4] - P2[6] - 0.1 P2[4] - P2[6] P2[4] - P2[6] + 0.1 V

Document Number: 3-12029 Rev. *E Page 19 of 31

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DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 17. DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Units

R

CT

C

SC

Resistor Unit Value (Continuous Time) – 12.24 – kΩ
Capacitor Unit V alue (Switch Cap) – 80 – fF

DC POR and LVD Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable
System-on-Chip Technical Reference Manual for more information on the VLT_CR register.

Table 18. DC POR and LVD Specifications

Symbol Description Min Typ Max Units

Vdd Value for PPOR Trip (positive ramp)

V

PPOR2R

PORLEV[1:0] = 10b 4.55 4.70 V
Vdd Value for PPOR Trip (negative ramp)

V

PPOR2

PORLEV[1:0] = 10b 4.55 V
PPOR Hysteresis

V

PH2

PORLEV[1:0] = 10b – 0 – mV

Vdd Value for LVD Trip
V
V

LVD6
LVD7

VM[2:0] = 110b

VM[2:0] = 111b

4.62

4.710

4.73

4.814

4.83

4.950

V
V

DC Programming Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 19. DC Programming Specifications

Symbol Description Min Typ Max Units Notes

Vdd

IWRITE

I

DDP

V

ILP

V

IHP

I

ILP

I

IHP

V

OLV

V

OHV

Flash

Flash

Flash

a. For the full temperatu re ran ge, th e user must employ a t emperat ure sen sor user modu le (FlashTemp) and feed the result to the temperature argument before writ­b. A maximum of 64 x 100 block endurance cycles is allowed.

c. Flash data retention based on the use condition of ≤ 7000 hours at TA ≤ 125°C and the remaining time at TA ≤ 65°C.

Supply Voltage for Flash Write Operations 4.75 – – V

Supply Current During Programming or Verify – 10 25 mA

Input Low Voltage During Programming or Verify – – 0.8 V

Input High Voltage During Programming or Verify 2.2 – – V

Input Current when Applying Vilp to P1[0] or P1[1] During

– – 0.2 mA Driving intern al

Programming or Verify

Input Current when Applying Vihp to P1[0] or P1[1] During

– – 1.5 mA Driving intern al

Programming or Verify

Output Low Voltage During Programming or Verify – – Vss + 0.75 V

Output High Voltage During Programming or Verify 3.5 – Vdd V

Flash Endurance (per block)

ENPB

Flash Endurance (total)

ENT

Flash Data Retention

DR

ing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

a

a,b

c

100 – – – Erase/write

6,400 – – – Erase/write

15 – – Years

pull down resistor.

pull down resistor.

cycles per block.

cycles.

Document Number: 3-12029 Rev. *E Page 20 of 31

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AC Electrical Characteristics

AC Chip-Level Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

Table 20. AC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

F

IMO24

F

CPU1

F

48M

F

24M

F

32K1

F

32K2

F

PLL

Jitter24M2 24 MHz Period Jitter (PLL) – – 800 ps
T

PLLSLEW

T

PLLSLEWSLOW

T

OS

T

OSACC

Jitter32k 32 kHz Period Jitter – 100 ns
T

XRST

DC24M 24 MHz Duty Cycle 40 50 60 %
Step24M 24 MHz Trim Step Size – 50 – kHz
Jitter24M1P 24 MHz Period Jitter (IMO) Peak-to-Peak – 300 ps
Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean

F

MAX

T

RAMP

a. See the individual user modu le data sheets for information on maximum frequencies for user modules.

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Internal Main Oscillator Frequency for 24 MHz 22.95 24 24.96 MHz Trimmed. Using factory trim

values.
CPU Frequency (5V Nominal) 0.09 12 12.48 MHz
Digital PSoC Block Frequency – – – MHz Not allowed.
Digital PSoC Block Frequency 0 24 24.96

a

MHz
Internal Low Speed Oscillator Frequency 15 32 64 kHz
External Crystal Oscillator – 32.768 – kHz Accuracy is capacitor and

crystal dependent. 50% duty
cycle.

PLL Frequency – 23.986 – MHz A multiple (x732) of crystal

frequency.

PLL Lock Time 0.5 – 10 ms
PLL Lock Time for Low Gain Setting 0.5 – 50 ms
External Crystal Oscillator Startup to 1% – 1700 2620 ms
External Crystal Oscillator Startup to 100 ppm – 2800 3800 ms

External Reset Pulse Width 10 – – μs

– – 600 ps

Squared
Maximum frequency of signal on row input or

– – 12.48 MHz

row output.
Supply Ramp Time 0 – – μs

Document Number: 3-12029 Rev. *E Page 21 of 31

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Figure 8. PLL Lock Timing Diagram

24 MHz

F

PLL

PLL

Enable

T

PLLSLEW

PLL

Gain

0

24 MHz

F

PLL

PLL

Enable

T

PLLSLEWLOW

PLL

Gain

1

32 kHz

F

32K2

32K

Select

T

OS

Jitter24M1

F

24M

Jitter32k

F

32K2

Figure 9. PLL Lock for Low Gain Setting Timing Diagr am

Figure 10. External Crystal Oscillator Startup Timing Diagram

Figure 11. 24 MHz Period Jitter (IMO) Timing Diagram

Figure 12. 32 kHz Period Jitter (ECO) Timing Diagram

Document Number: 3-12029 Rev. *E Page 22 of 31

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AC General Purpose IO Specifications

TFallF
TFallS

TRiseF

TRiseS

90%

10%

GPI O

Pin

Output

Voltage

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 21. AC GPIO Specifications

Symbol Description Min Typ Max Units Notes

F

GPIO

GPIO Operating Frequency 0 – 12.48 MHz Normal Strong Mode
TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 2 – 22 ns Vdd = 4.75 to 5.25V, 10% - 90%
TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 22 ns Vdd = 4.75 to 5.25V, 10% - 90%
TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 9 27 – ns Vdd = 4.75 to 5.25V, 10% - 90%
TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 9 22 – ns Vdd = 4.75 to 5.25V, 10% - 90%

Figure 13. GPIO Timing Diagram

AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 22. AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units

Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)

Power = Low

Power = Low, Opamp Bias = High

Power = Medium

Power = Medium, Opamp Bias = High

Power = High

Power = High, Opamp Bias = High

Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain)

Power = Low

Power = Low, Opamp Bias = High

Power = Medium

Power = Medium, Opamp Bias = High

Power = High

Power = High, Opamp Bias = High

Gain Bandwidth Product

Power = Low

Power = Low, Opamp Bias = High

Power = Medium

Power = Medium, Opamp Bias = High

Power = High

Power = High, Opamp Bias = High

0.15

0.15

0.15

1.7

1.7

6.5

0.01

0.01

0.01

0.5

0.5

4.0

0.75

0.75

0.75

3.1

3.1

5.4

–

–
–

–

–
–

–

–
–

SR

SR

BW

ROA

FOA

OA

V/μs
V/μs
V/μs
V/μs
V/μs
V/μs

V/μs
V/μs
V/μs
V/μs
V/μs
V/μs

MHz
MHz
MHz
MHz
MHz
MHz

Document Number: 3-12029 Rev. *E Page 23 of 31

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AC Low Power Comparator Specifications

100

1000

10000

0.001 0.01 0.1 1 10 100Freq (kHz)

dBV/rtHz

0

0.01

0.1

1.0
10

10

100

1000

10000

0.001 0.01 0.1 1 10 100

Freq (kHz)

nV/rtHz

PH_BH
PH_BL
PM_BL
PL_BL

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 23. AC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

T

RLPC

LPC response time – – 50 μs ≥ 50 mV overdrive comparator

reference set within V

REFLPC

.

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 14. Typical AGND Noise with P2[4] Bypass

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.

Figure 15. Typical Opamp Noise

Document Number: 3-12029 Rev. *E Page 24 of 31

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AC Digital Block Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 24. AC Digital Block Specifications

Function Description Min Typ Max Units Notes

All Functions Maximum Block Clocking Frequency 24.96 MHz
Timer Capture Pulse Width 50

a

– – ns
Maximum Frequency, No Capture – – 24.96 MHz 4.75V < Vdd < 5.25V
Maximum Frequency, With Capture – – 24.96 MHz

Counter Enable Pulse Width 50

a

– – ns
Maximum Frequency, No Enable Input – – 24.96 MHz 4.75V < Vdd < 5.25 V
Maximum Frequency, Enable Input – – 24.96 MHz

Dead Band Kill Pulse Width:

Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50
Disable Mode 50

a

– – ns

a

– – ns
Maximum Frequency – – 24.96 MHz 4.75V < Vdd < 5.25V

CRCPRS

Maximum Input Clock Frequency – – 24.96 MHz 4.75V < Vdd < 5.25V

(PRS Mode)
CRCPRS

Maximum Input Clock Frequency – – 24.96 MHz

(CRC Mode)
SPIM Maximum Input Clock Frequency – – 4.1 MHz Maximum data rate at 4.1 MHz

due to 2 x over clocking.

SPIS Maximum Input Clock Frequency – – 2.05 MHz

Width of SS_ Negated Between Transmissions 50

a

– – ns

Transmitter Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 3.08

MHz due to 8 x over clocking.

Receiver Maximum Input Clock Frequency – 16 24.96 MHz Maximum data rate at 3.08

MHz due to 8 x over clocking.

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

Document Number: 3-12029 Rev. *E Page 25 of 31

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AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 25. AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units

T

ROB

T

SOB

SR

SR

BW

BW

ROB

FOB

Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High

Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High

Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load

OB

Power = Low
Power = High

Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load

OB

Power = Low
Power = High

–
–

–
–

0.6

0.6

0.6

0.6

0.8

0.8

300
300

–
–

–
–

–
–

–
–

–
–

–
–

3
3

3
3

–
–

–
–

–
–

–
–

μs
μs

μs
μs

V/μs
V/μs

V/μs
V/μs

MHz
MHz

kHz
kHz

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 26. AC External Clock Specifications

Symbol Description Min Typ Max Units

F

OSCEXT

– High Period 20.6
– Low Period 20.6
– Power Up IMO to Switch 150

Frequency 0 – 24.24 MHz

– –ns
– –ns
– – μs

AC Programming Specifications

The following table lists guaranteed maximum and min imum specificat ions for the voltage and tempera ture ranges: 4.75V to 5.25V
and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

Table 27. AC Programming Specifications

Symbol Description Min Typ Max Units

T

RSCLK

T

FSCLK

T

SSCLK

T

HSCLK

F

SCLK

T

ERASEB

T

WRITE

T

DSCLK

Rise Time of SCLK 1 – 20 ns
Fall Time of SCLK 1 – 20 ns
Data Set up Time to Falling Edge of SCLK 40 – – ns
Data Hold Time from Falling Edge of SCLK 40 – – ns
Frequency of SCLK 0 – 8 MHz
Flash Erase Time (Bloc k ) – 15 – ms
Flash Block Write Time – 30 – ms
Data Out Delay from Falling Edge of SCLK – – 45 ns

Document Number: 3-12029 Rev. *E Page 26 of 31

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2

SDA

SCL

S

Sr SP

T

BUFI2C

T

SPI2C

T

HDSTAI2C

T

SUSTOI2C

T

SUSTAI2C

T

LOWI2C

T

HIGHI2C

T

HDDATI2C

T

HDSTAI2C

T

SUDATI2C

C Specifications

AC I

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T

Table 28. AC Characteristics of the I

Symbol Description

F

SCLI2C

T

HDSTAI2C

T

LOWI2C

T

HIGHI2C

T

SUSTAI2C

T

HDDATI2C

T

SUDATI2C

T

SUSTOI2C

T

BUFI2C

T

SPI2C

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

A

2

C SDA and SCL Pins

Standard Mode Fast Mode

Min Max Min Max

Units

SCL Clock Frequency 0 100 0 400 kHz
Hold Time (repeated) ST ART Condition. After this period, the first

4.0 –0.6– μs

clock pulse is generated.
LOW Period of the SCL Clock 4.7 –1.3– μs
HIGH Period of the SCL Clock 4.0 –0.6– μs
Setup Time for a Repeated START Condition 4.7 –0.6– μs
Data Hold Time 0 –0– μs
Data Setup Time 250 – 100

a

–ns
Setup Time for STOP Condition 4.0 –0.6– μs
Bus Free Time Between a STOP and START Condition 4.7 –1.3– μs
Pulse Width of spikes are suppressed by the input filter. – – 0 50 ns

≥ 250 ns must then be met. This is automatically the

SU;DAT

rmax

+ t

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

SU;DAT

Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus

Document Number: 3-12029 Rev. *E Page 27 of 31

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Packaging Information

51-85077 *C

This section illustrates the packaging specifications for the CY8C24x23A automotive PSoC device, along with the thermal impedances
for each package and the typical package capacitance on crystal pins.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

Figure 17. 20-Pin (210-Mil) SSOP

Document Number: 3-12029 Rev. *E Page 28 of 31

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Figure 18. 28-Pin (210-Mil) SSOP

51-85079 *C

Thermal Impedances Capacitance on Crystal Pins

Table 29. Thermal Impedances per Package

Package Typical θ

20 SSOP 117 oC/W
28 SSOP 101 oC/W

* TJ = TA + POWER x θ

JA

JA

*

Table 30. Typical Package Capacitance on Crystal Pins

Package Package Capacitance

20 SSOP 2.6 pF
28 SSOP 2.8 pF

Solder Reflow Peak Temperature

The following table lists the minimum solder reflow peak temperature to achieve good solderability.

Table 31. Solder Reflow Peak Temperature

Package Minimum Peak Temperature* Maximum Peak Temperature

20 SSOP 240oC 260oC
28 SSOP 240oC 260oC

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with
Sn-Pb or 245 ± 5

o

C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

Document Number: 3-12029 Rev. *E Page 29 of 31

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Ordering Information

CY 8 C 24 xxx-12xx

Package Type: Thermal Rating:

PX = PDIP Pb-Free C = Commercial
SX = SOIC Pb-Free I = Industrial
PVX = SSOP Pb-Free E = Extended
LFX = QFN Pb-Free
LKX = QFN Pb-Free

AX = TQFP Pb-Free
Speed: 12 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress

The following table lists the CY8C24x23A automotive PSoC device group’s key package features and ordering codes.

Table 32. CY8C24x23A Automotive PSoC Key Features and Ordering Information

Package

20 Pin (210 Mil) SSOP CY8C24223A-12PVXE 4K 256 No -40°C to +125°C 4 6 16 8 2 Yes
20 Pin (210 Mil) SSOP

(Tape and Reel)
28 Pin (210 Mil) SSOP CY8C24423A-12PVXE 4K 256 No -40°C to +125°C 4 6 24 10 2 Yes
28 Pin (210 Mil) SSOP

(Tape and Reel)

CY8C24223A-12PVXET 4K 256 No -40°C to +125°C 4 6 16 8 2 Yes

CY8C24423A-12PVXET 4K 256 No -40°C to +125°C 4 6 24 10 2 Yes

Ordering

Code

Flash

(Bytes)

RAM

(Bytes)

Pump

Switch Mode

Range

Temperature

Digital Blocks

Analog Blocks

Digital IO Pins

Analog Inputs

Analog Outputs

Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

Ordering Code Definitions

XRES Pin

Document Number: 3-12029 Rev. *E Page 30 of 31

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Document History Page

Document Title: CY8C24223A, CY8C24423A PSoC® Programmable System-on-Chip™
Document Number: 38-12029

Rev. ECN

**

238268 SFV See ECN First release of CY8C24x23A Automotive Preliminary Data Sheet.

*A

271471 HMT See ECN Update per SFV memo. Input MWR changes, including removing SMP. Change

Orig. of

Change

Submission

Date

Description of Change

to Final.

*B

286089 HMT See ECN Update characterization data. Fine tune pinouts. Add Reflow Peak Temp. table.

*C 512475 HMT See ECN Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add ISSP note

to pinout tables. Update typical and recommended Storage Temperature per
extended temp. specs. Update CY branding and QFN convention. Update
copyright and trademarks.

*D

2101387 AESA See ECN Post to www.cypress.com

*E 2619935 OGNE/AESA 12/11/2008 Changed title to “CY8C24223A, CY8C24423A PSoC® Programmable

System-on-Chip™”
Added note on digital signaling in DC Analog Reference Specifications on page

19.
Added Die Sales information note to Ordering Information on page 30.
Updated data sheet template.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office
closest to you, visit us at cypress.com/sales.

Products

PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com

PSoC Solutions

General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb

© Cypress Semiconductor Corporation, 2004- 2008. The infor mation cont ain ed herein is subj ect to change wi thout notice. C ypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor inte nd ed to be us ed for
medical, life support, life saving, critica l contr o l or safety applications, unless pursuant to an express wr itten agreement with Cypress. Furthermore, Cypress does not auth ori ze i t s products for use as
critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the us er . The inclu sion of Cypress p roducts in life -support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction wit h a Cypress
integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Co de except as speci fied above is pro hibited with out
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the applic ation or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot author ize its p roducts fo r use as critical compon ents in life-su pport systems whe re
a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 3-12029 Rev. *E Revised December 11, 2008 Page 31 of 31

PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered t rade mark of Cypress S em ic on duct or C orp. A ll other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.

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