CYPRESS CY8C24123A, CY8C24223A, CY8C24423A User Manual
Features
查询CY8C24123A供应商
PSoC™ Mixed-Signal Array Final Data Sheet
CY8C24123A,
CY8C24223A, and CY8C24423A
■ Powerful Harvard Architecture Processor
■ Advanced Peripherals (PSoC Blocks)
❐ M8C Processor Speeds to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 2.4 to 5.25 V Operating Voltage
❐ Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
Port 2 Port 1 Port 0
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Interrupt
Controller
SROM Flash 4K
CPU Core (M8C)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
(1 Row,
4 Blocks)
Global Analog I nte rconnect
ANALOG SYSTEM
Analog
Block
Array
(2 Columns,
6 Blocks)
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ High-Accuracy 24 MHz with Optional 32 kHz
Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 4K Bytes Flash Program Storage 50,000
Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP ™)
❐ Partial Flash Updat es
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐ Up to 10 Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
Analog
Drivers
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Sleep and
Watchdog
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of convenient pinouts and packages.
The PSoC architecture, as illustrated on the left, is com pri se d of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
Analog
Ref
the device r esources to be c ombined into a compl ete custom
system. The PSoC CY8C2 4x23A f amily ca n ha ve up t o three IO
ports that connec t to the gl obal di git al and a nalog i ntercon ne cts ,
Analog
Input
Muxing
providing access to 4 digital blocks and 6 analog blocks.
The PSoC Core
■ New CY8C24x23A PSoC Device
❐ Derived from the CY8C24x23 Device
❐ Low Power and Low Voltage (2.4V)
■ Additional System Resources
2
❐ I
C™ Slave, Master, and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software
(PSoC™ Designer)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
The PSoC Core is a powerful engine that supports a rich feature set. Th e co re in cl ud es a C PU , memo r y, clocks, and c on fig -
Digital
Clocks
Multiply
Accum.
Decimator
I2C
POR and LVD
System Rese ts
SYSTEM RESOURCES
Internal
Voltage
Ref.
Switch
Mode
Pump
urable GPIO (General Purpose IO).
The M8C C PU core is a powerfu l proce ssor wit h spee ds up t o
24 MHz, providing a four MI PS 8-bit Harvar d archit ecture m icro-
September 8, 2004 © Cypress MicroSystems, Inc. 2004 — Document No. 38-12028 Rev. *B 1
CY8C24x23A Final Data Sheet PSoC™ Overview
processor. The CPU utilizes an interrupt controller with 11 vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 4 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software
IP protection.
The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real Time Cloc k (RT C) and can opti onally genera te a crys tal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide conne ct ion t o the CP U, di gital and analog
resources of the devi ce. Each pin’ s dri ve mod e may b e selec te d
from eight options, allowing great flexibility in external interfacing. Every pin also has the c apa bility to gen erate a syste m inte rrupt on high level, low level, and change from last read.
Digital peripheral configurations include those listed below.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 24 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity
■ SPI master and slave
■ I2C slave and multi-master (1 available as a System
Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA (up to 1)
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This co nfig ura bil ity free s y our d e si gn s fro m th e co nstraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Charac-
teristics” on page 3.
The Analog System
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to fo rm 8, 16 , 24, and 32-bit p eriphe rals, wh ich
are called user module references.
Port 1
Port 2
D
C
l
a
t
i
g
i
m
C
F
o
r
c
o
k
l
r
o
e
To System Bus
s
DIGITAL SYSTEM
Digital PSoC Block Array
8
DBB00 DBB01 DCB02 DCB03
Row Input
Configuration
GIE[7:0]
GIO[7:0]
Row 0
Global Digital
Interconnect
Port 0
To Analog
System
4
4
GOE[7:0]
GOO[7:0]
Configuration
Row Output
8
The Analog System is com posed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and
can be customized to support specific appl ica tio n req uire me nts.
Some of the more common PSoC analog functions (most available as user modules) are listed below.
■ Analog-to-digital converters (up to 2, with 6- to 14-bit resolu-
tion, selectable as Incr emental, Delta Sigma, and SAR)
■ Filters (2 and 4 pole band-pass, low-pass, and notch)
■ Amplifiers (up to 2, with selectable gain to 48x)
■ Instrumentation amplifiers (1 with selectable gain to 93x)
■ Comparators (up to 2, with 16 selectable thresholds)
■ DACs (up to 2, with 6- to 9-bit resolution)
■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■ High current output drivers (two w ith 30 mA drive as a Core
88
Resource)
■ 1.3V refer ence (as a System Resource)
■ DTMF dialer
■ Modulators
■ Correlators
■ Peak detectors
■ Many other topologies possible
Digital System Block Diagram
September 8, 2004 Document No. 38-12028 Rev. *B 2
CY8C24x23A Final Data Sheet PSoC™ Overview
p
Analog blocks are arranged in a column of three, which
includes one CT (Continuous Time) and two SC (Switched
Capacitor) blocks, as shown in the figure below.
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Interface to
Digital System
Array Input Confi guration
ACI0[1:0]
Block Array
ACB00 ACB01
ASC10
ASD20
RefHi
RefLo
AGND
ACI1[1:0]
ASD11
ASC21
Analog Reference
Reference
Generators
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
RefIn
P2[4]
AGNDIn
P2[2]
P2[0]
AGNDIn
RefIn
Bandga
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below.
■ Digital clock dividers provide three customizable clock fre-
quencies for use in applic ations . The clo cks c an be route d to
both the digital a nd analog systems. Additiona l clocks c an be
generated using digital PSoC blocks as clock dividers.
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumula te, to assi st in both genera l math as well
as digital filters.
■ The decimator provides a custom hardware filter for digital
signal processing applications inc lud in g t he creation of De lt a
Sigma ADCs.
■ The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of f alling voltage levels, w hile the adv anced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■ An internal 1.3V refe rence provides an absolute reference fo r
the analog system, including ADCs and DACs.
■ An integrated switch mode pump (S MP) gene rate s norm al
operating volt ages f rom a single 1.2V batt ery cel l, providin g a
low cost boost converter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is shown in the next to the last row of
the table.
PSoC Device Characteristics
M8C Interface (Address Bus, Data Bus, Etc.)
Analog System Block Diagram
September 8, 2004 Document No. 38-12028 Rev. *B 3
PSoC Device
Group
Digital Rows
Digital Blocks
Digital IO (max)
CY8C29x66 64 4 16 12 4 4 12 2 KB 32 KB
CY8C27x43
CY8C24x23 24 1 4 12 2 2 6 256 Bytes 4 KB
CY8C24x23A 24 1 4 12 2 2 6 256 Bytes 4 KB
CY8C22x13
CY8C21x34
CY8C21x23
a. Limited analog functionality.
44 2 8 12 4 4 12 256 Bytes 16 KB
16 1 4 8 1 1 3 256 Bytes 2 KB
28 1 4 28 0 2
16 1 4 8 0 2
Analog Inputs
Analog Outputs
Analog Blocks
Analog Columns
a
4
a
4
Amount of SRAM
512 Bytes 8 KB
256 Bytes 4 KB
Amount of Flash
CY8C24x23A Final Data Sheet PSoC™ Overview
Getting Started
The quickest path to understanding th e PSoC s ili co n is by rea ding this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed Signal Array Technical Reference Manual.
For up-to-date Ordering, Packag ing, an d Electri cal Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at http://www.onfulfillment.com/cypressstore/ contains develop-
ment kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view
a current list of available items.
Tele-Training
Free PSoC "Tele-training" is available for beginners and taught
by a live marketing or appli ca tio n eng in eer ov er th e pho ne . F ive
training cl asses are availabl e to accelerate th e learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the
tele-training, see http://www.cypress.com/support/training.cfm.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to complete d PSoC d esign s. To contact or be come a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Development Tools
The Cypress MicroSystems PSoC Designer is a Microsoft
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
PSoCTM
Designer
Importable
Design
Database
Device
Database
Application
Database
Project
Database
User
Modules
Library
Graphical Designer
Interface
Results
Commands
TM
PSoC
Designer
Core
Engine
Context
Sensitive
Help
PSoC
Configuration
Sheet
Manufacturing
Information
File
®
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To locate the PSoC application notes, go to
Emulation
Pod
In-Circuit
Emulator
http://www.cypress.com/design/results.cfm.
PSoC Designer Subsystems
September 8, 2004 Document No. 38-12028 Rev. *B 4
Device
Programmer
CY8C24x23A Final Data Sheet PSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
The Device Edi tor su bsyst em al lows th e use r to se lect di ffere nt
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application programming in conj unc tion with the D evice Data S heet . Once the
framework is generated, the user can add application-specific
code to flesh out the fr am ew ork . It’s also possible to change the
selected components and regenerate the framework.
Design Browser
The Design Browser allows users to select and import preconfigured desi g ns into th e u se r’s project. Use rs ca n ea s il y br ow se
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tool s i nclude a 300-baud modem , LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, compile, link, and build.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consist s of a bas e unit th at conne ct s to th e PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family ar e ava ilabl e sep arate ly. The emulation pod t akes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries automatically use abso lut e addre ssing or ca n be co mpil ed in relat ive
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
September 8, 2004 Document No. 38-12028 Rev. *B 5
CY8C24x23A Final Data Sheet PSoC™ Overview
User Module Development Process
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and d igital hard ware blocks give the PS oC archite cture
a unique flexibility that p ays d ivide nds in mana gi ng specifi catio n
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its fu nction and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative devel op men t cy cl es perm it y ou to adapt the hardware as well as the software. This substantially lowers the risk
of having to select a different part to meet the final design
requirements.
To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
applicati on. For exam ple, a Pulse Width Modula tor User Module configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides highlevel functions to control and respond to hardware events at
run-time. The API als o provides o ptional inte rrupt servic e routines that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSo C Desi gn er ID E. Th es e data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user mod ule p ara me ter a nd d oc um ent s the setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to develo ping co de for the proj ect, yo u
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specif ic atio n an d pro vi des the high -le vel us er
module API functions.
Device Editor
User
Module
Selection
Placement
and
Parameter-
ization
Source
Code
Generator
Generate
Application
Application Editor
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the devel opm en t proc es s t ak es pla ce insi de the
PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint event s tha t inc lu de m oni tori ng ad dres s and da t a bu s
values, memory locations and external signals.
September 8, 2004 Document No. 38-12028 Rev. *B 6
CY8C24x23A Final Data Sheet PSoC™ Overview
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC™ Programmable System-on-Chip™
PWM pulse width modulator
SC switched capacitor
SLIMO slow IMO
SMP switch mode pump
SRAM static random access memory
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 15 lists all the abbreviations
used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexi d ec im al nu mber s ma y al so be re p res en t ed by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Table of Contents
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed Signal Array Technical Refer-
ence Manual. This document encompasses and is organized
into the following chapters and sections.
1. Pin Information .................................................... ...... ...8
1.1 Pinouts ................................................................... 8
1.1.1 8-Pin Part Pinout ........................................ 8
1.1.2 20-Pin Part Pinout ......................................9
1.1.3 28-Pin Part Pinout ....................................10
1.1.4 32-Pin Part Pinout ....................................11
2. Register Reference .....................................................12
2.1 Register Conventions ........................................... 12
2.1.1 Abbreviations Used .................................. 12
2.2 Register Mapping Tables ..................................... 12
3. Electrical Specifications ............................................ 15
3.1 Absolute Maximum Ratings ................................ 16
3.2 Operating Temperature ....................................... 16
3.3 DC Electrical Characteristics ................................17
3.3.1 DC Chip-Level Specifications ................... 17
3.3.2 DC General Purpose IO Specifications .... 18
3.3.3 DC Operational Amplifier Specifications ... 19
3.3.4 DC Analog Output Buffer Specifications ... 22
3.3.5 DC Switch Mode Pump Specifications ..... 24
3.3.6 DC Analog Reference Specifications ....... 25
3.3.7 DC Analog PSoC Block Specifications ..... 26
3.3.8 DC POR, SMP, and LVD Specifications ... 27
3.3.9 DC Programming Specifications ...............28
3.4 AC Electrical Characteristics ................................ 29
3.4.1 AC Chip-Level Specifications ...................29
3.4.2 AC General Purpose IO Specifications .... 32
3.4.3 AC Operational Amplifier Specifications ... 33
3.4.4 AC Digital Block Specifications ................. 34
3.4.5 AC Analog Output Buffer Specifications ... 36
3.4.6 AC External Clock Specifications ............. 37
3.4.7 AC Programming Specifications ............... 38
3.4.8 AC I2C Specifications ............................... 39
4. Packaging Information ............................................... 40
4.1 Packaging Dimensions ......................................... 40
4.2 Thermal Impedances ..........................................45
4.3 Capacitance on Crystal Pins ...............................45
5. Ordering Information .................................................. 46
5.1 Ordering Code Definitions .................................... 46
6. Sales and Company Information ............................... 47
6.1 Revision History ................................................... 47
6.2 Copyrights and Code Protection .......................... 47
September 8, 2004 Document No. 38-12028 Rev. *B 7
1. Pin Information
A
This chapter describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations.
1.1 Pinouts
The CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every
port pin (l abeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.1 8-Pin Part Pinout
Table 1-1. 8-Pin Part Pinout (PDIP, SOIC)
Pin
No.
1 IO IO P0[5] Analog column mux input and column output.
2 IO IO P0[3] Analog column mux input and column output.
3 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
4 Power Vss Ground connection.
5 IO P1[0] Crystal Output (XTALout), I2C Serial Data
6 IO I P0[2] Analog column mux input.
7 IO I P0[4] Analog column mux input.
8 Power Vdd Supply voltage.
Type
Digital Analog
Pin
Name
Description
(SDA)
CY8C24123A 8-Pin PSoC Device
AIO, P0[5]
AIO, P0[3]
I2C SCL, XTALin, P1[1]
Vss
1
PDIP
2
SOIC
3
4
Vdd
8
P0[4], AI
7
P0[2], AI
6
P1[0], XTALout, I2C SD
5
LEGEND: A = Analog, I = Input, and O = Output.
September 8, 2004 Document No. 38-12028 Rev. *B 8
CY8C24x23A Final Data Sheet 1. Pin Information
A
1.1.2 20-Pin Part Pinout
Table 1-2. 20-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
1 IO I P0[7] Analog column mux inpu t .
2 IO IO P0[5] Analog column mux input and column out p ut .
3 IO IO P0[3] Analog column mux input and column out p ut .
4 IO I P0[1] Analog column mux inpu t .
5 Power SMP Switch Mode Pump (SMP) connection to
6 IO P1[7] I2C Serial Clock (SCL)
7 IO P1[5] I2C Serial Data (SDA)
8 IO P1[3]
9 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
10 Power Vss Ground connection.
11 IO P1[0] Crystal Output (XTALout), I2C Serial Data
12 IO P1[2]
13 IO P1[4] Optional External Clock Input (EXTCLK)
14 IO P1[6]
15 Input XRES Active high external reset with internal pull
16 IO I P0[0] Analog column mux input.
17 IO I P0[2] Analog column mux input.
18 IO I P0[4] Analog column mux input.
19 IO I P0[6] Analog column mux input.
20 Power Vdd Supply voltage.
Type
Digital Analog
Pin
Name
external components requ i red .
(SDA)
down.
Description
I2C SCL, XTALin, P1[1]
CY8C24223A 20-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
Vss
10
1
2
3
4
5
6
7
8
9
PDIP
SSOP
SOIC
20
19
18
17
16
15
14
13
12
11
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SD
LEGEND: A = Analog, I = Input, and O = Output.
September 8, 2004 Document No. 38-12028 Rev. *B 9
CY8C24x23A Final Data Sheet 1. Pin Information
A
1.1.3 28-Pin Part Pinout
Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
1 IO I P0[7] Analog column mux input.
2 IO IO P0[5] Analog column mux input and column output.
3 IO IO P0[3] Analog column mux input and column output.
4 IO I P0[1] Analog column mux input.
5 IO P2[7]
6 IO P2[5]
7 IO I P2[3] Direct switched capacitor block input.
8 IO I P2[1] Direct switched capacitor block input.
9 Power SMP Switch Mode Pump (SMP) connection to
10 IO P1[7] I2C Serial Clock (SCL)
11 IO P1[5] I2C Serial Data (SDA)
12 IO P1[3]
13 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
14 Power Vss Ground connection.
15 IO P1[0] Crystal Output (XTALout), I2C Serial Data
16 IO P1[2]
17 IO P 1 [4] Opti o na l Ext er nal Clock Input (EXTCLK)
18 IO P1[6]
19 Input XRES Active high external reset with internal pull
20 IO I P2[0] Direct switched capacitor block input.
21 IO I P2[2] Direct switched capacitor block input.
22 IO P2[4] External Analog Ground (AGND)
23 IO P2[6] External Voltage Reference (VRef)
24 IO I P0[0] Analog column mux input.
25 IO I P0[2] Analog column mux input.
26 IO I P0[4] Analog column mux input.
27 IO I P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
Type
Digital Analog
Pin
Name
external components required.
(SDA)
down.
Description
I2C SCL, XTALin, P1[1]
CY8C24423A 28-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
AI, P2[3]
AI, P2[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P2[7]
P2[5]
SMP
P1[3]
Vss
10
11
12
13
14
1
2
3
4
5
6
7
8
9
PDIP
SSOP
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SD
LEGEND: A = Analog, I = Input, and O = Output.
September 8, 2004 Document No. 38-12028 Rev. *B 10
CY8C24x23A Final Data Sheet 1. Pin Information
O
I
f
D
1.1.4 32-Pin Part Pinout
Table 1-4. 32-Pin Part Pinout (MLF*)
Pin
No.
1 IO P2[7]
2 IO P2[5]
3 IO I P2[3] Direct switched capacitor block input.
4 IO I P2[1] Direct switched capacitor block input.
5 Power Vss Ground connection.
6 Power SMP Switch Mode Pump (SMP) connection to
7 IO P1[7] I2C Serial Clock (SCL)
8 IO P1[5] I2C Serial Data (SDA)
9 NC No connection. Do not use.
10 IO P1[3]
11 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
12 Power Vss Ground connection.
13 IO P1[0] Crystal Output (XTALout), I2C Serial Data
14 IO P1[2]
15 IO P1[4] Optional External Clock Input (EXTCLK)
16 NC No connection. Do not use.
17 IO P1[6]
18 Input XRES Active high external reset with internal pull
19 IO I P2[0] Direct switched capacitor block input.
20 IO I P2[2] Direct switched capacitor block input.
21 IO P2[4] External Analog Ground (AGND)
22 IO P2[6] External Voltage Reference (VR ef)
23 IO I P0[0] Analog column mux input.
24 IO I P0[2] Analog column mux input.
25 NC No connection. Do not use.
26 IO I P0[4] Analog column mux input.
27 IO I P0[6] Analog column mux input.
28 Power Vdd Su ppl y voltage.
29 IO I P0[7] Analog column mux input.
30 IO IO P0[5] Analog column mux input and column output.
31 IO IO P0[3] Analog column mux input and column output.
32 IO I P0[1] Analog column mux input.
Type
Digital Analog
Pin
Name
external componen ts requ ired.
(SDA)
down.
Description
CY8C24423A 32-Pin PSoC Device
P0[5], AIOP0[7], AI
Vdd
P0[3], AI
MLF
(Top View)
131415
Vss
I2C SCL, XTALin, P1[1]
I2C SDA, XTALout, P1[0]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
Vss
SMP
I2C SCL, P1[7]
2C SDA, P1[5]
P0[1], AI
32313029282726
1
2
3
4
5
6
7
8
9
101112
NC
P1[3]
P0[6], AI
P0[4], AI
NC
25
P0[2], AI
24
P0[0], AI
23
22
P2[6], External VRe
21
P2[4], External AGN
P2[2], AI
20
P2[0], AI
19
XRES
18
P1[6]
17
16
NC
P1[2]
EXTCLK, P1[4]
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to ground (Vss).
September 8, 2004 Document No. 38-12028 Rev. *B 11
2. Register Reference
This chapter lists the reg isters of the CY8C24 x23A PSoC device. Fo r detai led regi ster info rmatio n, referenc e the PSo C™ Mixed Si g-
nal Array Technical Reference Manual.
2.1 Register Conventions
2.1.1 Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
2.2 Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag regist er (CPU_F)
determines which bank the user is currently in. When the XOI
bit is set the user is in bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
September 8, 2004 Document No. 38-12028 Rev. *B 12
CY8C24x23A Final Data Sheet 2. Register Reference
Register Map Bank 0 Table: User Space
Access
Name
PRT0DR 00 RW 40 ASC10CR0 80 RW C0
PRT0IE 01 RW 41 ASC10CR1 81 RW C1
PRT0GS 02 RW 42 ASC10CR2 82 RW C2
PRT0DM2 03 RW 43 ASC10CR3 83 RW C3
PRT1DR 04 RW 44 ASD11CR0 84 RW C4
PRT1IE 05 RW 45 ASD11CR1 85 RW C5
PRT1GS 06 RW 46 ASD11CR2 86 RW C6
PRT1DM2 07 RW 47 ASD11CR3 87 RW C7
PRT2DR 08 RW 48 88 C8
PRT2IE 09 RW 49 89 C9
PRT2GS 0A RW 4A 8A CA
PRT2DM2 0B RW 4B 8B CB
DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW
DBB00DR2 22 RW 62 A2 INT_VC E2 RC
DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC
DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC
DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW
DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW
DCB02DR0 28 # 68 A8 MUL_X E8 W
DCB02DR1 29 W 69 A9 MUL_Y E9 W
DCB02DR2 2A RW 6A AA MUL_DH EA R
DCB02CR0 2B # 6B AB MUL_DL EB R
DCB03DR0 2C # 6C AC ACC_DR1 EC RW
DCB03DR1 2D W 6D AD ACC_DR0 ED RW
DCB03DR2 2E RW 6E AE ACC_DR3 EE RW
DCB03CR0 2F # 6F AF ACC_DR2 EF RW
Blank fields are Reserved and should not be accessed. # Access is bit specific.
(0,Hex)
Addr
0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 ASD20CR0 90 RW D0
11 51 ASD20CR1 91 RW D1
12 52 ASD20CR2 92 RW D2
13 53 ASD20CR3 93 RW D3
14 54 ASC21CR0 94 RW D4
15 55 ASC21CR1 95 RW D5
16 56 ASC21CR2 96 RW I2C_CFG D6 RW
17 57 ASC21CR3 97 RW I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 I2C_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C DC
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F DF
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Name
Access
(0,Hex)
Addr
Name
Access
(0,Hex)
Addr
Name
Access
(0,Hex)
Addr
September 8, 2004 Document No. 38-12028 Rev. *B 13
CY8C24x23A Final Data Sheet 2. Register Reference
Register Map Ba nk 1 Table: Con figuration Space
Access
Name
PRT0DM0 00 RW 40 ASC10CR0 80 RW C0
PRT0DM1 01 RW 41 ASC10CR1 81 RW C1
PRT0IC0 02 RW 42 ASC10CR2 82 RW C2
PRT0IC1 03 RW 43 ASC10CR3 83 RW C3
PRT1DM0 04 RW 44 ASD11CR0 84 RW C4
PRT1DM1 05 RW 45 ASD11CR1 85 RW C5
PRT1IC0 06 RW 46 ASD11CR2 86 RW C6
PRT1IC1 07 RW 47 ASD11CR3 87 RW C7
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 89 C9
PRT2IC0 0A RW 4A 8A CA
PRT2IC1 0B RW 4B 8B CB
DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW
DBB01FN 24 RW 64 A4 VLT_CMP E4 R
DBB01IN 25 RW 65 A5 E5
DBB01OU 26 RW AMD_CR1 66 RW A6 E6
DCB02FN 28 RW 68 A8 IMO_TR E8 W
DCB02IN 29 RW 69 A9 ILO_TR E9 W
DCB02OU 2A RW 6A AA BDG_TR EA RW
DCB03FN 2C RW 6C AC EC
DCB03IN 2D RW 6D AD ED
DCB03OU 2E RW 6E AE EE
Blank fields are Reserved and should not be accessed. # Access is bit specific.
(1,Hex)
Addr
0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 ASD20CR0 90 RW GDI_O_IN D0 RW
11 51 ASD20CR1 91 RW GDI_E_IN D1 RW
12 52 ASD20CR2 92 RW GDI_O_OU D2 RW
13 53 ASD20CR3 93 RW GDI_E_OU D3 RW
14 54 ASC21CR0 94 RW D4
15 55 ASC21CR1 95 RW D5
16 56 ASC21CR2 96 RW D6
17 57 ASC21CR3 97 RW D7
18 58 98 D8
19 59 99 D9
1A 5A 9A DA
1B 5B 9B DB
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
23 AMD_CR0 63 RW A3 VLT_CR E3 RW
27 ALT_CR0 67 RW A7 E7
2B 6B AB ECO_TR EB W
2F 6F AF EF
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Name
Access
(1,Hex)
Addr
Name
Access
(1,Hex)
Addr
Name
Access
(1,Hex)
Addr
September 8, 2004 Document No. 38-12028 Rev. *B 14
3. Electrical S pecifications
This chapter presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40
than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.
Refer to Table 3-20 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
o
C ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater
5.25
5.25
SLIMO
Mode=1
O
4.75
Vdd Voltage
3.00
2.40
93 kHz 12 MHz 24 MHz
3 MHz
V
p
a
l
e
R
CPU Frequency
i
d
r
a
e
t
g
i
n
i
o
g
n
Figure 3-1a. Voltage versus CPU Frequency Figure 3-1b. IMO Frequency Trim Options
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol Unit of Measure Symbol Unit of Measure
o
dB decibels mA milli-ampere
fF femto farad ms milli-second
Hz hertz mV milli-volts
KB 1024 bytes nA nano ampere
Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts
kΩ kilohm Ω ohm
MHz megahertz pA pico ampere
MΩ megaohm pF pico farad
µA micro ampere pp peak-to-peak
µF micro farad ppm parts per million
µH micro henry ps picosecond
µs microsecond sps samples per second
µV micro volts σ sigma: one standard deviation
µVrms micro volts root-mean-square V volts
degree Celsius µW micro watts
C
4.75
Vdd Voltage
SLIMO Mode = 0
3.60
3.00
2.40
93 kHz
SLIMO
Mode=1
SLIMO
Mode=1
6 MHz
IMO Frequency
SLIMO
Mode=1
12 MHz 24 MHz
SLIMO
Mode=0
SLIMO
Mode=0
September 8, 2004 Document No. 38-12028 Rev. *B 15
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