❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to 10 Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
■ Additional System Resources
2
❐ I
C™ Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
Cypress Semiconductor Corporation•198 Champion Court•San Jose, CA 95134-1709•408-943-2600
Document Number: 38-12011 Rev. *G Revised December 11, 2008
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PSoC® Functional Overview
DIGITAL SYSTEM
To System Bus
D
i
g
i
t
a
l
C
l
o
c
k
s
F
r
o
m
C
o
r
e
Digital PSoC Block Array
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 2Port 1Port 0
The PSoC® family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one, low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, and
Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user module references.
Figure 1. Digital System Block Diagram
programmable interconnects. This architecture allows the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and
packages.
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, is comprised of four main areas: PSoC Core, Digital
System, Analog System, and System Resources. Configurable
global busing allows all the device resources to be combined into
a complete custom system. The PSoC CY8C24x23 family can
have up to three IO ports that connect to the global digital and
analog interconnects, providing access to four digital blocks and
6 analog blocks.
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory , clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 11
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 4 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
Digital peripheral configurations include:
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8-bit with selectable parity (up to one)
■ SPI master and slave (up to one)
■ I2C slave and master (one available as a System Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA (up to one)
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are listed in the table PSoC Device Characteristics on
page 4.
Document Number: 38-12011 Rev. *GPage 2 of 43
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Analog System
ACB00ACB01
Block Array
Array Input Configuration
ACI1[1:0]
ASD20
ACI0[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators
AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Digital System
M8C Interface (Address Bus, Data Bus, Etc.)
Analog Reference
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
■ Analog-to-digital converters (up to two, with 6 to 14-bit
resolution, selectable as Incremental, Delta Sigma, and SAR)
■ Filters (two and four pole band-pass, low-pass, and notch)
■ Amplifiers (up to two, with selectable gain to 48x)
■ Instrumentation amplifiers (one with selectable gain to 93x)
■ Comparators (up to two, with 16 selectable thresholds)
■ DACs (up to two, with 6 to 9-bit resolution)
■ Multiplying DACs (up to two, with 6- to 9-bit resoluti on)
■ High current output drivers (two with 30 mA drive as a Core
Resource)
■ 1.3V reference (as a System Resource)
■ DTMF dialer
■ Modulators
■ Correlators
■ Peak detectors
■ Many other topologies possible
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The number of blocks is dependant on the device family
which is detailed in the table PSoC Device Characteristics on
page 4.
Figure 2. Analog System Block Diagram
Document Number: 38-12011 Rev. *GPage 3 of 43
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Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource follow:
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
■ The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■ The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■ An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources available
for specific PSoC device groups.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66 up to 64416124412
CY8C27x66
CY8C27x43
IO
Digital
Rows
Digital
Digital
up to 4428124412
up to 4428124412
Blocks
Inputs
Analog
Analog
Outputs
Analog
Columns
Analog
Getting Started
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, refer the PSoC Programmable Sytem-on-Chip Technical Reference Manual.
For up-to-date Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets on the web
at http://www.cypress.com/psoc.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click PSoC (Program-mable System-on-Chip) to view a current list of available items.
Technical Training
Free PSoC technical training is available for beginners and is
taught by a marketing or application engineer over the phone.
PSoC training classes cover designing, debugging, advanced
analog, and application-specific classes covering topics, such as
PSoC and the LIN bus. Go to http://www.cypress.com, click on
Design Support located on the left side of the web page, and
select Technical Training for more details.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support.
Blocks
Application Notes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are listed by date as default.
CY8C24x23 up to 241412226
CY8C22x13
Document Number: 38-12011 Rev. *GPage 4 of 43
up to 16148113
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Development Tools
Commands
Results
PSoC
TM
Designer
Core
Engine
PSoC
Configuration
Sheet
Manufacturing
Information
File
Device
Database
Importable
Design
Database
Device
Programmer
Graphical Designer
Interface
Context
Sensitive
Help
Emulation
Pod
In-Circuit
Emulator
Project
Database
Application
Database
User
Modules
Library
PSoCTM
Designer
The Cypress MicroSystems PSoC Designer is a Microsoft
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows 98, Windows NT
4.0, Windows 2000, Windows Millennium (Me), or Windows XP
(refer Figure 3).
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
PSoC Designer Software Subsystems
®
Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
Design Browser
The Design Browser allows users to select and imp ort preconfigured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler. The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available that
supports Cypress MicroSystems’ PSoC family devices. Even if
you have never worked in the C language before, the product
quickly allows you to create complete C programs for the PSoC
family devices.
The embedded, optimizing C compiler provides all th e features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Document Number: 38-12011 Rev. *GPage 5 of 43
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Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
operates with all PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (24 MHz) operation.
Figure 4. PSoC Development Tool Kit
User Modules and the PSoC Development
Process
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware as well as the software. This substantially lowers the
risk of having to select a different part to meet the final design
requirements.
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run-time. The API also provides optional interrupt service
routines that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a pictorial environment (GUI) for
configuring the hardware. You pick the user modules you need
for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and enter
parameter values directly or by selecting values from drop-down
menus. When you are ready to test the hardware configuration
or move on to developing code for the project, you perform the
“Generate Application” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the high-level user module API
functions.
Document Number: 38-12011 Rev. *GPage 6 of 43
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Figure 5. User Module and Source Code Development Flows
Debugger
Interface
to ICE
Application Editor
Device Editor
Project
Manager
Source
Code
Editor
Storage
Inspector
User
Module
Selection
Placement
and
Parameter
-ization
Generate
Application
Build
All
Event &
Breakpoint
Manager
Build
Manager
Source
Code
Generator
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (includ ing
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a ROM file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the ROM image to the In-Circuit Emulator (ICE)
where it runs at full speed. Debugger capabilities rival those of
systems costing many times more. In addition to traditional
single-step, run-to-breakpoint and watch-variable features, the
Debugger provides a large trace buffer and allows you define
complex breakpoint events that include monitoring address and
data bus values, memory locations and external signals.
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms
AcronymDescription
ACalternating current
ADCanalog-to-digital converter
APIapplication programming interface
CPUcentral processing unit
CTcontinuous time
DACdigital-to-analog converter
DCdirect current
EEPROM el ectrically erasable programmable read-only
memory
FSRfull scale range
GPIOgeneral purpose IO
IOinput/output
IPORimprecise power on reset
LSbleast-significant bit
LVDlow voltage detect
MSbmost-significant bit
PCprogram counter
PORpower on reset
PPORprecision power on reset
A units of measure table is located in the Electrical Specifications
section. Table 7 on page 11 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Programmable System-on-Chip
Document Number: 38-12011 Rev. *GPage 7 of 43
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Pinouts
PDIP
SOIC
1
2
3
4
8
7
6
5
Vdd
P0[4], AI
P0[2], AI
P1[0], XTALout, I2C SDA
AIO, P0[5]
AIO, P0[3]
I2C SCL, XTALin, P1[1]
Vss
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
PDIP
SSOP
SOIC
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
The CY8C24x23 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
8-Pin Part Pinout
Table 3. 8-Pin Part Pinout (PDIP, SOIC)
Pin
No.
1IOIOP0[5]Analog column mux input and column output
2IOIOP0[3]Analog column mux input and column output
3IOP1[1]Crystal Input (XTALin), I2C Serial Clock (SCL)
4PowerVssGround connection
5IOP1[0]Crystal Output (XT ALout), I2C Serial Data (SDA)
6IOIP0[2]Analog column mux input
7IOIP0[4]Analog column mux input
8PowerVddSupply voltage
LEGEND: A = Analog, I = Input, and O = Output.
20-Pin Part Pinout
Table 4. 20-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
1IOIP0[7]Analog column mux input
2IOIOP0[5]Analog column mux input and column output
3IOIOP0[3]Analog column mux input and column output
4IOIP0[1]Analog column mux input
5PowerSMPSwitch Mode Pump (SMP) connection to external
6IOP1[7]I2C Serial Clock (SCL
7IOP1[5]I2C Serial Data (SDA)
8IOP1[3]
9IOP1[1]Crystal Input (XTALin), I2C Serial Clock (SCL)
10PowerVssGround connection
11IOP1[0]Crystal Output (XT ALout), I2C Serial Data (SDA)
12IOP1[2]
13IOP1[4]Optional External Clock Input (EXTCLK)
14IOP1[6]
15InputXRES Active high external reset with internal pull down
16IOIP0[0]Analog column mux input
17IOIP0[2]Analog column mux input
18IOIP0[4]Analog column mux input
19IOIP0[6]Analog column mux input
20PowerVddSupply voltage
LEGEND: A = Analog, I = Input, and O = Output.
Document Number: 38-12011 Rev. *GPage 8 of 43
Type
Digital Analog
Type
Digital Analog
Pin
Name
Pin
Name
components required
Description
Description
Figure 6. CY8C24123 8-Pin PSoC Device
Figure 7. CY8C24223 20-Pin PSoC Device
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28-Pin Part Pinout
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
PDIP
SSOP
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Table 5. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
1IOIP0[7]Analog column mux input
2IOIOP0[5]Analog column mux input and column
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
32-Pin Part Pinout
Table 6. 32-Pin Part Pinout (MLF*)
Pin
No.
1IOP2[7]
2IOP2[5]
3IOIP2[3]Direct switched cap acitor block input
4IOIP2[1]Direct switched cap acitor block input
5PowerVssGround connection
6PowerSMPSwitch Mode Pump (SMP)
7IOP1[7]I2C Serial Clock (SCL)
8IOP1[5]I2C Serial Data (SDA)
9NCNo connection. Do not use.
10IOP1[3]
11IOP1[1]Crystal Input (XTALin), I2C Serial
12PowerVssGround connection
13IOP1[0]Crystal Output (XTALout), I2C Serial
14IOP1[2]
15IOP1[4 ]Optional External Clock Input
16NCNo connection. Do not use.
17IOP1[6]
18InputXRES Active high external reset with
19IOIP2[0] Direct switched capacitor block input
20IOIP2[2] Direct switched capacitor block input
21IOP2[4] External Analog Ground (AGND)
22IOP2[6] External Voltage Reference (VRef)
23IOIP0[0] Analog column mux input
24IOIP0[2] Analog column mux input
25NCNo connection. Do not use.
26IOIP0[4] Analog column mux input
27IOIP0[6] Analog column mux input
28PowerVddSupply voltage
29IOIP0[7] Analog column mux input
30IOIOP0[5] Analog column mux input and
31IOIOP0[3] Analog column mux input and
32IOIP0[1] Analog column mux input
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to the same ground as the
Vss pin.
Type
Digital Analog
Pin
Name
Description
connection to external components
required
Clock (SCL)
Data (SDA)
(EXTCLK)
internal pull down
column output
column output
Figure 9. CY8C24423 32-Pin PSoC Device
Document Number: 38-12011 Rev. *GPage 10 of 43
[+] Feedback
CY8C24123
CY8C24223, CY8C24423
Register Reference
This section lists the registers of the CY8C27xxx PSoC device
by way of mapping tables, in offset order. For detailed register
information, reference the PSoC ProgrammableSystem-on-Chip Technical Reference Manual.
Register Conventions
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Table 7. Abbreviations
ConventionDescription
RWRead and write register or bit(s)
RRead register or bit(s)
WWrite register or bit(s)
LLogical register or bit(s)
CClearable register or bit(s)
#Access is bit specific
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is also referred to as IO space and is
broken into two parts. The XOI bit in the Flag register determines
which bank the user is currently in. When the XOI bi t is set, the
user is said to be in the “extended” address space or the “configuration” registers.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.