Cypress CY8C23433, CY8C23533 User Manual
CY8C23433, CY8C23533
PSoC® Programmable System-on-Chip™
Features
DIGITAL SYSTEM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Inc ludes I MO, I LO, PLL, and E CO)
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
CPU Core (M8C)
SROM Flash 8K
Digital
Block
Array
Multiply
Accum.
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Resets
Decimator
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref
Analog
Input
Muxing
I2C
Por t 2 Por t 1 Port 0
Analog
Drivers
System Bus
Analog
Block A rray
1 Row
4 Blocks
2 Columns
4 Blocks
SAR8 ADC
Por t 3
Logic Block Diagram
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0 to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC Blocks)
❐ 4 Rail-to-Rail analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 8-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
❐ High-Speed 8-Bit SAR ADC Optimized for Motor Control
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillato r
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 8K Bytes Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configur ations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to Ten Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO
■ Additional System Resources
2
❐ I
C™ Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-44369 Rev. *B Revised December 05, 2008
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PSoC Functional Overview
DIGITAL SYSTEM
To System Bus
D
i
g
i
t
a
l
C
l
o
c
k
s
F
r
o
m
C
o
r
e
Digita l PS oC Block A rray
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8 Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GI E[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Por t 3 Por t 1 Por t 0Por t 2
The PSoC family consists of many mixed-signal array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
a low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, and
programmable interconnects. This architecture allows the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts and
packages.
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, consists of four main areas: PSoC Core, Digital Syste m,
Analog System, and System Resources. Configurable global
busing allows combining all the device resources into a complete
custom system. The PSoC CY8C23x33 family can have up to
three IO ports that connect to the global digital and analog
interconnects, providing access to four digital blocks and four
analog blocks.
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory , clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 11
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 8 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
Digital System
The Digital System consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or comb ined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references.
Figure 1. Digital System Block Diagram
Digital peripheral configurations are:
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity (up to 1)
■ SPI master and slave (up to 1)
■ I2C slave and master (1 available as a System Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA (up to 1)
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in the table titled PSoC Device Character-
istics on page 4.
Document Number: 001-44369 Rev. *B Page 2 of 37
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Analog System
ACB00 ACB01
Bloc k Ar ra y
Arra y Input Configura tion
ACI1[1:0]ACI0[1:0]
P0[ 6]
P0[ 4]
P0[ 2]
P0[ 0]
P2[ 2]
P2[ 0]
P2[ 6]
P2[ 4]
RefIn
AGNDIn
P0[ 7]
P0[ 5]
P0[ 3]
P0[ 1]
P2[ 3]
P2[ 1]
Refe r ence
Gene rators
AGNDIn
Ref In
Bandgap
Ref Hi
Ref Lo
AGND
ASD11
ASC21
Interface to
Dig it al Sys t e m
M8C Interface (Address Bus, Data Bus, Etc.)
Analog Refe rence
8-Bit SAR ADC
ACI2[3:0]
P0[7:0]
The Analog system consists of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
Each analog block consists of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
■ Filters (2 band pass, low-pass)
■ Amplifiers (up to 2, with selectable gain to 48x)
■ Instrumentation amplifiers (1 with selectable gain to 93x)
■ Comparators (1, with 16 selectable thresholds)
■ DAC (6 or 9 -bit DAC)
■ Multiplying DAC (6 or 9 -bit DAC)
■ High current output drivers (two with 30 mA drive)
■ 1.3V reference (as a System Resource)
■ DTMF dialer
■ Modulators
■ Correlators
■ Peak detectors
■ Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The Analog Column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
Figure 2. Analog System Block Diagram
Document Number: 001-44369 Rev. *B Page 3 of 37
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Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a multiplier, decimator,
low voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow:
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
■ The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■ The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on the PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources available
for specific PSoC device groups.
Table 1. PSoC Device Characteristics
Getting Started
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, refer the PSoC Mixed-Signal
Array Technical Reference Manual.
For latest Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets on the web
at http://www.cypress.com/psoc.
To determine which PSoC device meets your requirements,
navigate through the PSoC Decision Tree in the Application Note
AN2209 at http://www.cypress.com and select Application Notes
under the Design Resources.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com/onlinestore.
Technical Training Modules
Free PSoC technical training modules are available for u sers
new to PSoC. Training modules cover designing, debugging,
advanced analog and CapSense. Go to
http://www.cypress.com.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located at the top of the web page, and select CYPros
Consultants.
PSoC Part
Number
Digital IODigital
Rows
Digital
Blocks
Analog
Inputs
Analog
Analog
Outputs
Blocks
Analog
Columns
CY8C29x66 up to 644 16 12 4 4 12 No
SAR8
Technical Support
PSoC application engineers take pride in fast and accurate
ADC
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support.
Application Notes
CY8C27x43
CY8C24x94 56 1 4 48 2 2 6
CY8C23X33 up to 261 4 12 2 2
CY8C24x23A up to 241412226No
CY8C21x34 up to 281428024
CY8C21x23
CY8C20x34
Notes
1. One complete column, plus one Continuous Time Block.
2. Limited analog functionality
3. Two analog blocks and one CapSense.
Document Number: 001-44369 Rev. *B Page 4 of 37
up to 442 8 12 4 4 12 No
No
[1]
4 Yes
[2]
No
16 1 4 8 0 2 4
up to 280 0 28 0 0 3
.
[2]
[3]
No
No
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to
http://www.cypress.com/psocapnotes.
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Development Tools
Commands
Results
PSoC
Designer
Core
Engine
PSoC
Configuration
Sheet
Manufacturing
Information
File
Device
Database
Importable
Design
Database
Device
Programmer
Graphical Designer
Interface
Context
Sensitive
Help
Emulation
Pod
In-Circuit
Emulator
Project
Database
Application
Database
User
Modules
Library
PSoC
Designer
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP (refer section PSoC Desi gner
Subsystems on page 5).
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. Once the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
Design Browser
The Design Browser allows users to select and import
preconfigured designs into the user’s project. Users can easily
browse a catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler. The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries
automatically use absolute addressing or can be compiled in
relative mode, and linked with other software modules to get
absolute addressing.
C Language Compiler. A C language compiler is available that
supports the PSoC family of devices. Even if you have never
worked in the C language before, the product quickly allows you
to create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all th e features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Document Number: 001-44369 Rev. *B Page 5 of 37
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Debugger
Debugger
Interface
to IC E
Appli cati on Editor
Device Editor
Project
Manager
Source
Code
Editor
Storage
Inspector
User
Module
Selection
Placement
and
Parameter
-ization
Generate
Application
Build
All
Event &
Breakpoint
Manager
Build
Manager
Source
Code
Generator
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear
breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and can operate
with all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides high
level functions to control and respond to hardware events at
run-time. The API also provides optional interrupt service
routines that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by
interconnecting user modules to each other and the IO pins. At
this stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
Figure 4. User Module/Source Code Development Flows
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware and the software. This substantially lowers the risk of
having to select a different part to meet the final design
requirements.
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other uncommon peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
Document Number: 001-44369 Rev. *B Page 6 of 37
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The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (includ ing
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms Used (continued)
Acronym Description
PWM pulse width modulator
RAM random access memory
ROM read only memory
SC switched capacitor
Units of Measure
A units of measure table is located in the section Electrical
Specifications on page 14. Tabl e 8 on page 14 lists all the
abbreviations used to measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Table 2. Acronyms Used
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
EEPROM electrically erasable programmable read-only
memory
FSR full scale range
GPIO general purpose IO
IO input/output
IPOR imprecise pow er on reset
LSb least-significant bit
LVD low voltage detect
MSb most-sign ificant bit
PC program counter
POR power on reset
PPOR precision power on reset
PSoC® Programmable System-on-Chip™
Document Number: 001-44369 Rev. *B Page 7 of 37
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Note
4. Even though P3[0] is an odd port, it resides on the left side of the pinout.
GPIO, P2[7]
GPIO, P2[5]
A, I, P2[3]
A, I, P2[1]
AVref, P3[0]
NC
QFN
(Top View)
9
101112
131415
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32313029282726
25
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
Vdd
P0[6], A, I
P0[4], A, I
NC
I2C SCL, P1[7]
I2C SDA, P1[5]
P0[2], A, I
P0[0], A, I
XRES
P1[6], GPIO
NC
GPIO P1[3]
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
GPIO P1[2]
GPIO, EXTCLK, P1[4]
NC
P2[6], Vref
P2[4], AGnd
P2[2], A, I
P2[0], A, I
Pinouts
The PSoC CY8C23X33 is available in 32-pin QFN and 28-pin SSOP packages. Every port pin (labeled with a “P”), except for Vss and
Vdd in the following table and figure, is capable of Digital IO.
32-Pin Part Pinout
Table 3. Pin Definitions - 32-Pin (QFN)
Pin
No.
Type
Digital Analog
Pin
Name
Description
1 IO P2[7] GPIO
2 IO P2[5] GPIO
3 IO I P2[3] Direct Switched Capacitor Block Input
4 IO I P2[1] Direct Switched Capacitor Block Input
5 IO AVref P3[0]
[4]
GPIO/ADC Vref (optional)
6 NC No Connection
7 IO P1[7] I2C Serial Clock (SCL)
8 IO P1[5] I2C Serial Data (SDA)
9 NC No Connection
10 IO P1[3] GPIO
11 IO P1[1] GPIO, Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
12 Power Vss Ground Connection
13 IO P1[0] GPIO, Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
14 IO P1[2] GPIO
15 IO P1[4] GPIO, External Clock IP
16 NC No Connection
17 IO P1[6] GPIO
18 Input XRES Active High External Reset with Internal Pull Down
19 IO I P2[0] Direct Switched Capacitor Block Input
20 IO I P2[2] Direct Switched Capacitor Block Input
21 IO P2[4] External Analog Ground (AGnd)
22 IO P2[6] External Voltage Reference (VRef)
23 IO I P0[0] Analog Column Mux Input and ADC Input
24 IO I P0[2] Analog Column Mux Input and ADC Input
25 NC No Connection
26 IO I P0[4] Analog Column Mux Input and ADC Input
27 IO I P0[6] Analog Column Mux Input and ADC Input
28 Power Vdd Supply Voltage
ADC Input
ADC Input
29 IO I P0[7] Analog Column Mux Input and ADC Input
30 IO IO P0[5] Analog Column Mux Input, Column Output and
31 IO IO P0[3] Analog Column Mux Input, Column Output and
32 IO I P0[1] Analog Column Mux Input.and ADC Input
LEGEND: A = Analog, I = Input, and O = Output.
Figure 5. CY8C23533 32-Pin PSoC Device
Document Number: 001-44369 Rev. *B Page 8 of 37
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28-Pin Part Pinout
AIO, P0[7]
IO, P0[5]
IO, P0[3]
AIO, P0[1]
IO, P2[7]
IO, P2[5]
AIO, P2[3]
AIO, P 2[1]
AVref, IO, P3[0]
I2C SCL, IO, P1[7]
I2C SDA, IO, P1[5]
IO, P1[3]
I2C SCL,ISSP SCL,XTALin,IO, P1[1]
Vss
Vdd
P0[6], AIO, AnColMux and ADC IP
P0[4], AIO, AnColMux and ADC IP
P0[2], AIO, AnColMux and ADC IP
P0[0], AIO, AnColMux and ADC IP
P2[6], VREF
P2[4], AGND
P2[2], AIO
P2[0], AIO
P3[1], IO
P1[6], IO
P1[4], IO, EXTCLK
P1[2], IO
P1[0],IO,XTALout,ISSP SDA,I2C SDA
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Notes
5. Even though P3[0] is an odd port, it resides on the left side of the pinout.
6. ISSP pin, which is not High Z at POR.
7. Even though P3[1] is an even port, it resides on the right side of the pinout.
Table 4. Pin Definitions - 28-Pin (SSOP)
Description
Digital
CY8C23433
Pin Number
1 IO I P0[7] Analog Column Mux IP and ADC IP
2 IO IO P0[5] Analog Column Mux IP and Column
3 IO IO P0[3] Analog Column Mux IP and Column
4 IO I P0[1] Analog Column Mux IP and ADC IP
5 IO P2[7] GPIO
6 IO P2[5] GPIO
7 IO I P2[3] Direct Switched Capacitor Input
8 IO I P2[1] Direct Switched Capacitor Input
9IOAVref
10 IO P1[7] I2C SCL
11 IO P1[5] I2C SDA
12 IO P1[3] GPIO
13 IO
14 Power Vss Ground Pin
15 IO
16 IO P1[2] GPIO
17 IO P1[4] GPIO, External Clock IP
18 IO P1[6] GPIO
19 IO
20 IO I P2[0] Direct Switched Capacitor Input
21 IO I P2[2] Direct Switched Capacitor Input
22 IO P2[4] External Analog Ground (AGnd)
23 IO P2[6] Analog Voltage Reference (VRef)
24 IO I P0[0] Analog Column Mux IP and ADC IP
25 IO I P0[2] Analog Column Mux IP and ADC IP
26 IO I P0[4] Analog Column Mux IP and ADC IP
27 IO I P0[6] Analog Column Mux IP and ADC IP
28 Power Vdd Supply Voltage
LEGEND: A = Analog, I = Input, and O = Output.
Analog
P3[0]
P1[1]
P1[0]
P3[1]
Pin Name
O/P and ADC IP
O/P and ADC IP
[5]
GPIO/ADC Vref (optional)
[6]
GPIO, Xtal Input, I2C SCL, ISSP SCL
[6]
GPIO, Xtal Output, I2C SDA, ISSP
SDA
[7]
GPIO
Figure 6. CY8C23433 28-Pin PSoC Device
Document Number: 001-44369 Rev. *B Page 9 of 37
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Register Reference
This section lists the registers of the CY8C23433 PSoC device
by using mapping tables, in offset order.
Register Conventions
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Table 5. Abbreviations
Convention Description
R Read register or bits
W Write register or bits
L Logical register or bits
C Clearable register or bits
# Access is bit specific
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and must not be accessed.
Document Number: 001-44369 Rev. *B Page 10 of 37
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Table 6. Register Map Bank 0 Table: User Space
Name
PRT0DR 00 RW 40 80 C0
PRT0IE 01 RW 41 81 C1
PRT0GS 02 RW 42 82 C2
PRT0DM2 03 RW 43 83 C3
PRT1DR 04 RW 44 ASD11CR0 84 RW C4
PRT1IE 05 RW 45 ASD11CR1 85 RW C5
PRT1GS 06 RW 46 ASD11CR2 86 RW C6
PRT1DM2 07 RW 47 ASD11CR3 87 RW C7
PRT2DR 08 RW 48 88 C8
PRT2IE 09 RW 49 89 C9
PRT2GS 0A RW 4A 8A CA
PRT2DM2 0B RW 4B 8B CB
PRT3DR 0C RW 4C 8C CC
PRT3IE 0D RW 4D 8D CD
PRT3GS 0E RW 4E 8E CE
PRT3DM2 0F RW 4F 8F CF
DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW
DBB00DR2 22 RW 62 A2 INT_VC E2 RC
DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC
DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC
DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW
DBB01CR0 27 # SARADC_DL 67 RW A7 DEC_CR1 E7 RW
DCB02DR0 28 # 68 A8 MUL0_X E8 W
DCB02DR1 29 W SARADC_CR0 69 # A9 MUL0_Y E9 W
DCB02DR2 2A RW SARADC_CR1 6A RW AA MUL0_DH EA R
DCB02CR0 2B # 6B AB MUL0_DL EB R
DCB03DR0 2C # TMP_DR0 6C RW AC ACC0_DR1 EC RW
DCB03DR1 2D W TMP_DR1 6D RW AD ACC0_DR0 ED RW
DCB03DR2 2E RW TMP_DR2 6E RW AE ACC0_DR3 EE RW
DCB03CR0 2F # TMP_DR3 6F RW AF ACC0_DR2 EF RW
Gray fields are reserved. # Access is bit specific.
Addr
(0,Hex)
Access
10 50 90 D0
11 51 91 D1
12 52 92 D2
13 53 93 D3
14 54 ASC21CR0 94 RW D4
15 55 ASC21CR1 95 RW D5
16 56 ASC21CR2 96 RW I2C_CFG D6 RW
17 57 ASC21CR3 97 RW I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 I2C_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C DC
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F DF
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 * 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 * 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Document Number: 001-44369 Rev. *B Page 11 of 37
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Table 6. Register Map Bank 0 Table: User Space (continued)
Name
Gray fields are reserved. # Access is bit specific.
Addr
(0,Hex)
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Table 7. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0 00 RW 40 80 C0
PRT0DM1 01 RW 41 81 C1
PRT0IC0 02 RW 42 82 C2
PRT0IC1 03 RW 43 83 C3
PRT1DM0 04 RW 44 ASD11CR0 84 RW C4
PRT1DM1 05 RW 45 ASD11CR1 85 RW C5
PRT1IC0 06 RW 46 ASD11CR2 86 RW C6
PRT1IC1 07 RW 47 ASD11CR3 87 RW C7
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 89 C9
PRT2IC0 0A RW 4A 8A CA
PRT2IC1 0B RW 4B 8B CB
PRT3DM0 0C RW 4C 8C CC
PRT3DM1 0D RW 4D 8D CD
PRT3IC0 0E RW 4E 8E CE
PRT3IC1 0F RW 4F 8F CF
DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW
DBB01FN 24 RW 64 A4 VLT_CMP E4 R
DBB01IN 25 RW 65 A5 E5
DBB01OU 26 RW AMD_CR1 66 RW A6 E6
DCB02FN 28 RW 68 SARADC_TRS A8 RW IMO_TR E8 W
DCB02IN 29 RW 69 SARADC_TRCL A9 RW ILO_TR E9 W
DCB02OU 2A RW 6A SARADC_TRCH AA RW BDG_TR EA RW
DCB03FN 2C RW TMP_DR0 6C RW SARADC_LCR AC RW EC
DCB03IN 2D RW TMP_DR1 6D RW AD ED
DCB03OU 2E RW TMP_DR2 6E RW AE EE
Gray fields are reserved. # Access is bit specific.
Addr
(1,Hex)
10 50 90 GDI_O_IN D0 RW
11 51 91 GDI_E_IN D1 RW
12 52 92 GDI_O_OU D2 RW
13 53 93 GDI_E_OU D3 RW
14 54 ASC21CR0 94 RW D4
15 55 ASC21CR1 95 RW D5
16 56 ASC21CR2 96 RW D6
17 57 ASC21CR3 97 RW D7
18 58 98 D8
19 59 99 D9
1A 5A 9A DA
1B 5B 9B DB
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
23 AMD_CR0 63 RW A3 VLT_CR E3 RW
27 ALT_CR0 67 RW A7 E7
2B 6B SARADC_CR2 AB # ECO_TR EB W
2F TMP_DR3 6F RW AF EF
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Access
Document Number: 001-44369 Rev. *B Page 12 of 37
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