Cypress CY8C22x13 User Manual

September 2008

Silicon Errata for the CY8C22x13 PSoC

®

Mixed Signal Arrays

CY8C22x13

This document describes the errata for the PSoC® Mixed Signal Arrays CY8C22x13. Details include errata trigger
conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the
device’s data sheet for a complete functional description.

Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number Ordering Information

CY8C22x13 CY8C22113-24PI

CY8C22113-24SI

CY8C22113-24SIT

CY8C22213-24PI

CY8C22213-24PVI

CY8C22213-24PVIT

CY8C22213-24SI

CY8C22213-24SIT

CY8C22213-24LFI

CY8C22x13 Qualification Status

Product Status: Production

CY8C22x13 Errata Summary

The following table defines the errata applicability to available CY8C22x13 family devices. An "X" indicates that the
errata pertains to the selected device.

Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description.

Items Part Number Silicon Revision Fix Status

[1]. Internal Main Oscillator
(IMO) Tolerance Deviation at
Temperature Extremes

1. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes

■ PROBLEM DEFINITION

Asynchronous Digital Communications Interfaces may fail framing beyond 0 to 70°C. This problem does not
affect end-product usage between 0 and 70°C.

■ PARAMETERS AFFECTED

The IMO frequency tolerance. The worst case deviation when operated below 0°C and above +70°C and within
the upper and lower datasheet temperature range is ±5%.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134 • 408.943.2600

September 11, 2008 Document No. 001-48788 Rev. ** 1

CY8C22x13 A

Silicon fix is planned.

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CY8C22x13

Errata Document

■ TRIGGER CONDITION(S)

The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit of
±2.5% when operated beyond the temperature range of 0 to +70°C.

■ SCOPE OF IMPACT

This problem may affect UART, IrDA, and FSK implementations.

■ WORKAROUND

Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital
communications interface.

■ FIX STATUS

The cause of this problem and its solution has been identified. Silicon fix is planned to correct the deficiency
in silicon.

References

[1] Document # 38-12009, CY8C22113 and CY8C22213 PSoC® Mixed-Signal Array Final Data Sheet

September 11, 2008 Document No. 001-48788 Rev. ** 2

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