❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 2K Bytes Flash Program Storage 50,000
Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP )
❐ Partial Flash Updat es
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐ Up to 8 Analog Inputs on GPIO
❐ One 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
Analog
Drivers
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
Sleep and
Watchdog
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of convenient pinouts and packages.
The PSoC architecture, as illustrated on the left, is com pri se d of
four main areas: PSoC Core, Digital System, Analog System,
Analog
Ref
and System Resources. Configurable global busing allows all
the device r esources to be c ombined into a compl ete custom
system. The PSoC CY8C22x13 family can have up to two IO
ports that connec t to the gl obal di git al and a nalog i ntercon ne cts ,
Analog
Input
Muxing
providing access to 4 digital blocks and 3 analog blocks.
The PSoC Core
■ Additional System Resources
2
❐ I
C Slave, Master, and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
The PSoC Core is a powerful engine that supports a rich feature set. Th e co re in cl ud es a C PU , memo r y, clocks, and c on fig urable GPIO (General Purpose IO).
The M8C C PU core is a powerfu l proce ssor wit h spee ds up t o
24 MHz, providing a four MI PS 8-bit Harvar d archit ecture m icro-
processor. The CPU utilizes an interrupt controller with 10 vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 2 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software
IP protection.
The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real Time Cloc k (RT C) and can opti onally genera te a crys tal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide conne ct ion t o the CP U, di gital and analog
resources of the devi ce. Each pin’ s dri ve mod e may b e selec te d
from eight options, allowing great flexibility in external interfacing. Every pin also has the c apa bility to gen erate a syste m inte rrupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to fo rm 8, 16 , 24, and 32-bit p eriphe rals, wh ich
are called user module references.
Port 1Port 0
To System Bus
o
C
l
c
a
k
g
l
i
D
i
F
r
s
t
C
o
o
m
r
e
DIGITAL SYSTEM
Digital PSoC Block Array
8
DBB00 DBB01 DCB02 DCB03
Row Input
Configuration
Row 0
To Analog
System
4
4
Configuration
Row Output
8
Digital peripheral configurations include those listed below.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8-bit with selectable parity (up to 1)
■ SPI master and slave (up to 1)
■ I2C slave and master (1 available as a System Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA (up to 1)
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This co nfig ura bil ity free s y our d e si gn s fro m th e co nstraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Charac-
teristics” on page 3.
The Analog System
The Analog System is com posed of 3 configurable blocks, eac h
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and
can be customized to support specific application requirements .
Some of the more common PSoC analog functions (most available as user modules) are listed below.
■ Analog-to-digital converters (one with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■ Filters (two pole band-pass, low-pass, and notch)
■ Amplifiers (one with selectable gain to 48x)
■ Comparators (one with 16 sel ectable thresholds)
■ DACs (one with 6- to 9-bit resolution)
■ Multiplying DACs (one with 6- to 9-bit resolution)
■ High current output drivers (one with 30 mA drive as a Core
Resource)
■ 1.3V refer ence (as a System Resource)
■ Many other topologies possible
88
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital System Block Diagram
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p
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The number of bloc ks is depe ndant on the device family
which is detailed in the table titled “PSoC Device Characteris-
tics” on page 3.
P0[7]
P0[5]
P0[3]
P0[1]
Array Input Configuration
P0[6]
P0[4]
P0[2]
P0[0]
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Additional resources inclu de a deci mator, low voltage detection, and
power on reset. Brief statements describing the merits of each
system resource are presented below.
■ Digital clock dividers provide three customizable clock fre-
quencies for use in applic ations . The clo cks c an be route d to
both the digital a nd analog systems. Additiona l clocks c an be
generated using digital PSoC blocks as clock dividers.
■ The decimator provides a custom hardware filter for digital
signal processing applications inc lud in g t he c r eati on of D e lta
Sigma ADCs.
■ The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of f alling voltage levels, w hile the adv anced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■ An internal 1.3 voltage reference provides an absolute refer-
ence for the analog system, including ADCs and DACs.
PSoC Device Characteristics
Block Array
ACB01
ASD11
ASC21
Analog Reference
Interface to
Digital System
M8C Interface (Address Bus, Data Bus, Etc.)
RefHi
RefLo
AGND
Analog System Block Diagram
ACI1[1:0]ACI0[1:0]
Reference
Generators
AGNDIn
RefIn
Bandga
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources
available for specific PSoC device groups.
PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
CY8C27x66
CY8C27x43
CY8C24x23
CY8C22x13
Digital
up to
64
up to
44
up to
44
up to
24
up to
16
IO
Rows
Digital
Digital
416124412
28124412
28124412
1412226
148113
Blocks
Inputs
Analog
Analog
Outputs
Analog
Analog
Columns
Blocks
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CY8C22x13 Final Data SheetPSoC™ Overview
Getting Started
The quickest path to understanding th e PSoC s ili co n is by rea ding this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed Signal Array Technical Reference Manual.
For up-to-date Ordering, Packag ing, an d Electri cal Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at http://www.onfulfillment.com/cypressstore/ contains develop-
ment kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view
a current list of available items.
Tele-Training
Free PSoC "Tele-training" is available for beginners and taught
by a live marketing or appli ca tio n eng in eer ov er th e pho ne . F ive
training cl asses are availabl e to accelerate th e learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the
tele-training, see http://www.cypress.com/support/training.cfm.
Development Tools
The Cypress MicroSystems PSoC Designer is a Microsoft
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows 98, Windows
NT 4.0, Windows 2000, Windows Millennium (Me), or Windows
XP. (Reference the PSoC Designer Functional Flow diagram
below.)
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
TM
PSoC
Designer
Importable
Design
Database
Graphical Designer
Interface
Results
Commands
Context
Sensitive
Help
®
Consultants
Certified PSoC Consultants offer everything from technical
assistance to complete d PSoC d esign s. To contact or be come a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To locate the PSoC application notes, go to
http://www.cypress.com/design/results.cfm.
Device
Database
Application
Database
Project
Database
User
Modules
Library
Emulation
Pod
TM
PSoC
Designer
Core
Engine
In-Circuit
Emulator
Programmer
PSoC Designer Subsystems
PSoC
Configuration
Sheet
Manufacturing
Information
File
Device
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CY8C22x13 Final Data SheetPSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
The Device Edi tor su bsyst em al lows th e use r to se lect di ffere nt
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application programming in conj unc tion with the D evice Data S heet . Once the
framework is generated, the user can add application-specific
code to flesh out the fr am ew ork . It’s also possible to change the
selected components and regenerate the framework.
Design Browser
The Design Browser allows users to select and import preconfigured desi g ns into th e u se r’s project. Use rs ca n ea s il y br ow se
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tool s i nclude a 300-baud modem , LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consist s of a bas e unit th at conne ct s to th e PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family ar e ava ilabl e sep arate ly. The emulation pod t akes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation.
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, compile, link, and build.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries automatically use abso lut e addre ssing or ca n be co mpil ed in relat ive
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
PSoC Development Tool Kit
June 3, 2004Document No. 38-12009 Rev. *E5
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CY8C22x13 Final Data SheetPSoC™ Overview
User Modules and the PSoC
Development Process
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and d igital hard ware blocks give the PS oC archite cture
a unique flexibility that p ays d ivide nds in mana gi ng specifi catio n
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its fu nction and
connectivity to other blocks, multiplexers, buses, and to the IO
pins. Iterative devel op men t cy cl es perm it y ou to adapt the hardware as well as the software. This substantially lowers the risk
of having to select a different part to meet the final design
requirements.
To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
applicati on. For exam ple, a Pulse Width Modula tor User Module configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides highlevel functions to control and respond to hardware events at
run-time. The API als o provides o ptional inte rrupt servic e routines that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSo C Desi gn er ID E. Th es e data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user mod ule p ara me ter a nd d oc um ent s the setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Devi ce Edi t or, a pictorial environment (GUI) for
configuring the hardware. You pick the user modules you need
for your project and map them onto the PSoC blocks with pointand-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to develo ping co de for the proj ect, yo u
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your speci fic ati on an d pro vi des the hig h-le ve l us er
module API functions.
Device Editor
User
Module
Selection
Placement
and
Parameter
-ization
Source
Code
Generator
Generate
Application
Application Edito r
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
User Modules and Development Process Flow Chart
The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a ROM file image suitable for programming.
The last step in the devel opm en t proc es s t ak es pla ce insi de the
PSoC Designer’s Debugger subsystem. The Debugger downloads the ROM image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint event s tha t inc lu de m oni tori ng ad dres s and da t a bu s
values, memory locations and external signals.
Event &
Breakpoint
Manager
June 3, 2004Document No. 38-12009 Rev. *E6
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CY8C22x13 Final Data SheetPSoC™ Overview
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
AcronymDescription
ACalternating current
ADCanalog-to-digital converter
APIapplication programming interface
CPUcentral processing unit
CTcontinuous time
DACdigital-to-analog converter
DCdirect current
EEPROMelectrically erasable programmable read-only memory
FSRfull scale range
GPIOgeneral purpose IO
IOinput/output
IPORimprecise power on reset
LSbleast-significant bit
LVDlow voltage detect
MSbmost-significant bit
PCprogram counter
PORpower on reset
PPORprecision power on reset
PSoC™Programmable System-on-Chip
PWMpulse width modulator
RAMrandom access memory
ROMread only memory
SCswitched capacitor
SMPswitch mode pump
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 13 lists all the abbreviations
used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexi d ec im al nu mber s ma y al so be re p res en t ed by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Table of Contents
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed Signal Array Technical Refer-ence Manual. This document encompasses and is organized
into the following chapters and sections.
1.Pin Information .............................. ..... ...... .................... 8
This chapter describes, lists, and illustrates the CY8C22x13 PSoC device pins and pinout configurations.
1.1Pinouts
The CY8C22x13 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capab le of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.18-Pin Part Pinout
Table 1-1. 8-Pin Part Pinout (PDIP, SOIC)
Pin
No.
1IOIOP0[5]Analog column mux input and column output.
2IOIP0[3]Analog column mux input.
3IOP1[1]Crystal Input (XTALin), I2C Serial Clock (SCL)
4PowerVssGround connection.
5IOP1[0]Crystal Output (XTALout), I2C Serial Data
1NCNo connection. Do not use.
2NCNo connection. Do not use.
3NCNo connection. Do not use.
4NCNo connection. Do not use.
5PowerVssGround connection.
6PowerVssGround connection.
7IOP1[7]I2C Serial Clock (SCL)
8IOP1[5]I2C Serial Data (SDA)
9NCNo connection. Do not use.
10IOP1[3]
11IOP1[1]Crystal Input (XTALin), I2C Serial Clock (SCL)
12PowerVssGround connection.
13IOP1[0]Crystal Output (XTALout), I2C Serial Data
14IOP1[2]
15IOP1[4]Optional External Clock Input (EXTCLK)
16NCNo connection. Do not use.
17IOP1[6]
18InputXRESActive high external reset with internal pull
19NCNo connection. Do not use.
20NCNo connection. Do not use.
21NCNo connection. Do not use.
22NCNo connection. Do not use.
23IOIP0[0]Analog column mux input.
24IOIP0[2]Analog column mux input.
25NCNo connection. Do not use.
26IOIP0[4]Analog column mux input.
27IOIP0[6]Analog column mux input.
28PowerVddSupply voltage.
29IOIP0[7]Analog column mux input.
30IOIOP0[5]Analog column mux input and column output.
31IOIP0[3]Analog column mux input.
32IOIP0[1]Analog column mux input.
Type
Digital Analog
Pin
Name
Description
(SDA)
down.
I2C SCL, P1[7]
2C SDA, P1[5]
CY8C22213 PSoC Device
P0[1], A I
P0[3], A I
P0[5], A IO
P0[7], A I
Vdd
P0[6], A I
NC
NC
NC
NC
Vss
Vss
32313029282726
1
2
3
4
5
6
7
8
(Top View)
9
101112
NC
P1[3]
MLF
Vss
I2C SCL, XTALin, P1[1]
131415
P1[2]
I2C SDA, XT ALo u t, P1[0]
P0[4], A I
NC
25
P0[2], A
24
P0[0], A
23
22
NC
21
NC
20
NC
NC
19
XRES
18
P1[6]
17
16
NC
EXTCLK, P1[4]
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to the same ground
as the Vss pin.
June 3, 2004Document No. 38-12009 Rev. *E9
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2.Register Reference
This chapter lists the registers of the CY8C22x13 PSoC device by way of mapping tables, in offset order. For detailed register information, reference the PSoC™ Mixed Signal Array Technical Reference Manual.
2.1Register Conventions
2.1.1Abbreviations Used
The register conventions specific to this section are listed in the
following table.
ConventionDescription
RWRead and write register or bit(s)
RRead register or bit(s)
WWrite register or bit(s)
LLogical register or bit(s)
CClearable register or bit(s)
#Access is bit specific
2.2Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is also referred to as IO space and is
broken into two parts. The XOI bit in the Flag register determines which bank the user is currently in. When the XOI bit is
set, the user is said to be in the “extended” address space or
the “configuration” registers.
Note In the following register mapping tables, blank fields are
This chapter presents the DC and AC electrical specifications of the CY8C22x13 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by referencing the web at http://www.cypress.com/psoc.
Specifications are v alid for -40
at greater than 12 MHz are valid for -40
5.25
4.75
Vdd Voltage
o
C ≤ TA ≤ 85oC and TJ ≤ 100oC as specified, except where noted. Specifications for devices running
o
C ≤ TA ≤ 70oC and TJ ≤ 82oC.
O
V
p
a
l
e
R
i
d
r
a
e
t
g
i
n
i
o
g
n
3.00
93 kHz12 MHz24 MHz
CPU Frequency
Figure 3-1. Voltage versus Operating Frequency
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
SymbolUnit of Measur eSymbolUnit of Measure
o
dBdecibelsmAmilli-ampere
fFfemto faradmsmilli-second
HzhertzmVmilli-volts
KB1024 bytesnAnano amper e
Kbit1024 bitsnsnanosecond
kHzkilohertznVnanovolts
kΩkilohmΩohm
MHzmegahertzpApico ampere
MΩmegaohmpFpico farad
µAmicro amperepppeak-to-peak
µFmicro faradppmparts per million
µHmicro henrypspicosecond
µsmicrosecondspssamples per second
µVmicro voltsσsigma: one standard deviation
µVrmsmicro volts root-mean-squareVvolts
degree CelsiusµWmicro watts
C
June 2004Document No. 38-12009 Rev. *E13
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CY8C22x13 Final Data Sheet3. Electrical Specifications
3.1Ab solute Maximum Ratings
Table 3-2. Absolute Maximum Rat ings
SymbolDescriptionMinTypMaxUnitsNotes
T
STG
T
A
VddSupply Voltage on Vdd Relative to Vss-0.5–+6.0V
V
IO
–DC Voltage Applied to Tri-stateVss - 0.5 –Vdd + 0.5 V
I
The temperature rise from ambient to junction is
package specific. See “Thermal Impedances”
on page 34. The user must limit the power con-
sumption to comply with this requirement.
June 3, 2004Document No. 38-12009 Rev. *E14
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CY8C22x13 Final Data Sheet3. Electrical Specifications
3.3DC Electrical Characteristics
3.3.1DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Table 3-4. DC Chip-Level Specifications
SymbolDescriptionMinTypMaxUnitsNotes
VddSupply Voltage3.00–5.25V
I
DD
I
DD3
I
SB
I
SBH
I
SBXTL
I
SBXTLH
V
REF
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices tha t ha ve si mi la r fu n ct i o ns
enabled.
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Supply Current–58mA
Supply Current–3.36.0mA
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
a
WDT.
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT at high temperature.
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crystal.
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crystal at high temperature.
Reference Voltage (Bandgap)1.2751.31.325VTrimmed for appropriate Vdd.
a
a
a
–36.5µAConditions are with internal slow speed oscilla-
–425µAConditions are with internal slow speed oscilla-
–47.5µAConditions are with properly loaded, 1 µW max,
–526µAConditions are with properly loaded, 1 µW max,
Conditions are Vdd = 5.0V, 25 oC, CPU = 3
MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 =
93.75 kHz, VC3 = 93.75 kHz.
Condition s are Vdd = 3.3V, TA = 25 oC, CPU = 3
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Table 3-5. DC GPIO Specifications
SymbolDescriptionMinTypMaxUnitsNotes
R
PU
R
PD
V
OH
V
OL
V
IL
V
IH
V
H
I
IL
C
IN
C
OUT
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Pull up Resistor45.68kΩ
Pull down Resistor45. 68kΩ
High Output LevelVdd - 1.0 ––VIOH = 10 mA, Vdd = 4.75 to 5.25V (80 mA max-
Low Output Level––0.75VIOL = 25 mA, Vdd = 4.75 to 5.25V (1 50 mA
Input Low Level––0.8VVdd = 3.0 to 5.25
Input High Level2.1–VVdd = 3.0 to 5.25
Input Hysterisis–60–mV
Input Leakage (Absolute Value)–1–nAGross tested to 1 µA.
Capacitive Load on Pins as Input–3.510pF
Capacitive Load on Pins as Output–3.510pF
imum combined IOH budget)
maximum combined IOL budget)
Package and pin dependent. Temp = 25oC.
Package and pin dependent. Temp = 25oC.
June 3, 2004Document No. 38-12009 Rev. *E15
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CY8C22x13 Final Data Sheet3. Electrical Specifications
3.3.3DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
T able 3-6. 5V DC Operatio nal A mpli fier Sp eci fica tions
SymbolDescriptionMinTypMaxUnitsNotes
V
OSOA
TCV
OSOA
I
EBOA
C
INOA
V
CMOA
G
OLOA
V
OHIGHOA
V
OLOWOA
I
SOA
PSRR
OA
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Input Offset Voltage (absolute value) Low Power
Input Offset Voltage (absolute value) Mid Power
Input Offset Voltage (absolute value) High Power
Average Input Offset Voltage Drift–7.035.0
Input Leakage Current (Port 0 Analog Pins)–20–pAGross tested to 1 µA.
Input Capacitance (Port 0 Analog Pins)–4.59.5pF
Common Mode Voltage Range
Common Mode Voltage Range (high power or high
opamp bias)
Open Loop Gain
Power = Low
Power = Medium
Power = High
High Output Voltage Swing (worst case internal load)
Power = Low
Power = Medium
Power = High
Low Output Voltage Swing (worst case internal load)
Power = Low
Power = Medium
Power = High
Supply Current (including associated AGND buffer)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio60––dB
–1.6
–
–
0.0–Vdd
0.5–
60
60
80
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
–
–
–
1.3
1.2
––dBSpecification is applicable at high power. For all
–
–
–
–
–
–
150
300
600
1200
2400
4600
10
8
7.5
Vdd - 0.5
–
–
–
0.2
0.2
0.5
200
400
800
1600
3200
6400
mV
mV
mV
o
µV/
C
Package and pin dependent. Temp = 25
VThe common-mode input voltage range is mea-
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
sured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.
other bias modes (except high power, high
opamp bias), minimum is 60 dB.
o
C.
June 3, 2004Document No. 38-12009 Rev. *E16
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CY8C22x13 Final Data Sheet3. Electrical Specifications
Table 3-7. 3.3V DC Operational Amplifier Specifications
SymbolDescriptionMinTypMaxUnitsNotes
V
OSOA
TCV
I
EBOA
C
INOA
V
CMOA
G
OLOA
V
OHIGHOA
V
OLOWOA
I
SOA
PSRR
OSOA
Input Offset Voltage (absolute value) Low Power
Input Offset Voltage (absolute value) Mid Power
–
–
1.65
1.32
10
8
mV
mV
High Power is 5 Volt Only
Average Input Offset Voltage Drift–7.035.0
µV/
o
C
Input Leakage Current (Port 0 Analog Pins)–20–pAGross tested to 1 µA.
Input Capacitance (Port 0 Analog Pins)–4.59.5pF
Package and pin dependent. Temp = 25
Common Mode Voltage Range0.2–Vdd - 0.2 VThe common-mode input voltage range is
measured through an analog output buffer.
The specification includes the limitations
imposed by the characteristics of the analog
output buffer.
Open Loop Gain
Power = Low
Power = Medium
Power = High
60
60
80
––dBSpecification is applicable at high power. For
all other bias modes (except high power, high
opamp bias), minimum is 60 dB.
High Output Voltage Swing (worst case internal load)
Power = Low
Power = Medium
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
Low Output Voltage Swing (worst case internal load)
Power = Low
Power = Medium
Power = High
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
Supply Current (including associated AGND buffer)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio50––dB
OA
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
o
C.
June 3, 2004Document No. 38-12009 Rev. *E17
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CY8C22x13 Final Data Sheet3. Electrical Specifications
3.3.4DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Table 3-8. 5V DC Analog Output Buffer Specifications
SymbolDescriptionMinTypMaxUnitsNotes
V
OSOB
TCV
OSOB
V
CMOB
R
OUTOB
V
OHIGHOB
V
OLOWOB
I
SOB
PSRR
OB
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Input Offset Voltage (Absolute Value)–312mV
Average Input Offset Vol tage Drift–+6–µV/°C
Common-Mode Input Voltage Range0.5–Vdd - 1.0V
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio60––dB
–
–
0.5 x Vdd + 1.1
0.5 x Vdd
–
–
–
–
+ 1.1
1
1
–
–
–
–
1.1
2.6
–
–
–
–
0.5 x Vdd - 1.3
0.5 x Vdd
5.1
8.8
- 1.3
Ω
Ω
V
V
V
V
mA
mA
Table 3-9. 3.3V DC Analog Output Buffer Specifications
SymbolDescriptionMinTypMaxUnitsNotes
V
OSOB
TCV
V
CMOB
R
OUTOB
V
OHIGHOB
V
OLOWOB
I
SOB
PSRR
OSOB
Input Offset Voltage (Absolute Value)–312mV
Average Input Offset Voltage Drift–+6–µV/°C
Common-Mode Input Voltage Range0.5-Vdd - 1.0V
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 1K ohms to Vdd/2)
Power = Low
Power = High
Low Output Voltage Swing (Load = 1K ohms to Vdd/2)
Power = Low
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio50––dB
OB
–
–
0.5 x Vdd + 1.0
0.5 x Vdd
–
–
–
+ 1.0
1
1
–
–
–
–
0.8
2.0
–
–
–
–
0.5 x Vdd - 1.0
0.5 x Vdd
2.0
4.3
- 1.0
Ω
Ω
V
V
V
V
mA
mA
June 3, 2004Document No. 38-12009 Rev. *E18
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CY8C22x13 Final Data Sheet3. Electrical Specifications
3.3.5DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
The guaranteed specific ations are measure d throug h the Anal og Con tinuou s T im e PSoC block s. The powe r level s for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Table 3-10. 5V DC Analog Reference Specifications
SymbolDescriptionMinTypMaxUnits
–
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 2%.
Table 3-11. 3.3V DC Analog Reference Specifications
SymbolDescriptionMinTypMaxUnits
–
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 2%
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
AGND = Vdd/2
CT Block Power = High
AGND = Vdd/2
CT Block Power = High
a
Vdd/2 - 0.043Vdd/2 - 0.025Vdd/2 + 0.003V
a
Vdd/2 - 0.037Vdd/2 - 0.020Vdd/2 + 0.002V
3.3.6DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Table 3-12. DC Analog PSoC Block Specifications
SymbolDescriptionMinTypMaxUnitsNotes
R
CT
C
SC
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Resistor Unit Value (Continuous Time)–12.24–kΩ
Capacitor Unit Value (Switch Cap)–80–fF
June 3, 2004Document No. 38-12009 Rev. *E19
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CY8C22x13 Final Data Sheet3. Electrical Specifications
3.3.7DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed Signal Array Technical
Reference Manual for more information on the VLT_CR register.
Table 3-13. DC POR and LVD Specifications
SymbolDescriptionMinTypMaxUnitsNotes
V
PPOR0R
V
PPOR1R
V
PPOR2R
V
PPOR0
V
PPOR1
V
PPOR2
V
PH0
V
PH1
V
PH2
V
LVD0
V
LVD1
V
LVD2
V
LVD3
V
LVD4
V
LVD5
V
LVD6
V
LVD7
a. Always greater than 50 mV above PPOR (PORLEV = 00) for f alling supply.
b. Always greater than 50 mV above PPOR (PORLEV = 10) for f alling supply.
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
2.908
4.394
4.548
V
–
V
V
Vdd Value for PPO R Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
CY8C22x13 Final Data Sheet3. Electrical Specifications
3.3.8DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Table 3-14. DC Programming Specifications
SymbolDescriptionMinTypMaxUnitsNotes
I
DDP
V
ILP
V
IHP
I
ILP
I
IHP
V
OLV
V
OHV
Flash
ENPB
Flash
ENT
Flash
DR
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no single block ever
sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Supply Current During Programming or Verify–525mA
Input Low Voltage During Programming or Verify––0.8V
Input High Voltage During Programming or Verify2.2––V
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
Output Low Voltage During Programming or Verify––Vss + 0.75 V
Output High Voltage During Programming or VerifyVdd - 1.0–VddV
Flash Endurance (per block)50,000–––Erase/write cycles per block.
Flash Endurance (total)
Flash Data Retention10––Years
a
––0.2mADriving internal pull-down resistor.
––1.5mADriving internal pull-down resistor.
1,800,000 –––Erase/write cycles.
June 3, 2004Document No. 38-12009 Rev. *E21
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CY8C22x13 Final Data Sheet3. Electrical Specifications
E
3.4AC Electrical Characteristics
3.4.1AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
d. See the individual user module data sheets for information on maximum frequencies for user modules.
e. 3.0V < 5.25V.
f. The crystal oscillator frequency is within 100 ppm of its final value by the end of the T
32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Internal Main Oscillator Frequency23.424
CPU Frequency (5V Nomi nal)0.9324
CPU Frequency (3.3V Nominal)0.9312
Digital PSoC Block Frequency048
Figure 3-5. 24 MHz Period Jitter (IMO) Timing Diagram
32 kHz
Jitter32k
32K2
Figure 3-6. 32 kHz Period Jitter (ECO) Timing Diagram
June 3, 2004Document No. 38-12009 Rev. *E23
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CY8C22x13 Final Data Sheet3. Electrical Specifications
G
3.4.2AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Table 3-16. AC GPIO Specifications
SymbolDescriptionMinTypMaxUnitsNotes
F
GPIO
TRiseFRise Time, Normal Strong Mode, Cload = 50 pF3–18nsVdd = 4.5 to 5.25V, 10% - 90%
TFallFFall Time, Normal Strong Mode, Cload = 50 pF2–18nsVdd = 4.5 to 5.25V, 10% - 90%
TRiseSRise Time, Slow Strong Mode, Cload = 50 pF1027–nsVdd = 3 to 5.25V, 10% - 90%
TFallSFall Time, Slow Strong Mode, Cload = 50 pF1022–nsVdd = 3 to 5.25V, 10% - 90%
PIO
Pin
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
GPIO Operating Frequenc y0–12MHz
90%
10%
TRiseF
TRiseS
Figure 3-7. GPIO Timing Diagram
TFallF
TFallS
June 3, 2004Document No. 38-12009 Rev. *E24
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CY8C22x13 Final Data Sheet3. Electrical Specifications
3.4.3AC Operational Amplifie r Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 3-17. 5V AC Operational Amplifier Specifications
SymbolDescriptionMinTypMaxUnitsNotes
T
ROA
T
SOA
SR
ROA
SR
FOA
BW
OA
E
NOA
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)–200–nV/rt-Hz
–
–
–
–
–
–
–
–
–
–
–
–
0.15
1.7
6.5
0.01
0.5
4.0
0.75
3.1
5.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.9
0.72
0.62
5.9
0.92
0.72
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
V/
V/
V/
V/
V/
V/
V/
V/
V/
V/
V/
V/
MHz
MHz
MHz
MHz
MHz
MHz
Specification maximums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
Specification maximums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
Specification minimums for low power and
high opamp bias, medium power, and
µs
medium power and high opamp bias levels
µs
are between low and high power levels.
µs
µs
µs
µs
Specification minimums for low power and
high opamp bias, medium power, and
µs
medium power and high opamp bias levels
µs
are between low and high power levels.
µs
µs
µs
µs
Specification minimums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
June 3, 2004Document No. 38-12009 Rev. *E25
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CY8C22x13 Final Data Sheet3. Electrical Specifications
Table 3-18. 3.3V AC Operational Amplifier Specifications
SymbolDescriptionMinTypMaxUnitsNotes
T
T
SR
SR
BW
E
ROA
SOA
NOA
ROA
FOA
OA
Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High (3.3 V olt High Bias Operation not support ed)
Power = High, Opamp Bias = High (3.3 Volt High Power,
High Opamp Bias not supported)
–
–
3.92
–
–
–
–
–
–
–
–
0.72
–
–
µs
µs
µs
µs
µs
µs
Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High (3.3 V olt High Bias Operation not support ed)
–
–
–
–
–
–
–
–
5.41
0.72
–
µs
µs
µs
µs
µs
Power = High, Opamp Bias = High (3.3 Volt High Power,
High Opamp Bias not supported)
–
–
–
µs
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High (3.3 V olt High Bias Operation not support ed)
0.31
2.7
–
–
–
–
–
V/
V/
V/
V/
V/
Power = High, Opamp Bias = High (3.3 Volt High Power,
High Opamp Bias not supported)
–
–
–
V/
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High (3.3 V olt High Bias Operation not support ed)
Power = High, Opamp Bias = High (3.3 Volt High Power,
High Opamp Bias not supported)
0.24
1.8
–
–
–
–
–
–
–
–
V/
V/
V/
V/
V/
V/
Gain Bandwidth Product
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High (3.3 V olt High Bias Operation not support ed)
Specification maximums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
Specification maximums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
Specification minimums for low power and
high opamp bias, medium power, and
µs
medium power and high opamp bias levels
µs
are between low and high power levels.
µs
µs
µs
µs
Specification minimums for low power and
high opamp bias, medium power, and
µs
medium power and high opamp bias levels
µs
are between low and high power levels.
µs
µs
µs
µs
Specification minimums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
June 3, 2004Document No. 38-12009 Rev. *E26
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CY8C22x13 Final Data Sheet3. Electrical Specifications
3.4.4AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Maximum Frequency––49.2MHz4. 75V < Vdd < 5.25V.
Maximum Inpu t Clock Frequency––49.2MHz4.75V < Vdd < 5. 25V.
Maximum Inpu t Clock Frequency––24.6MHz
Width of SS_ Negated Between Transmissions
50
50
50
––ns
a
––ns
a
––ns
a
––ns
a
––ns
June 3, 2004Document No. 38-12009 Rev. *E27
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CY8C22x13 Final Data Sheet3. Electrical Specifications
3.4.5AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Table 3-20. 5V AC Analog Output Buffer Specifications
SymbolDescriptionMinTypMaxUnitsNotes
T
ROB
T
SOB
SR
ROB
SR
FOB
BW
OB
BW
OB
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Power = Low
Power = High
–
–
–
–
0.65
0.65
0.65
0.65
0.8
0.8
300
300
–
–
–
–
–
–
–
–
–
–
–
–
2.5
2.5
2.2
2.2
–
–
–
–
–
–
–
–
µs
µs
µs
µs
V/µs
V/
V/µs
V/
MHz
MHz
kHz
kHz
µs
µs
Table 3-21. 3.3V AC Analog Output Buffer Specifications
SymbolDescriptionMinTypMaxUnitsNotes
T
T
SR
SR
BW
BW
ROB
SOB
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
ROB
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
FOB
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
OB
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
OB
Power = Low
Power = High
–
–
–
–
0.5
0.5
0.5
0.5
0.7
0.7
200
200
–
–
–
–
–
–
–
–
–
–
–
–
3.8
3.8
2.6
2.6
–
–
–
–
–
–
–
–
µs
µs
µs
µs
V/µs
V/
V/µs
V/
MHz
MHz
kHz
kHz
µs
µs
June 3, 2004Document No. 38-12009 Rev. *E28
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CY8C22x13 Final Data Sheet3. Electrical Specifications
3.4.6AC External Cl ock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Table 3-22. 5V AC External Clo ck Specifications
SymbolDescriptionMinTypMaxUnitsNotes
F
OSCEXT
–High Period20.6
–Low Period20.6
–Power Up IMO to Switch150
Table 3-23. 3.3V AC External Clock Specifications
SymbolDescriptionMinTypMaxUnitsNotes
F
OSCEXT
F
OSCEXT
–High Period with CPU Clock divide by 141.7
–Low Period with CPU Clock divide by 141.7
–Power Up IMO to Switch150
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Frequency0–24.24MHz
––ns
––ns
––µs
Frequency with CPU Clock divide by 1
Frequency with CPU Clock divide by 2 or greater
a
b
0–12.12MHz
0–24.24MHz
––ns
––ns
––µs
3.4.7AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
Table 3-24. AC Programming Specifications
SymbolDescriptionMinTypMaxUnitsNotes
T
RSCLK
T
FSCLK
T
SSCLK
T
HSCLK
F
SCLK
T
ERASEB
T
WRITE
T
DSCLK
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Rise Time of SCLK 1–20ns
Fall Time of SCLK 1–20ns
Data Set up Time to Falling Edge of SCLK40––ns
Data Hold Time from Falling Edge of SCLK40––ns
Frequency of SCLK0–8MHz
Flash Erase Time (Block)–15–ms
Flash Block Write Time–30–ms
Data Out Delay from Falling Edge of SCLK––45ns
June 3, 2004Document No. 38-12009 Rev. *E29
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CY8C22x13 Final Data Sheet3. Electrical Specifications
S
3.4.8AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
are for design guidance only or unless otherwise specified.
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
Table 3-25. AC Characteristics of the I
SymbolDescription
F
SCLI2C
T
HDSTAI2C
T
LOWI2C
T
HIGHI2C
T
SUSTAI2C
T
HDDATI2C
T
SUDATI2C
T
SUSTOI2C
T
BUFI2C
T
SPI2C
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
SCL Clock Frequency01000400kHz
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
LOW Period of the SCL Clock4.7–1.3–µs
HIGH Period of the SCL Clock4.0–0.6–µs
Set-up Time for a Repeated START Condition4.7–0.6–µs
Data Hold Time0–0–µs
Data Set-up Time250–
Set-up Time for STOP Condition4.0–0.6–µs
Bus Free Time Between a STOP and START Condition 4.7–1.3–µs
Pulse Width of spikes are suppressed by the input fil-
ter.
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
+ t
bit to the SDA line t
rmax
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
SU;DAT
2
C SDA and SCL Pins
Standard ModeFast Mode
4.0–0.6–µs
––050ns
100
a
–ns
≥ 250 ns must then be met. This will automatically be
SU;DAT
UnitsNotesMinMaxMinMax
DA
T
LOWI2C
T
SUDATI2C
T
HDSTAI2C
T
SPI2C
T
BUFI2C
SCL
S
T
HDSTAI2C
T
HDDATI2C
T
HIGHI2C
T
SUSTAI2C
SrSP
Figure 3-8. Definition for Timing for Fast/Standard Mode on the I2C Bus
T
SUSTOI2C
June 3, 2004Document No. 38-12009 Rev. *E30
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4.Packaging Information
This chapter illustrates the packaging specifications for the CY8C22x13 PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
CY8C22x13 Final Data Sheet4. Packaging Information
Figure 4-2. 8-Lead (150-Mil) SOIC
Figure 4-3. 20-Lead (300-Mil) Molded DIP
51-85011-A
51-85011 - *A
51-85066 *B
51-85066 *B
51-85066 - *C
June 3, 2004Document No. 38-12009 Rev. *E32
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CY8C22x13 Final Data Sheet4. Packaging Information
Figure 4-4. 20-Lead (210-Mil) SSOP
51-85077 - *C
51-85024 - *B
Figure 4-5. 20-Lead (300-Mil) Molded SOIC
June 3, 2004Document No. 38-12009 Rev. *E33
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CY8C22x13 Final Data Sheet4. Packaging Information
X = 138 MIL
Y = 138 MIL
32
51-85188 - **
Figure 4-6. 32-Lead (5x5 mm) MLF
4.2Thermal Impeda nces
Table 4-1. Thermal Impedances per Package
PackageTypical θ
8 PDIP
8 SOIC
20 PDIP
20 SSOP
20 SOIC
32 MLF
* TJ = TA + POWER x θ
123 oC/W
185 oC/W
109 oC/W
117 oC/W
81 oC/W
22 oC/W
JA
JA
*
4.3Capacitance on Crystal Pins
Table 4-2: Typical Package Capacitance on Crystal Pins
PackagePackage Capacitance
8 PDIP2.8 pF
8 SOIC2.0 pF
20 PDIP3.0 pF
20 SSOP2.6 pF
20 SOIC2.5 pF
32 MLF2.0 pF
June 3, 2004Document No. 38-12009 Rev. *E34
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5.Ordering Information
C
The following table lists the CY8C22x13 PSoC Device family’s key package features and ordering codes.
Table 5-1. CY8C22x13 PSoC Device Family Key Features and Ordering Information
Package
8 Pin (300 Mil) DIPCY8C22113-24PI2256No-40C to +85C43641No
8 Pin (150 Mil) SOICCY8C22113-24SI2256No-40C to +85C43641No
8 Pin (150 Mil) SOIC
(Tape and Reel)
20 Pin (300 Mil) DIPCY8C22213-24PI2256No-40C to +85C431681Yes
20 Pin (210 Mil) SSOPCY8C22213-24PVI2256No-40C to +85C431681Yes
20 Pin (210 Mil) SSOP
(Tape and Reel)
20 Pin (300 Mil) SOICCY8C22213-24SI2256No-40C to +85C431681Yes
20 Pin (300 Mil) SOIC
(Tape and Reel)
32 Pin (5x5 mm) MLFCY8C22213-24LFI2256No-40C to +85C431681Yes
CY8C22113-24SIT2256No-40C to +85C43641No
CY8C22213-24PVIT2256No-40C to +85C431681Yes
CY8C22213-24SIT2256No-40C to +85C431681Yes
Ordering
Code
Flash (Kbytes)
RAM (Bytes)
Pump
Switch Mode
Range
Temperature
(Rows of 4)
Digital Blocks
Analog Blocks
(Columns of 3)
Digital IO Pins
Analog Inputs
Analog Outputs
5.1Ordering Code Definitions
Y 8 C 22 xxx-SPxx
Package Type:Thermal Rating:
P = PDIPC = Commercial
S = SOICI = Industrial
PV = SSOPE = Extended
LF = MLF
A = TQFP
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress MicroSystems
Company ID: CY = Cypress
XRES Pin
June 3, 2004Document No. 38-12009 Rev. *E35
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6.Sales and Company Information
To obtain information about Cypre ss Mi croSys tems or PSoC sales and tec hnic al support, refere nce the fol lowi ng infor mation or go to
the section titled “Getting Started” on page 4 in this document.
Cypress MicroSystems
2700 162nd Street SW
Building D
Lynnwood, WA 98037
Phone: 800.669.0557
Facsimile: 425.787.4641
Web Sites:Company Information – http://www.cypress.com
The information contained herein is subject to change without notice. Cypr ess MicroSystems assumes no responsibility for the use of any circuitry othe r than circuitry
embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not aut ho ri ze i t s pr od uc t s
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress MicroSystems against all charges. Cypr ess MicroSystems products are not warran ted nor intended to be used for medica l, life-support, life-saving, critical contr ol or safety
applications, unless pursuant to an express written agreement with Cypress MicroSystems.