Cypress CY8C21434, CY8C21234, CY8C21534, CY8C21634, CY8C21334 User Manual
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
PSoC® Programmable System-on-Chip™
Features
Logic Block Diagram
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Low power at high speed
❐ 2.4V to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V using On-Chip Switch
Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC
❐ 4 Analog Type “E” PSoC Blocks provide:
• 2 Comparators with DAC Refs
• Single or Dual 8-Bit 28 Channel ADC
❐ 4 Digital PSoC Blocks provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART, SPI™ Master or Slave
• Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Flexible On-Chip Memory
❐ 8K Flash Program Storage 50,000 Erase/Write Cycles
❐ 512 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Complete Development Tools
❐ Free Development Software
(PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
■ Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to 8 Analog Inputs on GPIO
❐ Configurable Interrupt on All GPIO
®
Blocks)
■ Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous Connection of IO Combinations
❐ Capacitive Sensing Application Capability
■ Additional System Resources
2
❐ I
C Master, Slave and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-12025 Rev. *O Revised April 06, 2009
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PSoC Functional Overview
DIGITAL SYSTEM
To System Bus
D
i
g
i
t
a
l
C
l
o
c
k
s
F
r
o
m
C
o
r
e
Digit al PSoC Block Arr ay
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8
Row 0
DBB00 DBB0 1 DCB 02 DCB 03
4
4
GIE[7:0]
GIO[7: 0]
GOE[7:0 ]
GOO[7:0 ]
Global Digital
Interconnect
Por t 3
Por t 2
Por t 1
Por t 0
The PSoC family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture enables the
user to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
The PSoC architecture, shown in Figure 1, consists of four main
areas: the Core, the System Resources, the Digital System, and
the Analog System. Configurable global bus resources allow
combining all the device resources into a complete custom
system. Each CY8C21x34 PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 general purpose IO (GPIO) are also included.
The GPIO provide access to the global digital and analog interconnects.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
System Resources provide the following additional capabilities:
■ Digital clocks to increase the flexibility of the PSoC
mixed-signal arrays.
■ I2C functionality to implement an I2C master and slave.
■ An internal voltage reference, MultiMaster, that provides an
absolute value of 1.3V to a number of PSoC subsystems.
■ A switch mode pump (SMP) that generates normal operating
voltages off a single battery cell.
■ Various system resets supported by the M8C.
The Digital System consists of an array of digital PSoC blocks
that may be configured into any number of digital peripherals.
The digital blocks are connected to the GPIO through a series of
global buses that can route any signal to any pin, freeing designs
from the constraints of a fixed peripheral controller.
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to 8
bits in precision.
The Digital System
The Digital System consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references. Digital peripheral configurations include
the following.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity
■ SPI master and slave
■ I2C slave and multi-master
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Ta b le 1 on page 4.
Figure 1. Digital System Block Diagram
Document Number: 38-12025 Rev. *O Page 2 of 45
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The Analog System
AC O L 1 M U X
ACE00 ACE01
Array
Array Input
Configuration
ASE10 ASE11
X
X
X
X
X
An a l o g Mux Bus
All IO
ACI0[1:0] ACI1[1:0]
The Analog System consists of 4 configurable blocks that allow
the creation of complex analog signal flows. Analog peripherals
are very flexible and may be customized to support specific
application requirements. Some of the common PSoC analog
functions for this device (most available as user modules) are:
■ Analog-to-digital converters (single or dual, with 8-bit or 10-bit
resolution)
■ Pin-to-pin comparator
■ Single-ended comparators (up to 2) with absolute (1.3V)
reference or 8-bit DAC reference
■ 1.3V reference (as a System Resource)
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x34 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT Type E block and one SC Type E block. Refer
to the PSoC Programmable System-on-Chip™ Technical
Reference Manual for detailed information on the CY8C21x34’s
Type E analog blocks.
Figure 2. Analog System Block Diagram
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins may
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional 8:1
analog input multiplexer provides a second path to bring Port 0
pins to the analog array.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Track pad, finger sensing.
■ Chip-wide mux that allows analog input from any IO pin.
■ Crosspoint connection between any IO pin combinations.
When designing capacitive sensing applications, refer to the
signal-to-noise system level requirement found in Application
Note AN2403 on the Cypress web site at
http://www.cypress.com.
Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow.
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■ An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
■ An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
■ Versatile analog multiplexer system.
Document Number: 38-12025 Rev. *O Page 3 of 45
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PSoC Device Characteristics
Notes
1. Limited analog functionality
.
2. Two analog blocks and one CapSense.
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. Table 1 lists the resources available for specific
PSoC device groups. The PSoC device covered by this data
sheet is highlighted in this table.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66 up to 644 16 12 4 4 12 2K 32K
CY8C27x43
CY8C24x94 56 1 4 48 2 2 6 1K 16K
CY8C24x23A
CY8C21x34 up to 281 4 28 0 2 4
CY8C21x23
CY8C20x34
Digital IODigital
up to 442 8 12 4 4 12 256
up to 241 4 12 2 2 6 256
16 1 4 8 0 2 4
up to 280 0 28 0 0 3
Rows
Digital
Blocks
Analog
Inputs
Analog
Analog
Outputs
Analog
Columns
[1]
[1]
[2]
Blocks
Bytes
Bytes
512
Bytes
256
Bytes
512
Bytes
Size
SRAM
16K
4K
8K
4K
8K
Flash
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip
Technical Reference Manual for CY8C28xxx PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
Size
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
Cypros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Document Number: 38-12025 Rev. *O Page 4 of 45
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Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional Integrated Development
Environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write IO registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Document Number: 38-12025 Rev. *O Page 5 of 45
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
2
(I
C-bus, for example), and the logic to control how they interact
with one another (called valuators).
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the IO pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
Document Number: 38-12025 Rev. *O Page 6 of 45
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms Used
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC® Programmable System-on-Chip™
PWM pulse width modulator
SC switched capacitor
SLIMO slow IMO
SMP switch mode pump
SRAM static random access memory
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 2 on page 7 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Document Number: 38-12025 Rev. *O Page 7 of 45
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Pin Information
Note
3. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
SOIC
Vd d
P0[6 ], A, I, M
P0[4 ], A, I, M
P0[2 ], A, I, M
P0[0 ], A, I, M
P1[4 ], EXTCL K, M
P1[2 ], M
P1[0 ], I2 C SDA, M
16
15
14
13
12
11
1
2
3
4
5
6
7
8
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
SMP
Vss
M, I2C SCL , P1 [1 ]
Vss
10
9
The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with
a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of
Digital IO.
16-Pin Part Pinout
Figure 3. CY8C21234 16-Pin PSoC Device
Table 3. Pin Definitions - CY8C21234 16-Pin (SOIC)
Pin No.
Digital Analog
1 IO I, M P0[7] Analog column mux input.
2 IO I, M P0[5] Analog column mux input.
3 IO I, M P0[3] Analog column mux input, integrating input.
4 IO I, M P0[1] Analog column mux input, integrating input.
5 Power SMP Switch Mode Pump (SMP) connection to required external components.
6 Power Vss Ground connection.
7 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK
8 Power Vss Ground connection.
9 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA
10 IO M P1[2]
11 IO M P1[4] Optional External Clock Input (EXTCLK).
12 IO I, M P0[0] Analog column mux input.
13 IO I, M P0[2] Analog column mux input.
14 IO I, M P0[4] Analog column mux input.
15 IO I, M P0[6] Analog column mux input.
16 Power Vdd Supply voltage.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Type
Name Description
[3]
.
[3]
..
Document Number: 38-12025 Rev. *O Page 8 of 45
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20-Pin Part Pinout
SSOP
Vd d
P0[6 ], A, I, M
P0[4 ], A, I, M
P0[2 ], A, I, M
P0[0 ], A, I, M
XRES
P1[6 ], M
P1[4 ], EXTCL K, M
P1[2 ], M
P1[0 ], I2 C SDA, M
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
M, I2C SC L , P1 [7 ]
SDA, P1 [ 5 ]
M, P1 [3 ]
SCL , P1[ 1 ]
Vss
Vss
M, I2 C
M, I2 C
Figure 4. CY8C21334 20-Pin PSoC Device
Table 4. Pin Definitions - CY8C21334 20-Pin (SSOP)
Pin No.
Digital Analog
1 IO I, M P0[7] Analog column mux input.
2 IO I, M P0[5] Analog column mux input.
3 IO I, M P0[3] Analog column mux input, integrating input.
4 IO I, M P0[1] Analog column mux input, integrating input.
5 Power Vss Ground connection.
6 IO M P1[7] I2C Serial Clock (SCL).
7 IO M P1[5] I2C Serial Data (SDA).
8 IO M P1[3]
9 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK
10 Power Vss Ground connection.
11 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA
12 IO M P1[2]
13 IO M P1[4] Optional External Clock Input (EXTCLK).
14 IO M P1[6]
15 Input XRES Active high external reset with internal pull down.
16 IO I, M P0[0] Analog column mux input.
17 IO I, M P0[2] Analog column mux input.
18 IO I, M P0[4] Analog column mux input.
19 IO I, M P0[6] Analog column mux input.
20 Power Vdd Supply voltage.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Type
Name Description
[3]
.
[3]
.
Document Number: 38-12025 Rev. *O Page 9 of 45
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CY8C21434, CY8C21334, CY8C21234
28-Pin Part Pinout
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
M, P2 [7 ]
M, P2 [5 ]
M, P2 [3 ]
M, P2 [1 ]
Vss
M, I2 C SC L , P1 [ 7 ]
M, I2 C SDA, P1[ 5]
M, P1 [3 ]
M, I2 C SC L , P1 [ 1 ]
Vss
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6 ], M
P2[4 ], M
P2[2 ], M
P2[0 ], M
XRES
P1[6 ], M
P1[4 ], EXTCL K, M
P1[2 ], M
P1[0], I2C SDA, M
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Figure 5. CY8C21534 28-Pin PSoC Device
Table 5. Pin Definitions - CY8C21534 28-Pin (SSOP)
Pin No.
Digital Analog
1 IO I, M P0[7] Analog column mux input.
2 IO I, M P0[5] Analog column mux input and column output.
3 IO I, M P0[3] Analog column mux input and column output, integrating input.
4 IO I, M P0[1] Analog column mux input, integrating input.
5 IO M P2[7]
6 IO M P2[5]
7 IO I, M P2[3] Direct switched capacitor block input.
8 IO I, M P2[1] Direct switched capacitor block input.
9 Power Vss Ground connection.
10 IO M P1[7] I2C Serial Clock (SCL).
11 IO M P1[5] I2C Serial Data (SDA).
12 IO M P1[3]
13 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK
14 Power Vss Ground connection.
15 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA
16 IO M P1[2]
17 IO M P1[4] Optional External Clock Input (EXTCLK).
18 IO M P1[6]
19 Input XRES Active high external reset with internal pull down.
20 IO I, M P2[0] Direct switched capacitor block input.
21 IO I, M P2[2] Direct switched capacitor block input.
22 IO M P2[4]
23 IO M P2[6]
24 IO I, M P0[0] Analog column mux input.
25 IO I, M P0[2] Analog column mux input.
26 IO I, M P0[4] Analog column mux input
27 IO I, M P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.
Document Number: 38-12025 Rev. *O Page 10 of 45
Typ e
Name Description
[3]
.
[3]
.
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
32-Pin Part Pinout
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
QFN
(Top View)
9
101112
131415
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32313029282726
25
Vss
P0[3], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
Vss
M, 12C SCL, P1[7]
P0[0], A, I, M
P2[6], M
P3[0], M
XRES
M, 12C SDA, P1[5]
M, P1[3]
M, 12C SCL, P1[1]
Vss
M, 12C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P0[5], A, I, M
Figure 6. CY8C21434 32-Pin PSoC Device
Figure 9. CY8C21634 32-Pin PSoC Device
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
QFN
(Top View)
9
101112
131415
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32313029282726
25
Vss
P0[3], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
M, P3[1]
M, 12C SCL, P1[7]
P0[0], A, I, M
P2[6], M
P3[0], M
XRES
M, 12C SDA, P1[5]
M, P1[3]
M, 12C SCL, P1[1]
Vss
M, 12C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P0[5], A, I, M
Figure 10. CY8C21434 32-Pin Sawn PSoC Device Figure 11. CY8C21634 32-Pin Sawn PSoC Device
Document Number: 38-12025 Rev. *O Page 11 of 45
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Table 6. Pin Definitions - CY8C21434/CY8C21634 32-Pin (QFN)
Note
4. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Pin
No.
Digital Analog
Typ e
Name Description
[4]
1 IO I, M P0[1] Analog column mux input, integrating input.
2 IO M P2[7]
3 IO M P2[5]
4 IO M P2[3]
5 IO M P2[1]
6 IO M P3[3] In CY8C21434 part.
6 Power SMP Switch Mode Pump (SMP) connection to required external components in
CY8C21634 part.
7 IO M P3[1] In CY8C21434 part.
7 Power Vss Ground connection in CY8C21634 part.
8 IO M P1[7] I2C Serial Clock (SCL).
9 IO M P1[5] I2C Serial Data (SDA).
10 IO M P1[3]
11 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK
[3]
.
12 Power Vss Ground connection.
13 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA
[3]
14 IO M P1[2]
15 IO M P1[4] Optional External Clock Input (EXTCLK).
16 IO M P1[6]
17 Input XRES Active high external reset with internal pull down.
18 IO M P3[0]
19 IO M P3[2]
20 IO M P2[0]
21 IO M P2[2]
22 IO M P2[4]
23 IO M P2[6]
24 IO I, M P0[0] Analog column mux input.
25 IO I, M P0[2] Analog column mux input.
26 IO I, M P0[4] Analog column mux input.
27 IO I, M P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
29 IO I, M P0[7] Analog column mux input.
30 IO I, M P0[5] Analog column mux input.
31 IO I, M P0[3] Analog column mux input, integrating input.
32 Power Vss Ground connection.
A = Analog, I = Input, O = Output, and M = Analog Mux Input.
LEGEND
Document Number: 38-12025 Rev. *O Page 12 of 45
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
56-Pin Part Pinout
SSOP
1
56 Vdd
2
AI, P0[7]
55
P0[6], AI
3
AI, P0[5]
54
P0[4], AI
4
AI, P0[3]
53
P0[2], AI
5
AI, P0[1]
52
P0[0], AI
6
P2[7]
51
P2[6]
7
P2[5]
50
P2[4]
8
P2[3]
49
P2[2]
9P2[1] 48
P2[0]
10
NC
47
NC
11
NC
46
NC
12NC 45 P3[2]
13
NC
44
P3[0]
14OCDE 43
CCLK
15
OCDO
42
HCLK
16
SMP
41
XRES
17
Vss
40
NC
18
Vss
39
NC
19
P3[3]
38
NC
20
P3[1]
37
NC
21
NC
36
NC
22
NC
35
NC
23I2C SCL, P1[7] 34
P1[6]
24
I2C SDA, P1[5]
33
P1[4], EXTCLK
25
NC
32
P1[2]
26
P1[3]
31
P1[0], I2C
SDA, SDATA
27
SCLK, I2C SCL, P1[1]
30 NC
28Vss
29
NC
Vss
The 56-pin SSOP part is for the CY8C21001 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Figure 12. CY8C21001 56-Pin PSoC Device
Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP)
Pin No.
Type
Digital Analog
Pin Name Description
1 Power Vss Ground connection.
2 IO I P0[7] Analog column mux input.
3 IO I P0[5] Analog column mux input and column output.
4 IO I P0[3] Analog column mux input and column output.
5 IO I P0[1] Analog column mux input.
6 IO P2[7]
7 IO P2[5]
8 IO I P2[3] Direct switched capacitor block input.
9 IO I P2[1] Direct switched capacitor block input.
10 NC No connection.
11 NC No connection.
12 NC No connection.
13 NC No connection.
14 OCD OCDE OCD even data IO.
15 OCD OCDO OCD odd data output.
16 Power SMP Switch Mode Pump (SMP) connection to required external components.
17 Power Vss Ground connection.
18 Power Vss Ground connection.
Document Number: 38-12025 Rev. *O Page 13 of 45
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP) (continued)
Pin No.
Type
Digital Analog
Pin Name Description
19 IO P3[3]
20 IO P3[1]
21 NC No connection.
22 NC No connection.
23 IO P1[7] I2C Serial Clock (SCL).
24 IO P1[5] I2C Serial Data (SDA).
25 NC No connection.
26 IO P1[3] I
27 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK
FMTEST
.
[3]
28 Power Vss Ground connection.
29 NC No connection.
30 NC No connection.
31 IO P1[0] Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA
32 IO P1[2] V
FMTEST
.
33 IO P1[4] Optional External Clock Input (EXTCLK).
34 IO P1[6]
35 NC No connection.
36 NC No connection.
37 NC No connection.
38 NC No connection.
39 NC No connection.
40 NC No connection.
41 Input XRES Active high external reset with internal pull down.
42 OCD HCLK OCD high-speed clock output.
43 OCD CCLK OCD CPU clock output.
44 IO P3[0]
45 IO P3[2]
46 NC No connection.
47 NC No connection.
48 IO I P2[0]
49 IO I P2[2]
50 IO P2[4]
51 IO P2[6]
52 IO I P0[0] Analog column mux input.
53 IO I P0[2] Analog column mux input and column output.
54 IO I P0[4] Analog column mux input and column output.
55 IO I P0[6] Analog column mux input.
56 Power Vdd Supply voltage.
..
[3]
..
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
Document Number: 38-12025 Rev. *O Page 14 of 45
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