CYPRESS CY 8C21234-24SXI Datasheet

PSoC® Mixed-Signal Array Final Data Sheet

CY8C21234, CY8C21334, CY8C21434, CY8C21534, and CY8C21634

Features

■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds to 24 MHz ❐ Low Power at High Speed ❐ 2.4V to 5.25V Operating Voltage ❐ Operating Voltages Down to 1.0V Using

On-Chip Switch Mode Pump (SMP)

❐ Industrial Temperature Range: -40°C to +85°C

■ Advanced Peripherals (PSoC Blocks)

❐ 4 Analog Type “E” PSoC Blocks Provide:

- 2 Comparators with DAC Refs

- Single or Dual 8-Bit 28 Channel ADC

❐ 4 Digital PSoC Blocks Provide:

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Full-Duplex UART, SPI™ Master or Slave

- Connectable to All GPIO Pins

❐ Complex Peripherals by Combining Blocks

■ Flexible On-Chip Memory

❐ 8K Flash Program Storage 50,00 0 Erase/Write

Cycles

❐ 512 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP™) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash

■ Complete Development Tools

❐ Free Development Software

(PSoC Designer™)

❐ Full-Featured, In-Circuit Emulator and

Programmer

❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Trace Memory

■ Precision, Programmable Clocking

❐ Internal ±2.5% 24/48 MHz Oscillator ❐ Internal Oscillator for Watchdog and Sleep

■ Programmable Pin Configurations

❐ 25 mA Drive on All GPIO ❐ Pull Up, Pull Down, High Z, Strong, or Open

Drain Drive Modes on All GPIO

❐ Up to 8 Analog Inputs on GPIO ❐ Configurable Interrupt on All GPIO

■ Versatile Analog Mux

❐ Common Internal Analog Bus ❐ Simultaneous Connection of IO Combinations ❐ Capacitive Sensing Application Capability

■ Additional System Resources

❐ I

C™ Master, Slave and Multi-Master to

400 kHz

❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Ref erence

PSoC® Functional Overview

The PSoC® family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to

replace multiple traditional MCU-based system components with one, low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, as well as programmable interconnect. This architecture allows the user to create customized peripheral configuration s, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts.

The PSoC architecture, as illustrated on the left, is comprised of four main areas: the Core, the System Resources, the Digital System, and the Analog System. Configurable global bus resources allow all the device resources to be combined into a complete custom system. Each CY8C21x34 PSoC device includes four digital blocks and four analog blocks. Depending on the PSoC package, up to 28 general purpose IO (GPIO) are also included. The GPIO provide access to the global digital and analog interconnects.

The PSoC Core

The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The

January 12, 2007 © Cypress Semiconductor Corp. 2004-2007 — Document No. 38-12025 Rev. *K 1

CY8C21x34 Final Data Sheet PSoC® Overview

CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor.

System Resources provide additional capability, such as digital clocks to increase the flexibility of the PSoC mixed-signal arrays, I2C functionality for implementing an I2C master, slave, MultiMaster, an internal voltage reference that provides an absolute value of 1.3V to a number of PSoC subsystems, a switch mode pump (SMP) that generates normal operating voltages off a single battery cell, and various system resets supported by the M8C.

The Digital System is composed of an array of digital PSoC blocks, which can be configured into any number of digital peripherals. The digital blocks can be connected to the GPIO through a series of global buses that can route any signal to any pin. Freeing designs from the constraints of a fixed peripheral controller.

The Analog System is composed of four analog PSoC blocks, supporting comparators and analog-to-digital conversion up to 8 bits in precision.

The Digital System

The Digital System is composed of 4 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below.

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 32 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity

■ SPI master and slave

■ I2C slave and multi-master

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller.

Digital System Block Diagram

Por t 3

Por t 2

i F

To System B us

Por t 1

Por t 0

To Analog

System

DIGITAL SYSTEM

Digital PSoC Block Array

Configuration

Row 0

DBB00 DBB01 DCB02 DCB03

Row Input

Configuration

GI E[7:0] GIO[7:0]

Global Digital Interconnect

GOE[7:0] GOO[7:0]

Row Output

The Analog System

The Analog System is composed of 4 configurable blocks, allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are listed below.

■ Analog-to-digital converters (single or dual, with 8-bit resolu-

tion)

■ Pin-to-pin comparator

■ Single-ended comparators (up to 2) with absolute (1.3V) ref-

erence or 8-bit DAC reference

■ 1.3V reference (as a System Resource)

In most PSoC devices, analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks. The CY8C21x34 devices provide limited functionality Type “E” analog blocks. Each column contains one CT Type E block and one SC Type E block. Refer to the PSoC Mixed-Signal Array Technical Reference Manual for detailed information on the CY8C21x34’s Type E analog blocks.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled “PSoC Device Charac-

teristics” on page 3.

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CY8C21x34 Final Data Sheet PSoC® Overview

Analog System Block Diagram

Ar r ay Inpu t

Configuration

ACI0[1:0] ACI1[1:0]

All IO

AC OL 1MU X

An al o g Mux Bus

Array

ACE00 ACE01

ASE10 ASE11

The Analog Multiplexer System

The Analog Mux Bus can connect to every GPIO pin. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array.

Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

■ Track pad, finger sensing.

■ Chip-wide mux that allows analog input from any IO pin.

■ Crosspoint connection between any IO pin combinations.

When designing capacitive sensing applications, refer to the signal-to-noise system level requirement found in Application Note AN2403 at http://www.cypress.com/design/AN2403 on the Cypress web site.

Additional System Resources

System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below.

■ Digital clock dividers provide three customizable clock fre-

quencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers.

■ The I2C module provides 100 and 400 kHz communication

over two wires. Slave, master, and multi-master modes are all supported.

■ Low Voltage Detection (LVD) interrupts can signal the appli-

cation of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3 voltage reference provides an absolute refer-

ence for the analog system, including ADCs and DACs.

■ An integrated switch mode pump (SMP) generates normal

operating voltages from a single 1.2V battery cell, providing a low cost boost converter.

■ Versatile analog multiplexer system.

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted below.

PSoC Device Characteristics

PSoC Part

Number

CY8C29x66

CY8C27x43 CY8C24x94 56 1 4 48 2 2 6 1K 16K CY8C24x23A

CY8C21x34

CY8C21x23

CY8C20x34

a. Limited analog functionality. b. Two analog blocks and one CapSense.

Digital

up to

16 1 4 8 0 2

up to

Rows

Digital

4 16 12 4 4 12 2K 32K

2 8 12 4 4 12

1 4 12 2 2 6

1 4 28 0 2

0 0 28 0 0

Inputs

Digital

Blocks

Analog

Outputs

Analog

Columns

Blocks

Analog

SRAM

256

Bytes

256

Bytes

512

Bytes

256

Bytes

512

Bytes

Size

Flash

16K

Size

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CY8C21x34 Final Data Sheet PSoC® Overview

Getting Started

The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual , which can be found on http://www.cypress.com/psoc.

For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com.

Development Kits

Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at

http://www.cypress.com, click the Online Store shopping cart

icon at the bottom of the web page, and click PSoC (Program- mable System-on-Chip) to view a current list of available items.

Technical Training Modules

Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http://

www.cypress.com/techtrain.

Development Tools

PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)

PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs.

PSoC Designer also supports a high-level C language compi ler developed specifically for the devices in the family.

PSoC Designer Subsystems

Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants.

Technical Support

PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.

Application Notes

A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, g o to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are sorted by date by default.

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CY8C21x34 Final Data Sheet PSoC® Overview

PSoC Designer Software Subsystems

Device Editor

The device editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time.

PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print o ut a con figuration sh eet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It’s also possible to change the selected components and regenerate the framework.

Design Browser

The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader.

Application Editor

In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build.

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compiler. A C language compiler is available that supports the PSoC family of devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices.

The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

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CY8C21x34 Final Data Sheet PSoC® Overview

Designing with User Modules

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements.

To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections.

Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed.

The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module.

The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.

User Module and Source Code Development Flows

Device Editor

User

Module

Se lection

Placement

and

Parameter

-ization

Source

Code

Generator

G e n e rate A p p licatio n

Application Editor

Project

Manager

Source

Code

Editor

Build

Manager

Build All

Debugger

Interface

to ICE

Storage

Inspector

The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all file dependencies and run the compiler and asse mbler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming.

The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger d ownloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.

Event &

Breakpoint

Manager

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CY8C21x34 Final Data Sheet PSoC® Overview

Document Conventions

Acronyms Used

The following table lists the acronyms that are used in this document.

Acronym Description

AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT continuous time DAC digital-to-analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programma ble read-only memory FSR full scale range GPIO general purpose IO GUI graphical user interface HBM human body model ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input/output IPOR imprecise power on reset LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoC® Programmable System-on-Chip™ PWM pulse width modulator SC switched capacito r SLIMO slow IMO SMP switch mode pump SRAM static random access memory

Units of Measure

A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 17 lists all the abbreviations used to measure the PSoC devices.

Numeric Naming

Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.

For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed-Signal Array Technical Refer- ence Manual on http://www.cypress.com. This document is organized into the following chapters and sections.

1. Pin Information ........................................................................................ 8

1.1 Pinouts ................... .......................................................... .............. 8

1.1.1 16-Pin Part Pinout .......................................................... 8

1.1.2 20-Pin Part Pinout .......................................................... 9

1.1.3 28-Pin Part Pinout ........................................................ 10

1.1.4 32-Pin Part Pinout ........................................................ 11

1.1.5 56-Pin Part Pinout ......................................................... 12

2. Regis ter Refe rence .......................... ... ............................... ... .. ... ............ 14

2.1 Register Conventions ................................................................... 14

2.2 Register Mapping Tables .............................................................14

3. Elect ric a l Specifications ............ ... .. ................................ .. .................... 17

3.1 Absolute Maximum Ratings ......................................................... 18

3.2 Operating Temperature ................................................................ 18

3.3 DC Electrical Characteristics ........................................................ 18

3.3.1 DC Chip-Level Specifications ........................................ 18

3.3.2 DC General Purpose IO Specification s ......................... 19

3.3.3 DC Operational Amplifier Specifications ....................... 20

3.3.4 DC Low Power Comparator Specifications ................... 20

3.3.5 DC Switch Mode Pump Specifications .......................... 21

3.3.6 DC Analog Mux Bus Specifications ............................... 22

3.3.7 DC POR and LVD Specifications .................................. 22

3.3.8 DC Programming Specifications ................................... 23

3.4 AC Electrical Characteristics ............... ... .. ... ................................. 24

3.4.1 AC Chip-Level Specifications ........................................ 24

3.4.2 AC General Purpose IO Specifications .........................26

3.4.3 AC Operational Amplifier Specifications ........................ 27

3.4.4 AC Low Power Comparator Specifications .. .. ... ............ 27

3.4.5 AC Analog Mux Bus Specifications ............................... 27

3.4.6 AC Digital Block Specifications ....... .............................. 27

3.4.7 AC External Clock Specifications .................................. 29

3.4.8 AC Programming Specifications ... ... .............................. 30

3.4.9 AC I2C Specifications ........... ... .. ... ................................. 31

4. Packaging Information .......................................................................... 32

4.1 Packaging Dimensions ...... ... .. ................................ .. ... .. ............... 32

4.2 Thermal Impedances .................................................................. 36

4.3 Solder Reflow Peak Temperature .......................... .. ... ................. 36

5. Development Tool Selection ................................................................ 37

5.1 Software ................. .......................................... ............................ 37

5.1.1 PSoC Designer............................................................... 37

5.1.2 PSoC Express‰ ........................................................... 37

5.1.3 PSoC Programmer ........................................................ 37

5.1.4 CY3202-C iMAGEcraft C Compiler ...............................37

5.2 Development Kits ......................................................................... 37

5.2.1 CY3215-DK Basic Development Kit ..............................37

5.2.2 CY3210-ExpressDK Development Kit ...........................38

5.3 Evaluation Tools ........................................................................... 38

5.3.1 CY3210-MiniProg1 ........................................................ 38

5.3.2 CY3210-PSoCEval1 ...................................................... 38

5.3.3 CY3214-PSoCEvalUSB ................................................38

5.4 Device Programmers ................................................................... 38

5.4.1 CY3216 Modular Programmer ......................................38

5.4.2 CY3207ISSP In-System Programmer ...........................38

5.5 Accessories (Emulation and Progra m m in g) ........ ......................... 39

5.6 3rd-Party Tools .......... ... ............................... ... .. ............................ 39

5.7 Build a PSoC Emulator into Your Board ...................................... 39

6. Order ing Inf ormation ............................................................................ 40

6.1 Ordering Code Definitions ............................................................ 40

7. Sales and Service Information ............................................................. 41

7.1 Revision History ........................................................................... 41

7.2 Copyrights and Code Protection ..................................................42

January 12, 2007 Document No. 38-12025 Rev. *K 7

1. Pin Information

This chapter describes, lists, and illustrates the CY8C21x3 4 PSoC device pins and pinout configurations.

1.1 Pinouts

The CY8C21x34 PSoC device is available in a variety of packages which are listed and illustrated in the foll owing tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.

1.1.1 16-Pin Part Pinout

T able 1-1. 16-Pin Part Pinout (SOIC)

Pin No.

1 IO I, M P0[7] Analog column mux input. 2 IO I, M P0[5] Analog column mux input. 3 IO I, M P0[3] Analog column mux input, integrating

4 IO I, M P0[1] Analog column mux input, integrating

5 Power SMP Switch Mode Pump (SMP) connection to

6 Power Vss Ground connection. 7 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK*. 8 Power Vss Ground connection.

9 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA*. 10 IO M P1[2] 11 IO M P1[4] Optional External Clock Input (EXTCLK). 12 IO I, M P0[0] Analog column mux input. 13 IO I, M P0[2] Analog column mux input. 14 IO I, M P0[4] Analog column mux input. 15 IO I, M P0[6] Analog column mux input. 16 Power Vdd Supply voltage.

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset).

See the PSoC Mixed-Signal Array Technical Reference Manual for details.

Type

Digital Analog

Name Description

input.

required external components.

CY8C21234 16-Pin PSoC Device

A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1]

M, I2C SCL, P1[1]

SMP

Vss

1 2 3 4

SOIC

5 6 7 8

16 15 14 13 12 11 10

Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P1[4], EXTCLK, M P1[2], M P1[0], I2C SDA, M

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CY8C21x34 Final Data Sheet 1. Pin Information

1.1.2 20-Pin Part Pinout

T a ble 1-2. 20-Pin Part Pinout (SSOP)

Pin No.

1 IO I, M P0[7] Analog column mux input. 2 IO I, M P0[5] Analog column mux input. 3 IO I, M P0[3] Analog column mux input, integrating

4 IO I, M P0[1] Analog column mux input, integrating

5 Power Vss Ground connection. 6 IO M P1[7] I2C Serial Clock (SCL). 7 IO M P1[5] I2C Serial Data (SDA). 8 IO M P1[3]

9 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK*. 10 Power Vss Ground connection. 11 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA*. 12 IO M P1[2] 13 IO M P1[4] Optional External Clock Input (EXT-

14 IO M P1[6] 15 Input XRES Active high external reset with internal

16 IO I, M P0[0] Analog column mux input. 17 IO I, M P0[2] Analog column mux input. 18 IO I, M P0[4] Analog column mux input. 19 IO I, M P0[6] Analog column mux input. 20 Power Vdd Supply voltage.

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset).

See the PSoC Mixed-Signal Array Technical Reference Manual for details.

Type

Digital Analog

Name Description

input.

CLK).

pull down.

CY8C21334 20-Pin PSoC Device

A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1]

M, I2C SCL, P1[7]

SDA, P1[5]

M, I2C

M, P1[3]

M, I2C

SCL, P1[1]

Vss

1 2 3 4 5 6 7 8 9

SSOP

20 19 18 17 16 15 14 13 12 11

Vdd P0[6], A, I, M

P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M

XRES

P1[6], M P1[4], EXTCLK, M P1[2], M

P1[0], I2C SDA, M

January 12, 2007 Document No. 38-12025 Rev. *K 9

CY8C21x34 Final Data Sheet 1. Pin Information

1.1.3 28-Pin Part Pinout

T a ble 1-3. 28-Pin Part Pinout (SSOP)

Pin No.

1 IO I, M P0[7] Analog column mux input. 2 IO I, M P0[5] Analog column mux input and column

3 IO I, M P0[3] Analog column mux input and column

4 IO I, M P0[1] Analog column mux input, integrating

5 IO M P2[7] 6 IO M P2[5] 7 IO I, M P2[3] Direct switched capacitor block input. 8 IO I, M P2[1] Direct switched capacitor block input.

9 Power Vss Ground connection. 10 IO M P1[7] I2C Serial Clock (SCL). 11 IO M P1[5] I2C Serial Data (SDA). 12 IO M P1[3] 13 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK*. 14 Power Vss Ground connection. 15 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA*. 16 IO M P1[2] 17 IO M P1[4] Optional External Clock Input (EXT-

18 IO M P1[6] 19 Input XRES Active high external reset with internal

20 IO I, M P2[0] Direct switched capacitor block input. 21 IO I, M P2[2] Direct switched capacitor block input. 22 IO M P2[4] 23 IO M P2[6] 24 IO I, M P0[0] Analog column mux input. 25 IO I, M P0[2] Analog column mux input. 26 IO I, M P0[4] Analog column mux input 27 IO I, M P0[6] Analog column mux input. 28 Power Vdd Supply voltag e.

LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset).

See the PSoC Mixed-Signal Array Technical Reference Manual for details.

Type

Digital Analog

Name Description

output.

output, integrating input.

input.

CLK).

pull down.

CY8C21534 28-Pin PSoC Device

A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1]

M, P2[7] M, P2[5]

M, P2[3]

M, P2[1]

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

M, P1[3]

M, I2C SCL, P1[1]

Vss

10 11 12 13 14

1 2 3 4 5 6 7 8 9

SSOP

28 27 26 25 24 23 22 21 20 19 18 17 16 15

Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M XRES P1[6], M P1[4], EXTCLK, M P1[2], M P1[0], I2C SDA, M

January 12, 2007 Document No. 38-12025 Rev. *K 10

CY8C21x34 Final Data Sheet 1. Pin Information

1.1.4 32-Pin Part Pinout

Table 1-4. 32-Pin Part Pinout (QFN**)

Pin No.

1 IO I, M P0[1] A nalog column mux input, integrating

2 IO MP2[7] 3 IO MP2[5] 4 IO M P2[3] 5 IO M P2[1] 6 IO M P3[3] In CY8C21434 part. 6 Power SMP Switch Mode Pump (SMP) connection to

7 IO M P3[1] In CY8C21434 part. 7 Power Vss Ground connection in CY8C21634 part. 8 IO M P1[7] I2C Serial Clock (SCL).

9 IO M P1[5] I2C Serial Data (SDA). 10 IO M P1[3] 11 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK*. 12 Power Vss Ground connection. 13 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA*. 14 IO M P1[2] 15 IO M P1[4] Optional External Clock Input (EXTCLK). 16 IO M P1[6]

Type

Digital Analog

Name Description

input.

required external components in CY8C21634 part.

CY8C21434 32-Pin PSoC Device

17 Input XRES Active high external reset with internal

18 IO MP3[0] 19 IO MP3[2] 20 IO M P2[0] 21 IO M P2[2] 22 IO M P2[4] 23 IO M P2[6] 24 IO I, M P0[0] Analog column mux input. 25 IO I, M P0[2] Analog column mux input. 26 IO I, M P0[4] Analog column mux input. 27 IO I, M P0[6] Analog column mux input. 28 Power Vdd Supply voltage. 29 IO I, M P0[7] Analog column mux input. 30 IO I, M P0[5] Analog column mux input. 31 IO I, M P0[3] Analog column mux input, integrating

32 Power Vss Ground connection.

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset).

See the PSoC Mixed-Signal Array Technical Reference Manual for details. ** The center pad on the QFN p acka ge sho uld be con nect ed to grou nd ( Vss)

for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not co nnected to any other signal.

pull down.

input.

CY8C21634 32-Pin PSoC Device

January 12, 2007 Document No. 38-12025 Rev. *K 11

CY8C21x34 Final Data Sheet 1. Pin Information

1.1.5 56-Pin Part Pinout

The 56-pin SSOP part is for the CY8C21001 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production. T a ble 1-5. 56-Pin Part Pinout (SSOP)

Pin No.

Type

Digital Analog

Name

Description

1 Power Vss Ground connection. 2 IO I P0[7] Analog column mux input. 3 IO I P0[5] Analog column mux input and column output. 4 IO I P0[3] Analog column mux input and column output. 5 IO I P0[1] Analog column mux input. 6 IO P2[7] 7 IO P2[5] 8 IO I P2[3] Direct switched capacitor block input. 9 IO I P2[1] Direct switched capacitor block input. 10 NC No connection. 11 NC No connection.. 12 NC No connection. 13 NC No connection.. 14 OCD OCDE OCD even data IO. 15 OCD OCDO OCD odd data output. 16 Power SMP Switch Mode Pump (SMP) connection to

required external components. 17 Power Vss Ground connection. 18 Power Vss Ground connection. 19 IO P3[3] 20 IO P3[1]

21 NC No connection. 22 NC No connection..

23 IO P1[7] I2C Serial Clock (SCL). 24 IO P1[5] I2C Serial Data (SDA). 25 NC No connection. 26 IO P1[3] I

27 IO P1[1] Crystal Input (XTALin), I2C Serial Clock

FMTEST

(SCL), ISSP-SCLK*. 28 Power Vss Ground connection. 29 NC No connection. 30 NC No connection.. 31 IO P1[0] Crystal Output (XTALout), I2C Serial Data

32 IO P1[2] V

(SDA), ISSP-SDATA*.

FMTEST

33 IO P1[4] Optional External Clock Input (EXTCLK). 34 IO P1[6] 35 NC No connection.. 36 NC No connection. 37 NC No connection.. 38 NC No connection. 39 NC No connection.. 40 NC No connection.. 41 Input XRES Active high external reset with internal pull

down. 42 OCD HCLK OCD high-speed clock output. 43 OCD CCLK OCD CPU clock output. 44 IO P3[0] 45 IO P3[2] 46 NC No connection. 47 NC No connection..

CY8C21001 56-Pin PSoC Device

Vss

1 AI, P0[7] AI, P0[5] AI, P0[3] AI, P0[1]

OCDO

I2C SDA, P1[5]

SCLK, I2C SCL, P1[1]

P2[7]

P2[5]

P2[3]

9P2[1] 48

NC NC

11 12NC 45 P3[2] 13

14OCDE 43

SSOP

15 16

SMP

Vss Vss

P3[3]

P3[1]

22 23I2C SCL, P1[7] 34

P1[3]

26 27 28Vss

Not for Production

56 Vdd 55

P0[6], AI P0[4], AI

P0[2], AI

P0[0], AI

P2[6]

P2[4]

P2[2]

P2[0] NC

P3[0]

CCLK HCLK

XRES

P1[6] P1[4], EXTCLK

P1[2]

P1[0], I2C

31 30 NC

SDA, SDATA

January 12, 2007 Document No. 38-12025 Rev. *K 12

CY8C21x34 Final Data Sheet 1. Pin Information

T a ble 1-5. 56-Pin Part Pinout (SSOP)

48 IO IP2[0] 49 IO IP2[2] 50 IO P2[4] 51 IO P2[6] 52 IO I P0[0] Analog column mux input. 53 IO I P0[2] Analog column mux input and column output. 54 IO I P0[4] Analog column mux input and column output. 55 IO I P0[6] Analog column mux input. 56 Power Vdd Supply voltage.

LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.

January 12, 2007 Document No. 38-12025 Rev. *K 13

2. Register Reference

This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, reference the PSoC Mixed-Signal Array Technical Reference Manual.

2.1 Register Conventions

The register conventions specific to this section are listed in the following table.

Convention Description

R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific

2.2 Register Mapping Tables

The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are Reserved and should not be accessed.

January 12, 2007 Document No. 38-12025 Rev. *K 14

CY8C21x34 Final Data Sheet 2. Register Reference

Access

Name

PRT0DR 00 RW 40 ASE10CR0 80 RW C0 PRT0IE 01 RW 41 81 C1 PRT0GS 02 RW 42 82 C2 PRT0DM2 03 RW 43 83 C3 PRT1DR 04 RW 44 ASE11CR0 84 RW C4 PRT1IE 05 RW 45 85 C5 PRT1GS 06 RW 46 86 C6 PRT1DM2 07 RW 47 87 C7 PRT2DR 08 RW 48 88 C8 PRT2IE 09 RW 49 89 C9 PRT2GS 0A RW 4A 8A CA PRT2DM2 0B RW 4B 8B CB PRT3DR 0C RW 4C 8C CC PRT3IE 0D RW 4D 8D CD PRT3GS 0E RW 4E 8E CE PRT3DM2 0F RW 4F 8F CF

DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W AMUXCFG 61 RW A1 INT_MSK1 E1 RW DBB00DR2 22 RW PWM_CR 62 RW A2 INT_VC E2 RC DBB00CR0 23 # 63 A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 E4 DBB01DR1 25 W 65 A5 E5 DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # DCB02DR0 28 # DCB02DR1 29 W DCB02DR2 2A RW DCB02CR0 2B # 6B AB EB DCB03DR0 2C # TMP_DR0 6C RW AC EC DCB03DR1 2D W TMP_DR1 6D RW AD ED DCB03DR2 2E RW TMP_DR2 6E RW AE EE DCB03CR0 2F # TMP_DR3 6F RW AF EF

Blank fields are Reserved and should not be accessed. # Access is bit specific.

(0,Hex)

Addr

10 50 90 CUR_PP D0 RW 11 51 91 STK_PP D1 RW 12 52 92 D2 13 53 93 IDX_PP D3 RW 14 54 94 MVR_PP D4 RW 15 55 95 MVW_PP D5 RW 16 56 96 I2C_CFG D6 RW 17 57 97 I2C_SCR D7 # 18 58 98 I2C_DR D8 RW 19 59 99 I2C_MSCR D9 # 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C DC 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F DF

30 70 RDI0RI B0 RW F0 31 71 RDI0SYN B1 RW F1 32 ACE00CR1 72 RW RDI0IS B2 RW F2 33 ACE00CR2 73 RW RDI0LT0 B3 RW F3 34 74 RDI0LT1 B4 RW F4 35 75 RDI0RO0 B5 RW F5 36 ACE01CR1 76 RW RDI0RO1 B6 RW F6 37 ACE01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD DAC_D FD RW 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF #

Name

67 ADC0_CR 68 ADC1_CR 69

Access

(0,Hex)

Addr

# A8 E8 # A9 E9

Name

A7 DEC_CR1 E7 RW

AA EA

Access

(0,Hex)

Addr

Access

Name

(0,Hex)

Addr

January 12, 2007 Document No. 38-12025 Rev. *K 15

CY8C21x34 Final Data Sheet 2. Register Reference

Access

Name

PRT0DM0 00 RW 40 ASE10CR0 80 RW C0 PRT0DM1 01 RW 41 81 C1 PRT0IC0 02 RW 42 82 C2 PRT0IC1 03 RW 43 83 C3 PRT1DM0 04 RW 44 ASE11CR0 84 RW C4 PRT1DM1 05 RW 45 85 C5 PRT1IC0 06 RW 46 86 C6 PRT1IC1 07 RW 47 87 C7 PRT2DM0 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 PRT2IC0 0A RW 4A 8A CA PRT2IC1 0B RW 4B 8B CB PRT3DM0 0C RW 4C 8C CC PRT3DM1 0D RW 4D 8D CD PRT3IC0 0E RW 4E 8E CE PRT3IC1 0F RW 4F 8F CF

DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

DBB01FN 24 RW CMP_GO_EN 64 RW A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 ADC0_TR E5 RW DBB01OU 26 RW AMD_CR1 66 RW A6 ADC1_TR E6 RW

DCB02FN 28 RW 68 A8 IMO_TR E8 W DCB02IN 29 RW 69 A9 ILO_TR E9 W DCB02OU 2A RW 6A AA BDG_TR EA RW

DCB03FN 2C RW TMP_DR0 6C RW AC EC DCB03IN 2D RW TMP_DR1 6D RW AD ED DCB03OU 2E RW TMP_DR2 6E RW AE EE

Blank fields are Reserved and should not be accessed. # Access is bit specific.

(1,Hex)

Addr

10 50 90 GDI_O_IN D0 RW 11 51 91 GDI_E_IN D1 RW 12 52 92 GDI_O_OU D2 RW 13 53 93 GDI_E_OU D3 RW 14 54 94 D4 15 55 95 D5 16 56 96 D6 17 57 97 D7 18 58 98 MUX_CR0 D8 RW 19 59 99 MUX_CR1 D9 RW 1A 5A 9A MUX_CR2 DA RW 1B 5B 9B MUX_CR3 DB RW 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW

23 AMD_CR0 63 RW A3 VLT_CR E3 RW

27 ALT_CR0 67 RW A7 E7

2B CLK_CR3 6B RW AB ECO_TR EB W

2F TMP_DR3 6F RW AF EF 30 70 RDI0RI B0 RW F0 31 71 RDI0SYN B1 RW F1 32 ACE00CR1 72 RW RDI0IS B2 RW F2 33 ACE00CR2 73 RW RDI0LT0 B3 RW F3 34 74 RDI0LT1 B4 RW F4 35 75 RDI0RO0 B5 RW F5 36 ACE01CR1 76 RW RDI0RO1 B6 RW F6 37 ACE01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FLS_PR1 FA RW 3B 7B BB FB 3C 7C BC FC 3D 7D BD DAC_CR FD RW 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF #

Name

(1,Hex)

Addr

Access

Name

(1,Hex)

Addr

Name

(1,Hex)

Addr

Access

January 12, 2007 Document No. 38-12025 Rev. *K 16

3. Electrical S pecifications

This chapter presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For the most up to date el ectrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC as specified, except where noted. Refer to Table 3-15 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.

Figure 3-1a. Voltage versus CPU Frequency Figure 3-1b. IMO Frequency Trim Options

5.25

4.75

Vdd V oltage

3.00

2.40

93 kHz 12 MHz 24 MHz

3 MHz

CPU Frequency

5.25

4.75

Vdd V oltage

3.60

3.00

2.40

93 kHz 12 MHz 24 MHz

The following table lists the units of measure that are used in this chapter.

Table 3-1: Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

dB decibels mA milli-ampere

fF femto farad ms milli-second Hz hertz mV milli-volts KB 1024 bytes nA nanoampere

Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts

kΩ kilohm Ω ohm

MHz megahertz pA picoampere

MΩ megaohm pF picofarad

µA microampere pp peak-to-peak µF microfarad ppm parts per million µH microhenry ps picosecond µs microsecond sps samples per second µV microvolts σ sigma: one standard deviation

µVrms microvolts root-mean-square V volts

degree Celsius µW microwatts

SLIMO

Mode=1

SLIMO Mode = 0

SLIMO

Mode=1

SLIMO

Mode=1

IMO Freque ncy

Mode=1

6 MHz

SLIMO

Mode=0

SLIMO

Mode=0

SLIMO

January 12, 2007 Document No. 38-12025 Rev. *K 17

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.1 Absolute Maximum Ratings

T able 3-2. Absolute Maximum Ratings

Symbol Description Min Typ Max Units Notes

STG

Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V V

IOZ

MIO

ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD. LU Latch-up Current – – 200 mA

Storage Temperature -55 25 +100

Ambient Temperature with Power Applied -40 – +85

DC Input Voltage Vss - 0.5 – Vdd + 0.5 V DC Voltage Applied to Tri-state Vss - 0.5 – Vdd + 0.5 V Maximum Current into any Port Pin -25 – +50 mA

Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25 age temperatures above 65 reliability.

C ± 25oC. Extended duration stor-

C will degrade

3.2 Operating Temperature

T able 3-3. Operating Temperature

Symbol Description Min Typ Max Units Notes

Ambient Temperature -40 – +85 Junction Temperature -40 – +100

The temperature rise from ambient to junction is package specific. See “Thermal Impedances”

on page 36. The user must limit the power con-

sumption to comply with this requirement.

3.3 DC Electrical Characteristics

3.3.1 DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

T able 3-4. DC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

Vdd Supply Voltage 2.40 – 5.25 V See t able titled “DC POR and LVD Specifica-

DD3

DD27

SB27

REF

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters

tions” on page22.

Supply Current, IMO = 24 MHz – 3 4 mA

Supply Current, IMO = 6 MHz using SLIMO mode. – 1.2 2 mA

Supply Current, IMO = 6 MHz using SLIMO mode. – 1.1 1.5 mA

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Mid temperature range.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active.

Reference Voltage (Bandgap) 1.28 1.30 1.32 V Trimmed for appropriate Vd d. Vdd = 3.0V to

– 2.6 4. µA

– 2.8 5 µA

Conditions are Vdd = 5.0V, TA = 25oC, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 =

93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25oC, CPU = 3

MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz.

Conditions are Vdd = 2.55V , TA = 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz.

Vdd = 2.55V, 0oC ≤ TA ≤ 40oC.

Vdd = 3.3V, -40oC ≤ TA ≤ 85oC.

5.25V.

January 12, 2007 Document No. 38-12025 Rev. *K 18

CY8C21x34 Final Data Sheet 3. Electrical Specifications

T able 3-4. DC Chip-Level Specifications (continued)

Symbol Description Min Typ Max Units Notes

REF27

AGND Analog Ground V

Reference Voltage (Bandgap) 1.16 1.30 1.33 V Trimmed for appropriate Vd d. Vdd = 2.4V to

REF

- 0.003

REF

+ 0.003

3.0V.

3.3.2 DC General Purpose IO Specifications

The following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 3-5. 5V and 3.3V DC GPIO Specifications

Symbol Description Min Typ Max Units Notes

OUT

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters

Pull-up Resistor 4 5.6 8 kΩ Pull-down Resistor 4 5.6 8 kΩ High Output Level Vdd - 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,

Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])).

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])). Input Low Level – – 0.8 V Vdd = 3.0 to 5.25. Input High Level 2.1 – V Vdd = 3.0 to 5.25. Input Hysteresis – 60 – mV Input Leakage (Absolute V alue) – 1 – nA Gross tested to 1 µA. Capacitive Load on Pins as Input – 3.5 10 pF Capacitive Load on Pins as Output – 3.5 10 pF

Package and pin dependent. Temp = 25oC.

T able 3-6. 2.7V DC GPIO Specifications

Symbol Description Min Typ Max Units Notes

OUT

Pull-up Resistor 4 5.6 8 kΩ Pull-down Resistor 4 5.6 8 kΩ High Output Level Vdd - 0.4 – – V IOH = 2.5 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16

mA maximum, 50 mA Typ combined IOH bud-

get). Low Output Level – – 0.75 V IOL = 10 mA, Vdd = 2.4 to 3.0V (90 mA maxi-

mum combined IOL budget). Input Low Level – – 0.75 V Vdd = 2.4 to 3.0. Input High Level 2.0 – – V Vdd = 2.4 to 3.0. Input Hysteresis – 90 – mV Input Leakage (Absolute V alue) – 1 – nA Gross tested to 1 µA. Capacitive Load on Pins as Input – 3.5 10 pF Capacitive Load on Pins as Output – 3.5 10 pF

Package and pin dependent. Temp = 25oC.

January 12, 2007 Document No. 38-12025 Rev. *K 19

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.3.3 DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-7. 5V DC Operation al Amp lifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV I

EBOA

INOA

CMOA

OSOA

Input Offset Voltage (absolute value) – 2.5 15 mV Average Input Offset Voltage Drift – 10 –

Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 µA. Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF

µV/

Package and pin dependent. Temp = 25

Common Mode Voltage Range 0.0 – Vdd - 1 V

OLOA

SOA

a. Atypical behavior: I

Open Loop Gain – 80 – dB Amplifier Supply Current – 10 30 µA

of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.

EBOA

T able 3-8. 3.3V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV

OSOA

EBOA

INOA

CMOA

OLOA

SOA

a. Atypical behavior: I

Input Offset Voltage (absolute value) – 2.5 15 mV Average Input Offset Voltage Drift – 10 –

Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 µA. Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF

µV/

Package and pin dependent. Temp = 25 Common Mode Voltage Range 0 – Vdd - 1 V Open Loop Gain – 80 – dB Amplifier Supply Current – 10 30 µA

of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.

EBOA

T able 3-9. 2.7V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV

OSOA

EBOA

INOA

CMOA

OLOA

SOA

a. Atypical behavior: I

Input Offset Voltage (absolute value) – 2.5 15 mV Average Input Offset Voltage Drift – 10 –

Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 µA. Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF

µV/

Package and pin dependent. Temp = 25 Common Mode Voltage Range 0 – Vdd - 1 V Open Loop Gain – 80 – dB Amplifier Supply Current – 10 30 µA

of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.

EBOA

3.3.4 DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T apply to 5V at 25°C and are for design guidance only.

Table 3-10. DC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

REFLPC

SLPC

OSLPC

January 12, 2007 Document No. 38-12025 Rev. *K 20

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters

Low power comparator (LPC) reference voltage range 0.2 – Vdd - 1 V LPC supply current – 10 40 µA LPC voltage offset – 2.5 30 mV

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.3.5 DC Switch Mode Pump Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

T able 3-11. DC Switch Mode Pump (SMP) Specifications

Symbol Description Min Typ Max Units Notes

PUMP5V

PUMP3V

PUMP2V

PUMP

BAT5V

BAT3V

BAT2V

BATSTART

∆V

PUMP_Line

∆V

PUMP_Load

∆V

PUMP_Ripple

PUMP

5V Output Voltage from Pump 4.75 5.0 5.25 V

3.3V Output Volt age from Pump 3.00 3.25 3.60 V

2.6V Output Volt age from Pump 2.45 2.55 2.80 V

Available Output Current V

BAT

= 1.8V, V = 1.5V, V = 1.3V, V

PUMP PUMP PUMP

= 5.0V = 3.25V = 2.55V

Input Voltage Range from Battery 1.8 – 5.0 V

Input Voltage Range from Battery 1.0 – 3.3 V

Input Voltage Range from Battery 1.0 – 2.8 V

Minimum Input Voltage f rom Battery to Start Pump 1.2 – – V

Line Regulation (over Vi range) – 5 – %V

Load Regulation – 5 – %V

Output Voltage Rippl e (depends on cap/load) – 100 – mVpp Efficiency 35 50 – %

Efficiency 35 80 – % For I load = 1mA, V

Switching Frequency – 1.3 – MHz Switching Duty Cycle – 50 – %

a. L1 = 2 µH inductor, C1 = 10 µF capacitor, D1 = Schottky diode. See Figure3-2.

Configuration of footnote. ripple. SMP trip voltage is set to 5.0V.

Configuration of footnote. ripple. SMP trip voltage is set to 3.25V.

Configuration of footnote. ripple. SMP trip voltage is set to 2.55V.

Configuration of footnote. 5 8 8

– – –

mA mA mA

SMP trip voltage is set to 5.0V.

SMP trip voltage is set to 3.25V.

SMP trip voltage is set to 2.55V.

Configuration of footnote.

set to 5.0V.

Configuration of footnote.

set to 3.25V.

Configuration of footnote.

set to 2.55V.

Configuration of footnote.

1.25V at TA = -40oC.

Configuration of footnote.a VO is the “Vdd V alue

for PUMP Trip” specified by the VM[2:0] setting

in the DC POR and LVD Specification, Table 3-

13 on page 22.

Configuration of footnote.a VO is the “Vdd V alue

for PUMP Trip” specified by the VM[2:0] setting

in the DC POR and LVD Specification, Table 3-

13 on page 22.

Configuration of footnote.

trip voltage is set to 3.25V.

10 uH inductor, 1 uF capacito r, and Schottky

diode.

Average, neglecting

SMP trip voltage is

a 0o

C ≤ TA ≤ 100.

Load is 5 mA.

Load is 5 mA. SMP

= 2.55V, V

PUMP

BAT

= 1.3V,

Figure 3-2. Basic Switch Mode Pump Circuit

Vdd

BAT

Battery

SMP

PSoC

PUMP

Vss

January 12, 2007 Document No. 38-12025 Rev. *K 21

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.3.6 DC Analog Mux Bus Specifications

Table 3-12. DC Analog Mux Bus Specifications

Symbol Description Min Typ Max Units Notes

VDD

Switch Resistance to Common Analog Bus – – 400

800

Resistance of Initialization Switch to Vdd – – 800 Ω

Ω Ω

Vdd ≥ 2.7V

2.4V ≤ Vdd ≤ 2.7V

3.3.7 DC POR and LVD Specifications

Table 3-13. DC POR and LVD Specifications

Symbol Description Min Typ Max Units Notes

PPOR0

PPOR1

PPOR2

Vdd Value for PPOR Trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

Vdd Value for LVD Trip V V V V V V V V

LVD0 LVD1 LVD2 LVD3 LVD4 LVD5 LVD6 LVD7

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

Vdd Value for PUMP Trip V

PUMP0

PUMP1

PUMP2

PUMP3

PUMP4

PUMP5

PUMP6

PUMP7

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

a. Always greater than 50 mV above V b. Always greater than 50 mV above V c. Always greater than 50 mV above V d. Always greater than 50 mV above

(PORLEV = 00) for falling supply.

PPOR

(PORLEV = 01) for falling supply.

PPOR

LVD0

LVD3

–

2.40

2.85

2.95

3.06

4.37

4.50

4.62

4.71

2.45

2.96

3.03

3.18

4.54

4.62

4.71

4.89

2.36

2.82

4.55

2.45

2.92

3.02

3.13

4.48

4.64

4.73

4.81

2.55

3.02

3.10

3.25

4.64

4.73

4.82

5.00

2.40

2.95

4.70

2.51

2.99

3.09

3.20

4.55

4.75

4.83

4.95

2.62

3.09

3.16

3.32

4.74

4.83

4.92

5.12

V V V

V V V V V V V

V V V

V V V V V

Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog.

January 12, 2007 Document No. 38-12025 Rev. *K 22

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.3.8 DC Programming Specifications

T able 3-14. DC Programming Specifications

Symbol Description Min Typ Max Units Notes

Vdd

IWRITE

DDP

ILP

IHP

ILP

IHP

OLV

OHV

Flash Flash Flash

a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of

Supply Voltage for Flash Write Operations 2.70 – – V

Supply Current During Programming or Verif y – 5 25 mA

Input Low Voltage Durin g Programming or Verify – – 0.8 V

Input High Voltage During Programming or Verify 2.2 – – V

Input Current when Applying Vilp to P1[0] or P1[1] During

Programming or Verify

Input Current when Applying Vihp to P1[0] or P1[1] During

Programming or Verify

Output Low Voltage During Programming or Verify – – Vss + 0.75 V

Output High Voltage During Programming or Verify Vdd - 1.0 – Vdd V

Flash Endurance (per block) 50,000 – – – Erase/write cycles per block.

ENPB

Flash Endurance (total)

ENT

Flash Data Retention 10 – – Years

25,000 maximum cycles each, or 36x4 blocks of 1 2,5 00 maximum c ycl es each (t o limit t he tot al number of cycles to 3 6x50 ,000 an d that no sing le block ever see s mo re th an 50,000 cycles).

For the full industrial range, the user must em ploy a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

– – 0.2 mA Driving internal pull-down resistor.

– – 1.5 mA Driving internal pull-down resistor.

1,800,000 – – – Erase/write cycles.

January 12, 2007 Document No. 38-12025 Rev. *K 23

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.4 AC Electrical Characteristics

3.4.1 AC Chip-Level Specifications

The following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-15. 5V and 3.3V AC Chip-Level Specification s

Symbol Description Min Typ Max Units Notes

IMO24

IMO6

CPU1

CPU2

BLK5

BLK33

32K1

Jitter32k 32 kHz RMS Period Jitter – 100 200 ns Jitter32k 32 kHz Peak-to-Peak Period Jitter – 1400 – T

XRST

DC24M 24 MHz Duty Cycle 40 50 60 % Step24M 24 MHz Trim Step Size – 50 – kHz Fout48M 48 MHz Output Frequency 46.8 48.0 Jitter24M1 24 MHz Peak-to-Peak Period Jitter (IMO) – 600 ps F

MAX

RAMP

a. 4.75V < Vdd < 5.25V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. 3.0V < Vdd < 3.6V. See Applic ation Not e AN201 2 “Adjus ting PSoC Microcontroller Trims for Dual Voltage-Range Ope ration” for information on t rimming for o peratio n at 3 .3V. d. See the individual user module data sheets for information on maximum frequencies for user modules.

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters

Internal Main Oscillator Frequency for 24 MHz 23.4 24

Internal Main Oscillator Frequency for 6 MHz 5.75 6

CPU Frequency (5V Nominal) 0.93 24 CPU Frequency (3.3V Nominal) 0.93 12 Digital PSoC Block Frequency0(5V Nominal)

0 48

Digital PSoC Block Frequency (3.3V Nominal) 0 24

24.6

6.35

24.6

12.3

49.2

24.6

a,b,c

MHz Trimmed for 5V or 3.3V operation using

a,b,c

MHz Trimmed for 5V or 3.3V operation using

a,b

MHz 24 MHz only for SLIMO mode = 0.

b,c

MHz

a,b,d

MHz Refer to the AC Digital Block Specifica-

b,d

MHz

factory trim values. See Figure 3-1b on

page 17. SLIMO mode = 0.

factory trim values. See Figure 3-1b on

page 17. SLIMO mode = 1.

tions below.

Internal Low Speed Oscillator Frequency 15 32 64 kHz

External Reset Pulse Width 10 – – µs

a,c

49.2

MHz Trimmed. Utilizing factory trim values.

Maximum frequency of signal on row input or row output. – – 12.3 MHz Supply Ramp Time 0 – – µs

T able 3-16. 2.7V AC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

IMO12

IMO6

CPU1

BLK27

32K1

Internal Main Oscillator Frequency for 12 MHz

11.5 12

Internal Main Oscillator Frequency for 6 MHz 5.75 6

CPU Frequency (2.7V Nominal) 0.093 3 Digital PSoC Block Frequency (2.7V Nominal) 0 12

Internal Low Speed Oscillator Frequency 8 32 96 kHz

12.7

6.35

3.15

12.5

a,b,c

MHz Trimmed for 2.7V operation using factory

a,b,c

MHz Trimmed for 2.7V operation using factory

a,b

MHz 24 MHz only for SLIMO mode = 0.

a,b,c

MHz Refer to the AC Digital Block Specifica-

trim values. See Figure 3-1b on page 17. SLIMO mode = 1.

tions below.

Jitter32k 32 kHz RMS Period Jitter – 150 200 ns Jitter32k 32 kHz Peak-to-Peak Period Jitter – 1400 – T F T

XRST MAX RAMP

External Reset Pulse Width 10 – – µs Maximum frequency of signal on row input or row output. – – 12.3 MHz Supply Ramp Time 0 – – µs

a. 2.4V < Vdd < 3.0V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for user modules.

January 12, 2007 Document No. 38-12025 Rev. *K 24

CY8C21x34 Final Data Sheet 3. Electrical Specifications

Figure 3-3. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

24M

Figure 3-4. 32 kHz Period Jitter (ILO) Timing Diagram

Jitter32k

32K1

January 12, 2007 Document No. 38-12025 Rev. *K 25

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.4.2 AC General Purpose IO Specifications

Table 3-17. 5V and 3.3V AC GPIO Specifications

Symbol Description Min Typ Max Units Notes

GPIO

TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 7 27 – ns Vdd = 3 to 5.25V, 10% - 90% TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 7 22 – ns Vdd = 3 to 5.25V, 10% - 90%

Table 3-18. 2.7V AC GPIO Specifications

Symbol Description Min Typ Max Units Notes

GPIO

TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF TFallF Fall Time, Normal Strong Mode, Cload = 50 pF TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF TFallS Fall Time, Slow Strong Mode, Cload = 50 pF

Figure 3-5. GPIO Timing Diagram

GPIO Operating Frequency 0 – 12 MHz Normal Strong Mode

GPIO Operating Frequency 0 – 3 MHz Normal Strong Mode

6 – 50 ns Vdd = 2.4 to 3.0V, 10% - 90% 6 – 50 ns Vdd = 2.4 to 3.0V, 10% - 90% 18 40 120 ns Vdd = 2.4 to 3.0V, 10% - 90% 18 40 120 ns Vdd = 2.4 to 3.0V, 10% - 90%

GPIO

Output

Voltage

90%

10%

TRiseF

TRiseS

TFallF TFallS

January 12, 2007 Document No. 38-12025 Rev. *K 26

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.4.3 AC Operational Amplifier Specifications

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

T a ble 3-19. AC Operational Amplifie r Specifications

Symbol Description Min Typ Max Units Notes

COMP

Comparator Mode Response Time, 50 mV Over drive 100

200

ns ns

Vdd ≥ 3.0V.

2.4V < Vcc < 3.0V.

3.4.4 AC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ T apply to 5V at 25°C and are for design guidance only.

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters

Table 3-20. AC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

RLPC

LPC response time – – 50 µs ≥ 50 mV overdrive comparator reference set

within V

REFLPC

3.4.5 AC Analog Mux Bus Specifications

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters

Table 3-21. AC Analog Mux Bus Specifications

Symbol Description Min Typ Max Units Notes

Switch Rate – – 3.17 MHz

3.4.6 AC Digital Block Specifications

Table 3-22. 5V and 3.3V AC Digital Block Specifications

Function Description Min Typ Max Units Notes

All Functions

Timer Capture Pulse Width

Counter Enable Pulse Width

Dead Band Kill Pulse Width:

CRCPRS (PRS Mode)

Maximum Block Clocking Frequency (> 4.75V) 49.2 MHz 4.75V < Vdd < 5.25V.

Maximum Block Clocking Frequency (< 4.75V) 24.6 MHz 3.0V < Vdd < 4.75V.

50 Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V. Maximum Frequency, With or Without Capture – – 24.6 MHz

50 Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V. Maximum Frequency, Enable Input – – 24.6 MHz

Asynchronous Restart Mode 20 – – ns Synchronous Restart Mode 50 – – ns

Disable Mode 50 – – ns Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V. Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.

– – ns

January 12, 2007 Document No. 38-12025 Rev. *K 27

CY8C21x34 Final Data Sheet 3. Electrical Specifications

Table 3-22. 5V and 3.3V AC Digital Block Specifications (continued)

CRCPRS (CRC Mode)

SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to 2 x over

SPIS Maximum Input Clock Frequency – – 4.1 MHz

Transmitter Maximum Input Clock Frequency

Receiver Maximum Input Clock Frequency

a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

Maximum Input Clock Frequency – – 24.6 MHz

Width of SS_ Negated Between Transmissions 50 – – ns

Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2 Stop Bits

– –

24.6

49.2

24.6

49.2

MHz MHz

clocking.

Maximum data rate at 3.08 MHz due to 8 x over

clocking.

Maximum data rate at 6.15 MHz due to 8 x over

clocking.

Maximum data rate at 3.08 MHz due to 8 x over

clocking.

Maximum data rate at 6.15 MHz due to 8 x over

clocking.

T able 3-23. 2.7V AC Digital Block Specifications

Function Description Min Typ Max Units Notes

All Functions

Timer Capture Pulse Width

Counter Enable Pulse Width 100 – – ns

Dead Band Kill Pulse Width:

CRCPRS (PRS Mode)

CRCPRS (CRC Mode)

SPIM Maximum Input Clock Frequency – – 6.35 MHz Maximum data rate at 3.17 MHz due to 2 x over

SPIS Maximum Input Clock Frequency – – 4.1 MHz

Transmitter Maximum Input Clock Frequency – – 12.7 MHz Maximum data rate at 1.59 MHz due to 8 x over

Receiver Maximum Input Clock Frequency – – 12.7 MHz Maximum data rate at 1.59 MHz due to 8 x over

a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

Maximum Block Clocking Frequency 12.7 MHz 2.4V < Vdd < 3.0V.

100

Maximum Frequency, With or Without Capture – – 12.7 MHz

Maximum Frequency, No Enable Input – – 12.7 MHz Maximum Frequency, Enable Input – – 12.7 MHz

Asynchronous Restart Mode 20 – – ns

Synchronous Restart Mode 100 – – ns

Disable Mode 100 – – ns Maximum Frequency – – 12.7 MHz Maximum Input Clock Frequency – – 12.7 MHz

Maximum Input Clock Frequency – – 12.7 MHz

Width of SS_ Negated Between Transmissions

100

– – ns

clocking.

– – ns

clocking.

January 12, 2007 Document No. 38-12025 Rev. *K 28

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.4.7 AC External Clock Specifications

The following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

T able 3-24. 5V AC External Clock Specifications

Symbol Description Min Typ Max Units Notes

OSCEXT

– High Period 20.6 – Low Period 20.6 – Power Up IMO to Switch 150

Table 3-25. 3.3V AC External Clock Specifications

Symbol Description Min Typ Max Units Notes

OSCEXT

– High Period with CPU Clock divide by 1 41.7 – Low Period with CPU Clock divide by 1 41.7 – Power Up IMO to Switch 150

Frequency 0.093 – 24.6 MHz

– 5300 ns – –ns – – µs

Frequency with CPU Clock divide by 1 0.093 –

Frequency with CPU Clock divide by 2 or greater 0.186 – 24.6 MHz If the frequency of the external clock is greater

– 5300 ns – –ns – – µs

12.3

MHz Maximum CPU frequency is 12 MHz at 3.3V.

With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.

Table 3-26. 2.7V AC External Clock Specifications

Symbol Description Min Typ Max Units Notes

OSCEXT

– High Period with CPU Clock divide by 1 160 – Low Period with CPU Clock divide by 1 160 – Power Up IMO to Switch 150

Frequency with CPU Clock divide by 1 0.093 –

Frequency with CPU Clock divide by 2 or greater 0.186 – 6.35 MHz If the frequency of the external clock is greater

– 5300 ns – –ns – – µs

3.08

MHz Maximum CPU frequency is 3 MHz at 2.7V.

With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

than 3 MHz, the CPU clock divider must be set to 2 or greater. In thi s case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.

January 12, 2007 Document No. 38-12025 Rev. *K 29

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.4.8 AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

T able 3-27. AC Programming Specifications

Symbol Description Min Typ Max Units Notes

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

ERASEB

WRITE

DSCLK

DSCLK3

DSCLK2

Rise Time of SCLK 1 – 20 ns Fall Time of SCLK 1 – 20 ns Data Set up Time to Falling Edge of SCLK 40 – – ns Data Hold Time from Falling Edge of SCLK 40 – – ns Frequency of SCLK 0 – 8 MHz Flash Erase Time (Block) – 15 – ms Flash Block Write Time – 30 – ms Data Out Delay from Falling Edge of SCLK – – 45 ns 3.6 < Vdd Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6 Data Out Delay from Falling Edge of SCLK – – 70 ns 2.4 ≤ Vdd ≤ 3.0

January 12, 2007 Document No. 38-12025 Rev. *K 30

CY8C21x34 Final Data Sheet 3. Electrical Specifications

3.4.9 AC I2C Specifications

T able 3-28. AC Characteristics of the I

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

SPI2C

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but t he requirement t

the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must out put the next data bit to the SDA line t

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters

C SDA and SCL Pins for Vdd ≥ 3.0V

Standard Mode Fast Mode

Units NotesMin Max Min Max

SCL Clock Frequency 0 100 0 400 kHz Hold Time (repeated) START Condition. After this

period, the first clock pulse is generated. LOW Period of the SCL Clock 4.7 –1.3– µs HIGH Period of the SCL Clock 4.0 –0.6– µs Set-up Time for a Repeated START Condition 4.7 –0.6– µs Data Hold Time 0 –0– µs Data Set-up Time 250 – Set-up Time for STOP Condition 4.0 –0.6– µs Bus Free Time Between a STOP and START Condition 4.7 –1.3– µs Pulse Width of spikes are suppressed by the input fil-

ter.

+ t

rmax

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

SU;DAT

4.0 –0.6– µs

100

– – 0 50 ns

–ns

≥ 250 ns must then be met. This will automatically be

SU;DAT

T able 3-29. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)

Standard Mode Fast Mode

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

SPI2C

SCL Clock Frequency 0 100 – – kHz Hold Time (repeated) START Condition. After this

period, the first clock pulse is generated. LOW Period of the SCL Clock 4.7 – – – µs HIGH Period of the SCL Clock 4.0 – – – µs Set-up Time for a Repeated START Condition 4.7 – – – µs Data Hold Time 0 – – – µs Data Set-up Time 250 – – –ns Set-up Time for STOP Condition 4.0 – – – µs Bus Free Time Between a STOP and START Condition 4.7 ––– µs Pulse Width of spikes are suppressed by the input fil-

ter.

Figure 3-6. Definition for Timing for Fast/Standard Mode on the I

SDA

LOWI2C

SUDATI2C

4.0 – – – µs

– –––ns

HDSTAI2C

Units NotesMin Max Min Max

SPI2C

C Bus

BUFI2C

SCL

HDSTAI2C

HDDATI2C

HIGHI2C

SUSTAI2C

Sr SP

January 12, 2007 Document No. 38-12025 Rev. *K 31

SUSTOI2C

4. Packaging Information

This chapter illustrates the packaging specifications for the CY8C21x34 PSoC device, along with the thermal impedances fo r each package.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

4.1 Packaging Dimensions

51-85068 *B

Figure 4-1. 16-Lead (150-Mil) SOIC

January 12, 2007 Document No. 38-12025 Rev. *K 32

CY8C21x34 Final Data Sheet 4. Packaging Information

Figure 4-2. 20-Lead (210-MIL) SSOP

51-85077 *C

51-85079 *C

Figure 4-3. 28-Lead (210-Mil) SSOP

January 12, 2007 Document No. 38-12025 Rev. *K 33

CY8C21x34 Final Data Sheet 4. Packaging Information

E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm)

Figure 4-4. 32-Lead (5x5 mm 0.93 MAX) QFN

51-85188 *A

E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm)

001-06392 *A

Figure 4-5. 32-Lead (5x5 mm 0.60 MAX) QFN

January 12, 2007 Document No. 38-12025 Rev. *K 34

CY8C21x34 Final Data Sheet 4. Packaging Information

Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

Figure 4-6. 56-Lead (300-Mil) SSOP

51-85062 *C

January 12, 2007 Document No. 38-12025 Rev. *K 35

CY8C21x34 Final Data Sheet 4. Packaging Information

4.2 Thermal Impedances

Table 4-1. Thermal Impedances per Package

Package Typical θJA * Typical θ

16 SOIC 20 SSOP 28 SSOP

32 QFN** 5x5 mm 0.60 MAX

32 QFN** 5x5 mm 0.93 MAX * TJ = TA + Power x θ ** To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the

PCB ground plane.

123 oC/W 55 oC/W 117 oC/W 41 oC/W

96 oC/W 39 oC/W 27 oC/W 15 oC/W 22 oC/W 12 oC/W

4.3 Solder Reflow Peak Temperatur e

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 4-2. Solder Reflow Peak Temperature

Package Minimum Peak Temperature* Maximum Peak Temperature

16 SOIC 20 SSOP 28 SSOP

32 QFN

*Higher temperatures may be required based on the solder melting point. Typical te mpera tur es for solder are 220 ± 5oC with Sn-Pb or 245 ± 5

C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

240oC 260oC 240oC 260oC 240oC 260oC 240oC 260oC

January 12, 2007 Document No. 38-12025 Rev. *K 36

5. Development Tool Selection

This chapter presents the development tools available for all current PSoC device families including the CY8C21x34 family.

5.1 Software

5.1.1 PSoC Designer™

At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://

www.cypress.com under DESIGN RESOURCES >> Software

and Drivers.

5.1.2 PSoC Express™

As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocex-

press.

5.1.3 PSoC Programmer

Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube InCircuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocpro-

grammer.

5.2 Development Kits

All development kits can be purchased from the Cypress Online Store.

5.2.1 CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes:

■ PSoC Designer Software CD

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ Mini-Eval Programming Board

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

5.1.4 CY3202-C iMAGEcraft C Compiler

CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items..

January 12, 2007 Document No. 38-12025 Rev. *K 37

CY8C21x34 Final Data Sheet 5. Development Tool Selection

5.2.2 CY3210-ExpressDK PSoC Express Development Kit

The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Cir-

cuit Emulator). It provides access to I

C buses, voltage reference, switches, upgradeable modules and more. The kit includes:

■ PSoC Express Software CD

■ Express Development Board

■ 4 Fan Modules

■ 2 Proto Modules

■ MiniProg In-System Serial Programmer

■ MiniEval PCB Evaluation Board

■ Jumper Wire Kit

■ USB 2.0 Cable

■ Serial Cable (DB9)

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples

■ 2 CY8C27443-24PXI 28-PDIP Chip Samples

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

5.3 Evaluation Tools

All evaluation tools can be purchased from the Cypress Online Store.

5.3.1 CY3210-MiniProg1

The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

5.3.2 CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

5.3.3 CY3214-PSoCEvalUSB

The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

■ PSoCEvalUSB Board

■ LCD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ PSoC Designer and Example Projects CD

■ Getting Started Guide

■ Wire Pack

5.4 Device Programmers

All device programmers can be purchased from the Cypress Online Store.

5.4.1 CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

■ Modular Programmer Base

■ 3 Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

5.4.2 CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust th an the MiniProg in a production-programming environment. Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

January 12, 2007 Document No. 38-12025 Rev. *K 38

CY8C21x34 Final Data Sheet 5. Development Tool Selection

5.5 Accessories (Emulation and Programming)

Table 5-1. Emulatio n and Programming Accessories

Part # Pin

CY8C21234

-24S CY8C21334

-24PVXI CY8C21434

-24LFXI CY8C21534

-24PVXI CY8C21634

-24LFXI

a. Flex-Pod kit includes a practice flex-pod and a practic e PCB, in addition to two b. Foot kit includes surface mount feet that can be soldered to the target PCB.

c. Programming adapter converts non-DIP package to DIP footprint. Specific

Package

16 SOIC CY3250-21X34 CY3250-

20 SSOP CY3250-21X34 CY3250-

32 QFN CY3250-

28 SSOP CY3250-21X34 CY3250-

32 QFN CY3250-

flex-pods.

details and ordering information for each of the adapters can be found at

http://www.emulation.com.

Flex-Pod Kit

21X34QFN

16SOIC-FK

20SSOP-FK CY3250-

32QFN-FK

28SSOP-FK CY3250-

32QFN-FK

Foot Kit

Adapter

See note c. below

5.6 3rd-Party Tools

Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards.

5.7 Build a PSoC Emulator into Your Board

For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com/

an2323.

January 12, 2007 Document No. 38-12025 Rev. *K 39

6. Ordering Information

CY8C21x34 PSoC Device Key Features and Ordering Information

Package

Code

Ordering

Flash

SRAM

(Bytes)

Switch Mode

Pump

Range

Digital

Blocks

Analog

Temperature

16 Pin (150-Mil) SOIC CY8C21234-24SXI 8K 512 Yes -40°C to +85°C 4 4 12 16 Pin (150-Mil) SOIC

(Tape and Reel)

CY8C21234-24SXIT 8K 512 Yes -40°C to +85°C 4 4 12

20 Pin (210-Mil) SSOP CY8C21334-24PVXI 8K 512 No -40°C to +85°C 4 4 16 20 Pin (210-Mil) SSOP

(Tape and Reel)

CY8C21334-24PVXIT 8K 512 No -40°C to +85°C 4 4 16

28 Pin (210-Mil) SSOP CY8C21534-24PVXI 8K 512 No -40°C to +85°C 4 4 24 28 Pin (210-Mil) SSOP

(Tape and Reel) 32 Pin (5x5 mm 0.93 MAX) QFN 32 Pin (5x5 mm 0.93 MAX) QFN

(Tape and Reel) 32 Pin (5x5 mm 0.60 MAX) QFN 32 Pin (5x5 mm 0.06 MAX) QFN

(Tape and Reel) 32 Pin (5x5 mm 0.93 MAX) QFN 32 Pin (5x5 mm 0.93 MAX) QFN

(Tape and Reel)

CY8C21534-24PVXIT 8K 512 No -40°C to +85°C 4 4 24

CY8C21434-24LFXI 8K 512 No -40°C to +85°C 4 4 28

CY8C21434-24LFXIT 8K 512 No -40°C to +85°C 4 4 28

CY8C21434-24LKXI 8K 512 No -40°C to +85°C 4 4 28

CY8C21434-24LKXIT 8K 512 No -40°C to +85°C 4 4 28

CY8C21634-24LFXI 8K 512 Yes -40°C to +85°C 4 4 26

CY8C21634-24LFXIT 8K 512 Yes -40°C to +85°C 4 4 26

56 Pin OCD SSOP CY8C21001-24PVXI 8K 512 Yes -40°C to +85°C 4 4 26

a. All Digital IO Pins also connect to the common analog mux. b. Refer to the “32-Pin Part Pinout” on page 11 for pin differences.

Digital IO

Pins

Analog

Inputs

Outputs

XRES Pin

0 No

0 Yes

6.1 Ordering Code Definitions

Y 8 C 21 xxx-24xx

January 12, 2007 Document No. 38-12025 Rev. *K 40

Package Type: Thermal Rating:

PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free

AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress

7. Sales and Service Information

Cypress Semiconductor

198 Champion Court San Jose, CA 95134

408.943.2600

Web Sites: Company Information – http://www.cypress.com

Sales – http://www.cypress.com/aboutus/sales_locations.cfm

Technical Support – http://www.cypress.com/support/login.cfm

7.1 Revision History

Document Title: CY8C21234, CY8C21334, CY8C21434, CY8C21534, and CY8C21634 PSoC Mixed-Signal Array Final Data Sheet Document Number: 38-12025

Revision ECN # Issue Date

** *A 235992 See ECN SFV

*B 248572 See ECN SFV

*C *D 285293 See ECN HMT Update 2.7V DC GPIO spec. Add Reflow Peak Temp. table.

*E 301739 See ECN HMT DC Chip-Level Specification changes. Update links to new CY.com Portal.

*G *H 390152 See ECN HMT Clarify MLF thermal pad connection info. Replace 16-pin 300-MIL SOIC with correct 150-MIL.

*I 413404 See ECN HMT Update 32-pin QFN E-Pad dimensions and rev. *A. Update CY branding and QFN convention.

Distribution: External/Public Posting: None

227340

277832 See ECN HMT Verify data sheet standards from SFV memo. Add Analog Input Mux to applicable pin outs.

329104 See ECN HMT Re-add pinout ISSP notation. Fix TMP register names. Clarify ADC feature. Update Electrical

352736 See ECN HMT Add new color and logo. Add URL to preferred dimensions for mounting MLF packages. Update

430185 See ECN HMT Add new 32-pin 5x5 mm 0.60 thickness QFN package and diagram, CY8C21434-24LKXI. Update

677717 See ECN HMT Add CapSense SNR requirement reference. Add new Dev. Tool section. Add CY8C20x34 to

5/19/2004 HMT New silicon and document (Revision **).

Origin of

Change

Description of Change

Updated Overview and Electrical Spec. chapters, along with revisions to the 24-pin pinout part. Revised the register mapping tables. Added a SSOP 28-pin part.

Changed title to include all part #s. Changed 28-pin SSOP from CY8C21434 to CY8C21534. Changed pin 9 on the 28-pin SSOP from SMP pin to Vss pin. Added SMP block to architecture diagram. Update Electrical Specifications. Added another 32-pin MLF part: CY8C21634.

Update PSoC Characteristics table. Update diagrams and specs. Final.

Specifications. Update Reflow Peak Temp. table. Add 32 MLF E-PAD dimensions. Add ThetaJC to Thermal Impedance table. Fix 20-pin package order number. Add CY logo. Update CY copyright.

Transmitter and Receiver AC Digital Block Electrical Specifications.

thermal resistance data. Add 56-pin SSOP on-chip debug non-production part, CY8C2100124PVXI. Update typical and recommended Storage Temperature per industrial specs. Update copyright and trademarks.

PSoC Device Characteristics table. Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Update rev. of 32-Lead (5x5 mm 0.60 MAX) QFN package diagram.

CY8C21x34 Final Data Sheet 7. Sales and Service Information

7.2 Copyrights and Code Protection

Copyrights

© Cypress Semiconductor Corp. 2004-2007. All rights reserved. PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor.

Flash Code Protection Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet the specifications contained in thei r particular data sheets. Cypress Semiconductor believes that its PSoC family of products is one

of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. C ode protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products.

January 12, 2007 Document No. 38-12025 Rev. *K 42

CYPRESS CY 8C21234-24SXI Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

PSoC® Functional Overview

Getting Started

Development Tools

Designing with User Modules

Document Conventions

Table of Contents

1. Pin Information

1.1 Pinouts

1.1.1 16-Pin Part Pinout

1.1.2 20-Pin Part Pinout

1.1.3 28-Pin Part Pinout

1.1.4 32-Pin Part Pinout

1.1.5 56-Pin Part Pinout

2. Register Reference

2.1 Register Conventions

2.2 Register Mapping Tables

3. Electrical S pecifications

3.1 Absolute Maximum Ratings

3.2 Operating Temperature

3.3 DC Electrical Characteristics

3.3.1 DC Chip-Level Specifications

3.3.2 DC General Purpose IO Specifications

3.3.3 DC Operational Amplifier Specifications

3.3.4 DC Low Power Comparator Specifications

3.3.5 DC Switch Mode Pump Specifications

3.3.6 DC Analog Mux Bus Specifications

3.3.7 DC POR and LVD Specifications

3.3.8 DC Programming Specifications

3.4 AC Electrical Characteristics

3.4.1 AC Chip-Level Specifications

3.4.2 AC General Purpose IO Specifications

3.4.3 AC Operational Amplifier Specifications

3.4.4 AC Low Power Comparator Specifications

3.4.5 AC Analog Mux Bus Specifications

3.4.6 AC Digital Block Specifications

3.4.7 AC External Clock Specifications

3.4.8 AC Programming Specifications

3.4.9 AC I2C Specifications

4. Packaging Information

4.1 Packaging Dimensions

4.2 Thermal Impedances

4.3 Solder Reflow Peak Temperatur e

5. Development Tool Selection

5.1 Software

5.1.3 PSoC Programmer

5.2 Development Kits

5.2.1 CY3215-DK Basic Development Kit

5.1.4 CY3202-C iMAGEcraft C Compiler

5.2.2 CY3210-ExpressDK PSoC Express Development Kit

5.3 Evaluation Tools

5.3.1 CY3210-MiniProg1

5.3.2 CY3210-PSoCEval1

5.3.3 CY3214-PSoCEvalUSB

5.4 Device Programmers

5.4.1 CY3216 Modular Programmer

5.4.2 CY3207ISSP In-System Serial Programmer (ISSP)

5.5 Accessories (Emulation and Programming)

5.6 3rd-Party Tools

5.7 Build a PSoC Emulator into Your Board

6. Ordering Information

6.1 Ordering Code Definitions

7. Sales and Service Information

7.1 Revision History

7.2 Copyrights and Code Protection