CYPRESS CY8C21123, CY8C21223, CY8C21323 User Manual
PSoC™ Mixed-Signal Array Final Data Sheet
CY8C21123,
CY8C21223, and CY8C21323
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Low Power at High Speed
❐ 2.4V to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V Using
On-Chip Switch Mode Pu mp (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC Blocks)
❐ 4 Analog Type “E” PSoC Blo cks Provide:
- 2 Comparators with DAC Refs
- Single or Dual 8-Bit 8:1 ADC
❐ 4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART, SPI™ Master or Slave
- Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
Po rt 1 Po rt 0
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
Interrupt
Controller
SROM Flash
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
PSoC Block
Array
Cloc k Sources
Global Analog Interconnect
CPU Core
(M8C)
ANALOG SYST EM
Analog
PSoC Block
Array
■ Flexible On-Chip Memory
❐ 4K Flash Program Storage 50,000 Erase/Write
Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Prog ramming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Mode s
❐ EEPROM Emulation in Flash
■ Complete Development Tools
❐ Free Development Software
(PSoC™ Designer)
❐ Full-Featured, In-C ircui t Emul a tor and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 Bytes Trace Memory
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable component. A
PSoC device includes configurable blocks of analog and digital
logic, as well as programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application. Addi-
Sleep and
Watchdog
Analog
Ref .
tionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient
pinouts.
The PSoC architecture, as illustrat ed on th e l ef t , is com pri se d of
four main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow all the device resources to be combined into a
complete custom system. Each PSoC device includes four digital blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 general purpose IO (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
■ Precision, Programm ab le Cloc kin g
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
■ Programmable Pin Configurations
❐ 25 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on All GPIO
❐ Up to 8 Analog Inputs on GPIO
❐ Configurable Interrupt on All GPIO
■ Additional System Resources
2
❐ I
C™ Master, Slave and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The
Digital
Clocks
I2C
POR and LVD
System Resets
Switch
Mode
Pump
Internal
Voltage
Ref .
SYSTEM R ESOUR CES
February 25, 2005 © Cypress Semiconductor Corp. 2004-2005 — Document No. 38-12022 Rev. *G 1
CY8C21x23 Final Data Sheet PSoC™ Overview
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microp rocessor.
System Resources prov ide additional capability, such as digital
clocks to increase the flexibility of the PSoC mixed-signal
arrays, I2C functionality for implementing an I2C master, slave,
MultiMaster, an internal voltage reference that provides an
absolute value of 1.3V to a number of PSoC subsystems, a
switch mode pump (SMP) that generates normal operating voltages off a single battery cell, and various system resets supported by the M8C.
The Digital System is composed of an array of digital PSoC
blocks, which can be configured into any number of digital
peripherals. The digi tal blocks can be connected to the GPIO
through a series of global busses that can route any signal to
any pin. Freeing designs from the constraints of a fixed peripheral controller.
The Analog System is composed of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to
8 bits in precision.
The Digital System
The Digital System is composed of 4 digital PSoC bloc ks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to fo rm 8, 16 , 24, and 32-bit p eriphe rals, wh ich
are called user module references. Digital peripheral configurations include those listed below.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity (up to 4)
■ SPI master and slave
■ I2C slave, master, multi-master (1 availab le as a System
Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA (up to 4)
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global bu ss es tha t c an rou t e any s ign al to any p in. The
busses also allow for signal multiplexing and for performing
logic operations. This config urabil ity frees your d esigns fro m the
constraints of a fixed peripheral controller.
Port 1
Port 0
o
c
k
o
r
e
To System Bus
s
To Analog
System
g
t
i
D
i
a
l
C
l
F
r
o
m
C
DIGITAL SYSTEM
Digital PSoC Block Array
Configuration
Row 0
DBB00 DBB01 DCB02 DCB03
Row Input
8
Configuration
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Row Ou t put
4
4
8
Digital System Block Diagram
The Analog System
The Analog System is composed of 4 configurable blocks to
allow creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are listed
below.
■ Analog-to-digital converters (single or dual, with 8-bit resolu-
tion)
■ Pin-to-pin comparato r s (1)
■ Single-ended comparators (up to 2) with absolute (1.3V) ref-
erence or 8-bit DAC reference
■ 1.3V refer ence (as a System Resource)
In most PSoC devices, analog blocks are provided in columns
of three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x23 devices provide
limited functionality Type “E” analog blocks. Each column contains one CT block and one SC block.
The number of blocks is on the device family which is detailed
in the table titled “PSoC Device Chara cte ris t ic s” on p age 3.
88
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Char ac-
teristics” on page3.
February 25, 2005 Document No. 38-12022 Rev. *G 2
CY8C21x23 Final Data Sheet PSoC™ Overview
PSoC Device Characteristics
Array Input
Configuration
ACI0[1:0] ACI1[1:0]
ACOL1MUX
Array
ACE00 ACE01
ASE10 ASE11
Analog System Block Diagram, CY8C21x23
Additional System Resources
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is highlighted below.
PSoC Device Characteristics
PSoC Device
Group
Digital Rows
Digital Blocks
Digital IO (Max)
CY8C29x66 64 4 16 12 4 4 12 2K 32K
CY8C27x43 44 2 8 12 4 4 12 256 Bytes 16K
CY8C24794 56 1 4 48 2 2 6 1K 16K
CY8C24x23A 24 1 4 12 2 2 6 256 Bytes 4K
CY8C24x23 24 1 4 12 2 2 6 256 Bytes 4K
CY8C21x34 28 1 4 28 0 2
CY8C21x23 16 1 4 8 0 2
a. Limited analog functionality.
Analog Inputs
Analog Outputs
Analog Blocks
Analog Columns
a
4
a
4
Amount of SRAM
512 Bytes 8K
256 Bytes 4K
Amount of Flash
System Resources, some of which have been previously listed,
provide addi tional capab ility useful to complete sy stems. Additional resources include a switch mode pump, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource are presented below.
■ Digital clock dividers provide three customizable clock fre-
quencies for use in applic ations . The clo cks can be routed to
both the digital a nd analog s ystems. Add itional c locks c an be
generated using digital PSoC blocks as clock dividers.
■ The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■ An internal 1.3 voltage reference provides an absolute refer-
ence for the analog system, including ADCs and DACs.
■ An integrated switch mode pump (SMP) generates normal
operating voltages fr om a single 1.2 V battery cell, pro viding a
low cost boost converter.
February 25, 2005 Document No. 38-12022 Rev. *G 3
CY8C21x23 Final Data Sheet PSoC™ Overview
Getting Started
The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC Mixed- Signal Array Technical Referenc e Manual, which
can be found on http://www.cypress.com/psoc.
For up-to-date Ordering, Packag ing, an d Electri cal Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypres s On lin e Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click PSoC (Program-
mable System-on-Chip) to view a current list of available items.
Technical Training
Free PSoC technical training is available for beginners and is
taught by a marketing or application engineer over the phone.
PSoC training classes cover designing, debugging, advanced
analog, as well as applica tion-specific classes covering topics
such as PSoC and the LIN bus. Go to http://www.cypress.com,
click on Design Support located on the left side of the web
page, and select Technical Training for more details.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to complete d PSoC d esign s. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows NT 4.0, Windows 2000, Windows Millennium
(Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.)
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
TM
PSoC
Designer
Importable
Design
Database
Dev ice
Database
Application
Database
Project
Database
User
Modules
Library
Graphical Designer
Interf ace
Results
Commands
TM
PSoC
Designer
Core
Engine
Context
Sensitive
Help
PSoC
Configuration
Sheet
Manufacturing
Information
File
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
Emulation
Pod
In-Circuit
Emulator
PSoC Designer Subsystems
A long list of application notes will assist you in every aspect of
your design effort. To view the PSoC application notes, go to
the http://www.cypress.com web site and select Application
Notes under the Design Resources list located in the center of
the web page. Application notes are sorted by date by default.
February 25, 2005 Document No. 38-12022 Rev. *G 4
Device
Programmer
CY8C21x23 Final Data Sheet PSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
The device editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application programming in conj unc tion with the D evice Data S heet . Once the
framework is generated, the user can add application-specific
code to flesh out the fr am ew ork . It’s also possible to change the
selected components and regenerate the framewor k.
Design Browser
The Design Browser allows users to select and import preconfigured desi g ns into th e u se r’s project. U se rs ca n ea s il y bro w se
a catalog of prec onfigured designs to facilitate time-to-design.
Examples provided in the tool s i nclude a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read the
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family are available separately. The emulation pod takes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, compile, link, and build.
Assembler. The macro assembler allows the assembly code
to be merged seam lessly with C code. The link libraries automatically use abso lut e addre ssing or ca n be co mpil ed in relat ive
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports PSoC family devices. Even if you have never
worked in the C langu age bef ore, the p rod uct qui ckly allows you
to create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
February 25, 2005 Document No. 38-12022 Rev. *G 5
CY8C21x23 Final Data Sheet PSoC™ Overview
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and d igital hard ware blocks give the PS oC archite cture
a unique flexibility that p ays d ivide nds in mana gi ng specifi catio n
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that de termine its function and
connectivity to other blocks, multiplexers, busses and to the IO
pins. Iterative devel op men t cy cl es perm it y ou to adapt the hardware as well as the software. This substantially lowers the risk
of having to select a different part to meet the final design
requirements.
To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
applicati on. For exam ple, a Pulse Width Modula tor User Module configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programm ing interface (API) provides highlevel functions to co ntrol and respond to hardware events at ru n
time. The API also provides optional interrupt service routines
that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSo C Desi gn er ID E. Th es e data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user mod ule p ara me ter a nd d oc um ent s the setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to develo ping co de for the proj ect, yo u
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specif ic atio n an d pro vi des the high -le vel us er
module API functions.
Devic e Ed itor
User
M odule
Selection
Placement
and
Parameter
-ization
Source
Code
Generat or
Generate
Application
Application Editor
Project
M anage r
Source
Code
Editor
Build
M ana ger
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
M ana ger
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (inc luding all generated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming .
The last step in the devel opm en t proc es s t ak es pla ce insi de the
PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint event s tha t inc lu de m oni tori ng ad dres s and da t a bu s
values, memory locations and external signals.
February 25, 2005 Document No. 38-12022 Rev. *G 6
CY8C21x23 Final Data Sheet PSoC™ Overview
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
EEPROM electrically erasable programmable read-only memory
FSR full scale range
GPIO general purpose IO
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
POR power on reset
PPOR precision power on reset
PSoC™ Programmable System-on-Chip
PWM pulse width modulator
ROM read only memory
SC switched capacitor
SMP switch mode pump
SRAM static random access memory
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 14 lists all the abbreviations
used to measure the PSoC devices.
Table of Cont ents
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed-Signal Array Technical Refer-
ence Manual on http://www.cypress.com. This data sheet
encompasses and is organized into the following chapters and
sections.
1. Pin Information .............................. ..... ...... ..... ............... 8
1.1 Pinouts ................................................................... 8
1.1.1 8-Pin Part Pinout ...................................... 8
1.1.2 16-Pin Part Pinout ..................................... 8
1.1.3 20-Pin Part Pinout .................................... 9
1.1.4 24-Pin Part Pinout ................................. 10
2. Register Reference ..................................................... 11
2.1 Register Conventions ........................................... 11
2.2 Register Mapping Tables ..................................... 11
3. Electrical Specifications ............................................14
3.1 Absolute Maximum Ratings ................................ 15
3.2 Operating Temperature ....................................... 15
3.3 DC Electrical Characteristics ................................15
3.3.1 DC Chip-Level Specifications ................... 15
3.3.2 DC General Purpose IO Specifications .... 16
3.3.3 DC Amplifier Specifications .....................17
3.3.4 DC Switch Mode Pump Specifications ..... 18
3.3.5 DC POR and LVD Specifications ............. 19
3.3.6 DC Programming Specifications ...............20
3.4 AC Electrical Characteristics ................................ 21
3.4.1 AC Chip-Level Specifications ...................21
3.4.2 AC General Purpose IO Specifications .... 23
3.4.3 AC Amplifier Specifications ...................... 24
3.4.4 AC Digital Block Specifications .................24
3.4.5 AC External Clock Specifications .............26
3.4.6 AC Programming Specifications ............... 27
3.4.7 AC I2C Specifications ............................... 27
4. Packaging Information ............................................... 29
4.1 Packaging Dimensions .........................................29
4.2 Thermal Impedances .......................................... 31
4.3 Solder Reflow Peak Temperature ........................ 31
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexi d ec im al nu mber s ma y al so be re p res en t ed by a ‘0x’
prefix, the C coding convention. Binary numbers have an
5.1 Ordering Code Definitions ................................... 32
6. Sales and Service Information ..................................33
6.1 Revision History .................................................. 33
6.2 Copyrights and Flash Code Protection ................ 33
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
February 25, 2005 Document No. 38-12022 Rev. *G 7
5. Ordering Information ..................................................32
1. Pin Information
This chapter describes, lists, and illustrates the CY8C21x23 PSoC device pins and pinout configurations.
1.1 Pinouts
The CY8C21x23 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.1 8-Pin Part Pinout
Table 1-1. 8-Pin Part Pinout (SOIC)
Pin
No.
1 IO I P0[5] Analog column mux input.
2 IO I P0[3] Analog column mux input.
3 IO P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
4 Power Vss Ground connection.
5 IO P1[0] I2C Serial Data (SDA), ISSP-SDATA.
6 IO I P0[2] Analog column mux input.
7 IO I P0[4] Analog column mux input.
8 Power Vdd Supply voltage.
Type
Digital Analog
Pin
Name
Description
CY8C21123 8-Pin PSoC Device
1
8
A, I, P0[5]
A, I, P0[3]
I2C SCL, P1[1]
Vss
2
SOIC
3
4
Vdd
P0[4], A, I
7
P0[2], A, I
6
5
P1[0], I2C SDA
LEGEND: A = Analog, I = Input, and O = Output.
1.1.2 16-Pin Part Pinout
Table 1-2. 16-Pin Part Pinout (SOIC)
Pin
No.
1 IO I P0[7] Analog column mux input.
2 IO I P0[5] Analog column mux input.
3 IO I P0[3] Analog column mux input.
4 IO I P0[1] Analog column mux input.
5 Power SMP Switch Mode Pump (SMP) connection to
6 Power Vss Ground connection.
7 IO P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
8 Power Vss Ground connection.
9 IO P1[0] I2C Serial Data (SDA), ISSP-SDATA.
10 IO P1[2]
11 IO P1[4] Optional External Clock Input (EXTCLK).
12 IO I P0[0] Analog column mux input.
13 IO I P0[2] Analog column mux input.
14 IO I P0[4] Analog column mux input.
15 IO I P0[6] Analog column mux input.
16 Power Vdd Supply voltage.
LEGEND A = Analog, I = Input, and O = Output.
Type
Digital Analog
Name Description
required external components.
CY8C21223 16-Pin PSoC Device
A, I, P0[7]
A, I, P0[5]
A, I, P0[3]
A, I, P0[1]
SMP
Vss
I2C SCL, P1[1]
Vss
1
2
3
4
5
6
7
8
SOIC
16
15
14
13
12
11
10
9
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P1[4], EXTCLK
P1[2]
P1[0], I2C SDA
February 25, 2005 Document No. 38-12022 Rev. *G 8
CY8C21x23 Final Data Sheet 1. Pin Information
1.1.3 20-Pin Part Pinout
Table 1-3. 20-Pin Part Pinout (SSOP)
Pin
No.
1 IO I P0[7] Analog column mux input.
2 IO I P0[5] Analog column mux input.
3 IO I P0[3] Analog column mux input.
4 IO I P0[1] Analog column mux input.
5 Power Vss Ground connection.
6 IO P1[7] I2C Serial Clock (SCL).
7 IO P1[5] I2C Serial Data (SDA).
8 IO P1[3]
9 IO P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
10 Power Vss Ground connection.
11 IO P1[0] I2C Serial Data (SDA), ISSP-SDATA.
12 IO P1[2]
13 IO P1[4] Optional External Clock Input (EXT-
14 IO P1[6]
15 Input XRES Active high external reset with internal
16 IO I P0[0] Analog column mux input.
17 IO I P0[2] Analog column mux input.
18 IO I P0[4] Analog column mux input.
19 IO I P0[6] Analog column mux input.
20 Power Vdd Supply voltage.
LEGEND A = Analog, I = Input, and O = Output.
Type
Digital Analog
Name Description
CLK).
pull down.
CY8C21323 20-Pin PSoC Device
A, I, P0[7 ]
A, I, P0[5]
A, I, P0[3]
A, I, P0[1]
Vss
I2C SCL, P1[7]
I2C SDA, P1[5 ]
P1[3]
I2C SCL, P1[1]
Vss
10
1
2
3
4
5
6
7
8
9
SSOP
20
19
18
17
16
15
14
13
12
11
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], I2C SDA
February 25, 2005 Document No. 38-12022 Rev. *G 9
CY8C21x23 Final Data Sheet 1. Pin Information
I
I
I
I
I
1.1.4 24-Pin Part Pinout
Table 1-4. 24-Pin Part Pinout (MLF*)
Pin
No.
1 IO I P0[1] Analog column mux input.
2 Power SMP Switch Mode Pump (SMP) connection to
3 Power Vss Ground connection.
4 IO P1[7] I2C Serial Clock (SCL).
5 IO P1[5] I2C Se ria l Data (SDA ) .
6 IO P1[3]
7 IO P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
8 NC No connection.
9 Power Vss Ground connection.
10 IO P1[0] I2C Serial Data (SDA), ISSP-SDATA.
11 IO P1[2]
12 IO P1[4] Optional External Clock Input (EXT-
13 IO P1[6]
14 Input XRES Active high external reset with internal
15 NC No connection.
16 IO I P0[0] Analog column mux input.
17 IO I P0[2] Analog column mux input.
18 IO I P0[4] Analog column mux input.
19 IO I P0[6] Analog column mux input.
20 Power Vdd Supply voltage.
21 Power Vss Ground connection.
22 IO I P0[7] Analog column mux input.
23 IO I P0[5] Analog column mux input.
24 IO I P0[3] Analog column mux input.
LEGEND A = Analog, I = Input, and O = Output.
* Note The MLF package has a center pad that must be connected to the
same ground as the Vss pin.
Type
Digital Analog
Name Description
required external compone nts.
CLK).
pull down.
CY8C21323 24-Pin PSoC Device
P0[5], A, IP0[7], A, IVss
P0[3], A,
A, I, P0 [1 ]
SMP
Vss
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
2423222120
1
2
MLF
3
(Top View )
4
5
6
789
NC
I2C SCL, P1[1]
101112
Vss
I2C SDA, P1[0]
P1[2]
Vdd
P0[6], A,
19
18
P0[4], A,
P0[2], A,
17
16
P0[0], A,
15
NC
14
XRE S
P1[6]
13
EXTCLK, P1[4]
February 25, 2005 Document No. 38-12022 Rev. *G 10
Loading...