Cypress CY8C20xx7/S CapSense Series Design Manual

AN78329 - CapSense® Design Guide

CY8C20xx7/S

Doc. No. 001-78329 Rev. *E

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

Phone (USA): 800.858.1810

Phone (Intnl): 408.943.2600

www.cypress.com

Copyrights

Copyrights

© Cypress Semiconductor Corporation, 2012-2015. The information contained herein is subject to change without notice.
Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a
Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted
nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an
express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury
to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all
risk of such use and in doing so indemnifies Cypress against all charges.

Trademarks

PSoC Designer™, Programmable System-on-Chip™, and SmartSense™ are trademarks and PSoC® and CapSense® are
registered trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are
property of the respective corporations.

Source Code

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected
by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international
treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use,
modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of
creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or
representation of this Source Code except as specified above is prohibited without the express written permission of
Cypress.

Disclaimer

CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described
herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein.
Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure
may reasonably be expected to result in significant injury to the user. The inclusion of Cypress‟ product in a life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against
all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 2

Contents

1. Introduction .......................................................................................................................................................... 6

1.1 Abstract ....................................................................................................................................................... 6

1.2 Cypress‟s CapSense Documentation Ecosystem ........................................................................................ 6

1.3 CY8C20xx7/S CapSense Family Features .................................................................................................. 8

1.4 Document Conventions ............................................................................................................................. 10

2. CapSense Technology ...................................................................................................................................... 11

2.1 CapSense Fundamentals .......................................................................................................................... 11

2.2 Capacitive Sensing Methods in CY8C20xx7/S .......................................................................................... 12

2.2.1 CapSense Sigma Delta (CSD) ..................................................................................................... 12

2.2.2 CapSense Sigma Delta (CSD) PLUS ........................................................................................... 15

2.2.3 SmartSense_EMCPLUS Auto-Tuning .......................................................................................... 18

2.2.4 Selecting the User Module ............................................................................................................ 19

3. CapSense Design Tools .................................................................................................................................... 20

3.1 Overview ................................................................................................................................................... 20

3.1.1 PSoC Designer and User Modules ............................................................................................... 20

3.1.2 CY8C20xx7/S QuietZone Starter Kit ............................................................................................. 21

3.1.3 CapSense Data Viewing Tools ..................................................................................................... 21

3.2 User Module Overview .............................................................................................................................. 22

3.3 CapSense User Module Global Arrays ...................................................................................................... 22

3.3.1 Raw Count .................................................................................................................................... 23

3.3.2 Baseline ........................................................................................................................................ 23

3.3.3 Difference Count (Signal) ............................................................................................................. 23

3.3.4 Sensor State ................................................................................................................................. 23

3.4 CSD/CSDPLUS User Module Parameters ................................................................................................ 23

3.4.1 User Module High-Level Parameters ............................................................................................ 24

3.4.2 CSD/CSDPLUS User Module Low-Level Parameters .................................................................. 27

3.5 SmartSense_EMCPLUS User Module Parameters ................................................................................... 31

4. CapSense Performance Tuning with User Modules ....................................................................................... 33

4.1 General Considerations ............................................................................................................................. 33

4.2 Tuning the CSD/CSDPLUS User Module .................................................................................................. 35

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 3

4.1.1 Signal, Noise, and SNR ................................................................................................................ 33

4.1.2 Charge/Discharge Rate ................................................................................................................ 34

4.1.3 Importance of Baseline Update Threshold Verification ................................................................. 35

4.2.1 Recommended C

Value for CSD/CSDPLUS........................................................................... 36

MOD

Contents

4.2.2 I

Range .................................................................................................................................... 37

DAC

4.2.3 Autocalibration .............................................................................................................................. 37

4.2.4 I

4.2.5 Compensation I

Value ..................................................................................................................................... 37

DAC

Value ............................................................................................................. 37

DAC

4.2.6 Precharge Source ......................................................................................................................... 37

4.2.7 Prescaler ...................................................................................................................................... 37

4.2.8 Resolution ..................................................................................................................................... 38

4.2.9 Scanning Speed ........................................................................................................................... 38

4.2.10 High-Level API Parameters .......................................................................................................... 39

4.2.11 Set High-Level Parameters ........................................................................................................... 40

4.3 Using the SmartSense_EMCPLUS User Module ...................................................................................... 40

4.3.1 Guidelines for SmartSense_EMC_PLUS ...................................................................................... 40

4.3.2 Understanding the Difference ....................................................................................................... 40

4.3.3 Recommended C

Value for SmartSense_EMC_PLUS ........................................................... 41

MOD

4.3.4 SmartSense_EMCPLUS User Module Parameters ...................................................................... 41

4.3.5 SmartSense_EMCPLUS User Module Specific Guidelines .......................................................... 41

4.3.6 Scan Time of a CapSense Sensor................................................................................................ 42

4.3.7 SmartSense_EMCPLUS Response Time ..................................................................................... 43

4.3.8 Method to Ensure Minimum SNR Using the SmartSense_EMCPLUS UM ................................... 44

4.3.9 Firmware Design Guidelines ......................................................................................................... 45

4.4 Design Migration from CY8C20xx6A/AS to CY8C20xx7/S ........................................................................ 47

4.4.1 Discontinued Support/User Modules ............................................................................................ 47

4.4.2 Improvement and New Features................................................................................................... 47

4.4.3 Pin Compatibility ........................................................................................................................... 47

5. Design Considerations ..................................................................................................................................... 48

5.1 Overlay Selection ...................................................................................................................................... 48

5.2 ESD Protection .......................................................................................................................................... 49

5.2.1 Prevent ......................................................................................................................................... 49

5.2.2 Redirect ................................................................ ........................................................................ 49

5.2.3 Clamp ........................................................................................................................................... 49

5.3 Electromagnetic Compatibility (EMC) Considerations ............................................................................... 49

5.3.1 Radiated Interference ................................................................................................................... 49

5.3.2 Radiated Emissions ...................................................................................................................... 50

5.3.3 Conducted Immunity and Emissions ............................................................................................. 50

5.4 Software Filtering ....................................................................................................................................... 50

5.5 Power Consumption .................................................................................................................................. 51

5.5.1 System Design Recommendations ............................................................................................... 51

5.5.2 Sleep-Scan Method ...................................................................................................................... 51

5.5.3 Response Time versus Power Consumption ................................................................................ 51

5.5.4 Measuring Average Power Consumption ..................................................................................... 52

5.6 Pin Assignments ........................................................................................................................................ 52

5.7 GPIO Load Transient ................................................................................................................................. 53

5.7.1 Hardware Guidelines to Reduce GPIO Load Transient Noise ...................................................... 54

5.7.2 Firmware Guidelines to Compensate GPIO Load Transient Noise ............................................... 55

5.8 PCB Layout Guidelines ............................................................................................................................. 57

6. Liquid-Tolerant Design Considerations .......................................................................................................... 58

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 4

Contents

6.1 Shield Electrode and Guard Sensor .......................................................................................................... 58

6.1.1 Shield ............................................................................................................................................ 58

6.1.2 Guard Sensor ............................................................................................................................... 61

6.2 Design Recommendations ........................................................................................................................ 63

7. Proximity Sensing Design Considerations ..................................................................................................... 64

7.1 Types of Proximity Sensors ....................................................................................................................... 64

7.1.1 Button ........................................................................................................................................... 64

7.1.2 Wire .............................................................................................................................................. 64

7.1.3 PCB Trace .................................................................................................................................... 64

7.1.4 Sensor Ganging ............................................................................................................................ 64

7.2 Design Recommendations ........................................................................................................................ 65

8. Low-Power Design Considerations ................................................................................................................. 66

8.1 Additional Power Saving Techniques ........................................................................................................ 66

8.1.1 Set Drive Modes to Analog HI-Z ................................................................................................... 66

8.1.2 Putting it All Together ................................................................................................................... 67

8.1.3 Recommended I2C Slave Implementation in Sleep Mode ............................................................ 67

8.1.4 Sleep Mode Complications ........................................................................................................... 67

8.1.5 Pending Interrupts ........................................................................................................................ 67

8.1.6 Global Interrupt Enable ................................................................................................................. 68

8.2 Post Wakeup Execution Sequence ........................................................................................................... 68

8.2.1 PLL Mode Enabled ....................................................................................................................... 68

8.2.2 Execution of Global Interrupt Enable ............................................................................................ 68

8.2.3 Recommended I2C Slave Implementation in Sleep Mode ............................................................ 68

8.2.4 Sleep Timer .................................................................................................................................. 69

9. Resources .......................................................................................................................................................... 70

9.1 Website ..................................................................................................................................................... 70

9.2 Datasheet ................................................................................................ .................................................. 70

9.3 Technical Reference Manual ..................................................................................................................... 70

9.4 Development Kits ...................................................................................................................................... 71

9.4.1 CY8C20xx7/S QuietZone Starter Kit ............................................................................................. 71

9.4.2 Universal CapSense Controller Kit ............................................................................................... 71

9.4.3 Universal CapSense Module Boards ............................................................................................ 71

9.5 Sample Board Files ................................................................................................................................... 72

9.6 PSoC Programmer .................................................................................................................................... 74

9.7 CapSense Data Viewing Tools .................................................................................................................. 74

9.8 PSoC Designer .......................................................................................................................................... 74

9.9 Code Examples ......................................................................................................................................... 74

9.10 Design Support .......................................................................................................................................... 74

Revision History ......................................................................................................................................................... 75

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 5

1. Introduction

1.1 Abstract

This document provides design guidance for implementing capacitive sensing (CapSense) functionality with the
CY8C20xx7/S family of CapSense controllers. The following topics are covered in this guide:

 Features of the CY8C20xx7/S family of CapSense controllers
 CapSense principles of operation
 Introduction to CapSense design tools
 Guide to tune the CapSense system for optimal performance
 System electrical and mechanical design considerations for CapSense
 Low-power design considerations for CapSense
 Additional resources and support for designing CapSense into your system

1.2 Cypress’s CapSense Documentation Ecosystem

Figure 1-1 and Table 1-1 summarize the Cypress CapSense documentation ecosystem. These resources allow

implementers to quickly access the information needed to successfully complete a CapSense product design.

Figure 1-1 shows the typical flow of a product design cycle with capacitive sensing; the information in this guide is

most pertinent to the topics highlighted in green. Table 1-1 provides links to the supporting documents for each of the
numbered tasks in Figure 1-1.

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 6

Introduction

3. CapSense device selection based
on needed functionality

2. Specify system requirements and

characteristics

11. Preproduction build (prototype)

12. Test and evaluate system functionality and
CapSense performance

Performance

satisfactory

13. Production

Yes

No

= Topics covered in this document

1. Understanding CapSense technology

4. Mechanical
design

5. Schematic
capture and

PCB layout

Design for CapSense

9. Programming PSoC

†

10. CapSense
Configuration*

6. PSoC Designer project

creation†

7. Firmware

development†

8. CapSense tuning†

*

†

= Applicable to MBR family of devices only

= Applicable to programmable devices only

Figure 1-1. Typical CapSense Product Design Flow

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 7

Introduction

Numbered Design Task

in Figure 1-1

Supporting Cypress CapSense Documentation

1

● Getting Started with CapSense

2

● Getting Started with CapSense

● CY8C20xx7/S CapSense Device Datasheet

3

● Getting Started with CapSense

● CY8C20xx7/S CapSense Design Guide (this document)

4

● Getting Started with CapSense

5

● Getting Started with CapSense

6

● PSoC® Designer™ User Guides

7

● Assembly Language User Guide

● C Language Compiler User Guide

● CapSense Code Examples

● PSoC CY8C20xx7/S Technical Reference Manual

8

● PSoC Family-Specific CapSense Design Guide (this document)

● PSoC Family-Specific CapSense User Module Datasheets (CSD, CSDPLUS, and

SmartSense_EMC_PLUS)

● PSoC CY8C20xx7/S Technical Reference Manual

● AN2397 -CapSense Data Viewing Tools

9

● Programmer User Guide

● MiniProg3 User Guide

● ISSP Programming Specifications - CY8C20045, CY8C20055, CY8C20065,

CY8C20xx6A,CY8C20xx7

● AN59389 - Host Sourced Serial Programming for CY8C20xx6A, CY8C20xx6AS, CY8C20xx6L, and

CY8C20xx7/S

11

● CY8C20xx7/S CapSense Design Guide (this document)

● CapSense Code Examples

Table 1-1. Cypress Documents Supporting Numbered Design Tasks of Figure 1-1

1.3 CY8C20xx7/S CapSense Family Features

Cypress‟s CY8C20xx7/S is a low-power, high-performance, programmable CapSense controller family that features:

Advanced Touch Sensing Features

 Programmable capacitive sensing elements

 Supports a combination of CapSense buttons, sliders, and proximity sensors
 Integrated API to implement buttons and sliders
 Supports up to 31a capacitive sensors or six slidersb
 Supports parasitic sensor capacitance range of 5 pF to 45 pF

 SmartSense™ Auto-tuning enables fast time to market

 Sets and monitors tuning parameters automatically at power on and at runtime
 Design portability – self-tunes for changes in user interface design
 Environmental compensation during runtime
 Detects touches as low as 0.1 pF

 Enhanced noise immunity and robustness

a

It is assumed that two pins are used for I

b

See the CY8C20xx7/S datasheet for more information.

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 8

2

C communication and one pin is used for C

connection.

MOD

Introduction

 SmartSense_EMCPLUS compensates for environment and noise variations automatically
 SmartSense_EMCPLUS offers superior noise immunity for applications with challenging conducted and

radiated noise conditions

 Internal regulator provides stability against power supply noise and ripple up to 500 mV of supply VDD ripple

acceptable

 Integrated API of software filters for SNR improvement

 Ultra low power consumption

 Three different power modes for optimized power consumption
 Active, sleep, and deep-sleep modes (deep-sleep current: 100 nA)
 28 μA per sensor at 125 ms wake from sleep rate

 Driven shield available on five GPIO pins

 Delivers best-in-class water tolerant designs
 Robust proximity sensing in the presence of metal objects
 Supports longer trace lengths
 Maximum load of 100 pF (3 MHz)

Device Features

 High-performance, low-power M8C Harvard-architecture processor

 Up to 4 MIPS with 24-MHz internal clock

 Flexible on-chip memory

 Up to 32 KB of flash and 2 KB of SRAM
 Emulated EEPROM supported

 Precision, programmable clocking

 Internal main oscillator (IMO): 6/12/24 MHz ± 5%
 Option for precision 32-kHz external crystal oscillator

 Enhanced general-purpose input/output (GPIO) features

 34 GPIOs with programmable pin configuration.
 25 mA sink current/GPIO and 120 mA total sink current/device
 Internal restive pull-up, HI-Z, open-drain, and strong drive modes on all GPIOs

 Peripheral features

 Three 16-bit timers
 I2C - master (100 kHz) and slave (400 kHz)
 SPI - master and slave - configurable range of 46.9 kHz to 12 MHz
 10-bit incremental ADC - 0 to 1.2-V input range

 Operating conditions

 Wide operating voltage: 1.71 V to 5.5 V
 Temperature range: –40 °C to +85 °C

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 9

Introduction

Convention

Usage

Courier New

Displays file locations, user entered text, and source code:
C:\ ...cd\icc\

Italics

Displays file names and reference documentation:
Read about the sourcefile.hex file in the PSoC Designer User Guide.

[Bracketed, Bold]

Displays keyboard commands in procedures:
[Enter] or [Ctrl] [C]

File > Open

Represents menu paths:
File > Open > New Project

Bold

Displays commands, menu paths, and icon names in procedures:
Click the File icon and then click Open.

Times New Roman

Displays an equation:
2 + 2 = 4

Text in gray boxes

Describes Cautions or unique functionality of the product.

1.4 Document Conventions

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 10

2. CapSense Technology

2.1 CapSense Fundamentals

CY8C20xx7/S

C

MOD

Sensor 1

C

X,1

Sensor 2

C

X,2

Sensor 3

C

X,3

Sensor 4

C

X,4

Sensor n

C

X,n

CapSense is a touch-sensing technology, which works by measuring the capacitance of each I/O pin on the
CapSense controller that has been designated as a sensor. As shown in Figure 2-1, the total capacitance on each
sensor pin can be modeled as equivalent lumped capacitors with values of CX,1 through CX,n for a design with n
sensors. The circuitry internal to the CY8C20xx7/S device converts the magnitude of each CX into a digital code that
is stored for post processing. The other component, C
will be discussed in more detail in Capacitive Sensing Methods in CY8C20xx7/S.

Figure 2-1. CapSense Implementation in a CY8C20xx7/S PSoC Device

, is used by the CapSense controller‟s internal circuitry and

MOD

As shown in Figure 2-1, each sensor I/O pin is connected to a sensor pad by traces, vias, or both, as necessary. The
overlay is a nonconductive cover over the sensor pad that constitutes the product‟s touch interface. When a finger
comes into contact with the overlay, the conductivity and mass of the body effectively introduces a grounded
conductive plane parallel to the sensor pad. This is represented in Figure 2-2. This arrangement constitutes a parallel
plate capacitor, whose capacitance is given by:

0



=



Where:
CF = The capacitance added by a finger in contact with the overlay over a sensor

ε

= Free space permittivity

0

ε

= Dielectric constant (relative permittivity) of overlay

r

A = Area of finger and sensor pad overlap
D = Overlay thickness

Equation 2-1



CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 11

CapSense Technology

Figure 2-2. Section of Typical CapSense PCB with the Sensor Being Activated by a Finger

In addition to the parallel plate capacitance, a finger in contact with the overlay causes electric field fringing between
itself and other conductors in the immediate vicinity. The effect of these fringing fields is typically minor compared to
that of the parallel plate capacitor and can usually be ignored.

Even without a finger touching the overlay, the sensor I/O pin has some parasitic capacitance (CP). CP results from
the combination of the CapSense controller internal parasitics and electric field coupling between the sensor pad,

traces, and vias, and other conductors in the system such as ground plane, other traces, any metal in the product‟s

chassis or enclosure, and so on. The CapSense controller measures the total capacitance (CX) connected to a
sensor pin.

When a finger is not touching a sensor:

=  Equation 2-2

With a finger on the sensor pad, CX equals the sum of CP and CF:

= +  Equation 2-3

In general, CP is an order of magnitude greater than CF. CP usually ranges from 10 pF to 20 pF, but in extreme cases
can be as high as 50 pF. CF usually ranges from 0.1 pF to 0.4 pF. The magnitude of CP is of critical importance when
tuning a CapSense system and is discussed in CapSense Performance Tuning with User Modules.

2.2 Capacitive Sensing Methods in CY8C20xx7/S

CY8C20xx7/S devices support CSD, CSDPLUS, and SmartSense_EMCPLUS CapSense methods for converting
sensor capacitance (CX) into digital counts. The CSDPLUS method is the superset of the CSD method and has
several improvements when compared to CSD. These two methods are implemented in the hardware. The
SmartSense_EMCPLUS uses the autotuning algorithm implemented in firmware to automatically tune all the
CSDPLUS parameters. The CSD, CSDPLUS, and SmartSense_EMCPLUS methods are implemented in the form of
a PSoC Designer User Module and are described in the following sections.

2.2.1 CapSense Sigma Delta (CSD)

Figure 2-3 shows a block diagram of the CSD method for converting sensor capacitance (CX) into digital counts. This

method can be conceptually broken into two blocks – switched-capacitor input, which converts capacitance to current
and sigma delta converter, which converts current to digital counts. These blocks are explained in the following
sections.

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 12

CapSense Technology

Sigma Delta

Modulator

High Z

input

R

BUS

Modulation

I

DAC

C

X

Precharge

clock

CY8C20xx7/S

V

REF

Switched-capacitor input

circuit converts

capacitance to current

External Connection

C

MOD

2.2nF/X7R/5V

Sigma delta converter converts current to digital counts

Analog Mux

Bus

Sw2

Sw1

Analog Mux Bus
(AMUXBUS)

Discharge
Clock

Break-

Before-Make

Circuitry

Pin

C

X

Sw2

Sw1

Figure 2-3. CSD Block Diagram

2.2.1.1 Switched-Capacitor Input

The CSD method in the CY8C20xx7/S device incorporates CX into a switched capacitor circuit, as Figure 2-3 shows.

Figure 2-4. Pin Configured as Switched-Capacitor Input

Two non-overlapping, out-of-phase clocks of frequency FSW (see Figure 2-6) control the switches Sw1 and Sw2. The
continuous switching of Sw1 and Sw2 forms an equivalent resistance RS, as Figure 2-5 shows. The value of the
equivalent resistance RS is:

CX F

1

Equation 2-4

SW

RS=

Where:
CX = Sensor capacitance
FSW = Frequency of the switching clock

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 13

CapSense Technology

C

X

R

S

AMUXBUS

Sw

1

Sw

2

AMUXBUS

I

SENSOR

I

SW

I

SENSOR

V

t

V

REF

(1V)

0

TSW = 1/F

SW

Sw2 CLOSED
Sw1 OPEN

Sw2 OPEN
Sw1 CLOSED

Figure 2-5. Switched-Capacitor Input Sinking Current from AMUXBUS

The sigma delta converter maintains the voltage of AMUXBUS at a constant V

(this process is explained in Sigma

REF

Delta Converter). Figure 2-6 shows the voltage waveform across the sensor capacitance. Driving switches Sw1 and

Sw2 through non-overlapping precharge clocks thus results in an average current sink (I
as Equation 2-5 shows. The magnitude of I

I

SENSOR

= V



REFRS

= CX FSWV

Equation 2-5

REF

is directly proportional to the magnitude of CX.

SENSOR

) from the AMUXBUS

SENSOR

Figure 2-6. Voltage across Sensor Capacitance (CX)

2.2.1.2 Sigma Delta Converter

The sigma delta converter converts the input current to a corresponding digital count. It consists of a sigma delta
modulator and one current-sourcing digital-to-analog converter (I

The sigma delta modulator controls the 8-bit I
I

and is referred as “I

DAC

external integrating capacitor C

” or “modulation I

DAC

, as Figure 2-3 on page 13 shows. The recommended value of C

MOD

The sigma delta modulator switches the modulation I
across C

, to maintain the C

MOD

voltage at V

MOD

current in an on/off manner. This I

DAC

in this document. The sigma delta converter also requires an

DAC”

ON or OFF corresponding to the small voltage variations

DAC

.

REF

In maintaining the average AMUX voltage at a steady state value (V
average charge current (I

DAC

) to I

by controlling the modulation bit stream duty cycle. The sigma delta converter

SENSOR

stores the bit stream over the duration of a sensor scan and the accumulated result is a digital output value, known as
raw count, which is proportional to CX.

The sigma delta converter can operate from 9-bit to 16-bit resolutions. If „N‟ is the resolution of the sigma delta
converter and I

raw count = (2

The raw count is interpreted by high-level algorithms to resolve the sensor state and detect touches. Figure 2-7 plots
the CSD raw counts from a number of consecutive scans during which the sensor is touched and then released by a
finger. As explained in CapSense Fundamentals, the finger touch causes CX to increase by CF, which in turn causes

is the value of the modulation I

DAC

V

N

 1)

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 14

REF FSW CX

I

DAC

current, the approximate equation for the raw count is

DAC

Equation 2-6

), as Figure 2-3 on page 13 shows.

DAC

is known as the modulation

DAC

), the sigma delta converter matches the

REF

is 2.2 nF.

MOD

CapSense Technology

raw counts to increase proportionally. By comparing the shift in steady state raw count level to a predetermined
threshold, the high-level algorithms can determine whether the sensor is in the ON (touch) or OFF (no touch) state.

Figure 2-7. CSD Raw Counts during a Finger Touch

The hardware parameters or the CSD/CSDPLUS User Module Low-Level Parameters such as I

and FSW, and the

DAC

firmware parameters or the User Module High-Level Parameters should be tuned to optimum values for reliable touch
detection. For a detailed discussion on tuning, see CapSense Performance Tuning with User Modules.

2.2.2 CapSense Sigma Delta (CSD) PLUS

Figure 2-8 shows a block diagram of the CSDPLUS method for converting sensor capacitance (CX) into digital

counts. The main difference between CSDPLUS and CSD method is the number of I
I

and the CSD uses a single I

DACs

DAC

.

used; CSDPLUS uses two

DACs

The CSDPLUS method can be conceptually broken into two blocks – switched-capacitor input, which converts
capacitance to current and sigma delta converter, which converts current to digital counts. Each block is explained in
the following sections.

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 15

CapSense Technology

Sigma Delta

Modulator

High Z

input

R

BUS

Modulation

I

DAC

Compensation

I

DAC

C

X

Precharge

clock

CY8C20xx7/S

V

REF

Switched-capacitor input

circuit converts

capacitance to current

External Connection

C

MOD

2.2 nF/X7R/5 V

Sigma delta converter converts current to digital counts

Analog Mux

Bus

Sw2

Sw1

Analog Mux Bus
(AMUXBUS)

Discharge
Clock

Break-

Before-Make

Circuitry

Pin

C

X

Sw2

Sw1

Figure 2-8. CSDPLUS Block Diagram

2.2.2.1 Switched-Capacitor Input

The CSDPLUS method in CY8C20xx7/S devices incorporates CX into a switched-capacitor circuit, as Figure 2-9
shows.

Figure 2-9. Pin Configured as Switched-Capacitor Input

Two non-overlapping, out-of-phase clocks of frequency FSW (see Figure 2-11) control switches Sw1 and Sw2. The
continuous switching of Sw1 and Sw2 forms an equivalent resistance RS, as Figure 2-10 shows. The value of the
equivalent resistance RS is:

RS=

1

Equation 2-7

CX F

SW

Where:
CX = Sensor capacitance
FSW = Frequency of the switching clock

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 16

CapSense Technology

C

X

R

S

AMUXBUS

Sw

1

Sw

2

AMUXBUS

I

SENSOR

I

SW

I

SENSOR

V

t

V

REF

(1V)

0

TSW = 1/F

SW

Sw2 CLOSED
Sw1 OPEN

Sw2 OPEN
Sw1 CLOSED

raw count = (2

N

 1)

V

REF FSW

I

DAC

C

X

 (2N 1)

I

COMP

I

DAC

Equation 2-9

Figure 2-10. Switched Capacitor Input Sinking Current from AMUXBUS

The sigma delta converter maintains the voltage of AMUXBUS at a constant V

(this process is explained in Sigma

REF

Delta Converter). Figure 2-11 shows the voltage waveform across the sensor capacitance. Driving switches Sw1 and

Sw2 through non-overlapping precharge clocks thus results in an average current sink (I
as Equation 2-8 shows. The magnitude of I

I

SENSOR

= V



REFRS

= CX FSWV

Equation 2-8

REF

is directly proportional to the magnitude of CX.

SENSOR

) from the AMUXBUS

SENSOR

Figure 2-11. Voltage across Sensor Capacitance (CX)

2.2.2.2 Sigma Delta Converter

The sigma delta converter converts the input current to a corresponding digital count. It consists of a sigma delta
modulator and two current-sourcing digital-to-analog converters (I

The sigma delta modulator controls the one 7-bit I
modulation I
compensation I

and is referred as “I

DAC

, is either always ON or always OFF. This I

DAC

” or “modulation I

DAC

current in an on/off manner. This I

DAC

DAC”

document.
The sigma delta converter also requires an external integrating capacitor C

recommended value of C
corresponding to the small voltage variations across C

is 2.2 nF. The sigma delta modulator switches the modulation I

MOD

, to maintain the C

MOD

In maintaining the average AMUX voltage at a steady state value (V
average charge current (I

DAC

) to I

by controlling the modulation bit stream duty cycle. The sigma delta converter

SENSOR

stores the bit stream over the duration of a sensor scan and the accumulated result is a digital output value, known as
raw count, which is proportional to CX.

The sigma delta converter can operate from 9-bit to 16-bit resolutions. If „N‟ is the resolution of the sigma delta
converter, I

is the value of the modulation I

DAC

current and I

DAC

equation for the raw count is

Note that raw count values are always positive. Thus, I

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 17

should always be less than 2N V

COMP

), as Figure 2-8 on page 16 shows.

DACs

in this document. The other 7-bit I

is referred as “Compensation I

DAC

, as Figure 2-8 on page 16 shows. The

MOD

voltage at V

MOD

), the sigma delta converter matches the

REF

is the compensation I

COMP

REF

current, the approximate

DAC

REF FSW

is known as the

DAC

, known as the

DAC

” or “I

DAC

COMP

ON or OFF

DAC

.

.

” in this

CapSense Technology

The raw count is interpreted by high-level algorithms to resolve the sensor state and detect touches. Figure 2-12 plots
the CSD raw counts from a number of consecutive scans during which the sensor is touched and then released by a
finger. As explained in CapSense Fundamentals, the finger touch causes CX to increase by CF, which in turn causes
raw counts to increase proportionally. By comparing the shift in steady state raw count level to a predetermined
threshold, the high-level algorithms can determine whether the sensor is in the ON (touch) or OFF (no touch) state.

Figure 2-12. CSD Raw Counts during a Finger Touch

The hardware parameters or the CSD/CSDPLUS User Module Low-Level Parameters such as I
and the firmware parameters or the User Module High-Level Parameters should be tuned to optimum values for
reliable touch detection. For a detailed discussion on tuning, see CapSense Performance Tuning with User Modules.

DAC, ICOMP

, and FSW,

2.2.3 SmartSense_EMCPLUS Auto-Tuning

Tuning the touch-sensing user interface is a critical step in ensuring proper system operation and a pleasant user
experience. The typical design flow involves tuning the sensor interface in the initial design phase, during system
integration, and finally production fine-tuning before the production ramp. Tuning is an iterative process and can be
time consuming. SmartSense_EMCPLUS Auto-Tuning was developed to simplify the user interface development
cycle. The process is easy to use and significantly reduces the design cycle time by eliminating the tuning process
throughout the entire product development cycle, from prototype to mass production. SmartSense_EMCPLUS tunes
each CapSense sensor automatically at power-up and then monitors and maintains optimum sensor performance
during runtime. This technology adapts for manufacturing variation in PCBs, overlays, and noise generators such as
LCD inverters, AC line noise, and switch-mode power supplies, and automatically tunes them out.

2.2.3.1 Process Variation

The SmartSense_EMCPLUS User Module (UM) for the CY8C20xx7/S is designed to work with sensor parasitic
capacitance in the range 5 pF to 45 pF, (typical sensor CP values are in the range 10 pF to 20 pF). The sensitivity
parameter for each sensor is set automatically, based on the characteristics of that particular sensor. This improves
the yield in mass production, because consistent response is maintained from every sensor regardless of CP variation
between sensors within the specified range (5 pF to 45 pF). Parasitic capacitance of the individual sensors can vary
due to PCB layout, PCB manufacturing process variation, or with vendor-to-vendor PCB variation within a
multisourced supply chain. The sensitivity of a sensor depends on its parasitic capacitance; higher CP values
decrease the sensor sensitivity and result in decreased finger touch signal amplitude. In some cases, the change in
CP value detunes the system, resulting in less than optimum sensor performance (either too sensitive or not sensitive
enough) or worst case, a nonoperational sensor. In either situation, you must retune the system, and in some cases
requalify the UI subsystem. SmartSense_EMCPLUS Auto-Tuning solves these issues.

SmartSense_EMCPLUS Auto-Tuning makes platform designs possible. Imagine the capacitive touch-sensing
multimedia keys in a laptop computer; the spacing between the buttons depends on the size of the laptop and
keyboard layout. In this example, the wide-screen machine has larger spaces between the buttons than a standard­screen model. More space between buttons means increased trace length between the sensor and the CapSense
controller, which leads to higher parasitic capacitance of the sensor. This means that the parasitic capacitance of the
CapSense buttons can be different in different models (Figure 2-13 and Figure 2-14) of the same platform design.
Though the functionality of these buttons is the same for all laptop models, the sensors must be tuned for each
model. SmartSense_EMCPLUS enables you to do platform designs using the recommended best practices shown in
the PCB Layout in Getting Started with CapSense, knowing the tuning will be done efficiently and automatically.

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 18

CapSense Technology

Feasibility

Study

Schematics

Design

PCB Layout

Design

Mechanical Design

Review

System

Integration

Re-tuning for any

changes

Tuning process

Production Fine

Tuning

Design

Validation

Production

Typical Capacitive User Interface Design Cycle

Firmware

Development

Feasibility

Study

Schematics

Design

PCB Layout

Design

Mechanical Design

Review

System

Integration

Design

Validation

Production

SmartSense-based Capacitive User Interface Design Cycle

Firmware

Development

Figure 2-13. Design of Laptop Multimedia Keys for a 21-Inch Model

Figure 2-14. Design of Laptop Multimedia Keys for a 15-Inch Model with Identical Functionality and Button Size

2.2.3.2 Reduced Design Cycle Time

Usually, the most time-consuming task for a capacitive sensor interface design is firmware development and sensor
tuning. With a typical touch-sensing controller, the sensor must be retuned when the same design is ported to
different models or when there are changes in the mechanical dimensions of the PCB or the sensor PCB layout. A
design with SmartSense_EMCPLUS solves these challenges because it needs less firmware development effort, no
tuning, and no retuning. This makes a typical design cycle much faster. Figure 2-15 compares the design cycles of a
typical touch-sensing controller and a SmartSense_EMC_PLUS-based design.

Figure 2-15. Typical Capacitive Interface Design Cycle Comparison

2.2.4 Selecting the User Module

The SmartSense_EMCPLUS eliminates the tuning process that is required by CSD and CSDPLUS UM. It is
recommended to use SmartSense_EMCPLUS to simplify the CapSense design process. However, there may be
instances where the sensor parameters such as resolution and prescaler need to be controlled to optimize device
power consumption or detect touch for a sensor with high CP. In such cases, use the CSD/CSDPLUS UM.

The following are the advantages of the CSDPLUS UM when compared to CSD:

 CSDPLUS UM provides higher SNR for a given sensor resolution (or scan time).
 CSDPLUS UM requires less time to scan a sensor to achieve the same SNR. Because of the short scan time,

the average power consumptiona of the CapSense device with CSDPLUS UM will be lower than the CSD UM
when they are tuned to achieve the same SNR.

However, if the sensor CP is below 10 pF, the CSDPLUS UM provides lower SNR when compared to the CSD UM
and it is recommended to use the CSD UM instead of the CSDPLUS UM.

Note: When I

a

Here the device is assumed to enter sleep mode after scanning the sensor and wakeup periodically to reduce the device power

consumption.

is set to „0‟, the CSDPLUS UM behavior will be the same as the CSD UM.

COMP

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 19

3. CapSense Design Tools

3.1 Overview

Cypress offers a full line of hardware and software tools for developing your CapSense capacitive touch-sensing
application. See Resources for ordering information.

3.1.1 PSoC Designer and User Modules

Cypress‟s exclusive integrated design environment, PSoC Designer, allows you to configure analog and digital

blocks, develop firmware, and tune and debug your design. Applications are developed in a drag-and-drop design
environment using a library of user modules. User modules are configured either through the Device Editor GUI or by
writing into specific registers with firmware. PSoC Designer comes with a built-in C compiler and an embedded
programmer. A pro compiler is available for complex designs.

The CSD and CSDPLUS User Module implements capacitive touch sensors using switched-capacitor circuitry, an
analog multiplexer, a comparator, digital counting functions, and high-level software routines (APIs). User modules for
other analog and digital peripherals are available to implement additional functionality such as I2C, SPI, TX8, and
timers.

Figure 3-1. PSoC Designer Device Editor

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 20

CapSense Design Tools

3.1.1.1 Getting Started with CapSense User Modules

To create a new CY8C20xx7/S project in PSoC Designer:

1. Create a new PSoC Designer project with CY8C20xx7/S as the target device.

2. Select and place the CSDPLUS/SmartSense_EMCPLUS User Module.

3. Right-click the user module to access the User Module wizard.

4. Set button sensor count, slider configuration, pin assignments, and associations.

5. Set pins and global user module parameters.

6. Generate the application and switch to the Application Editor.

7. Adapt sample code from the user module datasheet to implement buttons or sliders.
For a detailed procedure for creating a PSoC Designer project and configuring the User Module wizard, refer to the

datasheet of the specific user module. For code examples on CapSense user modules, see Code Examples.

3.1.2 CY8C20xx7/S QuietZone Starter Kit

The CY8C20xx7/S QuietZone Starter Kit features simple plug-in hardware to make prototyping easy. The kit is
available from our module partner ArtaFlex at the following link: www.artaflexmodules.com/quietzone

Figure 3-2. CY8C20xx7/S QuietZone Starter Kit

3.1.3 CapSense Data Viewing Tools

Many times during CapSense design, you will want to monitor CapSense data (raw counts, baseline, difference
counts, and so on) for tuning and debugging purposes. There are two CapSense data viewing tools, MultiChart and
Bridge Control Panel. These tools are explained in the application note AN2397 – CapSense Data Viewing Tools.

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 21

CapSense Design Tools

Raw Count

Difference
Count

3.2 User Module Overview

Figure 3-3. User Module Block Diagram

User modules contain an entire CapSense system from physical sensing to data processing. The behavior of the user
module is defined using a variety of parameters. These parameters affect different parts of the sensing system and
can be separated into low-level and high-level parameters that communicate with one another using global arrays.

Low-level parameters define the behavior of the sensing method at the physical layer and relate to the conversion
from capacitance to raw count such as the speed and resolutions for scanning sensors. Low-level parameters are
unique to each type of sensing method and are described in CSD/CSDPLUS User Module Low-Level Parameters
and SmartSense_EMCPLUS User Module Parameters.

High-level parameters, such as debounce counts and noise thresholds, define how the raw counts are processed to
produce information such as the sensor ON/OFF state and the estimated finger position on a slider. These
parameters are the same for all sensing methods and are described in User Module High-Level Parameters.

3.3 CapSense User Module Global Arrays

Before learning CapSense User Module parameters, you must be familiar with certain global arrays used by the
CapSense system. These arrays should not be altered manually, but may be inspected for debugging purposes.

Figure 3-4. Raw Count, Baseline, Difference Count, and Sensor State

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 22

CapSense Design Tools

3.3.1 Raw Count

The hardware circuit in the CapSense controller measures the sensor capacitance CX. The circuit stores the result in
a digital form called raw count upon calling the user module API UMname_ScanSensor(), where UMname can be
CSD, CSDPLUS, or SmartSenseEMC_PLUS.

The raw count of a sensor is proportional to its sensor capacitance. Raw count increases as the sensor capacitance
value increases.

The raw count values of sensors are stored in the UMname_waSnsResult[] integer array. This array is defined in the
header file UMname.h.

3.3.2 Baseline

Baseline can be considered as the raw count value corresponding to the parasitic capacitance of sensor, CP. Gradual
environmental changes such as temperature and humidity affect the sensor CP and hence CX, which results in
variations in the raw counts.

The user module uses a complex baselining algorithm to compensate for these variations. The algorithm uses
baseline variables to accomplish this. The baseline variables keep track of any gradual variation in raw count values.
Essentially, the baseline variables hold the output of a digital low-pass filter to which raw count values are input.

The baselining algorithm is executed by the user module API UMname_UpdateSensorBaseline, where UMname can
be CSD, CSDPLUS, or SmartSense_EMC_PLUS.

The baseline values of sensors are stored in UMname_waSnsBaseline[] integer array. This array is defined in the
header file UMname.h.

3.3.3 Difference Count (Signal)

The difference count, which is also known as the signal of a sensor, is defined as the difference in counts between a
sensor‟s raw count and baseline values. When the sensor is inactive, the difference count is zero. Activating sensors
(by touching) results in a positive difference count value.

The difference count values of sensors are stored in the UMname_waSnsDiff[] integer array, where UMname can be
CSD, CSDPLUS, or SmartSense_EMC_PLUS. This array is defined in the header file UMname.h.

Difference count variables are updated by the user module API UMname_UpdateSensorBaseline().

3.3.4 Sensor State

Sensor state represents the active/inactive status of the physical sensors. The state of the sensor changes from 0 to
1 upon finger touch and returns to 0 upon finger release.

Sensor states are stored in a byte array named UMname_baSnsOnMask[] array, where UMname can be CSD,
CSDPLUS, or SmartSense_EMCPLUS. This array is defined in the header file UMname.h. Each array element stores
the sensor state of eight consecutive sensors.

Sensor states are updated by the user module API UMname_bIsAnySensorActive().

3.4 CSD/CSDPLUS User Module Parameters

The CSD/CSDPLUS User Module parameters are classified into high-level and low-level parameters. See Figure 3-5
for a list of CSDPLUS user module parameters and how they are classified. The only difference between the CSD
and CSDPLUS UM parameter window is that the CSD UM does not have Compensation iDAC Value.

CY8C20xx7/S CapSense® Design Guide Doc. No. 001-78329 Rev. *E 23