Cypress CY8C20x46, CY8C20x36, CY8C20x66, CY8C20396 User Manual
CapSense™ Applications
CY8C20x36/46/66, CY8C20396
Features
■ 1.71V to 5.5V Operating Range
■ Low Power CapSense™ Block
❐ Configurable Capacitive Sensing Elements
❐ Supports Combination of CapSense Buttons, Sliders,
Touchpads, Touch Screens, and Proximity Sensor
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds Running to 24 MHz
❐ Low Power at High Speed
❐ Interrupt Controller
❐ Temperature Range: -40°C to +85°C
■ Flexible On-Chip Memory
❐ Three Program/Data Storage Size Options:
• CY8C20x36: 8K Flash / 1K SRAM
• CY8C20x46: 16K Flash / 2K SRAM
• CY8C20x66: 32K Flash / 2K SRAM
❐ 50,000 Flash Erase/Write Cycles
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ In-System Serial Programming (ISSP)
■ Full-Speed USB
❐ Available on CY8C20396 and CY8C20666 Only
❐ 12 Mbps USB 2.0 Compliant
❐ Eight Unidirectional Endpoints
❐ One Bidirectional Control Endpoint
❐ Dedicated 512 Byte Buffer
❐ Internally Regulated at 3.3V
■ Precision, Programmable Clocking
❐ Internal Main Oscillator: 6/12/24 MHz ± 5%
❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and
Sleep Timers
❐ Precision 32 kHz Oscillator for Optional External Crystal
(CY8C20x46/66 only)
❐ 0.25% Accuracy for USB with No External Components
(CY8C20396 and CY8C20666 only)
■ Programmable Pin Configurations
❐ Up to 36 GPIO (Depending on Package)
❐ Dual Mode GPIO: All GPIO Support Digital IO and Analog
Input
❐ 25 mA Sink Current on All GPIO
❐ Pull up, High Z, Open Drain Modes on All GPIO
❐ CMOS Drive Mode(5 mA Source Current) on Ports 0 and 1:
• 20 mA (at 3.0V) Total Source Current on Port 0
• 20 mA (at 3.0V) Total Source Current on Port 1
❐ Selectable, Regulated Digital IO on Port 1
❐ Configurable Input Threshold on Port 1
❐ Hot Swap Capability on all Port 1 GPIO
■ Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous Connection of IO
❐ High PSRR Comparator
❐ Low Dropout Voltage Regulator for All Analog Resources
■ Additional System Resources
2
❐ I
C™ Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• No Clock Stretching Required (under most conditions)
• Implementation During Sleep Modes with Less Than
100 µA
• Hardware Address Validation
❐ SPI™ Master and Slave: Configurable 46.9 kHz - 12 MHz
❐ Three 16-Bit Timers
❐ Watchdog and Sleep Timers
❐ Internal Voltage Reference
❐ Integrated Supervisory Circuit
■ Complete Development Tools
❐ Free Development Tool (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
■ Package Options
❐ CY8C20x36:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
❐ CY8C20x46:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
❐ CY8C20396: 24-Pin 4 x 4 x 0.6 mm QFN
❐ CY8C20x66:
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
• 48-Pin SSOP
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-12696 Rev. *D Revised March 17, 2009
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Block Diagram
CAPSENSE
SYSTEM
1K/2K
SRAM
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
Internal Low Speed Oscillator (ILO)
6/12/24 MHz Internal Main Oscillator
(IMO)
PSoC CORE
CPU Core (M8C)
Supervisory ROM (SROM)
8K/16K/32K Flash
Nonvolatile Memory
SYSTEM RESOURCES
SYSTEM BUS
Analog
Reference
SYSTEM BUS
Port 3 Port 2 Port 1 Port 0
CapSense
Module
Global Analog Interconnect
1.8/2.5/3V
LDO
Analog
Mux
Two
Comparators
I2C
Slave
SPI
Master/
Slave
POR
and
LVD
USB
System
Resets
Internal
Voltage
References
Three 16-Bit
Programmable
Timers
PWRSYS
(Regulator)
Port 4
Digital
Clocks
Document Number: 001-12696 Rev. *D Page 2 of 34
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IDAC
Reference
Buffer
Vr
Cinternal
Analog Global Bus
Cap Sense Counters
Comparator
Mux
Mux
Refs
CapSense
Clock Select
Oscillator
CSCLK
IMO
PSoC® Functional Overview
The PSoC family consists of on-chip Controller devices. These
devices are designed to replace multiple traditional MCU-based
components with one, low cost single-chip programmable
component. A PSoC device includes configurable analog and
digital blocks, and programmable interconnect. This architecture
allows the user to create customized periphe ral configurations,
to match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of
convenient pinouts.
The architecture for this device family, as shown in the Block
Diagram on page 2, is comprised of three main areas: the Core,
the CapSense Analog System, and the System Resources
(including a full speed USB port). A common, versatile bus allows
connection between IO and the analog system. Each
CY8C20x36/46/66, CY8C20396 PSoC device includes a
dedicated CapSense block that provides sensing and scanning
control circuitry for capacitive sensing applications. Depending
on the PSoC package, up to 36 general purpose IO (GPIO) are
also included. The GPIO provides access to the MCU and
analog mux.
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.
System Resources provide additional capability, such as
configurable USB and I2C slave/SPI master-slave
communication interface, three 16-bit programmable timers, and
various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block
and an internal 1.2V analog reference, which together support
capacitive sensing of up to 36 inputs.
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports.
Figure 1. Analog System Block Diagram
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin . Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Complex capacitive sensing interfaces, such as sliders and
touchpads.
■ Chip-wide mux that allows analog input from any IO pin.
■ Crosspoint connection between any IO pin combinations.
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under http://www.cypress.com >>
Documentation >> Application Notes. In general, and unless
otherwise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
Document Number: 001-12696 Rev. *D Page 3 of 34
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Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include low voltage detection and
power on reset. The merits of each system resource are listed
here:
■ The I2C slave/SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
■ The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power-On-Reset) circuit eliminates the need for a system
supervisor.
■ An internal reference provides an absolute reference for capac-
itive sensing.
■ The 5.5V maximum input, 1.8/2.5/3V-selectable output, low-
dropout regulator (LDO) provides regulation for IOs. A registercontrolled bypass mode allows the user to disable the LDO.
■ Standard Cypress PSoC IDE tools are available for debugging
the CY8C20x36/46/66, CY8C20396 family of parts. However,
the additional trace length and a minimal ground plane in the
Flex-Pod can create noise problems that make it difficult to
debug a Power PSoC design. A custom bonded On-Chip
Debug (OCD) device is available in an 48-pin QFN package.
The OCD device is recommended for debugging designs that
have high current and/or high analog accuracy requirements.
The QFN package is compact and is connected to the ICE
through a high density connector.
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming
details, see the PSoC
Technical Reference Manual for CY8C28xxx PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet, DigiKey, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
®
Programmable System-on-Chip™
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at 1-800541-4736.
Document Number: 001-12696 Rev. *D Page 4 of 34
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Development Tools
PSoC Designer™ is a Microsoft® Windows-based, integrated
development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Express. In this
view you solve design problems the same way you might think
about the system. Select input and output devices based upon
system requirements. Add a communication interface and define
the interface to the system (registers). Define when and how an
output device changes state based upon any/all other system
devices. Based upon the design, PSoC Designer automatically
selects one or more PSoC devices that match your system
requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.x. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over onchip resources. All views of the project share common code
editor, builder , and common debug, emulation, and programming
tools.
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Document Number: 001-12696 Rev. *D Page 5 of 34
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of
pre-built, pre-tested hardware peripheral components. In the
system-level view these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces (I2Cbus, for example), and the logic to control how they interact with
one another (called valuators).
In the chip-level view the components are called “user modules.”
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and progra mma ble
system-on-chip varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or b y
selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the IO pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions.
In the system-level view selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog-todigital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, you perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high-level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the In-Circuit
Emulator (ICE) where it runs at full speed. PSoC Designer
debugging capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations and external signals.
Document Number: 001-12696 Rev. *D Page 6 of 34
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 1. Acronyms
Acronym Description
AC alternating current
API application programming interface
CPU central processing unit
DC direct current
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
POR pow er on r eset
PPOR precision power on reset
PSoC® Programmable System-on-Chip™
SLIMO slow IMO
SRAM static random access memory
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 9 on page 15 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Document Number: 001-12696 Rev. *D Page 7 of 34
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Pinouts
QFN
(Top View)
AI, XOut, P2[5]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[ 3 ]
1
2
3
4
11
10
9
161514
13
P0[3], AI
P0[7], AI
Vdd
P0[4], AI
AI, CLK
1
, SPI MOSI, P1[1]
AI, DATA
1
, I2C SDA, SPI CLK, P1[0]
P1[2], AI
AI, XIn, P2[3]
P1[4], EXTCLK, AI
XRES
P0[1], AI
Vss
12
567
8
Notes
1. These are the ISSP pins, which are not High Z at POR (Power On Reset).
2. During power up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues.
The CY8C20x36/46/66, CY8C20396 PSoC device is available in a variety of packages which are listed and illustrated in the following
tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and
XRES are not capable of Digital IO.
16-Pin QFN
Table 2. Pin Definitions - CY8C20236, CY8C20246 PSoC Device
Pin
No.
Type
Digital Analog
Name Description
[2]
1 IO I P2[5] Crystal output (XOut)
2 IO I P2[3] Crystal input (XIn)
3 IOHR I P1[7] I 2C SCL, SPI SS
4 IOHR I P1[5] I2C SDA, SPI MISO
5 IOHR I P1[3] SPI CLK
6 IOHR I P1[1] ISSP CLK
[1]
, I2C SCL, SPI
MOSI
7 Power Vss Ground connection
8 IOHR I P1[0] ISSP DATA
[1]
, I2C SDA, SPI
CLK
9 IOHR I P1[2]
10 IOHR I P1[4] Optional external clock
(EXTCLK)
11 Input XRES Active high external reset with
internal pull down
12 IOH I P0[4]
13 Power Vdd Supply voltage
14 IOH I P0[7]
15 IOH I P0[3] Integrating input
16 IOH I P0[1] Integrating input
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Figure 2. CY8C20236, CY8C20246 PSoC Device
Document Number: 001-12696 Rev. *D Page 8 of 34
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24-Pin QFN
Note
3. The center pad (CP) on the QFN package must be connected t o gr ound (Vss) for be st mechanical, thermal, an d electrical perf ormance . If not connected t o ground , it
must be electrically floated and not connected to any other signal.
AI, DATA
2
, I2C SDA, SPI CLK, P1[0]
QFN
(Top View)
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[2], AI
P0[0], AI
2423222120
19
P0[3], AI
P0[5], AI
P0[7], AI
Vdd
P0[4], AI
7
8
9
10
11
12
SPI MOSI, P1[1]
AI, P1[2]
AI, P2[1]
NC
P1[6], AI
AI, EXTCLK, P1[4]
XRES
P2[0], AI
P0[6], AI
AI, CLK
2
, I2C SCL
P0[1], AI
Vss
AI, XOut, P2[5]
AI, XIn, P2[3]
Table 3. Pin Definitions - CY8C20336, CY8C20346
Pin
No.
Type
Digital Analog
Name Description
[2, 3]
Figure 3. CY8C20336, CY8C20346 PSoC Device
1 IO I P2[5] Crystal output (XOut)
2 IO I P2[3] Crystal input (XIn)
3 IO I P2[1]
4 IOHR I P1[7] I2C SCL, SPI SS
5 IOHR I P1[5] I2C SDA, SPI MISO
6 IOHR I P1[3] SPI CLK
7 IOHR I P1[1] ISSP CLK
MOSI
[1]
, I2C SCL, SPI
8 NC No connection
9 Power Vss Ground connection
10 IOHR I P1[0] ISSP DATA
[1]
, I2C SDA, SPI
CLK
11 IOHR I P1[2]
12 IOHR I P1[4] Optional external clock input
(EXTCLK)
13 IOHR I P1[6]
14 Input XRES Active high external reset with
internal pull down
15 IO I P2[0]
16 IOH I P0[0]
17 IOH I P0[2]
18 IOH I P0[4]
19 IOH I P0[6]
20 Power Vdd Supply voltage
21 IOH I P0[7]
22 IOH I P0[5]
23 IOH I P0[3] Integrating input
24 IOH I P0[1] Integrating input
CP Power Vss Center pad must be connected
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
to ground
Document Number: 001-12696 Rev. *D Page 9 of 34
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24-Pin QFN with USB Pinout
P0[7]
I2C SDA, SPI MISO, P1[5]
USB D-
QFN
(Top View)
I2C SCL, SPI SS, P1[7]
SPI CLK, P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[0]
XRES
2423222120
19
P0[3]
P0[5]
P0[6]
P0[2]
7
8
9
10
11
12
ISSP CLK, I2C SCL, SPI MOSI, P1[1]
VDD
P2[1]
Vss
P1[2]
ISSP DATA, I2C SDA, P1[0]
P1[4], EXTCLK
P1[6]
P0[4]
P0[1], AI
USB D+
P2[5]
P2[3]
Figure 4. CY8C20396 PSoC Device
Table 4. Pin Definitions - CY8C20396 PSoC Device
Pin No.
1 IO I P2[5]
2 IO I P2[3]
3 IO I P2[1]
4 IOHR I P1[7] I2C SCL, SPI SS
5 IOHR I P1[5] I2C SDA, SPI MISO
6 IOHR I P1[3] SPI CLK
7 IOHR I P1[1] ISSP CLK, I2C SCL, SPI MOSI
8 Power VSS Ground
9 IO I D+ USB D+
10 IO I D- USB D11 Power VDD Supply
12 IOHR I P1[0] ISSP DATA, I2C SDA
13 IOHR I P1[2]
14 IOHR I P1[4] Optional external clock input
15 IOHR I P1[6]
16 RESET INPUT XRES Active high external reset with
17 IOH I P0[0]
18 IOH I P0[2]
19 IOH I P0[4]
20 IOH I P0[6]
21 IOH I P0[7]
22 IOH I P0[5]
23 IOH I P0[3] Integrating input
24 IOH I P0[1] Integrating input
CP Power VSS Thermal pad must be
LEGEND I = Input, O = Output, OH = 5 mA High O utput Drive, R = Regulated Output
Type
Digital Analog
Name Description
(EXTCLK)
internal pull down
connected to Ground
[2, 3]
Document Number: 001-12696 Rev. *D Page 10 of 34
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CY8C20x36/46/66, CY8C20396
32-Pin QFN
AI, P0[1]
AI, P2[7]
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, P2[1]
AI, P3[3]
QFN
(Top View)
9
10111213141516
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32313029282726
25
Vss
P0[3], AI
P0[7], AI
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
P0[0], AI
P2[6], AI
P3[0], AI
XRES
AI, I2C SDA, SPI MISO, P1[5]
AI, SPICLK, P1[3]
Vss
AI, P1[2]
AI, EXTCLK, P1[4]
AI, P1[6]
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P0[5], AI
AI, CLK
4
, I2C SCL, SPI MOSI, P1[1]
AI, DATA
1
, I2C SDA, SPI CLK, P1[0]
Table 5. Pin Definitions - CY8C20436/46/66 PSoC Device
Pin
No.
1 IOH I P0[1] Integrating input
2 IO I P2[7]
3 IO I P2[5] Crystal output (XOut)
4 IO I P2[3] Crystal input (XIn)
5 IO I P2[1]
6 IO I P3[3]
7 IO I P3[1]
8 IOHR I P1[7] I2C SCL, SPI SS
9 IOHR I P1[5] I2C SDA, SPI MISO
10 IOHR I P1[3] SPI CLK.
11 IOHR I P1[1] ISSP CLK
12 Power Vss Ground connection.
13 IOHR I P1[0] ISSP DATA
14 IOHR I P1[2]
15 IOHR I P1[4] Optional external clock input
16 IOHR I P1[6]
17 Input XRES Active high external reset with
18 IO I P3[0]
Type
Digital Analog
Name Description
[1]
, I2C SCL, SPI MOSI.
[1]
, I2C SDA., SPI CLK
(EXTCLK)
internal pull down
[2, 3]
Figure 5. CY8C20436/46/66 PSoC Device
19 IO I P3[2]
20 IO I P2[0]
21 IO I P2[2]
22 IO I P2[4]
23 IO I P2[6]
24 IOH I P0[0]
25 IOH I P0[2]
26 IOH I P0[4]
27 IOH I P0[6]
28 Power Vdd Supply voltage
29 IOH I P0[7]
30 IOH I P0[5]
31 IOH I P0[3] Integrating input
32 Power Vss Ground connection
CP Power Vss Center pad must be connected to
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
ground
Document Number: 001-12696 Rev. *D Page 11 of 34
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