CYPRESS CY8C20534, CY8C20434, CY8C20334, CY8C20234 User Manual
CY8C20534, CY8C20434
CY8C20334, CY8C20234
PSoC® Mixed-Signal Array
Features
Logic Block Diagram
SRAM
512 Bytes
System Bus
Interrupt
Controller
6/12 MHz Internal Main Oscillator
Global Analog Interconnect
PSoC
CORE
CPU Cor e
(M8C)
SROM Flash 8K
SYSTEM RESOURCES
ANALOG
SYSTEM
Analog
Ref.
I2C Slave/SPI
Master-Slave
POR and LVD
System Re sets
Port 1 Port 0
Sleep and
Watchdog
Analog
Mux
Port 3 Port 2
CapSense
Block
Config LDO
■ Low Power CapSense Block
❐ Configurable Capacitive Sensing Elements
❐ Supports Combination of CapSense Buttons, Sliders, Touch-
pads, and Proximity Sensors
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds Running up to 12 MHz
❐ Low Power at High Speed
❐ 2.4V to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
■ Flexible On-Chip Memory
❐ 8K Flash Program Storage
50,000 Erase/Write Cycles
❐ 512 Bytes SRAM Data Storage
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ Interrupt Controller
❐ In-System Serial Programming (ISSP)
■ Complete Development Tools
❐ Free Development Tool (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator, and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
■ Precision, Programmable Clocking
❐ Internal ±5.0% 6/12 MHz Main Oscillator
❐ Internal Low Speed Oscillator at 32 kHz for W atchdog and Sl eep
■ Programmable Pin Configurations
❐ Pull Up, High Z, Open Drain, and CMOS Drive Modes on All
GPIO
❐ Up to 28 Analog Inputs on GPIO
❐ Configurable Inputs on All GPIO
❐ Selectable, Regulated Digital IO on Po rt 1
• 3.0V, 20 mA Total Port 1 Source Current
• 5 mA Strong Drive Mode on Port 1 Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous Connection of IO Combinations
❐ Comparator Noise Immunity
❐ Low Dropout Voltage Regulator for the Analog Array
■ Additional System Resources
❐ Configurable Communication Speeds
•I2C: Selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: Configurable between 46.9 kHz and 3 MHz
2
❐ I
C™ Slave
❐ SPI Master and SPI Slave
❐ Watchdog and Sleep Timers
❐ Internal Voltage Reference
❐ Integrated Supervisory Circuit
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-05356 Rev. *D Revised November 12, 2007
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IDAC
Reference
Buffer
Vr
Cinternal
Analog Global Bus
Cap Sense Counters
Comparator
Mux
Mux
Refs
CapS ens e
Clock Select
Relaxation
Oscillator
(RO)
CSCLK
IMO
PSoC Functional Overview
The PSoC® family consists of many Mixed Signal Arrays with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU based system components
with one low cost single chip programmable component. A
PSoC device includes configurable analog and digital blocks
and programmable interconnect. This architecture enables the
user to create customized peripheral configurations to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
The PSoC architecture for this device family, as shown in
Figure 1, is comprised of three main areas: the Core, the Sys-
tem Resources, and the CapSense Analog System. A common
versatile bus enables connection between IO and the analog
system. Each CY8C20x34 PSoC device includes a dedicated
CapSense block that provides sensing and scanning control cir
cuitry for capacitive sensing applications. Depending on the
PSoC package, up to 28 general purpose IO (GPIO) are also
included. The GPIO provide access to the MCU and analog
mux.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, IMO (Internal
Main Oscillator), and ILO (Internal Low speed Oscillator). The
CPU core, called the M8C, is a powerful processor with sp eed s
up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard architec
ture microprocessor.
System Resources provide additional capability such as a con figurable I2C slave or SPI master-slave communication inter-
face and various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block
and an internal 1.8V analog reference. Together they supp ort
capacitive sensing of up to 28 inputs.
The CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware per
forms capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each
GPIO pin. Scanning of enabled CapSense pins is completed
quickly and easily across multiple ports.
Figure 1. Analog System Block Diagram
-
-
The Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. Th e bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Complex capacitive sensing interfaces such as sliders and
touch pads
-
■ Chip-wide mux that enables analog input from any IO pin
■ Crosspoint connection between any IO pin combinations
When designing capacitive sensing applications, refer to the latest signal-to-noise signal level requi rements Application Notes,
found under
http://www.cypress.com >> DESIGN
RESOURCES >> Application Notes. In general, unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) requirement for CapSense applications
is 5:1.
Document Number: 001-05356 Rev. *D Page 2 of 34
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Additional System Resources
Technical Training Modules
System Resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits
of each system resource are presented below.
2
■ The I
■ Low Voltage Detection (LVD) interrupts signal the application
■ An internal 1.8V reference provides an absolute reference for
■ The 5V maximum input, 3V fixed output, low dropout regulator
C slave or SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires run at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
capacitive sensing.
(LDO) provides regulation for IOs. A register controlled bypass
mode enables the user to disable the LDO.
Getting Started
To understand the PSoC silicon read this datasheet and use the
PSoC Designer Integrated Development Environment (IDE).
This datasheet is an overview of the PSoC integrated circuit
and presents specific pin, register, and electrical specifications.
For in depth information, along with detailed programming infor
mation, refer to the PSoC Mixed Signal Array Technical Refer-
ence Manual on the web at http://www.cypress.com/psoc.
For up to date Ordering, Packaging, and Electrical Specification
information, refer to the latest PSoC device datasheets on the
http://www.cypress.com.
web at
Free PSoC technical training modules are available for new
users to PSoC. Training modules cover designing, debugging,
advanced analog, and CapSense. Go to
http://www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to
Support located on the left side of the web page and select
CYPros Consultants.
http://www.cypress.com, click on Design
Technical Support
PSoC application engineers take pride in fast and accurate
response. They are available with a four hour guaranteed
response at
http://www.cypress.com/support/login.cfm.
Application Notes
A long list of application notes assist you in every aspect of your
design effort. To view the PSoC application notes, go to the
http://www.cypress.com and select Application Notes under the
Design Resources list located in the center of the web page.
Application notes are sorted by date by default.
Development Tools
PSoC Designer is a Microsoft® Windows based, integrated
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avne t, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page and click PSoC (Program-
mable System-on-Chip) to view a current list of available items.
Document Number: 001-05356 Rev. *D Page 3 of 34
development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP. For more information, see
Figure 2 on page 4.
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high level C language compiler
developed specifically for the devices in the family.
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Figure 2. PSoC Designer Subsystems
Commands
Results
PSoC
Designer
Core
Engine
PSoC
Configuration
Sheet
Manufacturing
Information
File
Device
Database
Importable
Design
Database
Graphical Designer
Interfac e
Context
Sensitive
Help
Project
Database
Application
Database
User
Modules
Library
PSoC
Designer
PSoC Designer Software Subsystems
Assembler
The macro assembler enables the assembly code for seamless
merging with C code. The link lib raries automatically use abso
lute addressing or are compiled in relative mode and linked with
other software modules to get absolute a ddr e ssing .
C Language Compiler
C language compiler supports the PSoC family of devices. It
quickly enables you to create complete C programs for the
PSoC family devices.
The embedded optimizing C compiler provides all the features
of C language tailored to the PSoC architecture. It comes com
plete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math
functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, enabling the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands enable the designer to read the
program, read and write data memory, read and write IO regis
ters, read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also enables the designer to create a trace buffer of registers
and memory locations of interest.
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-
Device Editor
The device editor subsystem enables the user to select different
on board analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic reconfiguration enables changing configurations at run time.
PSoC Designer sets up power on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components. If the project uses more
than one operating configuration, then it contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer prints out a configuration sheet for a
given project configuration for use during application program
ming in conjunction with the device datasheet. Once the framework is generated, the user adds application specific code to
flesh out the framework. It is also possible to change the
selected components and regenerate the framework.
Application Editor
Application Editor edits C language and Assembly language
source code. It also assembles, compiles, links, and builds.
Online Help System
The online help system displays online and context sensitive
help for the user. Designed for procedural and quick reference,
each functional subsystem has its own context sensitive help.
This system also provides tutorials and links to FAQs and an
Online Support Forum to aid the designer to get started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
-
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Document Number: 001-05356 Rev. *D Page 4 of 34
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Designing with User Modules
Debugger
Interface
to ICE
Application Editor
Device Editor
Project
Manager
Source
Code
Editor
Storage
Inspector
User
Module
Selection
Placement
and
Parameter
-ization
Generate
Applic ation
Build
All
Event &
Breakpoint
Manager
Build
Manager
Source
Code
Generator
Figure 3. User Module and Source Code Development Flows
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture
a unique flexibility. It pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources are called PSoC Blocks. They
implement a wide variety of user selectable functions. Each
block has several registers to determine their function and con
-
nectivity to other blocks, multiplexers, buses, and to the IO pins.
Iterative development cycles permit you to adapt the hardware
and the software. This substantially lowers the risk of selecting
a different part to meet the final design requirements.
To speed the development process, the PSoC Design er Integrated Development Environment (IDE) provides a library of
pre-built and pre-tested hardware peripheral functions called as
User Modules. User modules make selecting and implementing
peripheral devices simple. They come in analog, digital, and
mixed signal varieties.
Each user module establishes the basic register settings to
implement the selected function. It also provides parameters to
tailor its precise configuration to a particular application. For
example, a Pulse Width Modulator user module configures one
or more digital PSoC blocks, one for each 8-bits of resolution.
The user module parameters permit you to establish the pulse
width and duty cycle. User modules also provide tested soft
ware to cut the development time. The user module application
programming interface (API) provides high level functions to
control and respond to hardware events at run time. The API
also provides optional interrupt service routines to adapt as
needed.
The API functions are documented in user module datasheets
that are viewed directly in the PSoC Designer IDE. These
datasheets explain the internal operation of the user module
and provide performance specifications. Each datasheet
describes the use of each user module parameter and docu
ments the setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. Select the user modules you need
for your project and map them on to the PSoC blocks with
point-and-click simplicity. Then, build signal chains by intercon
necting the user modules to each other and the IO pins. At this
stage, configure the clock source connections and enter parameter values directly or by selecting values from the drop down
menus. When the hardware configuration is ready for testing or
moves on to developing code for the project, perform the “Gen
erate Application” step. The PSoC Designer generates the
source code that automatically configures the device to your
specification and provides the high level user module API func
Now write the main program and any sub-routines using PSoC
Designer’s Application Editor subsystem. The Application Edi
tor includes a Project Manager that enables to open the project
source code files (including all generated code files) from a
hierarchal view. The source code editor provides syntax color
ing and advanced edit features for both C and assembly lan guage. File search capabilities include simple string searches
and recursive “grep-style” patterns. A single mouse click
invokes the Build Manager. It employs a professional strength
“makefile” system to automatically analyze all file dependencies
-
and run the compiler and assembler as necessary. Project level
options control optimization strategies used by the compiler and
linker. Syntax errors are displayed in a console window. Double
click the error message to show the offending line of source
code. When all is correct, the linker builds a HEX file image suit
able for programming.
The last step in the development process takes place inside the
-
PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single step,
run-to-breakpoint, and watch variable features, the Debugger
-
provides a large trace buffer. This enables to define complex
breakpoint events such as monitoring address and data bus
values, memory locations, and external signals.
-
tions.
Document Number: 001-05356 Rev. *D Page 5 of 34
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym Description
AC alternating current
API application programming interface
CPU central processing unit
DC direct current
GPIO general purpose IO
GUI graphical user interface
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input or output
LSb least significant bit
LVD low voltage detect
MSb most significant bit
POR power on reset
PPOR precision power on reset
PSoC® Programmable System-on-Chip™
SLIMO slow IMO
SRAM static random access memory
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 6 on page 13 lists all the abbreviations used
to measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in upper case with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers are also represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (For example, 01010100b or
01000011b). Numbers not indicated by an ‘h’, ‘b’, or 0x are dec
imals.
-
Document Number: 001-05356 Rev. *D Page 6 of 34
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Pinouts
QFN
(Top View)
AI, P2 [5 ]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
2
3
4
11
10
9
161514
13
P0[3], AI
P0[7], AI
Vdd
P0[4], AI
CLK, I2C SCL, SPI MOSI P1[1]
AI, DATA, I2C SDA, P1[0]
P1[2], AI
AI, P2 [1 ]
P1[4], AI, EXT CLK
XRES
P0[1], AI
Vss
12
567
8
Notes
1. These are the ISSP pins, that are not High Z at POR (Power On Reset). See the PSoC Mixed Signal Array Technical Reference Manual for details.
2. The center pad on the QFN package is connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not conn ected to ground, it is electrically
floated and not connected to any other signal.
This section describes, lists, and illustrates the CY8C20234, CY8C20334, CY8C20434, and CY8C2053 4 PSoC device pins and
pinout configurations.
The CY8C20x34 PSoC device is available in a variety of packages that are listed a nd shown in the fol lowing tables. Every port pin
(labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital IO.
16-Pin Part Pinout
Figure 4. CY8C20234 16-Pin PSoC Device
Table 1. 16-Pin Part Pinout (QFN
Pin No.
1 IO I P2[5]
2 IO I P2[1]
3 IOH I P1[7] I2C SCL, SPI SS.
4 IOH I P1[5] I2C SDA, SPI MISO.
5 IOH I P1[3] SPI CLK .
6 IOH I P1[1] CLK
7 Power Vss Ground connection.
8 IOH I P1[0] DATA
9 IOH I P1[2]
10 IOH I P1[4] Optional external clock input (EXTCLK).
11 Input XRES Active high external reset with internal pull down.
12 IO I P0[4]
13 Power Vdd Supply voltage.
14 IO I P0[7]
15 IO I P0[3] Integrating input.
16 IO I P0[1]
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Type
Digital Analog
[2]
)
Name Description
[1]
, I2C SCL, SPI MOSI.
[1]
, I2C SDA.
Document Number: 001-05356 Rev. *D Page 7 of 34
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24-Pin Part Pinout
QFN
(Top View)
AI, P2[5]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[2], A I
P0[0], A I
24
23
22
21
20
19
P0[3], AI
P0[5], AI
P0[7], AI
Vdd
P0[4], AI
7
8
9
10
11
12
SPI MOSI, P1[1]
AI, DATA*, I2C SDA, P1[0]
AI, P1[2]
AI, P2[3]
AI, P2[1]
NC
P1[6], AI
AI, EXTCLK, P1[4]
XRES
P2[0], AI
P0[6], AI
AI, CLK*, I2C SCL
P0[1], AI
Vss
Figure 5. CY8C20334 24-Pin PSoC Device
Table 2. 24-Pin Part Pinout (QFN
Pin No.
1 IO I P2[5]
2 IO I P2[3]
3 IO I P2[1]
4 IOH I P1[7] I2C SCL, SPI SS.
5 IOH I P1[5] I2C SDA, SPI MISO.
6 IOH I P1[3] SPI CLK.
7 IOH I P1[1] CLK
8 NC No connection.
9 Power Vss Ground connection.
10 IOH I P1[0] DATA
11 IOH I P1[2]
12 IOH I P1[4] Optional external clock input (EXTCLK).
13 IOH I P1[6]
14 Input XRES Active high external reset with internal pull down.
15 IO I P2[0]
16 IO I P0[0]
17 IO I P0[2]
18 IO I P0[4]
19 IO I P0[6] Analog bypass.
20 Power Vdd Supply voltage.
21 IO I P0[7]
22 IO I P0[5]
23 IO I P0[3] Integrating input.
24 IO I P0[1]
CP Power Vss Center pad is connected to ground.
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Document Number: 001-05356 Rev. *D Page 8 of 34
Type
Digital Analog
[2]
)
Name Description
[1]
, I2C SCL, SPI MOSI.
[1]
, I2C SDA.
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28-Pin Part Pinout
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[ 1]
Vss
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
XRES
P1[6], M
P1[4], EXTCLK, M
P1[2], M
P1[0], I2C SDA, M
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Figure 6. CY8C20534 28-Pin PSoC Device
Table 3. 28-Pin Part Pinout (SSOP )
Pin No.
1 IO I, M P0[7] Analog column mux input.
2 IO I, M P0[5] Analog column mux input and column output.
3 IO I, M P0[3] Analog column mux input and column output, integrating input.
4 IO I, M P0[1] Analog column mux input, integrating input.
5 IO M P2[7]
6 IO M P2[5]
7 IO I, M P2[3] Direct switched capacitor block input.
8 IO I, M P2[1] Direct switched capacitor block input.
9 Power Vss Ground connection.
10 IO M P1[7] I2C Serial Clock (SCL).
11 IO M P1[5] I2C Serial Data (SDA).
12 IO M P1[3]
13 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK
14 Power Vss Ground connection.
15 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA
16 IO M P1[2]
17 IO M P1[4] Optional External Clock Input (EXTCLK).
18 IO M P1[6]
19 Input XRES Active high external reset with internal pull down.
20 IO I, M P2[0] Direct switched capacitor block input.
21 IO I, M P2[2] Direct switched capacitor block input.
22 IO M P2[4]
23 IO M P2[6]
24 IO I, M P0[0] Analog column mux input.
25 IO I, M P0[2] Analog column mux input.
26 IO I, M P0[4] Analog column mux input
27 IO I, M P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *D Page 9 of 34
Type
Digital Analog
Name Description
[1]
.
[1]
.
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32-Pin Part Pinout
AI, P0[1]
AI, P2[7]
AI, P2[5]
AI, P2[3]
AI, P2[1]
AI, P3[3]
QFN
(Top View)
9
101112
131415
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32313029282726
25
Vss
P0[3], AI
P0[7], AI
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
AI, P3[1]
SPI SS, P1[7]
P0[ 0 ], AI
P2[ 6 ], AI
P3[ 0 ], AI
XRES
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
AI, CLK*, I2C SCL, SPI MOSI, P1[1]
Vss
AI, DATA*, I2C SDA, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
AI, P1[6]
P2[ 4 ], AI
P2[ 2 ], AI
P2[ 0 ], AI
P3[ 2 ], AI
P0[5], AI
AI, I2C SCL
Figure 7. CY8C20434 32-Pin PSoC Device
Table 4. 32-Pin Part Pinout (QFN
Pin No.
Type
Digital Analog
[2]
)
Name Description
1 IO I P0[1]
2 IO I P2[7]
3 IO I P2[5]
4 IO I P2[3]
5 IO I P2[1]
6 IO I P3[3]
7 IO I P3[1]
8 IOH I P1[7] I2C SCL, SPI SS.
9 IOH I P1[5] I2C SDA, SPI MISO.
10 IOH I P1[3] SPI CLK.
11 IOH I P1[1] CLK
[1]
, I2C SCL, SPI MOSI.
12 Power Vss Ground connection.
13 IOH I P1[0] DATA
[1]
, I2C SDA.
14 IOH I P1[2]
15 IOH I P1[4] Optional external clock input (EXTCLK).
16 IOH I P1[6]
17 Input XRES Active high external reset with internal pull down.
18 IO I P3[0]
19 IO I P3[2]
20 IO I P2[0]
21 IO I P2[2]
22 IO I P2[4]
23 IO I P2[6]
24 IO I P0[0]
25 IO I P0[2]
26 IO I P0[4]
27 IO I P0[6] Analog bypass.
Document Number: 001-05356 Rev. *D Page 10 of 34
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CY8C20534, CY8C20434
CY8C20334, CY8C20234
Table 4. 32-Pin Part Pinout (QFN
OCD
QFN
(Top View)
NC
Vss
P0[3], AI
P0[5], AI
P0[7], AI
OCDE
OCDO
Vdd
P0[6], AINCNC
NC
10
11
12
NC
AI, P0[1]
AI, P2[7]
AI, P2[5]
AI, P2[3]
AI, P2[1]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
NC
NC
35
34
33
32
31
30
29
28
27
26
25
36
4847464544434241403938
37
P0[2], AI
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P3[0], AI
XRES
P1[6], AI
P1[4], EXTCLK, AI
P0[4], AI
1
2
3
4
5
6
7
8
9
13
14
151617181920212223
24
NC
NC
AI, SPI CLK, P1[3]
AI, CLK*, I2C SCL, SPI MOSI, P1[1]
Vss
CCLK
HCLK
AI, DATA*, I2C SDA, P1[0]
AI, P1[2]
NCNCNC
[2]
) (continued)
28 Power Vdd Supply voltage.
29 IO I P0[7]
30 IO I P0[5]
31 IO I P0[3] Integrating input.
32 Power Vss Ground connection.
CP Power Vss Center pad is connected to ground.
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
48-Pin OCD Part Pinout
The 48-Pin QFN part table and pin diagram is for the CY8C20000 On-Chip Debug (OCD) PSoC device. This part is only used for
in-circuit debugging. It is NOT available for production.
Figure 8. CY8C20000 OCD PSoC Device
Table 5. 48-Pin OCD Part Pinout (QFN
Pin No. Digital Analog Name Description
1 NC No connection.
2 IO I P0[1]
3 IO I P2[7]
4 IO I P2[5]
5 IO I P2[3]
6 IO I P2[1]
7 IO I P3[3]
8 IO I P3[1]
9 IOH I P1[7] I2C SCL, SPI SS.
10 IOH I P1[5] I2C SDA, SPI MISO.
Document Number: 001-05356 Rev. *D Page 11 of 34
[2]
)
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