Cypress CY7C68320C, CY7C68321C, CY7C68300C, CY7C68301C User Manual

CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C

EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge

Features

• Fixed-function mass storage device—requires no firmware

• Two power modes: Self-powered and USB bus-powered to
enable bus powered CF readers and truly portable USB
hard drives

• Certified compliant for USB 2.0 (TID# 40490119), the USB
Mass Storage Class, and the USB Mass Storage Class
Bulk-Only Transport (BOT) Specification

• Operates at high-speed (480 Mbps) or full-speed (12 Mbps)
USB

• Complies with ATA/ATAPI-6 specification

• Supports 48 bit addressing for large hard drives

• Supports ATA security features

• Supports any ATA command with the ATACB function

• Supports mode page 5 for BIOS boot support

• Supports A TAPI serial number VPD page retrieval for Digital
Rights Management (DRM) compatibility

• Supports PIO modes 0, 3, and 4, multiword DMA mode 2,
and UDMA modes 2, 3, and 4

• Uses one small external serial EEPROM for storage of USB
descriptors and device configuration data

• ATA interface IRQ signal support

• Supports one or two ATA/ATAPI devices

• Supports CompactFlash and one ATA/ATAPI device

• Supports board-level manufacturing test using the USB I/F

• Can place the ATA interface in high impedance (Hi-Z) to
allow sharing of the AT A bus with another controller (i.e., an
IEEE-1394 to ATA bridge chip or MP3 Decoder)

• Low-power 3.3V operation

• Fully compatible with native USB mass storage class drivers

• Cypress mass storage class drivers available for Windows
(98SE, ME, 2000, XP) and Mac OS X operating systems

Features (CY7C68320C/CY7C68321C only)

• Supports HID interface or custom GPIOs to enable features
such as single button backup, power-off, LED-based notifi­cation, etc.

• 56-pin QFN and 100-pin TQFP lead-free packages

• CY7C68321C is ideal for battery-powered designs

• CY7C68320C is ideal for self- and bus-powered designs

Features (CY7C68300C/CY7C68301C only)

• Pin-compatible with CY7C68300A (using Backward
Compatibility mode)

• 56-pin SSOP and 56-pin QFN lead-free packages

• CY7C68301C is ideal for battery-powered designs

• CY7C68300C is ideal for self- and bus-powered designs

Block Diagram

24

MHz

XTAL

VBUS

D+

D-

SCL
SDA

PLL

USB 2.0

Tranceiver

I2C Bus Master

Internal Control Logic

CY Smart USB

FS/HS Engine

Reset

4 kByte FIFO

Misc control signals and GPIO

ATA 3-state Control

Control

Data

ATA

Interface

Logic

Control Signals

16 Bit ATA DataUSB

ATA Interface

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document 001-05809 Rev. *A Revised November 30, 2006

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CY7C68320C/CY7C68321C

Applications

The CY7C68300C/301C and CY7C68320C/321A implement
a USB 2.0 bridge for all ATA/ATAPI-6 compliant mass storage
devices, such as the following:

• Hard drives

• CD-ROM, CD-R/W

• DVD-ROM, DVD-RAM, DVD±R/W

• MP3 players

• Personal media players

• CompactFlash

• Microdrives

• Tape drives

• Personal video recorders

The CY7C68300C/301C and CY7C68320C/321A support one
or two devices in the following configurations:

• ATA/ATAPI master only

• ATA/ATAPI slave only

• ATA/ATAPI master and ATA/ATAPI slave

• CompactFlash only

• A TA/ATAPI slave and CompactFlash or other removable
IDE master

Additional Resources

• CY4615C EZ-USB AT2LP Reference Design Kit

• USB Specification version 2.0

• ATA Specification T13/1410D Rev 3B

• USB Mass Storage Class Bulk Only Transport Specification,
www.usb.org

data transfer rates by minimizing losses due to device seek
times. The ATA interface supports ATA PIO modes 0, 3, and 4,
multiword DMA mode 2, and Ultra DMA modes 2, 3, and 4.

The device initialization process is configurable, enabling the
AT2LP to initialize ATA/ATAPI devices without software inter­vention.

CY7C68300A Compatibility

As mentioned above, the CY7C68300C/301C contains a
backward compatibility mode that allows it to be used in
existing EZ-USB AT2 (CY7C68300A) designs. The backward
compatibility mode is enabled by programming the EEPROM
with the CY7C68300A signature.

During startup, the AT2LP checks the I
EEPROM with a valid signature in the first two bytes. If the
signature is 0x4D4D, the AT2LP configures it self for pin-to-pin
compatibility with the AT2 and begins normal mass storage
operation. If the signature is 0x534B, the AT2LP configures
itself with the AT2LP pinout and begins normal mass storage
operation.

Refer to the logic flow in Figure 1 for more information on the
pinout selection process.

Most designs that use the AT2 can migrate to the AT2LP with
no changes to either the board layout or EEPROM data.
Cypress has published an application note focused on
migrating from the AT2 to the AT2LP to help expedite the
process. It can be downloaded from the Cypress website
(http://www.cypress.com) or obtained through a Cypress
representative.

Figure 1. Simplified Pinout Selection Flowchart

2

C™ bus for an

Introduction

The EZ-USB AT2LP™ (CY7C68300C/CY7C68301C and
CY7C68320C/CY7C68321C) implements a fixed-function
bridge between one USB port and one or two ATA- or
ATAPI-based mass storage device ports. This bridge adheres
to the Mass Storage Class Bulk-Only Transport Specification
(BOT) and is intended for bus- and self-powered devices.

The AT2LP is the latest addition to the Cypress USB mass
storage portfolio, and is an ideal cost- and power-reduction
path for designs that previously used Cypress’s ISD-300A1,
ISD-300LP, or EZ-USB AT2.

Specifically, the CY7C68300C/CY7C68301C includes a
mode that makes it pin-for-pin compatible with the
EZ-USB AT2 (CY7C68300A).

The USB port of the CY7C68300C/301C and
CY7C68320C/321A (AT2LP) are connected to a host
computer directly or with the downstream port of a USB hub.
Software on the USB host system issues commands and
sends data to the AT2LP and receives status and data from
the AT2LP using standard USB protocol.

The ATA/ATAPI port of the AT2LP is connected to one or two
mass storage devices. A 4 KB buffer maximizes ATA/ATAPI

Read EEPROM

EEPROM
Signature

0x4D4D?

Yes

Set

EZ-USB AT2

(CY7C68300A)

Pinout

Normal Operation

No

Set

EZ-USB AT2LP

(CY7C68300B)

Pinout

Document 001-05809 Rev. *A Page 2 of 42

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CY7C68320C/CY7C68321C

Pin Diagrams

The AT2LP is available in different package types to meet a variety of design needs. The CY7C68320C/321C is available in 56-pin
QFN and 100-pin TQFP packages to provide the greatest flexibility for new designs. The CY7C68300C/301C is available in 56-pin
SSOP and QFN package types to ensure backward compatibility with CY7C68300A designs.

Figure 2. 56-pin SSOP Pinout (CY7C68300C/CY7C68301C only)

1

DD13

2

DD14

3

DD15

4

GND

5

ATAPUEN (GND)

6

VCC

7

GND

8

IORDY

9

DMARQ

10

AVCC

11

XTALOUT

12

XTALIN

13

AGND

14

VCC

15

DPLUS

16

DMINUS

17

GND

18

VCC

19

GND

(ATA_EN) VBUS_ATA_ENABLE

(VBUS_PWR_VALID) DA2

(DA2) DRVPWRVLD

EZ-USB AT2LP

CY7C68300C
CY7C68301C

56-pin SSOP

DD12
DD11
DD10

DD9
DD8

VCC

RESET#

GND

ARESET#

CS1#
CS0#

DA1
DA0

INTRQ

VCC

DMACK#

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38

20

PWR500# (PU 10K)

21

GND (Reserved)

22

SCL

23

SDA

24

VCC

25

DD0

26

DD1

27

DD2

28

DD3

Document 001-05809 Rev. *A Page 3 of 42

NOTE: Labels in italics denote pin functionality

during CY7C68300A compatibility mode.

DIOR#

DIOW#

GND

VCC

GND

DD7
DD6
DD5
DD4

37
36
35
34
33
32
31
30
29

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CY7C68320C/CY7C68321C

Figure 3. 56-pin QFN Pinout (CY7C68300C/CY7C68301C)

GND

VCC

ATAPUEN (NC)

GND

DD15

DD14

DD13

DD12

DD11

DD10

DD9

DD8

VBUS_ATA_ENABLE (ATA_EN)

VCC

IORDY

DMARQ

AVCC

XTALOUT

XTALIN

AGND

VCC

DPLUS

DMINUS

GND

VCC

GND

(PU10K) PWR500#

GND

56555453525150494847464544

1
2
3
4
5
6
7
8

9
10
11
12

NOTE: Italic labels denote pin functionality

13
14

EZ-USB AT2LP

CY7C68300C
CY7C68301C

56-pin QFN

during CY7C68300A compatibility mode.

1516171819

SCL

SDA

VCC

202122232425262728

DD0

DD1

DD2

DD3

DD4

DD5

DD6

DD7

GND

43

RESET#

42

GND

41

ARESET#

40

DA2 (VBUS_PWR_VALID)

39

CS1#

38

CS0#

37

DRVPWRVLD (DA2)

36

DA1

35

DA0

34

INTRQ

33

VCC

32

DMACK#

31

DIOR#

30

DIOW#

29

VCC

GND

Document 001-05809 Rev. *A Page 4 of 42

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CY7C68320C/CY7C68321C

Figure 4. 56-pin SSOP Pinout (CY7C68320C/CY7C68321C)

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

DD13
DD14
DD15
GND
GPIO2
VCC
GND
IORDY
DMARQ
AVCC
XTALOUT
XTALIN
AGND
VCC
DPLUS
DMINUS
GND
VCC
GND
GPIO1
GND
SCL
SDA
VCC
DD0
DD1
DD2
DD3

VBUS_ATA_ENABLE

EZ-USB AT2LP

CY7C68320C
CY7C68321C
56-pin SSOP

DD12
DD11
DD10

DD9
DD8

VCC

RESET#

GND

ARESET#

DA2
CS1#
CS0#

GPIO0

DA1

DA0

INTRQ

VCC

DMACK#

DIOR#

DIOW#

GND

VCC

GND

DD7

DD6

DD5

DD4

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

Document 001-05809 Rev. *A Page 5 of 42

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CY7C68320C/CY7C68321C

Figure 5. 56-pin QFN Pinout (CY7C68320C/CY7C68321C)

GND

VCC

GPIO2

GND

DD15

DD14

DD13

DD12

DD11

DD10

DD9

DD8

VBUS_ATA_ENABLE

VCC

IORDY

DMARQ

AVCC

XTALOUT

XTALIN

AGND

VCC

DPLUS

DMINUS

GND

VCC

GND

GPIO1

GND

56555453525150494847464544

1
2
3
4
5
6
7
8

9
10
11
12
13
14

EZ-USB AT2LP

CY7C68320C
CY7C68321C

56-pin QFN

1516171819

SCL

SDA

VCC

202122232425262728

DD0

DD1

DD2

DD3

DD4

DD5

DD6

DD7

43

RESET#

42

GND

41

ARESET#

40

DA2

39

CS1#

38

CS0#

37

GPIO0

36

DA1

35

DA0

34

INTRQ

33

VCC

32

DMACK#

31

DIOR#

30

DIOW#

29

VCC

GND

GND

Document 001-05809 Rev. *A Page 6 of 42

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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

VCC
GND
IORDY
DMARQ
GND
GND
GND
GND
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
VCC
DPLUS
DMINUS
GND
VCC
GND
SYSIRQ
GND
GND
GND
PWR500#
GND
NC
SCL
SDA

CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C

Figure 6. 100-pin TQFP Pinout (CY7C68320C/CY7C68321C only)

99989796959493929190898887868584838281

100

NC

NC

VCC

GND

DD11

DD10

VBUS_ATA_ENABLE

ATAPUEN

GND

DD15

DD14

DD13

GND

DD12

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

DRVPWRVLD

EZ-USB AT2LP

CY7C68320A
CY7C68321A

C
C

100-pin TQFP

VBUSPWRD

LOWPWR#

DD9

DD8

VCC

RESET#

NC

GND

ARESET#

DA2
CS1#
CS0#

DA1

DA0

INTRQ

VCC

GND

NC
NC

NC
NC
NC

NC

DMACK#

DIOR#

DIOW#

VCC

NC
NC

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NCNCVCC

31323334353637383940414243444546474849

Document 001-05809 Rev. *A Page 7 of 42

DD0

DD1

DD2

DD3

VCC

GNDNCGNDNCGND

DD4

DD5

DD6

DD7

GND

VCC

GND

50

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CY7C68320C/CY7C68321C

Pin Descriptions

The following table lists the pinouts for the 56-pin SSOP , 56-pin
QFN and 100-pin TQFP package options for the AT2LP. Refer
to the “Pin Diagrams” on page 3 for differences between the

68300C/01C and 68320C/321C pinouts for the 56-pin
packages. For information on the CY7C68300A pinout, refer
to the CY7C68300A data sheet that is found in the ’EZ-USB
AT2’ folder of the CY4615C reference design kit CD.

Table 1. AT2LP Pin Descriptions

Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode)

100

TQFP

1 55 6 V

56

QFN

56

SSOP

Pin Name

CC

Pin

Type

Default State

at Startup

Pin Description

PWR VCC. Connect to 3.3V power source.
2 56 7 GND GND Ground.
3 1 8 IORDY I
4 2 9 DMARQ I
5

N/A N/A GND Ground.

[1]
[1]

Input ATA control. Apply a 1k pull up to 3.3V.
Input ATA control.

6
7
8

9 3 10 AV

CC

PWR Analog VCC. Connect to VCC through the shortest path

possible.

10 4 11 XTALOUT Xtal Xtal 24 MHz crystal output. (See “XTALIN, XTALOUT” on

page 11).

11 5 12 XTALIN Xtal Xtal 24 MHz crystal input. (See “XTALIN, XTALOUT” on

page 11).

12 6 13 AGND GND Analog ground. Connect to ground with as short a

path as possible.

13

N/A N/A NC No connect.
14
15

16 7 14 V

CC

PWR VCC. Connect to 3.3V power source.
17 8 15 DPLUS IO Hi-Z USB D+ signal (See “DPLUS, DMINUS” on page 11).
18 9 16 DMINUS IO Hi-Z USB D–signal (See “DPLUS, DMINUS” on page 11).
19 10 17 GND GND Ground.
20 11 18 V

CC

PWR VCC. Connect to 3.3V power source.
21 12 19 GND GND Ground.
22 N/A N/A SYSIRQ I Input USB interrupt request. (See “SYSIRQ” on page 12).

Active HIGH. Connect to GND if functionality is not
used.

23

N/A N/A GND GND Ground.
24
25

26

[3]

13

[3]

20 PWR500#

(PU 10K)

[2]

O bMaxPower request granted indicator. (See

“PWR500#” on page 14). Active LOW.

N/A for CY7C68320C/CY7C68321C 56-pin packages.
27 14 21 GND (RESERVED) Reserved. Tie to GND.
28 N/A N/A NC No connect.
29 15 22 SCL O Active for

several ms at

Clock signal for I2C interface. (See “SCL, SDA” on

page 11). Apply a 2.2k pu ll up resistor.

startup.

Notes

1. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See

page 14

2. A ‘#’ sign after the pin name indicates that it is active LOW.

.

“VBUS_ATA_ENABLE” on

Document 001-05809 Rev. *A Page 8 of 42

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Table 1. AT2LP Pin Descriptions

Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued)

100

TQFP

56

QFN

56

SSOP

Pin Name

Pin

Type

Default State

at Startup

Pin Description

30 16 23 SDA IO Data signal for I2C interface. (See “SCL, SDA” on

page 11).

Apply a 2.2k pull up resistor.
31

N/A N/A NC No connect.

32
33 17 24 V

CC

34 18 25 DD0 IO
35 19 26 DD1 IO
36 20 27 DD2 IO
37 21 28 DD3 IO
38 N/A N/A V

CC

PWR VCC. Connect to 3.3V power source.

[1]
[1]
[1]
[1]

Hi-Z ATA data bit 0.
Hi-Z ATA data bit 1.
Hi-Z ATA data bit 2.
Hi-Z ATA data bit 3.

PWR VCC. Connect to 3.3V power source.
39 N/A N/A GND GND Ground.
40 N/A N/A NC NC No connect.
41 N/A N/A GND Ground.
42 N/A N/A NC NC No connect.
43 N/A N/A GND Ground.
44 22 29 DD4 IO
45 23 30 DD5 IO
46 24 31 DD6 IO
47 25 32 DD7 IO

[1]
[1]
[1]
[1]

Hi-Z ATA data bit 4.
Hi-Z ATA data bit 5.
Hi-Z ATA data bit 6.

Hi-Z ATA data bit 7. Apply a 1k pull down to GND.
48 26 33 GND GND Ground.
49 27 34 V

CC

PWR VCC. Connect to 3.3V power source.
50 28 35 GND GND Ground.
51

N/A N/A NC NC No connect.

52
53 N/A N/A V

CC

54 29 36 DIOW#

[2]

PWR VCC. Connect to 3.3V power source.

[1]

O/Z

Driven HIGH

ATA control.

(CMOS)

55 30 37 DIOR# O/Z

[1]

Driven HIGH

ATA control.

(CMOS)

56 31 38 DMACK# O/Z

[1]

Driven HIGH

ATA control.

(CMOS)
57 N/A N/A NC NC No connect.
58 N/A N/A LOWPWR# O USB suspend indicator. (See “LOWPWR#” on

page 13).

59

N/A N/A NC NC No connect.
60
61

62 N/A N/A VBUSPWRD I Input Bus-powered mode selector. (See “VBUSPWRD” on

page 14).

63

N/A N/A NC NC No connect.
64

65 N/A N/A GND GND Ground.
66 32 39 V

CC

67 33 40 INTRQ I

PWR VCC. Connect to 3.3V power source.

[1]

Input ATA interrupt request.

Document 001-05809 Rev. *A Page 9 of 42

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Table 1. AT2LP Pin Descriptions

Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued)

100

TQFP

68 34 41 DA0 O/Z

56

QFN

56

SSOP

Pin Name

Pin

Type

[1]

Default State

at Startup

Driven HIGH

Pin Description

ATA address.

after 2 ms

delay

69 35 42 DA1 O/Z

[1]

Driven HIGH

ATA address.

after 2 ms

delay

70

[3]

36

[3]

43 DRVPWRVLD

(DA2)

I Input Device presence detect. (See “DRVPWRVLD” on

page 13). Configurable logical polarity is controlled by

EEPROM address 0x08. This pin must be pulled HIGH
if functionality is not utilized.

Alternate function. Input when the EEPROM configu­ration byte 8 has bit 7 set to one. The input value is
reported through EP1IN (byte 0, bit 0).

71 37 44 CS0# O/Z

[1]

Driven HIGH

ATA chip select.

after 2 ms

delay

72 38 45 CS1# O/Z

[1]

Driven HIGH

ATA chip select.

after 2 ms

delay

73 39 46 DA2

(VBUS_PWR_VALID)

O/Z

[1]

Driven HIGH

after 2 ms

ATA address.

delay

74 40 47 ARESET# O/Z

[1]

ATA reset.
75 41 48 GND GND Ground.
76 N/A N/A NC NC No connect.
77 42 49 RESET# I Input Chip reset (See “RESET#” on page 14).
78 43 50 V

CC

79 44 51 VBUS_ATA_ENABLE

(ATA_EN)
80 45 52 DD8 IO
81 46 53 DD9 IO
82 47 54 DD10 IO
83 48 55 DD11 IO

PWR VCC. Connect to 3.3V power source.

I Input VBUS detection (See “VBUS_ATA_ENABLE” on

page 14).

[1]
[1]
[1]
[1]

Hi-Z ATA data bit 8.
Hi-Z ATA data bit 9.
Hi-Z ATA data bit 10.

Hi-Z ATA data bit 11.
84 N/A N/A GND Ground.
85 N/A N/A V
86

N/A N/A NC NC No connect.

CC

PWR VCC. Connect to 3.3V power source.

87
88

89
90
91
92
93

36
13
54

[3]

N/A GPIO0

[3]
[3]

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5

IO

[3]

General purpose IO pins (See “GPIO Pins” on

page 13). The GPIO pins must be tied to GND if

functionality is not used.

94 N/A N/A GND GND Ground.
95 49 56 DD12 IO
96 50 1 DD13 IO
97 51 2 DD14 IO
98 52 3 DD15 IO

[1]
[1]
[1]
[1]

Hi-Z ATA data bit 12.

Hi-Z ATA data bit 13.

Hi-Z ATA data bit 14.

Hi-Z ATA data bit 15.
99 53 4 GND GND Ground.

Document 001-05809 Rev. *A Page 10 of 42

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Table 1. AT2LP Pin Descriptions

Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued)

100

TQFP

100

56

QFN

[3]

54

56

SSOP

[3]

5 ATAPUEN

Pin Name

Pin

Default State

Type

IO Bus-powered ATA pull up voltage source (see

(NC)

Additional Pin Descriptions

The following sections provide additional pin information.

DPLUS, DMINUS

DPLUS and DMINUS are the USB signaling pins; they must
be tied to the D+ and D– pins of the USB connector. Because
they operate at high frequencies, the USB signals require
special consideration when designing the layout of the PCB.
See “General PCB Layout Recommendations For USB Mass

Storage Designs” on page 39 for PCB layout recommenda-

tions.
When RESET# is released, the assertion of the internal pull

up on D+ is gated by a combination of the state of the
VBUS_ATA_ENABLE pin, the value of configuration address
0x08 bit 0 (DRVPWRVLD Enable), and the detection of a
non-removable ATA/ATAPI drive on the IDE bus. See Table 2
for a description of this relationship.

at Startup

Pin Description

“ATAPUEN” on page 14).

Alternate function: General purpose input when the
EEPROM configuration byte 8 has bit 7 set to ‘1’. The
input value is reported through EP1IN (byte 0, bit 2).

pins must still be connected to pull up resistors. The SCL and
SDA pins are active for several milliseconds at startup.

XTALIN, XTALOUT

The AT2LP requires a 24 MHz (

±100 ppm) signal to derive

internal timing. Typically, a 24 MHz (12 pF, 500 μW,
parallel-resonant, fundamental mode) crystal is used, but a 24
MHz square wave (3.3V, 50/50 duty cycle) from another
source can also be used. If a crystal is used, connect its pins
to XTALIN and XTALOUT, and also through 12 pF capacitors
to GND as shown in Figure 7. If an alternate clock source is
used, apply it to XTALIN and leave XTALOUT unconnected.

Figure 7. XTALIN/XTALOUT Diagram

Table 2. D+ Pull Up Assertion Dependencies

VBUS_ATA_EN111100

DRVPWRVLD Enable Bit110011

A TA/A TAPI Drive Detected

YesNoYesNoYesNo

State of D+ pull up111000

SCL, SDA

The clock and data pins for the I

2

C port must be connected to

the configuration EEPROM and to 2.2K pull up resistors tied

. If no EEPROM is used in the design, the SCL and SDA

to V

CC

24MHz Xtal

12pF

XTALIN XTALOUT

12pF

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SYSIRQ

The SYSIRQ pin provides a way for systems to request service
from host software by using the USB Interrupt pipe on endpoint
1 (EP1). If the AT2LP has no pending interrupt data to return,
USB interrupt pipe data requests are NAKed. If pending data
is available, the AT2LP returns 16 bits of data. This data
indicates whether AT2LP is operating in high-speed or
full-speed, whether the AT2LP is reporting self-powered or
bus-powered operation, and the states of any GPIO pins that
are configured as inputs. GPIO pins can be individually set as

Table 3. Interrupt Data Bitmap

EP1 Data Byte 1 EP1 Data Byte 0

7654321076543210

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

USB High-Speed

inputs or outputs, with byte 0x09 of the configuration data. The
state of any GPIO pin that is not set as an input is reported as
‘0’ in the EP1 data.

Table 3 gives the bitmap for the data returned on the interrupt

pipe and Figure 8 depicts the latching algorithm incorporated
by the AT2LP .

The SYSIRQ pin must be pulled LOW if HID functionality is
used. Refer to “HID Functions for Button Controls” on page 15
for more details on HID functionality.

VBUS Powered

RESERVED

RESERVED

GPIO[5]

GPIO[4]

GPIO[3]

GPIO[2]

GPIO[1]

GPIO[0]

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Figure 8. SYSIRQ Latching Algorithm

No

USB Interrupt

Pipe Polled?

Yes

Int_Data = 1?

No

NAK Request

Return Interrupt Data

Yes

Set Int_Data = 0

DRVPWRVLD

When this pin is enabled with bit 0 of configuration address
0x08 (DRVPWRVLD Enable), the A T2LP informs the host that
a removable device, such as a CF card, is present. The AT2LP
uses DRVPWRVLD to detect that the removable device is
present. Pin polarity is controlled by bit 1 of configuration
address 0x08. When DRVPWRVLD is deasserted, the AT2LP
reports a “no media present” status (ASC = 0x3A, ASQ = 0x00)
when queried by the host. When the media has been detected
again, the AT2LP reports a “media changed” status to the host
(ASC = 0x28, ASQ = 0x00) when queried.

When a removable device is used, it is always considered by
the AT2 LP to be the IDE master device. Only one removable
device may be attached to the AT2LP. If the system only
contains a removable device, bit 6 of configuration address
0x08 (Search AT A Bus) must be set to ‘0’ to disable A T A device
detection at startup. If a non-removable device is connected in
addition to a removable media device, the non-removable
device must be configured as IDE slave (device address 1).

GPIO Pins

The GPIO pins allow for a general purpose input an d output
interface. There are several different interfaces to the GPIO
pins:

• Configuration bytes 0x09 and 0x0A contain the default
settings for the GPIO pins upon initial AT2LP configuration.

No

SYSIRQ=1?

Yes

Yes

Latch State of IO Pins

Set Int_Data = 1

No

Int_Data = 0

and

SYSIRQ=0?

• The host can modify the settings of the GPIO pins during
operation. This is done with vendor-specific commands
described in “Programming the EEPROM” on page 33.

• The status of the GPIO pins is returned on the interrupt
endpoint (EP1) in response to a SYSIRQ. See “SYSIRQ”

on page 12 for SYSIRQ details.

LOWPWR#

LOWPWR# is an output pin that is driven to ‘0’ when the
AT2LP is not in suspend. LOWPWR# is placed in Hi-Z when
the AT2LP is in a suspend state. This pin only indicates the
state of the AT2LP and must not be used to determine the
status of the USB host because of variations in the behavior
of different hosts.

ATA Interface Pins

The ATA Interface pins must be connected to the corre­sponding pins on an IDE connector or mass storage device.
To allow sharing of the IDE bus with other master devices, the
AT2LP can place all ATA Interface Pins in a Hi-Z state
whenever VBUS_ATA_ENABLE is not asserted. Enabling this
feature is done by setting bit 4 of configuration address 0x08
to ‘1’. Otherwise, the ATA bus is driven by the AT2LP to a
default inactive state whenever VBUS_ATA_ENABLE is not
asserted.

Design practices for signal integrity as outlined in the
ATA/ATAPI-6 specification must be followed with systems that
utilize a ribbon cable interconnect between the AT2LP’s ATA

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