CYPRESS CY7C68300B, CY7C68301B, CY7C68320, CY7C68321 User Manual

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge

1.0 Features (CY7C68300B/CY7C68301B and
CY7C68320/CY7C68321)

• Fixed-funct ion mass st orage devi ce—requires no firmware
code

• Two power modes: Self-powered and USB bus-powered to
enable bus powered CF readers and truly portabl e USB
hard drives

• Certified co mpliant for USB 2.0 ( TI D# 40460273 ), t he USB
Mass Storage Class, and the USB Mass Storage Cl ass
Bulk-Only Transport (BO T) Specification

• Operates at high (4 80-Mbps) or full (12 -Mbps) speed USB

• Complies with ATA/ATAPI-6 specif ication

• Supports 48-bit addressing fo r large hard drives

• Supports ATA security features

• Supports al l ATA commands via ATACB function

• Supports mode page 5 for BIOS boot support

• Supports A T API serial number VPD p age retrieval for Digi tal
Rights Management (DRM) compatibility

• Supports PIO modes 0, 3, 4, multiword DM A mo de 2, and
UDMA modes 2, 3, 4

• Uses one external serial EEPROM for storage of USB
descriptor s and device configuration data

• ATA interface IRQ signal support

• Support for one or two ATA/ATAPI devices

2.0 Block Diagram

• Support for Compact Flash and one ATA/ATAPI device

• Can place the ATA interface in high-impedance (Hi-Z) t o
allow sharing of the ATA bus with anothe r cont roller (e.g.,
an IEEE-1394 to ATA bridge chip or MP3 Decoder)

• Support for board-le vel manufacturing tes t vi a USB
interface

• Low-power 3.3V operation

• Fully compati ble with native USB mass storage class driver s

• Cypress mass s torage cl ass dri vers avai labl e for Windo ws
(98SE, ME, 2000, XP) and Mac OS X

1.1 Features (CY7C68320/CY7C68321 only)

• Supports HID interface or c ustom GPIOs to en able feature s
such as single butto n backup, power-off, L ED-based notifi­cation, etc.

• Lead-free 56-pin QF N and 100-pi n TQ FP packages

• CY7C68321 is ideal for bat tery-powered designs

• CY7C68320 is ideal for sel f- and bus-powered designs

1.2 Features (CY7C68300B/CY7C68301B only)

• Pin-compatible with CY7C68300A ( using Backward
Compat ibility mode)

• Lead-free 56-pin SSOP and 56-pi n Q FN packages

• CY7C68301B is ideal for bat tery-powered designs

• CY7C68300B is ideal for sel f- and bus-powered designs

24

MHz

XTAL

VBUS

D+

D-

SCL

SDA

PLL

USB 2.0 XCVR

I2C B us Controller

RESET

Internal Control Logic

CY Smar t US B

FS/HS Engine

4kByt e FIFO

Figure 2-1. Block Diagram

Control

Dat a

A

T

M isc control si gnal s

_

E

N

A

(

A

T

A

n

I

ATA

Interf ace

Logic

f

t

a

c

e

r

e

3

ATA Interf ace

Contro l Signals

16 Bit ATA Data

s

a

t

t

-

e

)

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document 38-08033 Rev. *C Revised February 14, 2005

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

3.0 Applications

The CY7C68300B/301B and CY7C68320/321 implement a
USB 2.0 bridge for all ATA/ATAPI-6 compliant mass storage
devices, such as the following.

• Hard drives

• CD-ROM, CD-R/W

• DVD-ROM, DVD-RAM, DVD+/–R/W

• MP3 players

• Personal media players

• CompactFlash

• Microdrives

• Tape drives

• Personal video recorders

The CY7C68300B/301 B and CY7C68320/321 support one or
two devices in the following configurations.

• ATA/ATAPI master only

• ATA/ATAPI slave only

• ATA/ATAPI master and slave

• CompactFl ash only

• A TA/ATAPI slave and CompactFlas h or ot her removable
IDE mast e r

3.1 Additional Resources

• CY4615B EZ-USB AT2LP Reference Design Kit

• USB Specification version 2.0

• ATA Specification T13/1410D Rev 3B

• USB Mass Storage Cl ass Bulk Only Transport Specification,
www.usb.org

4.0 Introduction

The EZ-USB AT2LP (CY7C68300B/CY7C68301B and
CY7C68320/CY7C68321) implements a fixed function bridge
between one USB port and one or two ATA- or ATAPI-based

mass storage device ports. This bridge adheres to the Mass
Storage Class Bulk-Only Transport Specification and is
intended for bus- and self-powered devices .

The AT2LP is the latest addition to t he Cypress USB mass
storage portfolio, and is an ideal cost - and power- reduct ion
path for designs that previously used the ISD-300A1, ISD­300LP, or EZ-USB AT2.

Specifically, the CY7C68300B/CY7C68301B includes a
mode that makes it pin-for-pin compatible with the EZ­USB AT2 (CY7C68300A).

The USB port of the CY7C68300B/30 1B and CY7C68320/321
(AT2LP) are connect ed to a host computer directly or via the
downstream port of a USB hub. Host software issues
commands and data to the AT2LP and receives status and
data from the AT2LP using standard USB protocol.

The ATA/ATAPI port of the AT2LP is connected to one or two
mass storage devi ces. A 4- Kbyte buf fer maximi zes A T A/ A T API
data transfer rates by minimizing losses due to device seek
times. The ATA i nter face s upport s A TA PIO modes 0, 3, a nd 4 ,
multiword DMA mode 2 and Ultra DMA modes 2, 3, and 4.

The device initialization process is configurable, enabling the
AT2LP to initialize ATA/ATAPI devices without software inter­vention.

5.0 68300A Compatibility

The CY7C68300B/301B a nd CY7 C68320/ 321 ar e avail able i n
three package t ypes that ar e pictured i n the followi ng sections .
As mentioned above, the CY7C68300B/301B contains a
backward compatibility mode that allows the
CY7C68300B/301B to be used in existing EZ-USB AT2
(CY7C68300A) designs. Please refer to the logic flow below
for more information on the pinout selection process.

Read EEPROM

EEPROM
Signature

0x4D4D?

Yes

Set

EZ-USB AT2

(CY7C68300A)

Pinout

Normal Operation

Figure 5-1. Simplifi ed Startup Flowchart (68300B only)

Document 38-08033 Rev. *C Page 2 of 36

No

Set

EZ-USB AT2LP

(CY7C68300B)

Pinout

5.1 Pin Diagrams

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

1

DD13

2

DD14

3

DD15

4

GND

5

ATAPUEN (GND)

6

VCC

7

GND

8

IORDY

9

DMARQ

10

AVCC

11

XTALOUT

12

XTALIN

13

AGND

14

VCC

15

DPLUS

16

DMINUS

17

GND

18

VCC

19

GND

20

PWR500# ( PU 10K )

21

GND (Reserved)

(ATA_EN) V BUS_A TA _ENABLE

(VBUS_PWR_VALID ) DA2

(DA2) DRVPWRVLD

EZ-USB AT2LP

CY7C68300B
CY7C68301B
56-pin SSOP

DD12
DD11
DD10

DD9
DD8

VCC

RESET#

GND

ARESET#

CS1#
CS0#

DA1
DA0

INTRQ

VCC

DMACK#

DIOR#

DIOW#

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36

22

SCL

23

SDA

24

VCC

25

DD0

26

DD1

27

DD2

28

DD3

Figure 5-2. 56-pin SSOP Pinout (CY7C6 8300B/CY7C68301B only)

Document 38-08033 Rev. *C Page 3 of 36

NOTE: Labels in italics denote pin functionality

during CY7C68300A compatibility mode.

GND

VCC

GND

DD7
DD6
DD5
DD4

35
34
33
32
31
30
29

GND

VCC

ATA PUE N (NC)

GND

DD15

DD14

DD13

DD12

DD11

DD10

DD9

DD8

VBUS_ATA_ENABLE (ATA_EN)

56555453525150494847464544

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

VCC

43

IORDY

DMARQ

AVCC

XTALOUT

XTALI N

AGND

VCC

DPL US

DMI NUS

GND
VCC
GND

(PU 10K) PWR500#

GND

RESET#

1
2
3
4
5
6
7
8

9
10
11
12
13
14

EZ-USB AT2LP

CY7C68300B
CY7C68301B

56-pin QFN

NOTE: Italic labels denote pin functionality

during CY7C68300A compatibility mode.

15161718192021222324252627

SCL

DD0

DD1

DD2

DD3

SDA

VCC

DD4

DD5

DD6

DD7

GND

42

GND

41

ARESET#

40

DA2 ( VBUS_PWR_VALID)

39

CS1#

38

CS0#

37

DRVPWRVLD (DA2)

36

DA1

35

DA0

34

INT RQ

33

VCC

32

DMACK#

31

DIOR#

30

DIOW#

29

28

VCC

GND

Figure 5-3. 56-pin QFN Pinout (CY7C68300B/CY7C68301B)

Document 38-08033 Rev. *C Page 4 of 36

GND

VCC

GPIO2

GND

DD15

DD14

DD13

DD12

DD11

DD10

DD9

DD8

VBUS_ATA_ENABLE

56555453525150494847464544

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

VCC

43

IORDY

DMAR Q

AVCC

XTALOUT

XTALI N

AGND

VCC

DP LUS

DM INUS

GND
VCC
GND

GPIO1

GND

1
2
3
4
5
6
7
8

9
10
11
12
13
14

EZ-USB AT2LP

CY7C68320
CY7C68321

56-pin QFN

15161718192021222324252627

SCL

DD0

DD1

DD2

DD3

SDA

VCC

DD4

DD5

DD6

DD7

GND

42
41
40
39
38
37
36
35
34
33
32
31
30
29

28

VCC

GND

Figure 5-4. 56-pin QFN Pinout (CY7 C68320/CY7C68321)

RESET#
GND
ARESET#
DA2
CS1#
CS0#
GPIO0
DA1
DA0
INT RQ
VCC
DMACK#
DIOR#
DIOW#

Document 38-08033 Rev. *C Page 5 of 36

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

VCC
GND
IORDY
DMARQ
GND
GND
GND
GND
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
VCC
DPLUS
DMINUS
GND
VCC
GND
SYSIRQ
GND
GND
GND
PWR500#
GND
NC
SCL
SDA

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

99989796959493929190898887868584838281

100

NC

NC

GND

DD15

DD14

GND

DD13

DD12

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

ATAPUEN

VCC

GND

VBUS_ATA_ENABLE

EZ-USB AT2LP

CY7C68320B
CY7C68321B

100-pin T QFP

DD9

DD11

DD10

RESET#

ARESET#

DRVPWRVLD

INTRQ

VBUSPWRD

LOWPWR#

DMACK#

DIOR#

DIOW#

DD8

VCC

NC

GND

DA2
CS1#
CS0#

DA1

DA0

VCC

GND

NC
NC

NC
NC
NC

NC

VCC

NC
NC

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NCNCVCC

31323334353637383940414243444546474849

Figure 5-5. 100-pin TQFP Pinout (CY7C68320/CY7C68321 only)

Document 38-08033 Rev. *C Page 6 of 36

DD0

DD1

DD2

DD3

VCC

GNDNCGND

NC

GND

DD4

DD5

DD6

DD7

GND

VCC

GND

50

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

5.2 Pin Descriptions

The following table lists the pinouts for the 56-pin SSOP, 56­pin QFN and 100-pin TQFP package options for the AT2LP.
Please refer to the Pin Diagrams in section for differences

between the 68300B/01B and 68320/321 pinouts for the 56­pin packages. For information on the CY7C68300A pinout,
please refer to the CY7C6 8300A data sheet that is foun d in the
“EZ-USB A T2” fol der of the CY4615 B refe rence d esign ki t CD.

T able 5-1. AT2LP Pin Descriptions

Note: (Italics pin names denote pin functionality during CY7C68300A-co mp atibility mode)

56

SSOP

56

QFN

100

TQFP Pin N ame

Pin

Type

1 50 96 DD13 I/O
2 51 97 DD14 I/O
3 52 98 DD15 I/O

Default St ate

at Start-up Pin Description

[1]
[1]
[1]

Hi-Z ATA Data bi t 13.
Hi-Z ATA Data bi t 14.

Hi-Z ATA Data bi t 15.
4 53 99 GND GND Ground.
5 54

[3]

100

[3]

ATAPUEN

(NC)

I/O ATA pull-up voltage source for bus-powered applica-

tions (see section 5.3.10).
Alternate Function: Input when the EEPROM config-

uration byte 8 has bit 7 set to one. The input value is
reported through EP1IN (byte 0, bit 2).

6 55 1 V

CC

PWR VCC. Connect to 3.3V power source.
7 56 2 GND GND Ground.
8 1 3 IORDY I
9 2 4 DMARQ I

N/A N/A 5

GND Ground.

[1]
[1]

Input ATA Control.
Input ATA Control.

6
7
8

10 3 9 AV

CC

PWR Anal og VCC. Connect to VCC through the shortest p ath

possible.
11 4 10 XTALOUT Xtal Xtal 24-MHz Crystal Output (see section ).
12 5 11 XTALIN Xtal Xtal 24-MHz Crystal Input (see section ).
13 6 12 AGND GND Analog Ground. Connect to ground with as shor t a

path as possi b l e .

N/A N/A 13

NC No Connect.
14
15

14 7 16 V

CC

PWR VCC. Connect to 3.3V power source.
15 8 17 DPLUS I/O Hi-Z USB D+ Signal (see section 5.3.1).
16 9 18 DMINUS I/O Hi-Z USB D– Signal (see section 5.3.1).
17 10 19 GND GND Gr ound.
18 11 20 V

CC

PWR VCC. Connect to 3.3V power source.
19 12 21 GND GND Gr ound.

N/A N/A 22 SYSIRQ I Input Active HIGH. USB interrup t req uest (see section

5.3.4). T ie to GND if functionali ty i s not used.

N/A N/A 23

GND GND Ground.
24
25

20 13

[3]

26

[3]

PWR500#

(PU 10K)

[2]

I/O Active LOW. VBUS power granted indicator used in

bus-powered designs (see section 5.3. 11).
Alternate Function for 68320.

21 14 27 GND (RESER VE D ) Reserved. Tie to GND.

Notes:

1. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See section 5.3.9.

2. A ‘#’ sign after the pin name indicates that it is active LOW.

3. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320/CY7C68321.

Document 38-08033 Rev. *C Page 7 of 36

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

T able 5-1. AT2LP Pin Descriptions

Note: (Italics pin names denote pin functionality during CY7C68300A-co mp atibility mode) (continued)

56

SSOP

N/A N/A 28 NC No Connect.

22 15 29 SCL O Active for
23 16 30 SDA I/O Data signal for I2C interface (see section 5.3.2).

N/A N/A 31

24 17 33 V
25 18 34 DD0 I/O
26 19 35 DD1 I/O
27 20 36 DD2 I/O

28 21 37 DD3 I/O
N/A N/A 38 V
N/A N/A 39 GND GND Ground.
N/A N/A 40 NC NC No Connect.
N/A N/A 41 GND Ground.
N/A N/A 42 NC NC No Connect.
N/A N/A 43 GND Ground.

29 22 44 DD4 I/O

30 23 45 DD5 I/O

31 24 46 DD6 I/O

32 25 47 DD7 I/O

33 26 48 GND GND Gr ound.

34 27 49 V

35 28 50 GND GND Gr ound.
N/A N/A 51

N/A N/A 53 V

36 29 54 DIOW#

37 30 55 DIOR# O/Z

38 31 56 DMACK# O/Z

N/A N/A 57 NC NC No Connect.
N/A N/A 58 LOWPWR# O USB suspend indicator (see section 5.3.7).

N/A N/A 59

N/A N/A 62 VBUSPWRD I Input Bus-powered operation selector. U s ed in sy st e m s

N/A N/A 63

N/A N/A 65 GND GND Ground.

56

QFN

100

TQFP Pin N ame

NC No Connect.

32

CC

CC

CC

NC NC No Connect.

52

CC

[2]

NC NC No Connect.
60
61

NC NC No Connect.
64

Pin

Default St ate

Type

at Start-up Pin Description

Clock signal for I2C interface (s ee section 5.3.2).

several ms at

start-up.

PWR VCC. Connect to 3.3V power source.

[1]
[1]
[1]
[1]

Hi-Z ATA Data bit 0.
Hi-Z ATA Data bit 1.
Hi-Z ATA Data bit 2.
Hi-Z ATA Data bit 3.

PWR VCC. Connect to 3.3V power source.

[1]
[1]
[1]
[1]

Hi-Z ATA Data bit 4.
Hi-Z ATA Data bit 5.
Hi-Z ATA Data bit 6.
Hi-Z ATA Data bit 7.

PWR VCC. Connect to 3.3V power source.

PWR VCC. Connect to 3.3V power source.

[1]

O/Z

Driven HIGH

ATA Control.

(CMOS)

[1]

Driven HIGH

ATA Control.

(CMOS)

[1]

Driven HIGH

ATA Control.

(CMOS)

‘0’ = Chip active. VBUS power draw gover ned by
PWR500# pin.
‘Hi-Z’ = Chip s uspen d. VBUS system cu rr ent li mited to
USB suspend mode value.

that are capabl e of bei ng bus or self-powered to
indicate the current power mode.

Document 38-08033 Rev. *C Page 8 of 36

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

T able 5-1. AT2LP Pin Descriptions

Note: (Italics pin names denote pin functionality during CY7C68300A-co mp atibility mode) (continued)

56

SSOP

39 32 66 V
40 33 67 INTRQ I
41 34 68 DA0 O/Z

42 35 69 DA1 O/Z

43 36

44 37 71 CS0# O/Z

45 38 72 CS1# O/Z

46 39 73 DA2

47 40 74 ARESET# O/Z
48 41 75 GND GND Gr ound.

N/A N/A 76 NC NC No Connect.

49 42 77 RESET# I Input Chip Reset (see section 5.3.13). This pin is normally

50 43 78 V
51 44 79 VBUS_ATA_ENABLE

52 45 80 DD8 I/O
53 46 81 DD9 I/O
54 47 82 DD10 I/O

55 48 83 DD11 I/O
N/A N/A 84 GND Ground.
N/A N/A 85 V
N/A N/A 86

N/A 36

N/A N/A 94 GND GND Ground.

56 49 95 DD12 I/O

56

QFN

[3]

[3]
[3]

13

[3]

54

100

TQFP Pin N ame

CC

[3]

70

DRVPWRVLD

(DA2)

(VBUS_PWR_VALID)

CC

(ATA_EN)

CC

NC NC No Connect.

87
88

89
90
91
92
93

GPIO0
GPIO1

GPIO2_nHS

GPIO3
GPIO4
GPIO5

Pin

Default St ate

Type

at Start-up Pin Description

PWR VCC. Connect to 3.3V power source.

[1]

[1]

Input ATA Interrupt request.

Driven HIGH

ATA Address.

after 2 ms

delay

[1]

Driven HIGH

ATA Address.

after 2 ms

delay

I Input Device Presence Detect (see section 5.3.5). Config-

urable polarity, controlled by EEPROM address 0x08.
This pin must be connect ed to GND if functionality is
not utilized.

Alternate Function: Input when the EEPROM config­uration byte 8 has bit 7 set to one. The input value is
reported through EP1IN (byte 0, bit 0).

[1]

Driven HIGH

ATA Chip Select.

after 2 ms

delay

[1]

Driven HIGH

ATA Chip Select.

after 2 ms

delay

[1]

O/Z

Driven HIGH

ATA Address.

after 2 ms

delay

[1]

ATA Reset.

tied to V
through a 0.1-µF capac itor , supplying a 10-ms reset.

through a 100K resistor, and to GND

CC

PWR VCC. Connect to 3.3V power source.

I Input VBUS detection (see section 5.3.9). Indicates to the

CY7C68300B/CY7C68301B that VBUS power is
present.

[1]
[1]
[1]
[1]

Hi-Z ATA Data bit 8.
Hi-Z ATA Data bit 9.
Hi-Z ATA Data bi t 10.
Hi-Z ATA Data bit 11.

PWR VCC. Connect to 3.3V power source.

[3]

I/O

General purpose I/O pins (see section 5.3.6). The
GPIO pins must be tied to GND if funct ionality is not
utilized. If the hs_indicator conf ig bit is set, the
GPIO2_nHS pin will reflect the operating speed:
‘1’ = full-speed operation.
‘0’ = high-speed operation.

[1]

Hi-Z ATA Data bi t 12.

Document 38-08033 Rev. *C Page 9 of 36

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

5.3 Additional Pin Descriptions

5.3.1 DPLUS, DMINUS

DPLUS and DMINUS a re the USB signal ing pins; they should
be tied to the D+ and D– pins of the USB connector. Because
they operate at high frequencies, the USB signals require
special consideration when designing the layout of the PCB.
See section 15.0 for PCB layout recommendations. When
RESET# is released, the internal pull-up on D+ is controlled
by VBUS_ATA_ENABLE. When VBUS_ATA_ENABLE is
HIGH, D+ is pulled up.

5.3.2 SCL, SDA

The clock and data pins for the I
to the con figuration EEPROM and to 2 .2K pull -up resi stors t ied
to V

. The SCL and SDA pins are active for several milli-

CC

seconds at start-up.

5.3.3 XTALIN, XTALOUT

The AT2LP requires a 24-MHz (
internal timing. Typically, a 24-MHz (20-pF, 500-µW, pa r a ll e l -

2

C port should be connected

±100ppm) signal to derive

24MHz Xtal

12pF

resonant fundamental mode) crystal is used, but a 24-MHz
square wave fr om another source can also be used. If a cryst al
is used, connect its pins to XTALIN and XTALOUT, and also
through 12-pF capac itors to GND as shown in Figure 5-6 . If an
alternate clock source is used, apply it to XTALIN and leave
XTALOUT open.

5.3.4 SYSI RQ

The SYSIRQ pin provides a way for systems to request service
from host software by using the USB Interrupt pipe. If the
AT2LP has no pending interrupt data to return, USB interrupt
pipe data req uests are NAKed. If pend ing data is a vailable , the
AT2LP returns 16 bits of data; this data indicates the
HS_MODE signal (that indicates whether AT2LP is operating
in high-speed or full-speed), the VBUSPWRD pin, and the
GPIO pin s . Table 5-2 gives the bi tmap for the data retur ned on
the interrupt pipe and Figur e 5 -7 depict s the latching algorithm
incorporated by AT2LP.

The SYSIRQ pin must be tied low if the HID function is used
(refer to Section 6.0).

12pF

XTALIN XTALOUT

Figure 5-6. XTALIN / XTALOUT Diagram

T able 5-2. USB Interrupt Pipe Data Bitmap

USB Interrupt Data Byte 1 USB Interrupt Data Byte 0

7654321076543210

RESERVED

Document 38-08033 Rev. *C Page 10 of 36

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

USB High-Speed

VBUSPWRD

RESERVED

RESERVED

GPIO[5]

GPIO[4]

GPIO[3]

GPIO[2]

GPIO[1]

GPIO[0]

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

No

USB Inte rrupt

Pipe Polled?

Yes

Int_Data = 1?

No

NAK Request

Return I n te rrupt Data

Yes

Set Int_Data = 0

Figure 5-7. SYSIRQ Latching Algorithm

5.3.5 DRVPWRVLD

When this pin is enable d via EEPROM byte 8, bit 0, the A T2 LP
will inform the host that a removable device, such as a CF
card, is present. The CY7C68300B/CY7C68301B will use
DRVPWRVLD to det ect that the removabl e device is present.
Pin polarit y is co ntrol led b y b it 1 of EEPROM addr ess 8. When
DRVPWRVLD is deasserted, the AT2LP will report a “no
media present” status ( ASC = 0x3A, ASQ = 0x00) to the host.
When the media has been detected again, the AT2LP will
report a “media changed” status to the host (ASC = 0x28,
ASQ = 0x00).

When a removable device is used, it is always the master
device. Only one removable device may be attached to the
AT2LP. If the system only contains a removable device,
EEPROM byte 8, bit 6 must be set to ‘0’ to dis able ATA device
detection at start-up. If a non-removable device is connected
in addition t o a remov able medi a devic e, it must be conf igure d
as a slave (device address 1).

DRVPWRVLD can also be configured as an input. See

Section 6.0 HID Functions fo r Button Controls.

5.3.6 GPIO Pins

The GPIO pins allow for a general purpose Input/Output
interface. There are several different interfaces to the GPIO
pins:

• Configuration bytes 0x09 and 0x0A cont a in the defaul t se t­tings for the GPIO pins.

• The host can modify the settings of the GPIO pin s during
operation. This is done with vendor-spec ific commands de­scribed in Section 8.6.

No

SYSIRQ=1?

Yes

Yes

• The status of the GPIO pins is also ret urned on the interru pt
endpoint (EP1 ) i n response to a SYSIRQ. See section for

Latch State of IO Pins

Set Int_Data = 1

No

Int_Data = 0

and

SYSIRQ=0?

SYSIRQ details.

GPIO2_nHS also has an alter nate function. I f the “HS Indicator
Enable” configuration (bit 2 of EEPROM address 8) is set, the
GPIO2_nHS pin will reflect the operating speed of the device
(full- or high-speed USB).

5.3.7 LOWPWR#

LOWPWR# is an output pin that is driven to ‘0’ when the
AT 2LP is active. LOW PWR# is placed in Hi- Z when the A T2LP
is in a suspend state.

5.3.8 AT A Interface Pins

Design practices for signal integrity as outlined in the
ATA/ATAPI-6 Specification should be followed with systems
that utilize a ribbon cable interconnect between the
CY7C68300B/CY7C68301B’s ATA interface and the attached
ATA/ATAPI device, especially if Ul tr a DMA Mode is uti li zed.

5.3.9 VBUS_ATA_ENABLE

VBUS_ATA_ENABLE is typically used to indicate to the
AT2LP that power is present on VBUS. This pin is polled by
the AT2LP at start-up and then every 20ms thereafter. If this
pin is ‘1’, the inter nal 1.5K pull-up is att ached to D+. If this pin
is ‘0’, th e AT2LP will rel e as e th e pull-up on D+ as re quired by
the USB specification. Also, If EEPROM byte 8, bit 4 is ‘0’, t he
ATA interface pins will be placed in a hi gh impedance (Hi-Z)
state when VBUS_ATA_ENABLE is ‘0’. If EEPROM byte 8, bit
4 is ‘1’, the ATA interface pins will still be driven when
VBUS_A TA_ENABLE is ‘0’.

Document 38-08033 Rev. *C Page 1 1 of 36

CY7C68300B/CY7C68301B

CY7C68320/CY7C68321

5.3.10 ATAPUEN

This output controls the required host pull-up resistors on the
ATA interface. ATAPUEN is driven to ‘0’ when the ATA bus is
inactive. ATAPUEN is drive n to ‘1’ when the A TA bus is active.
ATAPUEN is set to a Hi-Z state along with all other ATA
interface pins if VBUS_ATA_ENABLE is deasserted and t he
ATA_EN functionality (EEPROM byte 8, bit 4) is enabled.
A T APUEN can al so be conf igured as an input. See Section 6.0

HID Functions for Button Controls

5.3.11 PWR500#

The AT2LP asserts PW R500# to indicate that VBUS current
may be drawn up to the l imit sp ecified by the bMax Power fi eld
of the USB conf iguration descriptors. In the 100-pin package,
PWR500# will only be asserted if VBUSPWRD and
DRVPWRVLD are also asserted. In the 56-pin package,
PWR500# only funct ions dur in g bus-power ed op eration. If the
AT2LP enters a low-power state, PWR500# is deasserted.
When normal operation is resumed, PWR500# is restored
accordingl y . Natural ly , the PWR500# pi n should n ever be used
to control power sources for the AT2LP. In the 68320 parts,
PWR500# can also be configured as an input. If the Drive
Power Valid Enable bit is set (EEPROM byte 8, bit 1),
PWR500# will ONLY be driven when Drive Power Valid is
active. See Section 6.0 HID Functions for Button Controls.

5.3.12 VBUSPWRD

Some devices have the ability to be either self-powered or
bus-powered. The VBUSPWRD input pin enables these
devices to change between self-powered to bus-powered
modes by changing the contents of the bMaxPower field and
the self-powe red bi t in the configurat ion descriptor.

Note that current host drivers do not poll the device for this
information, so this pin is only effective on a USB or power-up
reset.

T able 5-3. Bus-Power Descript ion

VBUSPWRD

value 1 0

PWR500# 1 when Confi g = 0

0 when Config = 1

bMaxPower 250 (500mA) 1 (2mA) EEPROM value

bmAttributes

bit 6

0 1 EEPROM value

1 1 when Config = 0

Not present

(56-pin)

0 when Confi g = 1

used

used

5.3.13 RESET#

Asserting RESET# for 1 0 ms wil l r eset t he enti re ch ip. T his pi n
is normally tied to V
through a 0.1-µF capacito r, as shown in the figure below.

Figure 5-8. Typical Reset Circuit

Cypress does not recommend an RC reset circuit for bus­powered devices. See the application note EZ-USB

FX2



/AT2/SX2 Reset and Power Considerations at

www.cypress.com for more information.

through a 100k resistor, and to GND

CC

100KΩ

Ω

ΩΩ

RESET#

0.1µµµµF

6.0 HID Functions for Button Controls

Cypress’ CY7C68320/CY7C6 8321 introduces the capa bility to
support Human Int erface Devi ce (HID) si gnaling to the host for
such functions as but tons. The abili ty to add button s to a mass
storage solut ion opens new applications for backup and other
device-side notification to th e host.

Optional HID functions can be added to the EEPROM
descriptors by setti ng bit 7 of byte 8 of the EEPROM to a value
of ‘1’. When this bit is set, several pins adopt alternate
functions for the 56-pin package. This allows the pins to be
used as button inputs. If there is a HID descriptor in the
EEPROM, these pins are polled by the hardware approxi­mately every 17 ms. If a c hange is det ected i n the pi n(s) s tate ,
a report is sent via EP1. The report format for byte 0 and byte
1 are shown in Ta ble 6-1 .

T able 6-1. EP1 Data Bitmap

EP1 Data Byte 1 EP1 Data Byt e 0

7654321076543210

RESERVED

Document 38-08033 Rev. *C Page 12 of 36

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

USB High-Speed

VBUSPWRD

DRVPWRVLD

GPIO[4]

GPIO[3]

GPIO[2]

GPIO[1]

GPIO[0]

ATAPUEN

PWR500#