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CY7C68300A
User Manual
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CYPRESS CY7C68300A User Manual

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CY7C68300
EZ-USB AT2™ USB 2.0 to ATA/ATAPI Bridge
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-08031 Rev. *B Revised August 15, 2003
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TABLE OF CONTENTS
1.0 INTRODUCTION ..............................................................................................................................4
1.1 Features ................................. ...................... ...................... .........................................................4
2.0 PIN ASSIGNMENTS ............................................................................... .........................................6
2.1 Pin Diagram ................................................................................................................................6
2.2 Pin Descriptions ..........................................................................................................................8
2.3 Additional Pin Descriptions ......... ......................................................................... .......................9
2.3.1 DPLUS, DMINUS ..............................................................................................................................9
2.3.2 SCL, SDA ..........................................................................................................................................9
2.3.3 XTALIN, XTALOUT ...........................................................................................................................9
2.3.4 ATA_EN ..........................................................................................................................................10
2.3.5 ATA Interface Pins ..........................................................................................................................10
2.3.6 VBUS_PWR_VALID ........................................................................................................................10
2.3.7 RESET# ..........................................................................................................................................10
3.0 APPLICATIONS .............................................................................................................................11
3.1 Additional Resources .......................................................... ....................................... ...............11
4.0 FUNCTIONAL OVERVIEW ................................................. .... ...................................... .. .. .............11
4.1 USB Signaling Speed .......................................................................................... .. ...................11
4.2 ATA Interface ............................................................................................................................11
5.0 ENUMERATION .................... .. .................................................................... ...................................11
5.1 Board Manufacturing Test Mode ............................................................................................. ..11
5.1.1 CfgCB ..............................................................................................................................................11
5.1.2 MfgCB .............................................................................................................................................12
5.2 Normal Operation Mode ............................................................................................................13
5.3 EEPROM Organization ............................................ .. .. .. ........................... .. .. .. ..........................13
6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................22
7.0 OPERATING CONDITIONS
[6] ...................................................................................................................................................................22
8.0 DC CHARACTERISTICS ........................ .. .. .. .. .. ................................. ............................................22
9.0 AC ELECTRICAL CHARACTERISTICS ..................................... .. ...................... .. ...................... ..22
9.1 USB Transceiver .......................................................................................................................22
9.2 ATA Timing ...............................................................................................................................22
10.0 ORDERING INFORMATION ...................................... .............................................................. ....23
11.0 PACKAGE DIAGRAMS .............................................................................................................. 23
12.0 PCB LAYOUT RECOMMENDATIONS ....................... .. .. .. .. .. .................................. .. .. .. .. .............24
13.0 QUAD FLAT PACKAGE NO LEADS (QFN) PACKAGE DESIGN NOTES .......................... .. .. ..24
14.0 OTHER DESIGN CONSIDERATIONS ................. .. .. .. ..................................................................25
14.1 Proper Power-up Sequence ....................................................................................................25
14.2 IDE Removable Media Devices ..............................................................................................25
14.3 Devices With Small Buffers .....................................................................................................25
15.0 DISCLAIMERS, TRADEMARKS, AND COPYRIGHTS ............... .. ..............................................25
Document #: 38-08031 Rev. *B Page 2 of 26
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LIST OF FIGURES
Figure 1-1. Blo c k Di a gr a m .......................... .. ... ............. .. ............. .. ........................... .. .............................5
Figure 2-1. 56 -p in S S OP .... .. ............. .. .............. .. ............. .. ... ............. .. ............. ... .. ............. .. . .................6
Figure 2-2. 56 -p in Q F N........... ............. ... ............. .. ............. ... .. ............. .. .............. .. .. ...............................7
Figure 2-3. XT AL IN , XTALOUT Diag ram .. ............. .. .............. .. ............. .. .. .............. .. ............. .. ... ...........10
Figure 2-4. Ty p ic a l Re s e t C ir c u it .............. .. ............. ... .. ............. .. ............. ... .. ............. .. .........................10
Figure 11-1. 56-lead Shrunk Small Outline Package 056......................................................................23
Figure 11-2. 56-lead Quad Flatpack No Lead (8 x 8 mm) LF56............................................................23
Figure 13-1. Cross-Section of the Area Underneath the QFN Package................................................24
Figure 13-2. P lo t of th e S o ld e r Ma s k (White Area) ................ ............. .. ........................... .. ............. .. .....25
Figure 13-3. X -r a y Im a g e of th e As s e m b ly .............. ... ............. .. ............. .. ... ............. .. ............. ... .. .........25
LIST OF TABLES
Table 5-1. Command Block Wrapper ....................... ...................... .. ...................... .. ...................... ......12
Table 5-2. Example CfgCB .................. ..................... .. ........................ .. ........................ ........................12
Table 5-3. Example MfgCB .............................. .. .. .......................... .......................................................12
Table 5-4. Mfg_load Data Format ............... ........................................................................... ...............12
Table 5-5. Mfg_read Data Format ............................ .. .. .......................... .. ....................... .. .. .................13
Table 5-6. EEPROM Organization .................................. .. ..................................................... .. ............. 14
Document #: 38-08031 Rev. *B Page 3 of 26
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1.0 Introduction
The CY7C68300A implem ents a fix ed-function br idge between on e USB port and one ATA- or ATAPI-bas ed mass storage device port. This bridge adheres to the Mass Storage Cla ss Bulk- Only Transport Specification a nd is inten ded fo r self -powe red de vices .
The USB port of the CY7C68300A is connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the CY7C68300A and receives status and data from the CY7C68300A using standard USB protoc ol.
The ATA/ATAPI port of the CY7C68300A is connected to a mass storage device. A 4-Kbyte buffer maximizes ATA/ATAPI data transfer rates by minimizi ng lo ss es due to dev ic e see k times . The ATA interfa ce supp ort s ATA PIO modes 0, 3, and 4, and Ultr a DMA modes 2 and 4.
The device initialization process is configurable, enabling the CY7C68300A to initialize ATA/ATAPI devices without software intervention.
1.1 Features
• Complies with USB-IF specifications for USB 2.0, the USB Mass Storage Class, and the USB Mass Storage Class
Bulk-Only Transport Specifica tion
• Operates at high (480-Mbps) or full (12-Mbps) speed
• Complies with T13’s ATA/ATAPI-6 Draft Specification
• Supports 48-bit addressing for large hard drives
• Supports PIO modes 0, 3, 4, and UDMA modes 2, 4
• Uses one external serial EEPROM con taining the USB devic e seria l nu mbe r, vendor an d p roduct ide ntific atio n d ata, and device configuration data
• A TA interface IRQ sign al suppo rt
• Support for a single ATA/ATAPI device configured either as master or slave
• “ATA-Enable” input signal, which three-states all signals on the ATA interface in order to allow sharing of the bus with another controller (e.g., an IEEE-1394 to ATA bridge chip)
• Support for board-level manufacturing test via USB interface
• 3.3V operation for self-powered devices
• 56-pin SSOP and 56-pin QFN packages.
Document #: 38-08031 Rev. *B Page 4 of 26
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SCL
SDA
I2C-Compatible
Bus Controller
T E S E R
24
MHz
XTAL
VBUS
D+
D-
PLL
USB 2.0 XCVR
AT2 Internal Logic
CY Smart USB
FS/HS Engine
Figure 1-1. Block Diagram
4kByte FIFO
A
Control
Data
I
3
t
(
T
A
N
n
E
A
_
T
A
ATA
Interface
Logic
e
e
r
f
a
c
-
s
t
ATA Interf ace
Control Signals
16 Bit ATA Data
a
t
)
e
Document #: 38-08031 Rev. *B Page 5 of 26
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2.0 Pin Assignments
2.1 Pin Diagram
1 2
3 4 5 6 7 8
9 10 11 12 13 14 15 16 17
DD13 DD14 DD15 GND NC Vcc GND IORDY DMARQ AVcc XTALOUT XTALIN AGND Vcc DPLUS DMINUS GND
VBUS_PWR_VALID
EZ-USB AT2
CY7C68300A
56-pin SSOP
DD12 DD11 DD10
DD9 DD8
ATA_EN
Vcc
RESET#
GND
ARESET#
CS1# CS0#
DA2 DA1
DA0
INTRQ
56 55
54 53 52 51 50 49 48 47 46 45 44 43 42 41
40 18 19 20 21 22 23 24 25 26 27 28
Vcc GND
PU10K RESERVED SCL SDA Vcc DD0 DD1 DD2 DD3
DMACK#
DIOR#
DIOW#
Vcc
GND
Vcc
GND
DD7 DD6 DD5 DD4
39
38
37
36
35
34
33
32
31
30
29
Figure 2-1. 56-pin SSOP
Document #: 38-08031 Rev. *B Page 6 of 26
A
IORDY
DMARQ
AVCC
XTALOUT
XTALIN
AGND
VCC
DPLUS
DMINUS
GND VCC GND
PU10K
RESERVED
GND
56
55
1 2 3 4 5 6 7 8
9 10 11 12 13 14
16
15
GND
DD15
DD14
DD13
54
53
52
51
50
EZ-USB AT2
CY7C68300A
56-pin QFN
21
20
19
18
17
DD12
DD11
49
48
23
22
NC
VCC
DD9
DD10
47
24
DD8
46
45
26
25
ATA_EN
44
27
VCC
4328
42 41 40 39 38 37 36 35 34 33 32 31 30 29
RESET#
GND
ARESET#
VBUS_PWR_VALID
CS1# CS0#
DA2 DA1 DA0
INTRQ
VCC
DMACK#
DIOR#
DIOW#
SCL
SDA
DD0
DD1
DD2
DD3
DD4
DD5
DD6
VCC
DD7
GND
VCC
GND
Figure 2-2. 56-pin QFN
Document #: 38-08031 Rev. *B Page 7 of 26
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2.2 Pin Descriptions
SSOP
Note:
QFN
Pin
Pin Pin Name
1 50 DD13 I/O 2 51 DD14 I/O 3 52 DD15 I/O
Pin
T yp e Default Stat e at Start-up Pin Description
[1] [1] [1]
Hi-Z ATA Data bit 13. Hi-Z ATA Data bit 14.
Hi-Z ATA Data bit 15. 4 53 GND GND Ground. 5 54 NC Hi-Z Reserved. This pin should remain a no-connect. 6 55 V
CC
PWR VCC. Connect to 3.3V power source. 7 56 GND GND Ground. 8 1 IORDY I 9 2 DMARQ I
10 3 AV
CC
[1] [1]
I A TA Control. I A TA Control.
PWR Analog VCC. Connect the VCC through the shortest path
possible. 11 4 XTALOUT Xtal Xtal 24-MHz Crystal Output (see section 2.3.3). 12 5 XTALIN Xtal Xtal 24-MHz Crystal Input (see section 2.3.3). 13 6 AGND GND Analog Ground. Connect to ground with as short a pa t h as
possible. 14 7 V
CC
15 8 DPLUS I/O Pulled high when Reset is
PWR VCC. Connect to 3.3V power source.
USB D+ Signal (see section 2.3.1).
active. When Reset is released, the pull-up is controlled by pin 46(SSOP)/ 39(QFN). When VBUS_ PWR_V ALID is high, the line is pulled up. VBUS_PWR _VALID is polled at start-up
and then every 20 ms. 16 9 DMINUS I/O Hi-Z USB D- Signal (see section 2.3.1). 17 10 GND GND Ground. 18 11 V
CC
PWR VCC. Connect to 3.3V power source. 19 12 GND GND Ground. 20 13 PU10K Hi-Z Tied to 10k ± 5% pull-up resisto r. 21 14 RESERVED Reserved. Tie to GND. 22 15 SCL O SCL/SDA will be active for 23 16 SDA I/O Data signal for I2C-compatible interface (see section 2.3.2).
24 17 V
CC
several ms at start-up . Then driven high.
PWR VCC. Connect to 3.3V power source.
Clock signal for I2C-compatible interface (see section 2.3.2).
25 18 DD0 I/O Hi-Z ATA Data bit 0. 26 19 DD1 I/O Hi-Z ATA Data bit 1. 27 20 DD2 I/O Hi-Z ATA Data bit 2. 28 21 DD3 I/O Hi-Z ATA Data bit 3. 29 22 DD4 I/O Hi-Z ATA Data bit 4. 30 23 DD5 I/O Hi-Z ATA Data bit 5. 31 24 DD6 I/O Hi-Z ATA Data bit 6. 32 25 DD7 I/O Hi-Z ATA Data bit 7. 33 26 GND GND Ground. 34 27 V
1. ATA interface pins are not active when ATA_EN is not asserted.
CC
PWR VCC. Connect to 3.3V power source.
Document #: 38-08031 Rev. *B Page 8 of 26
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