Cypress CY7C68053 User Manual
MoBL-USB™ FX2LP18 USB Microcontroller
1.0 CY7C68053 Features
• USB 2.0 – USB-IF High-Speed and Full-Speed Compliant
(TID# 40000188)
• Single-chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
• Ideal for mobile applications (cell phone, smart phones,
PDAs, MP3 players)
— Ultra low power
— Suspend current: 20 µA (typical)
• Software: 8051 code runs from:
— Internal RAM, which is loaded from EEPROM
• 16 kBytes of on-chip Code/Data RAM
• Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
— Buffering options: double, triple, and quad
• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
• 8- or 16-bit external data interface
• Smart Media Standard ECC generation
• GPIF (General Programmable Interface)
— Allows direct connection to most parallel interface
— Programmable waveform descriptors and configuration
registers to define waveforms
— Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
CY7C68053
• Integrated, industry standard enhanced 8051
— 48 MHz, 24 MHz, or 12 MHz CPU operation
— Four clocks per instruction cycle
— Three counter/timers
— Expanded interrupt system
— Two data pointers
• 1.8V core operation
• 1.8V - 3.3V IO operation
• Vectored USB interrupts and GPIF/FIFO interrupts
• Separate data buffers for the Set-up and Data portions of a
CONTROL transfer
• Integrated I
• Four integrated FIFO’s
— Integrated glue logic and FIFO’s lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— Uses external clock or asynchronous strobes
— Easy interface to ASIC and DSP IC’s
• Available in Industrial temperature grade
• Available in one lead-free package with up to 24 GPIO’s
— 56-pin VFBGA (24 GPIO’s)
2
C™ controller, runs at 100 or 400 kHz
Block Diagram
24 MHz
Ext. XTAL
High-performance micro
using standard tools
with lower-power options
MoBL-USB FX2LP18
2
I
C
Master
Additional I/Os (24)
GPIF
4 KB
FIFO
RDY (2)
CTL (3)
8/16
Abundant I/O
General
Programmable I/F
To Baseband processors/
Application processors/
ASICS/DSPs
Up to 96 MBytes/sec
Burst Rate
Integrated
Full- and High-speed
XCVR
D+
D–
VCC
1.5K
Connected for
Full-Speed
USB
XCVR
Enhanced USB Core
Simplifies 8051 Code
2.0
x20
PLL
/0.5
/1.0
/2.0
CY
Smart
USB
1.1/2.0
Engine
8051 Core
12/24/48 MHz,
Four Clocks/Cycle
16 KB
RAM
“Soft Configuration”
Easy Firmware Changes
ECC
Address (16)/ Data Bus(8)
FIFO and Endpoint Memory
(master or slave operation)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document # 001-06120 Rev *F Revised September 9th 2006
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CY7C68053
Cypress Semiconductor Corporation’s MoBL-USB FX2LP18
(CY7C68053) is a low-voltage (1.8 volt) version of the EZ-
®
USB
FX2LP (CY7C68013A), which is a highly integrated,
low-power USB 2.0 microcontroller. By integrating the USB 2.0
transceiver, serial interface engine (SIE), enhanced 8051
microcontroller, and a programmable peripheral interface in a
single chip, Cypress has created a very cost-effective solution
that provides superior time-to-market advantages with low
power to enable bus powered applications.
The ingenious architecture of MoBL-USB FX2LP18 results in
data transfer rates of over 53 Mbytes per second, the
maximum allowable USB 2.0 bandwidth, while still using a lowcost 8051 microcontroller in a package as small as a 56
VFBGA (5 mm x 5 mm). Because it incorporates the USB 2.0
transceiver, the MoBL-USB FX2LP18 is more economical,
providing a smaller footprint solution than USB 2.0 SIE or
external transceiver implementations. With MoBL-USB
FX2LP18, the Cypress Smart SIE handles most of the USB 1.1
and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility.
The General Programmable Interface (GPIF) and
Master/Slave Endpoint FIFO (8- or 16-bit data bus) provide an
easy and glueless interface to popular interfaces such as
UTOPIA, EPP, PCMCIA, and most DSP/processors.
The 56VFBGA package is defined for the family.
The MoBL-USB FX2LP18 is also referred to as FX2LP18 in
this document.
ATA,
2.0 Applications
There are a wide variety of applications for the MoBL-USB
FX2LP18. It is used in cell phone, smart phones, PDAs, and
MP3 players, to name a few.
The ‘Reference Designs’ section of the Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. For more information, visit http://www.cypress.com.
3.0 Functional Overview
The functionality of this chip is described in the sections below.
3.1 USB Signaling Speed
FX2LP18 operates at two of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000.
• Full-speed, with a signaling bit rate of 12 Mbps
• High-speed, with a signaling bit rate of 480 Mbps.
FX2LP18 does not support the low-speed signaling mode of
1.5 Mbps.
3.2 8051 Microprocessor
The 8051 microprocessor embedded in the FX2LP18 family
has 256 bytes of register RAM, an expanded interrupt system,
and three timer/counters.
3.2.1 8051 Clock Frequency
FX2LP18 has an on-chip oscillator circuit that uses an external
24 MHz (±100-ppm) crystal with the following characteristics:
• Parallel resonant
• Fundamental mode
• 500 µW drive level
• 12 pF (5% tolerance) load capacitors
An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
as required by the transceiver/PHY; internal counters divide it
down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically.
Figure 3-1. Crystal Configuration
24 MHz
C1
12 pf
20 × PLL
12 pF capacitor values assumes a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
The CLKOUT pin, which can be tri-stated and inverted using
internal control bits, outputs the 50% duty cycle 8051 clock, at
the selected 8051 clock frequency — 48, 24, or 12 MHz.
3.2.2 Special Function Registers
Certain 8051 Special Function Register (SFR) addresses are
populated to provide fast access to critical FX2LP18 functions.
These SFR additions are shown in Ta bl e 3- 1. Bold type
indicates non-standard, enhanced 8051 registers. The two
SFR rows that end with ‘0’ and ‘8’ contain bit-addressable
registers. The four IO ports A – D use the SFR addresses used
in the standard 8051 for ports 0 – 3, which are not implemented
in FX2LP18. Because of the faster and more efficient SFR
addressing, the FX2LP18 IO ports are not addressable in
external RAM space (using the MOVX instruction).
C2
12 pf
Document # 001-06120 Rev *F Page 2 of 39
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CY7C68053
Table 3-1. Special Function Registers
x 8x 9x Ax Bx Cx Dx Ex Fx
0
1SP EXIF
2DPL0 MPAGE OEA
3DPH0
4 DPL1
5 DPH1 OED
6 DPS
7PCON
8 TCON SCON0 IE IP T2CON EICON EIE EIP
9TMOD SBUF0
ATL0AUTOPTRH1 EP2468STAT EP01STAT RCAP2L
BTL1AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H
CTH0Reserved EP68FIFOFLGS TL2
DTH1AUTOPTRH2 GPIFSGLDATH TH2
E CKCON AUTOPTRL2 GPIFSGLDATLX
F Reserved AUTOPTRSET-UP GPIFSGLDATLNOX
IOA IOB IOC IOD SCON1 PSW ACC B
INT2CLR IOE SBUF1
OEB
OEC
OEE
3.3 I2C™ Bus
FX2LP18 supports the I2C bus as a master only at 100-/400KHz. SCL and SDA pins have open-drain outputs and
hysteresis inputs. These signals must be pulled up to either
V
CC
to V
or V
CC_IO
, even if no I2C device is connected.(Connecting
CC_IO
may be more convenient.)
3.4 Buses
This 56-pin package has an 8- or 16-bit ‘FIFO’ bidirectional
data bus, multiplexed on IO ports B and D.
3.5 USB Boot Methods
During the power-up sequence, internal logic checks the I2C
port for the connection of an EEPROM whose first byte is
0xC2. If found, it boot-loads the EEPROM contents into
internal RAM (0xC2 load). If no EEPROM is present, an
external processor must emulate an I
2
C slave. The FX2LP18
does not enumerate using internally stored descriptors (for
example, Cypress’ VID/PID/DID is not used for enumer-
[1]
ation).
3.6 ReNumeration™
Because the FX2LP18’s configuration is soft, one chip can
take on the identities of multiple distinct USB devices.
When first plugged into USB, the FX2LP18 enumerates
automatically and downloads firmware and USB descriptor
tables over the USB cable. Next, the FX2LP18 enumerates
again, this time as a device defined by the downloaded information. This patented two-step process, called
ReNumeration, happens instantly when the device is
Note
1. The I
2
C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
plugged in, with no hint that the initial download step has
occurred.
Two control bits in the USBCS (USB Control and Status)
register control the ReNumeration process: DISCON and
RENUM. To simulate a USB disconnect, the firmware sets
DISCON to 1. To reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM
bit to indicate whether the firmware or the Default USB Device
handles device requests over endpoint zero: if RENUM = 0,
the Default USB Device handles device requests; if
RENUM = 1, the firmware does.
3.7 Bus-powered Applications
The FX2LP18 fully supports bus-powered designs by enumerating with less than 100 mA as required by the USB 2.0 specification.
3.8 Interrupt System
The FX2LP18 interrupts are described in this section.
3.8.1 INT2 Interrupt Request and Enable Registers
FX2LP18 implements an autovector feature for INT2. There
are 27 INT2 (USB) vectors. See the MoBL-USB™ Technical
Reference Manual (TRM) for more details.
3.8.2 USB Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that is normally required to
identify the individual USB interrupt source, the FX2LP18
provides a second level of interrupt vectoring, called ‘Autovectoring.’ When a USB interrupt is asserted, the FX2LP18
Document # 001-06120 Rev *F Page 3 of 39
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CY7C68053
pushes the program counter onto its stack then jumps to
address 0x0043, where it expects to find a ‘jump’ instruction to
the USB interrupt service routine.
The FX2LP18 jump instruction is encoded as shown in
Tab le 3- 2.
Table 3-2. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority INT2VEC Value Source Notes
1 00 SUDAV Set-up Data Available
2 04 SOF Start of Frame (or microframe)
3 08 SUTOK Set-up Token Received
4 0C SUSPEND USB Suspend request
5 10 USB RESET Bus reset
6 14 HISPEED Entered high-speed operation
7 18 EP0ACK FX2LP18 ACK’d the CONTROL Handshake
8 1C Reserved
9 20 EP0-IN EP0-IN ready to be loaded with data
10 24 EP0-OUT EP0-OUT has USB data
11 28 EP1-IN EP1-IN ready to be loaded with data
12 2C EP1-OUT EP1-OUT has USB data
13 30 EP2 IN: buffer available. OUT: buffer has data
14 34 EP4 IN: buffer available. OUT: buffer has data
15 38 EP6 IN: buffer available. OUT: buffer has data
16 3C EP8 IN: buffer available. OUT: buffer has data
17 40 IBN IN-Bulk-NAK (any IN endpoint)
18 44 Reserved
19 48 EP0PING EP0 OUT was Pinged and it NAK’d
20 4C EP1PING EP1 OUT was Pinged and it NAK’d
21 50 EP2PING EP2 OUT was Pinged and it NAK’d
22 54 EP4PING EP4 OUT was Pinged and it NAK’d
23 58 EP6PING EP6 OUT was Pinged and it NAK’d
24 5C EP8PING EP8 OUT was Pinged and it NAK’d
25 60 ERRLIMIT Bus errors exceeded the programmed limit
26 64
27 68 Reserved
28 6C Reserved
29 70 EP2ISOERR ISO EP2 OUT PID sequence error
30 74 EP4ISOERR ISO EP4 OUT PID sequence error
31 78 EP6ISOERR ISO EP6 OUT PID sequence error
32 7C EP8ISOERR ISO EP8 OUT PID sequence error
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP
register), the FX2LP18 substitutes its INT2VEC byte.
Therefore, if the high byte (‘page’) of a jump-table address is
preloaded at location 0x0044, the automatically-inserted
INT2VEC byte at 0x0045 directs the jump to the correct
address out of the 27 addresses within the page.
Document # 001-06120 Rev *F Page 4 of 39
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Figure 3-2. Reset Timing Plots
CY7C68053
RESET#
V
IL
1.8V
1.62V
V
CC
0V
T
RESET
Power on Reset
3.9 Reset and Wakeup
The reset and wakeup pins are described in detail in this
section.
3.9.1 Reset Pin
The input pin, RESET#, resets the FX2LP18 when asserted.
This pin has hysteresis and is active LOW. When a crystal is
used with the CY7C68053, the reset period must allow for the
stabilization of the crystal and the PLL. This reset period must
be approximately 5 ms after VCC has reached 3.0V. If the
crystal input pin is driven by a clock signal the internal PLL
stabilizes in 200 µs after VCC has reached 3.0V
shows a power on reset condition and a reset applied during
operation. A power on reset is defined as the time reset is
asserted while power is being applied to the circuit. A powered
reset is defined to be when the FX2LP18 has previously been
powered on and operating and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation and can be found
on the Cypress web site. For more information on reset implementation for the MoBL-USB™ family of products, visit the
Cypress web site at http://www.cypress.com.
Table 3-3. Reset Timing Values
Condition T
Power on Reset with crystal 5 ms
Power on Reset with external
200 µs + Clock stability time
clock
Powered Reset 200 µs
3.9.2 Wakeup Pins
The 8051 puts itself and the rest of the chip into a power-down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
restarts, after the PLL stabilizes, and then the 8051 receives a
wakeup interrupt. This applies whether or not FX2LP18 is
connected to the USB.
[2]
RESET
. Figure 3-2
RESET#
V
IL
1.8V
V
CC
0V
T
RESET
Powered Reset
The FX2LP18 exits the power-down (USB suspend) state
using one of the following methods:
• USB bus activity (if D+/D– lines are left floating, noise on
these lines may indicate activity to the FX2LP18 and initiate
a wakeup)
• External logic asserts the WAKEUP pin
• External logic asserts the PA3/WU2 pin
The second wakeup pin, WU2, can also be configured as a
general purpose IO pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is by default active LOW.
3.9.3 Lowering Suspend Current
Good design practices for CMOS circuits dictate that any
unused input pins must not be floating between V
Floating input pins will not damage the chip, but can substan-
and VIH.
IL
tially increase suspend current. To achieve the lowest suspend
current, any unused port pins must be configured as outputs.
Any unused input pins must be tied to ground. Some examples
of pins that need attention during suspend are:
• Port pins. For Port A, B, D pins, extra care must be taken in
shared bus situations.
— Completely unused pins must be pulled to V
GND.
CC_IO
or
— In a single-master system, the firmware must output en-
able all the port pins and drive them high or low, before
FX2LP18 enters the suspend state.
— In a multi-master system (FX2LP18 and another proces-
sor sharing a common data bus), when FX2LP18 is suspended, the external master must drive the pins high or
low. The external master may not let the pins float.
• CLKOUT. If CLKOUT is not used, it must be tri-stated during
normal operation, but driven during suspend.
• IFCLK, RDY0, RDY1. These pins must be pulled to V
or GND or driven by another chip.
CC_IO
• CTL0-2. If tri-stated via GPIFIDLECTL, these pins must be
pulled to V
• RESET#, WAKEUP#. These pins must be pulled to V
or GND or driven by another chip during suspend.
or GND or driven by another chip.
CC_IO
CC_IO
Note
2. If the external clock is powered at the same time as the CY7C680xx and has a stabilization wait period, it must be added to the 200 µs.
Document # 001-06120 Rev *F Page 5 of 39
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CY7C68053
Figure 3-3. FX2LP18 Internal Code Memory
FFFF
7.5 kBytes
USB regs and
4K FIFO buffers
E200
E1FF
0.5 kBytes RAM
Data
E000
.
.
.
3FFF
16 kBytes RAM
Code and Data
0000
3.10 Program/Data RAM
This section describes the FX2LP18 RAM.
3.10.1 Size
The FX2LP18 has 16 kBytes of internal program/data RAM.
No USB control registers appear in this space.
Memory maps are shown in Figure 3-3 and Figure 3-4.
3.10.2 Internal Code Memory
This mode implements the internal 16-kByte block of RAM
(starting at 0) as combined code and data memory. Only the
internal 16 kBytes and scratch pad 0.5 kBytes RAM spaces
have the following access:
• USB download
• USB upload
• Set-up data pointer
2
•I
C interface boot load
3.11 Register Addresses
Figure 3-4. Register Address Memory
FFFF
F000
EFFF
E800
E7FF
E7C0
E7BF
E780
E77F
E740
E73F
E700
E6FF
E500
E4FF
E480
E47F
E400
E3FF
E200
E1FF
E000
4 kBytes EP2-EP8
buffers
(8 x 512)
2 kBytes RESERVED
64 Bytes EP1IN
64 Bytes EP1OUT
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addressable Registers
(512)
Reserved (128)
128 Bytes GPIF Waveforms
Reserved (512)
512 Bytes
8051 xdata RAM
3.12 Endpoint RAM
This section describes the FX2LP18 Endpoint RAM.
3.12.1 Size
• 3 × 64 bytes (Endpoints 0, 1)
• 8 × 512 bytes (Endpoints 2, 4, 6, 8)
3.12.2 Organization
• EP0
• Bidirectional endpoint zero, 64-byte buffer
• EP1IN, EP1OUT
• 64-byte buffers: bulk or interrupt
• EP2, 4, 6, 8
• Eight 512-byte buffers: bulk, interrupt, or isochronous. EP4
and EP8 can be double buffered, while EP2 and 6 can be
double, triple, or quad buffered. For high-speed endpoint
configuration options, see Figure 3-5.
3.12.3 Set-up Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the set-up
data from a CONTROL transfer.
3.12.4 Endpoint Configurations (High-speed Mode)
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT. The endpoint buffers can be
configured in any one of the 12 configurations shown in the
Document # 001-06120 Rev *F Page 6 of 39
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CY7C68053
vertical columns of Figure 3-5. When operating in full-speed
BULK mode only the first 64 bytes of each buffer are used. For
example, in high-speed the maximum packet size is 512 bytes,
but in full-speed it is 64 bytes. Even though a buffer is
configured to be a 512 byte buffer, in full-speed only the first
Figure 3-5. Endpoint Configuration
EP0 IN&OUT
EP1 IN
EP1 OUT
64
64
64
EP2
512
512
EP4
512
512
EP6
512
512
EP8
512
512
1
64
64
64
EP2
512
512
EP4
512
512
EP6
512
512
512
512
2
64
64
64
EP2
512
512
EP4
512
512
EP6
1024
1024
3
EP2
512
512
512
512
EP6
512
EP8
512
512
64
64
64
512
4
64
64
64
EP2
512
512
512
512
EP6
512
512
512
512
5
64 bytes are used. The unused endpoint buffer space is not
available for other operations. An example endpoint configuration is:
EP2–1024 double buffered; EP6–512 quad buffered
(column 8).
64
64
64
EP2
512
512
512
512
EP6
1024
1024
6
64
64
64
EP2
1024
1024
EP6
512
512
EP8
512
512
64
64
64
EP2
1024
1024
EP6
512
512
512
512
7
64
64
64
EP2
1024
1024
EP6
1024
1024
8
64
64
64
EP2
512
512
512
EP6
512
512
512
EP8
512
512
10
9
64
64
64
EP2
1024
1024
1024
1024
EP8
512
512
11
64
64
64
EP2
1024
1024
1024
1024
12
3.12.5 Default Full-Speed Alternate Settings
Table 3-4. Default Full-Speed Alternate Settings
[3, 4]
Alternate Setting 0 1 2 3
ep0 64 64 64 64
ep1out 0 64 bulk 64 int 64 int
ep1in 0 64 bulk 64 int 64 int
ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×)
ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
Notes
3. ‘0’ means ‘not implemented.’
4. ‘2×’ means ‘double buffered.’
Document # 001-06120 Rev *F Page 7 of 39
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3.12.6 Default High-Speed Alternate Settings
CY7C68053
Table 3-5. Default High-Speed Alternate Settings
[3, 4]
Alternate Setting 0 1 2 3
ep0 64 64 64 64
ep1out 0 512 bulk
ep1in 0 512 bulk
[5]
[5]
64 int 64 int
64 int 64 int
ep2 0 512 bulk out (2×) 512 int out (2×) 512 iso out (2×)
ep4 0 512 bulk out (2×) 512 bulk out (2×) 512 bulk out (2×)
ep6 0 512 bulk in (2×) 512 int in (2×) 512 iso in (2×)
ep8 0 512 bulk in (2×) 512 bulk in (2×) 512 bulk in (2×)
3.13 External FIFO Interface
The architecture, control signals, and clock rates are
presented in this section.
3.13.1 Architecture
The FX2LP18 slave FIFO architecture has eight 512-byte
blocks in the endpoint RAM that directly serve as FIFO
memories and are controlled by FIFO control signals (such as
IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from
the SIE while the others are connected to the IO transfer logic.
The transfer logic takes two forms: the GPIF for internally
generated control signals or the slave FIFO interface for externally controlled transfers.
In Slave (S) mode, the FX2LP18 accepts either an internally
derived clock or externally supplied clock (IFCLK, maximum
frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE,
PKTEND signals from external logic. When using an external
IFCLK, the external clock must be present before switching to
the external clock with the IFCLKSRC bit. Each endpoint can
individually be selected for byte or word operation by an
internal configuration bit, and a Slave FIFO Output Enable
signal (SLOE) enables data of the selected width. External
logic must insure that the output enable signal is inactive when
writing data to a slave FIFO. The slave interface can also
operate asynchronously, where the SLRD and SLWR signals
act directly as strobes, rather than a clock qualifier as in
synchronous mode. The signals SLRD, SLWR, SLOE and
PKTEND are gated by the signal SLCS#.
3.13.2 Master/Slave Control Signals
The FX2LP18 endpoint FIFO’s are implemented as eight
physically distinct 256x16 RAM blocks. The 8051/SIE can
switch any of the RAM blocks between two domains, the USB
(SIE) domain and the 8051-IO Unit domain. This switching is
instantaneous, giving zero transfer time between ‘USB FIFO’s’
and ‘Slave FIFO’s.’ Since they are physically the same
memory, no bytes are actually transferred between buffers.
At any given time, some RAM blocks are filling and emptying
with USB data under SIE control, while other RAM blocks are
available to the 8051 and/or the IO control unit. The RAM
blocks operate as single port in the USB domain, and dual port
in the 8051-IO domain. The blocks can be configured as
single, double, triple, or quad buffered as previously shown.
The IO control unit implements either an internal master (M for
master) or external master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls
FIFOADR[1:0] to select a FIFO. The two RDY pins can be
used as flag inputs from an external FIFO or other logic. The
GPIF can be run from either an internally derived clock or
externally supplied clock (IFCLK), at a rate that transfers data
up to 96 Megabytes/s (48 MHz IFCLK with 16-bit interface).
3.13.3 GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively, an externally supplied clock of 5 MHz – 48 MHz feeding
the IFCLK pin can be used as the interface clock. IFCLK can
be configured to function as an output clock when the GPIF
and FIFO’s are internally clocked. An output enable bit in the
IFCONFIG register turns this clock output off. Another bit
within the IFCONFIG register will invert the IFCLK signal
whether internally or externally sourced.
3.14 GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a
user programmable finite state machine. It allows the
CY7C68053 to perform local bus mastering, and can
implement a wide variety of protocols such as ATA interface,
parallel printer port, and Utopia.
The GPIF has three programmable control outputs (CTL), and
two general purpose ready inputs (RDY). The data bus width
can be 8 or 16 bits. Each GPIF vector defines the state of the
control outputs, and determines what state a ready input (or
multiple inputs) must be before proceeding. The GPIF vector
can be programmed to advance a FIFO to the next data value,
advance an address, and so on. A sequence of the GPIF
vectors make up a single waveform that is executed to perform
the desired data move between the FX2LP18 and the external
device.
Notes
5. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Document # 001-06120 Rev *F Page 8 of 39
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CY7C68053
3.14.1 Three Control OUT Signals
The 56-pin package brings out three of these signals,
CTL0–CTL2. The 8051 programs the GPIF unit to define the
CTL waveforms. CTLx waveform edges can be programmed
to make transitions as fast as once per clock cycle (20.8 ns
using a 48 MHz clock).
3.14.2 Two Ready IN Signals
The FX2LP18 package brings out all two Ready inputs
(RDY0–RDY1). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching.
3.14.3 Long Transfer Mode
In master mode, the 8051 appropriately sets GPIF transaction
count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 2
32
transactions.
The GPIF automatically throttles data flow to prevent under or
overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers
to represent the current status of the transaction.
3.15 ECC Generation
[6]
The MoBL-USB can calculate Error Correcting Codes (ECC’s)
on data that passes across its GPIF or Slave FIFO interfaces.
There are two ECC configurations: two ECC’s, each calculated
over 256 bytes (SmartMedia Standard) and one ECC calculated over 512 bytes.
The ECC can correct any 1-bit error or detect any 2-bit error.
3.15.1 ECC Implementation
The two ECC configurations are selected by the ECCM bit.
3.15.1.1 ECCM = 0
Two 3-byte ECC’s are each calculated over a 256-byte block
of data. This configuration conforms to the SmartMedia
Standard.
This configuration writes any value to ECCRESET, then
passes data across the GPIF or Slave FIFO interface. The
ECC for the first 256 bytes of data is calculated and stored in
ECC1. The ECC for the next 256 bytes is stored in ECC2. After
the second ECC is calculated, the values in the ECCx registers
do not change until ECCRESET is written again, even if more
data is subsequently passed across the interface.
3.15.1.2 ECCM = 1
One 3-byte ECC is calculated over a 512-byte block of data.
This configuration writes any value to ECCRESET then
passes data across the GPIF or Slave FIFO interface. The
ECC for the first 512 bytes of data is calculated and stored in
ECC1; ECC2 is unused. After the ECC is calculated, the value
in ECC1 does not change until ECCRESET is written again,
even if more data is subsequently passed across the interface.
3.16 USB Uploads and Downloads
The core has the ability to directly edit the data contents of the
internal 16-kByte RAM and of the internal 512-byte scratch
pad RAM via a vendor-specific command. This capability is
normally used when ‘soft’ downloading user code and is
available only to and from internal RAM, only when the 8051
is held in reset. The available RAM spaces are 16 kBytes from
0x0000–0x3FFF (code/data) and 512 bytes from
0xE000–0xE1FF (scratch pad data RAM).
[7]
3.17 Autopointer Access
FX2LP18 provides two identical autopointers. They are similar
to the internal 8051 data pointers, but with an additional
feature: they can optionally increment after every memory
access.The autopointers are available in external FX2LP18
registers, under control of a mode bit (AUTOPTRSET-UP.0).
Using the external FX2LP18 autopointer access (at 0xE67B –
0xE67C) allows the autopointer to access all RAM. Also, the
autopointers can point to any FX2LP18 register or endpoint
buffer space.
3.18 I2C Controller
FX2LP18 has one I2C port that is driven by two internal
controllers. One automatically operates at boot time to load the
VID/PID/DID, configuration byte, and firmware and a second
controller that the 8051, once running, uses to control external
2
I
C devices. The I2C port operates in master mode only.
2
3.18.1 I
The I
up resistors even if no EEPROM is connected to the FX2LP18.
The value of the pull up resistors required may vary, depending
on the combination of V
EEPROM. The pull up resistors used must be such that when
the EEPROM pulls SDA low, the voltage level meets the V
specification of the FX2LP18. For example, if the EEPROM
runs off a 3.3V supply and V
recommended are 10K ohm. This requirement may also vary
depending on the devices being run on the I2C pins. Refer to
the I
External EEPROM device address pins must be configured
properly. See Tab le 3- 6 for configuring the device address
pins.
If no EEPROM is connected to the I
emulation is required by an external processor.This is because
the FX2LP18 comes out of reset with the DISCON bit set, so
the device will not enumerate without an EEPROM (C2 load)
or EEPROM emulation.
C Port Pins
2
C pins SCL and SDA must have external 2.2K ohm pull
and the supply used for the
CC_IO
is 1.8V, the pull up resistors
CC_IO
2
C specifications for details.
2
C port, EEPROM
IL
Notes
6. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
7. After the data has been downloaded from the host, a ‘loader’ can execute from internal RAM in order to transfer downloaded data to external memory.
Document # 001-06120 Rev *F Page 9 of 39
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CY7C68053
Table 3-6. Strap Boot EEPROM Address Lines to These
Val ues
Bytes Example EEPROM A2 A1 A0
16 24AA00
[8]
N/A N/A N/A
12824AA01 000
25624AA02 000
4K 24AA32 0 0 1
8K 24AA64 0 0 1
16K 24AA128 0 0 1
3.18.2 I2C Interface Boot Load Access
At power on reset the I2C interface boot loader loads the
VID/PID/DID and configuration bytes and up to 16 kBytes of
program/data. The available RAM spaces are 16 kBytes from
Figure 4-1. Signals
Port GPIF Master Slave FIFO
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
IFCLK
CLKOUT
DPLUS
DMINUS
PB5
PB4
PB3
PB2
PB1
PB0
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The
8051 is reset. I
2
C interface boot loads only occur after power
on reset.
3.18.3 I
The 8051 can control peripherals connected to the I2C bus
using the I2CTL and I2DAT registers. FX2LP18 provides I
master control only, it is never an I
2
C Interface General Purpose Access
2
C slave.
2
4.0 Pin Assignments
Figure 4-1 identifies all signals for the package. It is followed
by the pin diagram.Three modes are available: Port, GPIF
master, and Slave FIFO. These modes define the signals on
the right edge of the diagram. The 8051 selects the interface
mode using the IFCONFIG[1:0] register bits. Port mode is the
power on default configuration.
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
RDY0
RDY1
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
INT0#/PA0
INT1#/PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
C
Note
8. This EEPROM does not have address pins.
Document # 001-06120 Rev *F Page 10 of 39
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Figure 4-2. CY7C68053 56-pin VFBGA Pin Assignment - Top view
12345678
CY7C68053
A
B
C
D
E
F
G
H
1A 2A 3A 4A 5A 6A 7A 8A
1B 2B 3B 4B 5B 6B 7B 8B
1C 2C 3C 4C 5C 6C 7C 8C
1D 2D 7D 8D
1E 2E 7E 8E
1F 2F 3F 4F 5F 6F 7F 8F
1G 2G 3G 4G 5G 6G 7G 8G
1H 2H 3H 4H 5H 6H 7H 8H
Document # 001-06120 Rev *F Page 11 of 39
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CY7C68053
4.1 CY7C68053 Pin Descriptions
Table 4-1. FX2LP18 Pin Descriptions
56 VFBGA Name Type Default Description
2D AV
1D AV
CC
CC
Power N/A Analog VCC. Connect this pin to 3.3V power source. This signal provides
Power N/A Analog VCC. Connect this pin to 3.3V power source. This signal provides
2F AGND Ground N/A Analog Ground. Connect this pin to ground with as short a path as
1F AGND Ground N/A Analog Ground. Connect to this pin ground with as short a path as
1E DMINUS I/O/Z Z USB D– Signal. Connect this pin to the USB D– signal.
2E DPLUS I/O/Z Z USB D+ Signal. Connect this pin to the USB D+ signal.
8B RESET# Input N/A Active LOW Reset. This pin resets the entire chip. See Section 3.9 ”Reset
1C XTALIN Input N/A Crystal Input. Connect this signal to a 24 MHz parallel resonant, funda-
2C XTALOUT Output N/A Crystal Output. Connect this signal to a 24 MHz parallel resonant, funda-
2B CLKOUT O/Z 12 MHz CLKOUT. 12-, 24- or 48-MHz clock, phase locked to the 24 MHz input
Port A
8G PA0 or
I/O/Z I
INT0#
6G PA1 or
I/O/Z I
INT1#
8F PA2 or
I/O/Z I
SLOE
7F PA3 or
I/O/Z I
WU2
[9]
power to the analog section of the chip.
Appropriate bulk/bypass capacitance should be provided for this
supply rail.
power to the analog section of the chip.
possible.
possible.
and Wakeup” on page 5 for more details.
mental mode crystal and load capacitor to GND.
It is also correct to drive XTALIN with an external 24-MHz square wave
derived from another clock source.
mental mode crystal and load capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
clock. The 8051 defaults to 12 MHz operation. The 8051 may tri-state this
output by setting CPUCS.1 = 1.
(PA0)
(PA1)
(PA2)
(PA3)
Multiplexed pin whose function is selected by PORTACFG.0
PA0 is a bidirectional IO port pin.
INT0# is the active LOW 8051 INT0 interrupt input signal, which is either
edge triggered (IT0 = 1) or level triggered (IT0 = 0).
Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional IO port pin.
INT1# is the active LOW 8051 INT1 interrupt input signal, which is either
edge triggered (IT1 = 1) or level triggered (IT1 = 0).
Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPINPOLAR.4) for the slave FIFO’s connected to FD[7:0] or FD[15:0].
Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional IO port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit
(WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in
suspend and WU2EN = 1, a transition on this pin starts up the oscillator
and interrupts the 8051 to allow it to exit the suspend mode. Asserting this
pin inhibits the chip from suspending, if WU2EN = 1.
Note
9. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and
in standby. Note also that no pins should be driven while the device is powered down
Document # 001-06120 Rev *F Page 12 of 39
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