Cypress CY7C68024, CY7C68023 User Manual
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CY7C68023/CY7C68024
EZ-USB NX2LP™ USB 2.0 NAND
Flash Controlle
1.0 Features
• High (480-Mbps) or full (12-Mbps) speed USB support
• Both common NAND page sizes supported
— 512bytes—Up to 1 Gbit Capacity
— 2K bytes—Up to 8 Gbit Capacity
• 8 chip enable pins
— Up to 8 NAND Flash single-device chips
— Up to 4 NAND Flash dual-device chips
• Industry standard ECC NAND Flash correction
— 1 bit per 256 correction
— 2 bit error detection
• Industry standard (SmartMedia) page management for
wear leveling algorithm, bad block handling, and
Physical to Logical management.
• Supports 8-bit NAND Flash interfaces
• Supports 30-ns, 50-ns, 100-ns NAND Flash timing
• Complies with USB Mass Storage Class Specification
rev 1.0
• CY7C68024 complies with USB 2.0 Specification for
Bus-Powered Devices (TID# 40460274)
• 43-mA Typical Active Current
• Space-saving and lead-free 56-QFN package (8 mm
8mm)
• Support for board-level manufacturing test via USB
interface
• 3.3V NAND Flash operation
• NAND Flash power management support
×
2.0 Introduction
The EZ-USB NX2LP (NX2LP) implements a USB 2.0 NAND
Flash controller. This controller adheres to the Mass Storage
Class Bulk-Only Transport Specification. The USB port of the
NX2LP is connected to a host computer directly or via the
downstream port of a USB hub. Host software issues
commands and data to the NX2LP and receives status and
data from the NX2LP using standard USB protocol.
The NX2LP supports industry leading 8-bit NAND Flash interfaces and both common NAND page sizes of 512 and 2k
bytes. Eight chip enable pins allow the NX2LP to be connected
to up to eight single- or four dual-device NAND Flash chips.
Certain NX2LP features are configurable, enabling the NX2LP
to meet the needs of different designs’ requirements.
24 MHz
Xtal
VBUS
D+
D-
Chip Reset
PLL
USB 2.0
Xceiver
EZ-USB NX2LP
Internal Control Logic
Smart HS/
FS USB
Engine
Figure 1-1. NX2LP Block Diagram
Data
Control
Write Protect
LED2#
LED1#
NAND Flash
Interface
Logic
NAND Control Signals
Chip Enable Signals
8-bit Data Bus
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08055 Rev. *B Revised October 5, 2005
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3.0 Pin Assignments
3.1 Pin Diagram
GND
CY7C68023/CY7C68024
VCC
N/C
GND
CE7#
CE6#
CE5#
CE4#
CE3#
CE2#
CE1#
CE0#
Reserved
VCC
R_B1#
R_B2#
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
N/C
GND
56555453525150494847464544
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EZ-USB NX2LP
56-pin QFN
1516171819
VCC
Reserved
Reserved
202122232425262728
DD0
DD1
DD2
DD3
DD4
Figure 3-1. 56-pin QFN
43
RESET#
42
GND
41
N/C
40
N/C
39
WP_SW#
38
WP_NF#
37
LED2#
36
LED1#
35
ALE
34
CLE
33
VCC
32
RE1#
31
RE0#
30
WE#
29
DD5
DD6
DD7
VCC
GND
GND
3.2 Pin Descriptions
Pin Name Type Default State at Start-up Description
1 R_B1#
2 R_B2# I Z Ready/Busy 2 (2.2k to 4k pull-up resistor is required)
3 AVC C PWR PWR Analog 3.3V supply
4 XTALOUT Xtal N/A Crystal output
5 XTALIN Xtal N/A Crystal input
6 AGND GND GND Ground
7 AVC C PWR PWR Analog 3.3V supply
8 DPLUS I/O Z USB D+
9 DMINUS I/O Z USB D-
10 AGND GND GND Ground
11 VCC PWR PWR 3.3V supply
12 GND GND GND Ground
13 N/C N/A N/A No connect
14 GND GND GND Ground
15 Reserved N/A N/A Must be tied HIGH (no pull-up resistor required)
Note:
1. A # sign after the pin name indicates that it is an active LOW signal.
Document #: 38-08055 Rev. *B Page 2 of 9
[1]
I Z Ready/Busy 1 (2.2k to 4k pull-up resistor is required)
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CY7C68023/CY7C68024
3.2 Pin Descriptions (continued)
Pin Name Type Default State at Start-up Description
16 Reserved N/A N/A Must be tied HIGH (no pull-up resistor required)
17 VCC PWR PWR 3.3V supply
18 DDO I/O Z Data 0
19 DD1 I/O Z Data 1
20 DD2 I/O Z Data 2
21 DD3 I/O Z Data 3
22 DD4 I/O Z Data 4
23 DD5 I/O Z Data 5
24 DD6 I/O Z Data 6
25 DD7 I/O Z Data 7
26 GND GND GND Ground
27 VCC PWR PWR 3.3V supply
28 GND GND GND Ground
29 WE# O H Write enable
30 RE0# O H Read Enable 0
31 RE1# O H Read Enable 1
32 VCC PWR PWR 3.3V supply
33 CLE O Z Command latch enable
34 ALE O Z Address latch enable
35 LED1# O Z Data activity LED sink
36 LED2# O Z Chip active LED sink
37 WP_NF# O Z Write-protect NAND Flash
38 WP_SW# I Z Write-protect switch input
39 N/C N/A N/A No connect
40 N/C N/A N/A No connect
41 GND GND GND Ground
42 RESET# I Z NX2LP chip reset
43 VCC PWR PWR 3.3V supply
44 Reserved N/A N/A Must be tied HIGH
45 CE0# O Z Chip enable 0
46 CE1# O Z Chip enable 1
47 CE2# O Z Chip enable 2
48 CE3# O Z Chip enable 3
49 CE4# O Z Chip enable 4
50 CE5# O Z Chip enable 5
51 CE6# O Z Chip enable 6
52 CE7# O Z Chip enable 7
53 GND GND GND Ground
54 N/C N/A N/A No connect
55 VCC PWR PWR 3.3V supply
56 GND GND GND Ground
Document #: 38-08055 Rev. *B Page 3 of 9
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