■ CY7C68015A: Ideal for Non Battery Powered Applications
❐ Suspend current: 300 A (typ)
■ Available in Pb-free 56-pin QFN Package (26 GPIOs)
■ Two more GPIOs than CY7C68013A/14A enabling additional
features in same footprint
Cypress Semiconductor Corporation•198 Champion Court•San Jose, CA 95134-1709•408-943-2600
Document #: 38-08032 Rev. *V Revised February 7, 2012
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Address (16)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
VCC
1.5k
D+
D–
Address (16) / Data Bus (8)
FX2LP
GPIF
CY
Smart
USB
1.1/2.0
Engine
USB
2.0
XCVR
16 KB
RAM
4 kB
FIFO
Integrated
full speed and
Additional I/Os (24)
ADDR (9)
CTL (6)
RDY (6)
8/16
Data (8)
24 MHz
Ext. XTAL
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Up to 96 MBytes/s
burst rate
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
Abundant I/O
including two USARTs
High performance micro
using standard tools
with lower-power options
Master
connected for
full speed
ECC
XCVR
high speed
Logic Block Diagram
Cypress’s EZ-USB® FX2LP (CY7C68013A/14A) is a low
power version of the EZ-USB FX2(CY7C68013), which is a
highly integrated, low power USB 2.0 microcontroller. By
integrating the USB 2.0 transceiver, serial interface engine (SIE),
enhanced 8051 microcontroller, and a programmable peripheral
interface in a single chip,
Cypress has created a cost effective solution that provides
superior time-to-market advantages with low power to enable
bus powered applications.
The ingenious architecture of FX2LP results in data transfer
rates of over 53 Mbytes per second, the maximum allowable
USB 2.0 bandwidth, while still using a low cost 8051
microcontroller in a package as small as a 56 VFBGA (5 mm x 5
mm). Because it incorporates the USB 2.0 transceiver, the
FX2LP is more economical, providing a smaller footprint solution
Document #: 38-08032 Rev. *V Page 2 of 66
than USB 2.0 SIE or external transceiver implementations. With
EZ-USB FX2LP, the Cypress Smart SIE handles most of the
USB 1.1 and 2.0 protocol in hardware, freeing the embedded
microcontroller for application specific functions and decreasing
development time to ensure USB compatibility.
The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and
glueless interface to popular interfaces such as
A TA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
The FX2LP draws less current than the FX2 (CY7C68013), has
double the on-chip code/data RAM, and is fit, form and function
compatible with the 56, 100, and 128 pin FX2.
Five packages are defined for the family: 56 VFBGA, 56 SSOP,
56 QFN, 100 TQFP, and 128 TQFP.
12 pF capacitor values assumes a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
Note
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.
1. Applications
■ Portable video recorder
■ MPEG/TV conversion
■ DSL modems
■ ATA interface
■ Memory card readers
■ Legacy conversion devices
■ Cameras
■ Scanners
■ Wireless LAN
■ MP3 players
■ Networking
The “Reference Designs” section of the Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Visit
www.cypress.com for more information.
2. Functional Overview
2.1 USB Signaling Speed
FX2LP operates at two of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
■ Full speed, with a signaling bit rate of 12 Mbps
■ High speed, with a signaling bit rate of 480 Mbps
FX2LP does not support the low speed signaling mode of
1.5 Mbps.
2.2 8051 Microprocessor
The 8051 microprocessor embedded in the FX2LP family has
256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
2.2.1 8051 Clock Frequency
FX2LP has an on-chip oscillator circuit that uses an external
24 MHz (±100 ppm) crystal with the following characteristics:
■ Parallel resonant
■ Fundamental mode
■ 500 W drive level
■ 12 pF (5% tolerance) load capacitors
An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
as required by the transceiver/PHY and internal counters divide
it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically.
Figure 2-1. Crystal Configuration
The CLKOUT pin, which can be three-stated and inverted using
internal control bits, outputs the 50% duty cycle 8051 clock, at
the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.
2.2.2 USARTs
FX2LP contains two standard 8051 USART s, addressed through
Special Function Register (SFR) bits. The USART interface pins
are available on separate I/O pins, and are not multiplexed with
port pins.
UART0 and UART1 can operate using an internal clock at
230 KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and
12 MHz) such that it always presents the correct frequency for
230 KBaud operation.
[1]
2.2.3 Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX2LP functions. These SFR additions are
shown in Table 1 on page 5. Bold type indicates non standard,
enhanced 8051 registers. The two SFR rows that end with “0”
and “8” contain bit addressable registers. The four I/O ports A to
D use the SFR addresses used in the standard 8051 for ports 0
to 3, which are not implemented in FX2LP . Because of the faster
and more efficient SFR addressing, the FX2LP I/O ports are not
addressable in external RAM space (using the MOVX
instruction).
2.3 I2C Bus
FX2LP supports the I2C bus as a master only at 100/400 KHz.
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3V, even if no I
2
C
device is connected.
2.4 Buses
All packages, 8-bit or 16-bit “FIFO” bidirectional data bus,
multiplexed on I/O ports B and D. 128-pin package: adds 16-bit
output-only 8051 address bus, 8-bit bidirectional data bus.
Document #: 38-08032 Rev. *V Page 4 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 1. Special Function Registers
Note
2. The I
2
C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
During the power up sequence, internal logic checks the I2C port
for the connection of an EEPROM whose first byte is either 0xC0
or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
in place of the internally stored values (0xC0), or it boot-loads the
EEPROM contents into internal RAM (0xC2). If no EEPROM is
detected, FX2LP enumerates using internally stored descriptors.
The default ID values for FX2LP are VID/PID/DID (0x04B4,
0x8613, 0xAxxx where xxx = Chip revision).
Because the FX2LP’s configuration is soft, one chip can take on
the identities of multiple distinct USB devices.
When first plugged into USB, the FX2LP enumerates
automatically and downloads firmware and USB descriptor
tables over the USB cable. Next, the FX2LP enumerates again,
this time as a device defined by the downloaded information.
This patented two step process called ReNumeration happens
instantly when the device is plugged in, without a hint that the
initial download step has occurred.
Two control bits in the USBCS (USB Control and S tatus) register,
control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To
reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit
to indicate whether the firmware or the Default USB Device
handles device requests over endpoint zero: if RENUM = 0, the
Default USB Device handles device requests; if RENUM = 1, the
firmware services the requests.
2.7 Bus-Powered Applications
The FX2LP fully supports bus powered designs by enumerating
with less than 100 mA as required by the USB 2.0 specification.
2.8 Interrupt System
2.8.1 INT2 Interrupt Request and Enable Registers
FX2LP implements an autovector feature for INT2 and INT4.
There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)
vectors. See EZ-USB Technical Reference Manual (TRM) for
more details.
2.8.2 USB Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that is required to identify the
individual USB interrupt source, the FX2LP provides a second
level of interrupt vectoring, called Autovectoring. When a USB
interrupt is asserted, the FX2LP pushes the program counter to
its stack, and then jumps to the address 0x0043 where it expects
to find a “jump” instruction to the USB Interrupt service routine.
Document #: 38-08032 Rev. *V Page 5 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
The FX2LP jump instruction is encoded as follows:
Table 3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
PriorityINT2VEC ValueSource Notes
1 00SUDAV Setup data available
2 04 SOF Start of frame (or microframe)
3 08SUTOK Setup token received
4 0CSUSPEND USB suspend request
5 10USB RESETBus reset
6 14HISPEED Entered high speed operation
7 18 EP0ACK FX2LP ACK’d the CONTROL Handshake
8 1C reserved
9 20 EP0-IN EP0-IN ready to be loaded with data
10 24 EP0-OUT EP0-OUT has USB data
11 28 EP1-IN EP1-IN ready to be loaded with data
12 2C EP1-OUT EP1-OUT has USB data
13 30 EP2 IN: buffer available. OUT: buffer has data
14 34 EP4 IN: buffer available. OUT: buffer has data
15 38 EP6 IN: buffer available. OUT: buffer has data
16 3C EP8 IN: buffer available. OUT: buffer has data
17 40 IBN IN-Bulk-NAK (any IN endpoint)
18 44reserved
19 48 EP0PINGEP0 OUT was pinged and it NAK’d
20 4C EP1PING EP1 OUT was pinged and it NAK’d
21 50 EP2PING EP2 OUT was pinged and it NAK’d
22 54 EP4PING EP4 OUT was pinged and it NAK’d
23 58 EP6PING EP6 OUT was pinged and it NAK’d
24 5C EP8PING EP8 OUT was pinged and it NAK’d
25 60 ERRLIMITBus errors exceeded the programmed limit
26 64 ––
27 68 –Reserved
28 6C –Reserved
29 70 EP2ISOERR ISO EP2 OUT PID sequence error
30 74 EP4ISOERR ISO EP4 OUT PID sequence error
31 78 EP6ISOERR ISO EP6 OUT PID sequence error
32 7C EP8ISOERR ISO EP8 OUT PID sequence error
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high
byte (“page”) of a jump table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs
the jump to the correct address out of the 27 addresses within the page.
2.8.3 FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual
FIFO/GPIF sources. The FIFO/GPIF Interrupt, similar to the USB Interrupt, can employ autovectoring. Table 4 on page 7 shows the
priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.
Document #: 38-08032 Rev. *V Page 6 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Ta bl e 4. Individ ua l FI FO /GPIF Interrupt Sources
Note
3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 s.
PriorityINT4VEC ValueSource Notes
180EP2PFEndpoint 2 programmable flag
2 84 EP4PFEndpoint 4 programmable flag
388EP6PFEndpoint 6 programmable flag
48CEP8PFEndpoint 8 programmable flag
590EP2EFEndpoint 2 empty flag
694EP4EFEndpoint 4 empty flag
798EP6EFEndpoint 6 empty flag
89CEP8EFEndpoint 8 empty flag
9A0 EP2FFEndpoint 2 full flag
10A4EP4FFEndpoint 4 full flag
1 1 A8EP6FFEndpoint 6 full flag
12AC EP8FFEndpoint 8 full flag
13 B0GPIFDONEGPIF operation complete
14 B4GPIFWFGPIF waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the FX 2LP substitutes its INT4VEC byte. Therefore, if
the high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically inserted INT4VEC byte at
0x0055 directs the jump to the correct address out of the 14
addresses within the page. When the ISR occurs, the FX2LP
pushes the program counter to its stack then jumps to address
0x0053, where it expects to find a “jump” instruction to the ISR
Interrupt service routine.
2.9 Reset and Wakeup
2.9.1 Reset Pin
The input pin, RESET#, resets the FX2LP when asserted. This
pin has hysteresis and is active LOW. When a crystal is used with
the CY7C680xxA the reset period must enable stabilization of
the crystal and the PLL. This reset period must be approximately
5 ms after VCC reaches 3.0V . If the cryst al input pin is driven by
a clock signal the internal PLL stabilizes in 200 s after VCC has
reached 3.0V.
Figure 2-2 on page 8 shows a power on reset condition and a
reset applied during operation. A power on reset is defined as
the time reset that is asserted while power is being applied to the
circuit. A powered reset is when the FX2LP powered on and
operating and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation. For more
information about reset implementation for the FX2 family of
products visit http://www.cypress.com.
[3]
Document #: 38-08032 Rev. *V Page 7 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
V
IL
0V
3.3V
3.0V
T
RESET
VCC
RESET#
Power on Reset
T
RESET
VCC
RESET#
V
IL
Powered Reset
3.3V
0V
Figure 2-2. Reset Timing Plots
Table 2-1. Reset Timing Values
ConditionT
RESET
Power on reset with crystal5 ms
Power on reset with external
200 s + Clock stability time
clock
Powered Reset200 s
2.9.2 Wakeup Pins
The 8051 puts itself and the rest of the chip into a power down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic the oscillator
restarts after the PLL stabilizes, and the 8051 receives a wakeup
interrupt. This applies whether or not FX2LP is connected to the
USB.
The FX2LP exits the power down (USB suspend) state using one
of the following methods:
■ USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX2LP and initiate a wakeup)
■ External logic asserts the WAKEUP pin
■ External logic asserts the PA3/WU2 pin
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This enables a simple external R-C
network to be used as a periodic wakeup source. WAKEUP is by
default active LOW.
2.10 Program/Data RAM
2.10.1 Size
The FX2LP has 16 KBytes of internal program/d ata RAM, where
PSEN#/RD# signals are internally ORed to enable the 8051 to
access it as both program and data memory. No USB control
registers appear in this space.
Two memory maps are shown in the following diagrams:
Figure 2-3 on page 9 shows the Internal Code Memory, EA = 0
Figure 2-4 on page 10 shows the External Code Memory, EA = 1.
2.10.2 Internal Code Memory, EA = 0
This mode implements the internal 16 KByte block of RAM
(starting at 0) as combined code and data memory. When
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside the
chip. This enables the user to connect a 64 KByte memory
without requiring address decodes to keep clear of internal
memory spaces.
Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM
spaces have the following access:
■ USB download
■ USB upload
■ Setup data pointer
2
■ I
C interface boot load.
2.10.3 External Code Memory, EA = 1
The bottom 16 KBytes of program memory is external and
therefore the bottom 16 KBytes of internal RAM is accessible
only as a data memory.
Document #: 38-08032 Rev. *V Page 8 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 2-3. Internal Code Memory, EA = 0
Inside FX2LPOutside FX2LP
7.5 KBytes
USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KBytes RAM
Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KBytes
External
Data
Memory
(RD#,WR#)
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KBytes RAM
Code and Data
(PSEN#,RD#,WR#)*
48 KBytes
External
Code
Memory
(PSEN#)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
*SUDPTR, USB upload/download, I2C interface boot access
FFFF
E200
E1FF
E000
3FFF
0000
DataCode
Document #: 38-08032 Rev. *V Page 9 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 2-4. External Code Memory, EA = 1
Inside FX2LPOutside FX2LP
7.5 KBytes
USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KBytes RAM
Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KBytes
External
Data
Memory
(RD#,WR#)
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KBytes
RAM
Data
(RD#,WR#)*
64 KBytes
External
Code
Memory
(PSEN#)
*SUDPTR, USB upload/download, I2C interface boot access
FFFF
E200
E1FF
E000
3FFF
0000
DataCode
FFFF
E800
E7BF
E740
E73F
E700
E6FF
E500
E4FF
E480
E47F
E400
E200
E1FF
E000
E3FF
EFFF
2 KBytes RESERVED
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addressable Registers
Reserved (128)
128 bytes GPIF Waveforms
512 bytes
8051 xdata RAM
F000
(512)
Reserved (512)
E780
64 Bytes EP1OUT
E77F
64 Bytes EP1IN
E7FF
E7C0
4 KBytes EP2-EP8
buffers
(8 x 512)
2.11 Register Addresses
Document #: 38-08032 Rev. *V Page 10 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
2.12 Endpoint RAM
64
64
64
512
512
1024
1024
1024
1024
1024
1024
1024
512
512
512
512
512
512
512
512
512
512
EP2
EP2
EP2
EP6
EP6
EP8
EP8
EP0 IN&OUT
EP1 IN
EP1 OUT
1024
1024
EP6
1024
512
512
EP8
512
512
EP6
512
512
512
512
EP2
512
512
EP4
512
512
EP2
512
512
EP4
512
512
EP2
512
512
EP4
512
512
EP2
512
512
512
512
EP2
512
512
512
512
EP2
512
512
1024
EP2
1024
1024
EP2
1024
1024
EP2
1024
512
512
EP6
1024
1024
EP6
512
512
EP8
512
512
EP6
512
512
512
512
EP6
1024
1024
EP6
512
512
EP8
512
512
EP6
512
512
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
1
2
3
4
5
6
7
8
9
10
11
12
2.12.1 Size
■ 3 × 64 bytes(Endpoints 0 and 1)
■ 8 × 512 bytes (Endpoints 2, 4, 6, 8)
2.12.2 Organization
■ EP0
■ Bidirectional endpoint zero, 64 byte buffer
■ EP1IN, EP1OUT
■ 64 byte buffers, bulk or interrupt
■ EP2, 4, 6, 8
■ Eight 512 byte buffers, bulk, interrupt, or isochronous. EP4 and
EP8 can be double buffered; EP2 and 6 can be either double,
triple, or quad buffered. For high speed endpoint configuration
options, see Figure 2-5.
Figure 2-5. Endpoint Configuration
2.12.3 Setup Data Buffer
A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data
from a CONTROL transfer.
2.12.4 Endpoint Configurations (High Speed Mode)
Endpoints 0 and 1 are the same for every configuration. Endpoint
0 is the only CONTROL endpoint, and endpoint 1 can be either
BULK or INTERRUPT.
The endpoint buffers can be configured in any 1 of the 12
configurations shown in the vertical columns. When operating in
the full speed BULK mode only the first 64 bytes of each buffer
are used. For example, in high speed, the max packet size is 512
bytes but in full speed it is 64 bytes. Even though a buffer is
configured to a 512 byte buffer, in full speed only the first 64 bytes
are used. The unused endpoint buffer space is not available for
other operations. An example endpoint configuration is the
EP2–1024 double buffered; EP6–512 quad buffered (column 8).
Document #: 38-08032 Rev. *V Page 11 of 66
CY7C68013A, CY7C68014A
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2.12.5 Default Full Speed Alternate Settings
Notes
4. “0” means “not implemented.”
5. “2×” means “double buffered.”
6. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Table 5. Default Full Speed Alternate Settings
Alternate Setting0123
ep064646464
ep1out064 bulk64 int64 int
ep1in064 bulk64 int64 int
ep2064 bulk out (2×)64 int out (2×)64 iso out (2×)
ep4064 bulk out (2×)64 bulk out (2×)64 bulk out (2×)
ep6064 bulk in (2×)64 int in (2×)64 iso in (2×)
ep8064 bulk in (2×)64 bulk in (2×)64 bulk in (2×)
2.12.6 Default High Speed Alternate Settings
Table 6. Default High Speed Alternate Settings
Alternate Setting0123
ep064646464
ep1out0512 bulk
ep1in0512 bulk
ep20512 bulk out (2×)512 int out (2×)512 iso out (2×)
ep40512 bulk out (2×)512 bulk out (2×)512 bulk out (2×)
ep60512 bulk in (2×)512 int in (2×)512 iso in (2×)
ep80512 bulk in (2×)512 bulk in (2×)512 bulk in (2×)
[4, 5]
[6]
[6]
[4, 5]
64 int64 int
64 int64 int
2.13 External FIFO Interface
2.13.1 Architecture
The FX2LP slave FIFO architecture has eight 512 byte blocks in
the endpoint RAM that directly serve as FIFO memories and are
controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from the
SIE, while the others are connected to the I/O transfer logic. The
transfer logic takes two forms, the GPIF for internally generated
control signals and the slave FIFO interface for externally
controlled transfers.
2.13.2 Master/Slave Control Signals
The FX2LP endpoint FIFOS are implemented as eight physically
distinct 256x16 RAM blocks. The 8051/SIE can switch any of the
RAM blocks between two domains, the USB (SIE) domain and
the 8051-I/O Unit domain. This switching is done virtually
instantaneously, giving essentially zero transfer time between
“USB FIFOS” and “Slave FIFOS.” Because they are physically
the same memory no bytes are actually transferred between
buffers.
At any time, some RAM blocks are filling/emptying with USB data
under SIE control, while other RAM blocks are available to the
8051, the I/O control unit or both. The RAM blocks operate as
single port in the USB domain, and dual port in the 8051-I/O
domain. The blocks can be configured as single, double, triple,
or quad buffered as previously shown.
The I/O control unit implements either an internal master (M for
master) or external master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0]
to select a FIFO. The RDY pins (two in the 56-pin package, six
in the 100-pin and 128-pin packages) can be used as flag inputs
from an external FIFO or other lo gic if desired. The GPIF can be
run from either an internally derived clock or externally supplied
clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s
(48 MHz IFCLK with 16-bit interface).
In Slave (S) mode, the FX2LP accepts either an internally
derived clock or externally supplied clock (IFCLK, max frequency
48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals
from external logic. When using an external IFCLK, the external
clock must be present before switching to the external clock with
the IFCLKSRC bit. Each endpoint can individually be selected
for byte or word operation by an internal configuration bit and a
Slave FIFO Output Enable signal SLOE enables data of the
selected width. External logic must ensure that the output enable
signal is inactive when writing data to a slave FIFO. The slave
interface can also operate asynchronously, where the SLRD and
SLWR signals act directly as strobes, rather than a clock qualifier
as in synchronous mode. The signals SLRD, SLWR, SLOE and
PKTEND are gated by the signal SLCS#.
Document #: 38-08032 Rev. *V Page 12 of 66
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2.13.3 GPIF and FIFO Clock Rates
Notes
7. T o use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
8. After the data is downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory.
An 8051 register bit selects one of two frequencies for the
internally supplied interface clock: 30 MHz and 48 MHz.
Alternatively, an externally supplied clock of 5 MHz–48 MHz
feeding the IFCLK pin can be used as the interface clock. IFCLK
can be configured to function as an output clock when the GPIF
and FIFOs are internally clocked. An output enable bit in the
IFCONFIG register turns this clock output off, if desire d. Another
bit within the IFCONFIG register inverts the IFCLK signal
whether internally or externally sourced.
2.14 GPIF
The GPIF is a flexible 8-bit or 16-bit parallel interface driven by
a user programmable finite state machine. It enables the
CY7C68013A/15A to perform local bus mastering and can
implement a wide variety of protocols such as ATA interface,
printer parallel port, and Utopia.
The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general-purpose ready
inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF
vector defines the state of the control outputs, and determines
what state a ready input (or multiple inputs) must be before
proceeding. The GPIF vector can be programmed to advance a
FIFO to the next data value, advance an address, etc. A
sequence of the GPIF vectors make up a single waveform that
is executed to perform the desired data move between the
FX2LP and the external device.
2.14.1 Six Control OUT Signals
The 100-pin and 128-pin packages bring out all six Control
Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to
define the CTL waveforms. The 56-pin package brings out three
of these signals, CTL0–CTL2. CTLx waveform edges can be
programmed to make transitions as fast as once per clock (20.8
ns using a 48 MHz clock).
2.14.2 Six Ready IN Signals
The 100-pin and 128-pin packages bring out all six Ready inputs
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56-pin package brings out two
of these signals, RDY0–1.
2.14.3 Nine GPIF Address OUT Signals
Nine GPIF address lines are available in the 100-pin and 128-pin
packages, GPIFADR[8..0]. The GPIF address lines enable
indexing through up to a 512 byte block of RAM. If more address
lines are needed I/O port pins are used.
2.14.4 Long Transfer Mode
In the master mode, the 8051 appropriately sets GPIF
transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1,
or GPIFTCB0) for unattended transfers of up to 2
The GPIF automatically throttles data flow to prevent under or
overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
32
transactions.
2.15 ECC Generation
The EZ-USB can calculate ECCs (Error Correcting Codes) on
data that passes across its GPIF or Slave FIFO interfaces. There
are two ECC configurations: Two ECCs, each calculated over
256 bytes (SmartMedia Standard); and one ECC calculated over
512 bytes.
The ECC can correct any one-bit error or detect any two-bit error.
2.15.1 ECC Implementation
The two ECC configurations are selected by the ECCM bit:
ECCM = 0
Two 3 byte ECCs, each calculated over a 256 byte block of data.
This configuration conforms to the SmartMedia Standard.
Write any value to ECCRESET, then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 256 bytes of data
is calculated and stored in ECC1. The ECC for the next 256 bytes
is stored in ECC2. After the second ECC is calculated, the values
in the ECCx registers do not change until ECCRESET is written
again, even if more data is subsequently passed across the
interface.
ECCM = 1
One 3 byte ECC calculated over a 512 byte block of data.
Write any value to ECCRESET then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 512 bytes of data
is calculated and stored in ECC1; ECC2 is unused. After the
ECC is calculated, the values in ECC1 do not change even if
more data is subsequently passed across the interface, till
ECCRESET is written again.
[7]
2.16 USB Uploads and Downloads
The core has the ability to directly edit the da ta contents of the
internal 16 KByte RAM and of the internal 512 byte scratch pad
RAM via a vendor specific command. This capability is normally
used when soft downloading user code and is available only to
and from internal RAM, only when the 8051 is held in reset. The
available RAM spaces are 16 KBytes from 0x0000–0x3FFF
(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad
data RAM).
[8]
2.17 Autopointer Access
FX2LP provides two identical autopointers. They are similar to
the internal 8051 data pointers but with an additional feature:
they can optionally increment after every memory access. This
capability is available to and from both internal and external
RAM. The autopointers are available in external FX2LP registers
under control of a mode bit (AUTOPTRSET-UP.0). Using the
external FX2LP autopointer access (at 0xE67B – 0xE67C)
enables the autopointer to access all internal and external RAM
to the part.
Also, the autopointers can point to any FX2LP register or
endpoint buffer space. When autopointer access to external
memory is enabled, location 0xE67B and 0xE67C in XDAT A and
code space cannot be used.
Document #: 38-08032 Rev. *V Page 13 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
2.18 I2C Controller
Note
9. This EEPROM does not have address pins.
FX2LP has one I2C port that is driven by two internal controllers,
one that automatically operates at boot time to load VID/PID/DID
and configuration information, and another that the 8051 uses
when running to control external I
operates in master mode only.
2.18.1 I
The I
2
C Port Pins
2
C pins SCL and SDA must have external 2.2 k pull up
resistors even if no EEPROM is connected to the FX2LP.
External EEPROM device address pins must be configured
properly. See Table 7 for configuring the device address pins.
Table 7. Strap Boot EEPROM Address Lines to These V alues
For designers migrating from the FX2 to the FX2LP a change in
the bill of material and review of the memory allocation (due to
increased internal memory) is required. For more information
about migrating from EZ-USB FX2 to EZ-USB FX2LP, see th e
application note titled Migrating from EZ-USB FX2 to EZ-USB FX2LP available in the Cypress web site.
Table 8. Part Number Conversion Table
EZ-USB FX2
Part Number
CY7C68013-56PVC CY7C68013A-56PVXC or
CY7C68013-56PVCT CY7C68013A-56PVXCT or
EZ-USB FX2LP
Part Number
CY7C68014A-56PVXC
CY7C68014A-56PVXCT
Package
Description
56-pin
SSOP
56-pin
SSOP –
Tape and
Reel
CY7C68013-56LFCCY7C68013A-56LFXC or
56-pin QFN
CY7C68014A-56LFXC
CY7C68013-100ACCY7C68013A-100AXC or
CY7C68014A-100AXC
CY7C68013-128ACCY7C68013A-128AXC or
CY7C68014A-128AXC
100-pin
TQFP
128-pin
TQFP
2.18.2 I2C Interface Boot Load Access
At power on reset the I
2
C interface boot loader loads the
VID/PID/DID configuration bytes and up to 16 KBytes of
program/data. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051
is in reset. I
2
C interface boot loads only occur after power on
reset.
2
2.18.3 I
The 8051 can control peripherals connected to the I2C bus using
the I
control only, it is never an I
C Interface General-Purpose Access
2
CTL and I2DAT registers. FX2LP provides I2C master
2
C slave.
2.19 Compatible with Previous Generation
EZ-USB FX2
The EZ-USB FX2LP is form, fit and with minor exceptions
functionally compatible with its predecessor, the EZ-USB FX2.
This makes for an easy transition for designers wanting to
upgrade their systems from the FX2 to the FX2LP. The pinout
and package selection are ide nt i cal an d a vast majo ri ty of
firmware previously developed for the FX2 functions in the
FX2LP.
2.20 CY7C68013A/14A and CY7C68015A/16A
Differences
CY7C68013A is identical to CY7C68014A in form, fit, and
functionality. CY7C68015A is identical to CY7C68016A in form,
fit, and functionality. CY7C68014A and CY7C68016A have a
lower suspend current than CY7C68013A and CY7C68015A
respectively and are ideal for power sensitive battery
applications.
CY7C68015A and CY7C68016A are available in 56-pin QFN
package only. Two additional GPIO signals are available on the
CY7C68015A and CY7C68016A to provide more flexibility when
neither IFCLK or CLKOUT are needed in the 56-pin package.
USB developers wanting to convert their FX2 56-pin application
to a bus-powered system directly benefit from these additional
signals. The two GPIOs give developers the signals they need
for the power control circuitry of their bus-powered application
without pushing them to a high pincount version of FX2LP.
The CY7C68015A is only available in the 56-pin QFN package
Table 9. CY7C68013A/14A and CY7C68015A/16A
Pin Differences
CY7C68013A/CY7C68014ACY7C68015A/CY7C68016A
IFCLKPE0
CLKOUTPE1
Document #: 38-08032 Rev. *V Page 14 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
3. Pin Assignments
Figure 3-1 on page 16 identifies all signals for the five package
types. The following pages illustrate the individual pin diagrams,
plus a combination diagram showing which of the full set of
signals are available in the 128-pin, 100-pin, and 56-pin
packages.
The signals on the left edge of the 56-pin package in Figure 3-1
on page 16 are common to all versions in the FX2LP family with
the noted differences between the CY7C68013A/14A and the
CY7C68015A/16A.
Three modes are available in all package versi o n s: Port , GPIF
master, and Slave FIFO. These modes define the signals on the
right edge of the diagram. The 8051 selects the interface mode
using the IFCONFIG[1:0] register bits. Port mode is the power on
default configuration.
The 100-pin package adds functionality to the 56-pin package by
adding these pins:
■ PORTC or alternate GPIFADR[7:0] address signals
■ PORTE or alternate GPIFADR[8] address signal and seven
additional 8051 signals
■ Three GPIF Control signals
■ Four GPIF Ready signals
■ Nine 8051 signals (two USART s, three timer inputs, INT4,and
INT5#)
■ BKPT, RD#, WR#.
The 128-pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100-pin version.
In the 100-pin and 128-pin versions, an 8051 control bit can be
set to pulse the RD# and WR# pins when the 8051 reads
from/writes to PORTC. This feature is enabled by setting
PORTCSTB bit in CPUCS register.
Section 9.5 displays the timing diagram of the read and write
Figure 3-6. CY7C68013A 56-pin VFBGA Pin Assignment – Top View
12345678
A
B
C
D
E
F
G
H
1A2A3A4A5A6A7A8A
1B2B3B4B5B6B7B8B
1C2C3C4C5C6C7C8C
1D2D7D8D
1E2E7E8E
1F2F3F4F5F6F7F8F
1G2G3G4G5G6G7G8G
1H2H3H4H5H6H7H8H
Document #: 38-08032 Rev. *V Page 21 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
3.1 CY7C68013A/15A Pin Descriptions
The FX2LP pin descriptions follow.
Table 10. FX2LP Pin Descriptions
128
TQFP
Note
100
TQFP
1091032DAVCCPowerN/AAnalog VCC. Connect this pin to 3.3V power source.
17161471DAVCCPowerN/AAnalog VCC. Connect this pin to 3.3V power source.
13121362FAGNDGroundN/AAnalog Ground. Connect to ground with as short a path
201917101FAGNDGroundN/AAnalog Ground. Connect to ground with as short a path
19181691EDMINUSI/O/ZZUSB D– Signal . Connect to the USB D– signal.
18171582EDPLUSI/O/ZZUSB D+ Signal. Connect to the USB D+ signal.
94––––A0OutputL8051 Address Bus. This bus is driven at all times.
95––––A1OutputL
96––––A2OutputL
59––––D0I/O/ZZ8051 Data Bus. This bidirectional bus is high
60––––D1I/O/ZZ
61––––D2I/O/ZZ
62––––D3I/O/ZZ
63––––D4I/O/ZZ
86––––D5I/O/ZZ
87––––D6I/O/ZZ
88––––D7I/O/ZZ
39––––PSEN#OutputHProgram Store Enable. This active-LOW signal
10.Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in
standby . Note also that no pins should be driven while the device is powered down.
56
SSOP
56
QFN56VFBGA
[10]
NameTypeDefaultDescription
This signal provides power to the analog section of the
chip.
This signal provides power to the analog section of the
chip.
as possible.
as possible.
When the 8051 is addressing internal RAM it reflects
the internal address.
impedance when inactive, input for bus reads, and
output for bus writes. The data bus is used for external
8051 program and data memory. The data bus is active
only for external bus accesses, and is driven LOW in
suspend.
indicates an 8051 code fetch from external memory. It
is active for program memory fetches from
0x4000–0xFFFF when the EA pin is LOW, or from
0x0000–0xFFFF when the EA pin is HIGH.
Document #: 38-08032 Rev. *V Page 22 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
3428––BKPTOutputLBreakpoint. This pin goes active (HIGH) when the 8051
997749428BRESET#InputN/AActive LOW Reset. Resets the entire chip. See section
35––––EAInputN/AExternal Access. This pin determines where the 8051
12111251CXTALINInputN/ACrystal Input. Connect this signal to a 24 MHz
11101142CXTALOUTOutputN/ACrystal Output. Connect this signal to a 24 MHz
11005542BCLKOUT on
Port A
826740338GPA0 or
836841346GPA1 or
846942358FPA2 or
56
SSOP
56
QFN56VFBGA
NameTypeDefaultDescription
address bus matches the BPADDRH/L registers and
breakpoints are enabled in the BREAKPT register
(BPEN = 1). If the BPPULSE bit in the BREAKPT
register is HIGH, this signal pulses HIGH for eight
12-/24-/48 MHz clocks. If the BPPULSE bit is LOW, the
signal remains HIGH until the 8051 clears the BREAK
bit (by writing 1 to it) in the BREAKPT register.
2.9 ”Reset and Wakeup” on page 7 for more details.
fetches code between addresses 0x0000 and 0x3FFF .
If EA = 0 the 8051 fetches this code from its internal
RAM. IF EA = 1 the 8051 fetches this code from external
memory.
parallel-resonant, fundamental mode crystal and load
capacitor to GND.
It is also correct to drive XTALIN with an external
24-MHz square wave derived from another clock
source. When driving from an external source, the
driving signal should be a 3.3V square wave.
parallel-resonant, fundamental mode crystal and load
capacitor to GND.
If an external clock is used to drive XTALIN, leave this
pin open.
O/Z
CY7C68013A
and
CY7C68014A
-----------------PE1 on
CY7C68015A
and
CY7C68016A
INT0#
INT1#
SLOE or
----------I/O/Z
I/O/ZI
I/O/ZI
I/O/ZI
12 MHz
----------
(PA0)
(PA1)
(PA2)
CLKOUT: 12-, 24- or 48 MHz clock, phase locked to the
24 MHz input clock. The 8051 defaults to 12 MHz
operation. The 8051 may three-state this output by
setting CPUCS.1 = 1.
-----------------------------------------------------------------------PE1 is a bidirectional I/O port pin.
I
Multiplexed pin whose function is sel ected by
PORTACFG.0
PA0 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input
signal, which is either edge triggered (IT0 = 1) or level
triggered (IT0 = 0).
Multiplexed pin whose function is sel e cte d by:
PORTACFG.1
PA1 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input
signal, which is either edge triggered (IT1 = 1) or level
triggered (IT1 = 0).
Multiplexed pin whose fu nction is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional I/O port pin.
SLOE is an input-only output enable with program-
mable polarity (FIFOPINPOLAR.4) fo r the slave FIFOs
connected to FD[7..0] or FD[15..0].
Document #: 38-08032 Rev. *V Page 23 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
857043367FPA3 or
897144376FPA4 or
907245388CPA5 or
917346397CPA6 or
927447406CPA7 or
Port B
443425183HPB0 or
453526194FPB1 or
463627204HPB2 or
473728214GPB3 or
544429225HPB4 or
56
SSOP
56
QFN56VFBGA
NameTypeDefaultDescription
WU2
FIFOADR0
FIFOADR1
PKTEND
FLAGD or
SLCS#
FD[0]
FD[1]
FD[2]
FD[3]
FD[4]
I/O/ZI
(PA3)
I/O/ZI
(PA4)
I/O/ZI
(PA5)
I/O/ZI
(PA6)
I/O/ZI
(PA7)
I/O/ZI
(PB0)
I/O/ZI
(PB1)
I/O/ZI
(PB2)
I/O/ZI
(PB3)
I/O/ZI
(PB4)
Multiplexed pin whose function is sel ected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled
by WU2EN bit (WAKEUP.1) and polarity set by
WU2POL (WAKEUP.4). If the 8051 is in suspend and
WU2EN = 1, a transition on this pin starts up the oscillator and interrupts the 8051 to enable it to exit the
suspend mode. Asserting this pin inhibits the chip from
suspending, if WU2EN = 1.
Multiplexed pin whose function is sel e cte d by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave
FIFOs connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is sel e cte d by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave
FIFOs connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by the
IFCONFIG[1:0] bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet
data to the endpoint and whose polarity is programmable via FIFOPINPOLAR.5.
Multiplexed pin whose function is selected by the
IFCONFIG[1:0] and PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status
flag signal.
SLCS# gates all other slave FIFO enable/strobes
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
Document #: 38-08032 Rev. *V Page 24 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
554530235GPB5 or
564631245FPB6 or
574732256HPB7 or
PORT C
7257–––PC0 or
7358–––PC1 or
7459–––PC2 or
7560–––PC3 or
7661–––PC4 or
7762–––PC5 or
7863–––PC6 or
7964–––PC7 or
PORT D
1028052458APD0 or
1038153467APD1 or
56
SSOP
56
QFN56VFBGA
NameTypeDefaultDescription
FD[5]
FD[6]
FD[7]
GPIFADR0
GPIFADR1
GPIFADR2
GPIFADR3
GPIFADR4
GPIFADR5
GPIFADR6
GPIFADR7
FD[8]
FD[9]
I/O/ZI
(PB5)
I/O/ZI
(PB6)
I/O/ZI
(PB7)
I/O/ZI
(PC0)
I/O/ZI
(PC1)
I/O/ZI
(PC2)
I/O/ZI
(PC3)
I/O/ZI
(PC4)
I/O/ZI
(PC5)
I/O/ZI
(PC6)
I/O/ZI
(PC7)
I/O/ZI
(PD0)
I/O/ZI
(PD1)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is sel ected by
PORTCCFG.0
PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
Multiplexed pin whose function is sel ected by
PORTCCFG.1
PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
Multiplexed pin whose function is sel ected by
PORTCCFG.2
PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
Multiplexed pin whose function is sel ected by
PORTCCFG.3
PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
Multiplexed pin whose function is sel ected by
PORTCCFG.4
PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
Multiplexed pin whose function is sel ected by
PORTCCFG.5
PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
Multiplexed pin whose function is sel ected by
PORTCCFG.6
PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
Multiplexed pin whose function is sel ected by
PORTCCFG.7
PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
Document #: 38-08032 Rev. *V Page 25 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
1048254476BPD2 or
1058355486APD3 or
1219556493BPD4 or
122961503APD5 or
123972513CPD6 or
124983522APD7 or
Port E
10886–––PE0 or
10987–––PE1 or
11088–––PE2 or
11189–––PE3 or
56
SSOP
56
QFN56VFBGA
NameTypeDefaultDescription
FD[10]
FD[11]
FD[12]
FD[13]
FD[14]
FD[15]
T0OUT
T1OUT
T2OUT
RXD0OUT
I/O/ZI
(PD2)
I/O/ZI
(PD3)
I/O/ZI
(PD4)
I/O/ZI
(PD5)
I/O/ZI
(PD6)
I/O/ZI
(PD7)
I/O/ZI
(PE0)
I/O/ZI
(PE1)
I/O/ZI
(PE2)
I/O/ZI
(PE3)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
PORTECFG.0 bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051
Timer-counter0. T0OUT outputs a high level for one
CLKOUT clock cycle when Timer0 overflows. If T imer0
is operated in Mode 3 (two separate timer/counters),
T0OUT is active when the low byte timer/counter
overflows.
Multiplexed pin whose function is selected by the
PORTECFG.1 bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active-HIGH signal from 8051
Timer-counter1. T1OUT outputs a high level for one
CLKOUT clock cycle when Timer1 overflows. If T imer1
is operated in Mode 3 (two separate timer/counters),
T1OUT is active when the low byte timer/counter
overflows.
Multiplexed pin whose function is selected by the
PORTECFG.2 bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051
Timer2. T2OUT is active (HIGH) for one clock cycle
when Timer/Counter 2 overflows.
Multiplexed pin whose function is selected by the
PORTECFG.3 bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0.
If RXD0OUT is selected and UART0 is in Mode 0, this
pin provides the output data for UART0 only when it is
in sync mode. Otherwise it is a 1.
Document #: 38-08032 Rev. *V Page 26 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
11290–––PE4 or
11391–––PE5 or
11492–––PE6 or
11593–––PE7 or
56
SSOP
56
QFN56VFBGA
NameTypeDefaultDescription
RXD1OUT
INT6
T2EX
GPIFADR8
I/O/ZI
(PE4)
I/O/ZI
(PE5)
I/O/ZI
(PE6)
I/O/ZI
(PE7)
Multiplexed pin whose function is selected by the
PORTECFG.4 bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1.
When RXD1OUT is selected and UART1 is in Mode 0,
this pin provides the output data for UART1 only when
it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.
Multiplexed pin whose function is selected by the
PORTECFG.5 bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT6 interrupt request input signal. The
INT6 pin is edge-sensitive, active HIGH.
Multiplexed pin whose function is selected by the
PORTECFG.6 bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active-HIGH input signal to the 8051 Timer2.
T2EX reloads timer 2 on its falling edge. T2EX is active
only if the EXEN2 bit is set in T2CON.
Multiplexed pin whose function is selected by the
PORTECFG.7 bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
43811ARDY0 or
SLRD
54921BRDY1 or
SLWR
65–––RDY2InputN/ARDY2 is a GPIF input signal.
76–––RDY3InputN/ARDY3 is a GPIF input signal.
87–––RDY4InputN/ARDY4 is a GPIF input signal.
98–––RDY5InputN/ARDY5 is a GPIF input signal.
695436297HCTL0 or
FLAGA
InputN/AMultiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable
polarity (FIFOPINPOLAR.3) for the slave FIFOs
connected to FD[7..0] or FD[15..0].
InputN/AMultiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable
polarity (FIFOPINPOLAR.2) for the slave FIFOs
connected to FD[7..0] or FD[15..0].
O/ZHMultiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status
flag signal.
Defaults to programmable for the FIFO selected by the
FIFOADR[1:0] pins.
Document #: 38-08032 Rev. *V Page 27 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
705537307GCT L1 or
715638318HCTL2 or
6651–––CTL3O/ZHCTL3 is a GPIF control output.
6752–––CTL4OutputHCTL4 is a GPIF control output.
9876–––CTL5OutputHCTL5 is a GPIF control output.
322620132GIFCLK on
2822–––INT4InputN/AINT4 is the 8051 INT4 interrupt request input signal. The
10684–––INT5#InputN/AINT5# is the 8051 INT5 interrupt request input signal.
3125–––T2InputN/AT2 is the active-HIGH T2 input signal to 8051 Timer2,
3024–––T1InputN/AT1 is the active-HIGH T1 signal for 8051 Timer1, which
2923–––T0InputN/AT0 is the active-HIGH T0 signal for 8051 Timer0, which
5343–––RXD1InputN/ARXD1is an active-HIGH input signal for 8051 UART1,
5242–––TXD1OutputHTXD1is an active-HIGH output pin from 8051 UART1,
5141–––RXD0InputN/ARXD0 is the active-HIGH RXD0 input to 8051 UART0,
56
SSOP
56
QFN56VFBGA
NameTypeDefaultDescription
O/ZHMultiplexed pin whose function is selected by the
FLAGB
FLAGC
CY7C68013A
and
CY7C68014A
-----------------PE0 on
CY7C68015A
and
CY7C68016A
O/ZHMultiplexed pin whose function is selected by the
I/O/Z
----------I/O/Z
----------
following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status
flag signal.
Defaults to FULL for the FIFO selected by the
FIFOADR[1:0] pins.
following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status
flag signal.
Defaults to EMPTY for the FIFO selected by the
FIFOADR[1:0] pins.
Z
Interface Clock, used for synchronously clocking data
into or out of the slave FIFOs. IFCLK also serves as a
timing reference for all slave FIFO control signals and
GPIF . When internal c locking is used (IFCONFIG.7 = 1)
the IFCLK pin can be configured to output 30/48 MHz
by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be
inverted, whether internally or externally sourced, by
setting the bit IFCONFIG.4 =1.
----------------------------------------------------------------------PE0 is a bidirectional I/O port pin.
I
INT4 pin is edge-sensitive, active HIGH.
The INT5 pin is edge-sensitive, active LOW.
which provides the input to Timer2 when C/T2 = 1.
When C/T2 = 0, Timer2 does not use this pin.
provides the input to Timer1 when C/T1 is 1. When C/T1
is 0, Timer1 does not use this bit.
provides the input to Timer0 when C/T0 is 1. When C/T0
is 0, Timer0 does not use this bit.
which provides data to the UART in all modes.
which provides the output clock in sync mode, and the
output data in async mode.
which provides data to the UART in all modes.
Document #: 38-08032 Rev. *V Page 28 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
5040–––TXD0OutputHTXD0 is the active-HIGH TXD0 output from 8051
42–––CS#OutputHCS# is the active-LOW chip select for external memory.
4132–––WR#OutputHWR# is the active-LOW write strobe output for external
4031–––RD#OutputHRD# is the active-LOW read strobe output for external
38–––OE#OutputHOE# is the active-LOW output enable for external
332721142HReservedInputN/AReserved. Connect to ground.
1017951447BWAKEUPInputN/AUSB Wakeup. If the 8051 is in suspend, asserting this
362922153FSCLODZClock for the I
373023163GSDAODZData for I
56
SSOP
56
QFN56VFBGA
NameTypeDefaultDescription
UART0, which provides the output clock in sync mode,
and the output data in async mode.
memory.
memory.
memory.
pin starts up the oscillator and interrupts the 8051 to
enable it to exit the suspend mode. Holding WAKEUP
asserted inhibits the EZ-USB
This pin has programmable polarity (WAKEUP.4).
2
C interface. Connect to VCC with a 2.2K
resistor , even if no I
2
C compatible interface. Connect to VCC with a 2.2K resistor, even if no I
peripheral is attached.
2
C peripheral is attached.
chip from suspending.
2
C compatible
216555AVCCPowerN/AVCC. Connect to 3.3 V power source.
262018111GVCCPowerN/AVCC. Connect to 3.3 V power source.
433324177EVCCPowerN/AVCC. Connect to 3.3 V power source.
4838–––VCCPowerN/AVCC. Connect to 3.3 V power source.
644934278EVCCPowerN/AVCC. Connect to 3.3 V power source.
6853–––VCCPowerN/AVCC. Connect to 3.3 V power source.
816639325CVCCPowerN/AVCC. Connect to 3.3 V power source.
1007850435BVCCPowerN/AVCC. Connect to 3.3 V power source.
10785–––VCCPowerN/AVCC. Connect to 3.3 V power source.
1413–––NCN/AN/ANo Connect. This pin must be left open.
1514–––NCN/AN/ANo Connect. This pin must be left open.
1615–––NCN/AN/ANo Connect. This pin must be left open.
Document #: 38-08032 Rev. *V Page 29 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
4. Register Summary
FX2LP register bit definitions are described in the FX2LP TRM in greater detail.
E640 1EP2ISOINPKTSEP2 (if ISO) IN Packets per
E641 1EP4ISOINPKTSEP4 (if ISO) IN Packets per
E642 1EP6ISOINPKTSEP6 (if ISO) IN Packets per
E643 1EP8ISOINPKTSEP8 (if ISO) IN Packets per
E644 4reserved
E670 1PORTACFGI/O PORTA Alternate
E671 1PORTCCFGI/O PORTC Alternate
E672 1PORTECFGI/O PORTE Alternate
E673 4reserved
E677 1reserved
E678 1I2CSI²C Bus
E679 1I2DATI²C Bus
E67A 1I2CTLI²C Bus
E67B 1XAUTODAT1Autoptr1 MOVX access,
E67C 1XAUTODAT2Autoptr2 MOVX access,
E67D 1UDMACRCH
E67E 1UDMACRCL
E67F 1UDMACRC-
E680 1USBCSUSB Control & StatusHSM000DISCONNOSYNSOF RENUMSIGRSUME x0000000 rrrrbbbb
E681 1SUSPENDPut chip into suspendxxxxxxxxxxxxxxxx W
E682 1WAKEUPCSWakeup Control & Status WU2WUWU2POLWUPOL0DPENWU2ENWUENxx000101 bbbbrbbb
E683 1TOGCTLToggle ControlQSRI/OEP3EP2EP1EP0x0000000 rrrbbbbb
E684 1USBFRAMEHUSB Frame count H00000FC10FC9FC800000xxx R
E685 1USBFRAMELUSB Frame count LFC7FC6FC5FC4FC3FC2FC1FC0xxxxxxxx R
E686 1MICROFRAMEMicroframe count, 0-700000MF2MF1MF000000xxx R
E687 1FNADDRUSB Function address0FA6FA5FA4FA3FA2FA1FA00xxxxxxx R
E688 2reserved
tus
and Status
Status
tus
tus
tus
tus
Flags
Flags
Flags
Flags
total byte count H
total byte count L
total byte count H
total byte count L
total byte count H
total byte count L
total byte count H
total byte count L
address byte
dress byte
Mode
HSNAK00000BUSYSTALL10000000 bbbbbbrb
000000BUSYSTALL00000000 bbbbbbrb
000000BUSYSTALL00000000 bbbbbbrb
0NPAK2NPAK1NPAK0FULLEMPTY0STALL00101000 rrrrrrrb
00NPAK1NPAK0FULLEMPTY0STALL00101000 rrrrrrrb
0NPAK2NPAK1NPAK0FULLEMPTY0STALL00000100 rrrrrrrb
00NPAK1NPAK0FULLEMPTY0STALL00000100 rrrrrrrb
00000PFEFFF00000010 R
00000PFEFFF00000010 R
00000PFEFFF00000110 R
00000PFEFFF00000110 R
000BC12BC11BC10BC9BC800000000 R
BC7BC6BC5BC4BC3BC2BC1BC000000000 R
00000BC10BC9BC800000000 R
BC7BC6BC5BC4BC3BC2BC1BC000000000 R
0000BC11BC10BC9BC800000000 R
BC7BC6BC5BC4BC3BC2BC1BC000000000 R
00000BC10BC9BC800000000 R
BC7BC6BC5BC4BC3BC2BC1BC000000000 R
A15A14A13A12A11A10A9A8xxxxxxxx RW
A7A6A5A4A3A2A10xxxxxxx0 bbbbbbbr
0000000SDPAUTO 00000001 RW
E6F0 1XGPIFSGLDATHGPIF Data H
E6F1 1XGPIFSGLDATLXRead/Write GPIF Data L &
E6F2 1XGPIFSGLDATLNOX Read GPIF Data L, no
E6F3 1GPIFREADYCFGInternal RDY, Sync/Async,
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
[11]
[11]
[11]
GPIF Transaction Count
Byte 2
GPIF Transaction Count
Byte 1
GPIF Transaction Count
Byte 0
[11]
Endpoint 2 GPIF Flag
select
transaction on prog. flag
[11]
Endpoint 2 GPIF Trigger xxxxxxxxxxxxxxxx W
[11]
Endpoint 4 GPIF Flag
select
transaction on GPIF Flag
[11]
Endpoint 4 GPIF Trigger xxxxxxxxxxxxxxxx W
[11]
Endpoint 6 GPIF Flag
select
transaction on prog. flag
[11]
Endpoint 6 GPIF Trigger xxxxxxxxxxxxxxxx W
[11]
Endpoint 8 GPIF Flag
select
transaction on prog. flag
[11]
Endpoint 8 GPIF Trigger xxxxxxxxxxxxxxxx W
(16-bit mode only)
trigger transaction
transaction trigger
RDY pin states
Supply current8051 running, connected to USB HS–5085mA
8051 running, connected to USB FS–3565mA
Reset time after valid powerVCC min = 3.0 V5.0––mS
Pin reset after powered on200––S
A
A
mA
mA
8.1 USB Transceiver
USB 2.0 compliant in full speed and high speed modes.
Document #: 38-08032 Rev. *V Page 38 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9. AC Electrical Characteristics
t
CL
t
DH
t
SOEL
t
SCSL
PSEN#
D[7..0]
OE#
A[15..0]
CS#
t
STBL
data in
t
ACC1
t
AV
t
STBH
t
AV
CLKOUT
[17]
[18]
Notes
17.CLKOUT is shown with positive polarity.
18.t
ACC1
is computed from these parameters as follows:
t
ACC1
(24 MHz) = 3*tCL – tAV – t
DSU
= 106 ns.
t
ACC1
(48 MHz) = 3*tCL – tAV – t
DSU
= 43 ns.
9.1 USB Transceiver
USB 2.0 compliant in full speed and high speed modes.
9.2 Program Memory Read
Figure 9-1. Program Memory Read Timing Diagram
Table 14. Program Memory Read Parameters
ParameterDescriptionMinTypMaxUnitNotes
t
CL
t
AV
t
STBL
t
STBH
t
SOEL
t
SCSL
t
DSU
t
DH
Document #: 38-08032 Rev. *V Page 39 of 66
1/CLKOUT Frequency–20.83–ns48 MHz
Delay from Clock to Valid Address0–10.7ns–
Clock to PSEN Low0–8ns–
Clock to PSEN High0–8ns–
Clock to OE Low––11.1ns–
Clock to CS Low––13ns–
Data Setup to Clock9.6––ns–
Data Hold Time0––ns–
–41.66–ns24 MHz
–83.2–ns12 MHz
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.3 Data Memory Read
data in
t
CL
A[15..0]
t
AV
t
AV
RD#
t
STBL
t
STBH
t
DH
D[7..0]
data in
t
ACC1
[19]
t
DSU
Stretch = 0
Stretch = 1
t
CL
A[15..0]
t
AV
RD#
t
DH
D[7..0]
t
ACC1
t
DSU
CS#
CS#
t
SCSL
OE#
t
SOEL
CLKOUT
[17]
CLKOUT
[17]
[19]
Note
19.t
ACC2
and t
ACC3
are computed from these parameters as follows:
t
ACC2
(24 MHz) = 3*tCL – tAV –t
DSU
= 106 ns.
t
ACC2
(48 MHz) = 3*tCL – tAV – t
DSU
= 43 ns.
t
ACC3
(24 MHz) = 5*tCL – tAV –t
DSU
= 190 ns.
t
ACC3
(48 MHz) = 5*tCL – tAV – t
DSU
= 86 ns.
Figure 9-2. Data Memory Read Timing Diagram
Table 15. Data Memory Read Parameters
ParameterDescriptionMinTypMaxUnitNotes
t
CL
t
AV
t
STBL
t
STBH
t
SCSL
t
SOEL
t
DSU
t
DH
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either
RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which
is based on the stretch value
Document #: 38-08032 Rev. *V Page 40 of 66
1/CLKOUT frequency–20.83–ns48 MHz
Delay from clock to valid address––10.7ns–
Clock to RD LOW––11ns–
Clock to RD HIGH––11ns–
Clock to CS LOW––13ns–
Clock to OE LOW––11.1ns–
Data setup to clock9.6––ns–
Data hold time0––ns–
–41.66–ns24 MHz
–83.2–ns12 MHz
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.4 Data Memory Write
t
OFF1
CLKOUT
A[15..0]
WR#
t
AV
D[7..0]
t
CL
t
STBL
t
STBH
data out
t
OFF1
CLKOUT
A[15..0]
WR#
t
AV
D[7..0]
t
CL
data out
Stretch = 1
t
ON1
t
SCSL
t
AV
CS#
t
ON1
CS#
Figure 9-3. Data Memory Write Timing Diagram
Table 16. Data Memory Write Parameters
t
AV
t
STBL
t
STBH
t
SCSL
t
ON1
t
OFF1
ParameterDescriptionMinMaxUnitNotes
Delay from clock to valid address010.7ns–
Clock to WR pulse LOW011.2ns–
Clock to WR pulse HIGH011.2ns–
Clock to CS pulse LOW–13.0ns–
Clock to data turn-on013.1ns–
Clock to data hold time013.1ns–
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on
the stretch value.
Document #: 38-08032 Rev. *V Page 41 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.5 PORTC Strobe Feature Timings
CLKOUT
WR#
t
CLKOUT
PORTC IS UPDATED
t
STBL
t
STBH
CLKOUT
t
CLKOUT
DATA MUST BE HELD FOR 3 CLK CYLCES
DATA CAN BE UPDATED BY EXTERNAL LOGIC
8051 READS PORTC
RD#
t
STBL
t
STBH
The RD# and WR# are present in the 100-pin version and the
128-pin package. In these 100-pin and 128-pin versions, an
8051 control bit can be set to pulse the RD# and WR# pins when
the 8051 reads from or writes to PORTC. This feature is enabled
by setting PORTCSTB bit in CPUCS register.
The RD# and WR# strobes are asserted for two CLKOUT cycles
when PORTC is accessed.
The WR# strobe is asserted two clock cycles after PORTC is
updated and is active for two clock cycles after that, as shown in
Figure 9-4.
As for read, the value of PORTC three clock cycles before the
assertion of RD# is the value that the 8051 reads in. The RD# is
pulsed for 2 clock cycles after 3 clock cycles from the point when
the 8051 has performed a read function on PORTC.
Figure 9-4. WR# Strobe Function when PORTC is Accessed by 8051
The RD# signal prompts the external logic to prepare the next
data byte. Nothing gets sampled internally on assertion of the
RD# signal itself, it is just a prefetch type signal to get the next
data byte prepared. So, using it with that in mind easily meets the
setup time to the next read.
The purpose of this pulsing of RD# is to allow the external
peripheral to know that the 8051 is done reading PORTC and the
data was latched into PORTC three CLKOUT cycles before
asserting the RD# signal. After the RD# is pulsed, the external
logic can update the data on PORTC.
Following is the timing diagram of the read and write strobing
function on accessing PORTC. Refer to Section 9.3 and Section
9.4 for details on propagation delay of RD# and WR# signals.
Document #: 38-08032 Rev. *V Page 42 of 66
Figure 9-5. RD# Strobe Function when PORTC is Accessed by 8051
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.6 GPIF Synchronous Signals
DATA(output)
t
XGD
IFCLK
RDY
X
DATA(input)
valid
t
SRY
t
RYH
t
IFCLK
t
SGD
CTL
X
t
XCTL
t
DAH
N
N+1
GPIFADR[8:0]
t
SGA
Notes
20.Dashed lines denote signals with programmable polarity.
21.GPIF asynchronous RDY
x
signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK.
Table 17. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
ParameterDescriptionMinMax
t
IFCLK
t
SRY
t
RYH
t
SGD
t
DAH
t
SGA
t
XGD
t
XCTL
t
IFCLKR
t
IFCLKF
t
IFCLKOD
t
IFCLKJ
IFCLK Period20.83–––ns
RDYX to Clock Setup Time8.9–––ns
Clock to RDYX 0 –––ns
GPIF Data to Clock Setup Time9.2–––ns
GPIF Data Hold Time0–––ns
Clock to GPIF Address Propagation Delay–7.5––ns
Clock to GPIF Data Output Propagation Delay–11––ns
Clock to CTLX Output Propagation Delay–6.7––ns
IFCLK rise time–––900p s
IFCLK fall time–––900ps
IFCLK Output duty cycle––4951%
IFCLK jitter peak to peak–––300ps
Table 18. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
ParameterDescriptionMinMaxUnit
t
IFCLK
t
SRY
t
RYH
t
SGD
t
DAH
t
SGA
t
XGD
t
XCTL
Document #: 38-08032 Rev. *V Page 43 of 66
IFCLK Period
RDYX to Clock Setup Time2.9–ns
Clock to RDYX 3.7–ns
GPIF Data to Clock Setup Time3.2–ns
GPIF Data Hold Time4.5–ns
Clock to GPIF Address Propagation Delay–11.5ns
Clock to GPIF Data Output Propagation Delay–15ns
Clock to CTLX Output Propagation Delay–10.7ns
IFCLK period20.83–––ns
SLRD to clock setup time18.7–––ns
Clock to SLRD hold time0–––ns
SLOE turn on to FIFO data valid–10.5––ns
SLOE turn off to FIFO data hold–10.5––ns
Clock to FLAGS output propagation delay–9.5––ns
Clock to FIFO data output propagation delay–11––ns
IFCLK rise time–––900ps
IFCLK fall time–––900ps
IFCLK Output duty cycle––4951%
IFCLK jitter peak to peak–––300ps
23.Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
[21]
ParameterDescriptionMinMaxUnit
t
IFCLK
t
SRD
t
RDH
t
OEon
t
OEoff
t
XFLG
t
XFD
IFCLK period20.83200ns
SLRD to clock setup time12.7–ns
Clock to SLRD hold time3.7–ns
SLOE turn on to FIFO data valid–10.5ns
SLOE turn off to FIFO data hold–10.5ns
Clock to FLAGS output propagation delay–13.5ns
Clock to FIFO data output propagation delay–15ns
SLRD pulse width LOW50–ns
SLRD pulse width HIGH50–ns
SLRD to FLAGS output propagation delay–70ns
SLRD to FIFO data output propagation delay–15ns
SLOE turn-on to FIFO data valid–10.5ns
SLOE turn-off to FIFO data hold–10.5ns
IFCLK period20.83–ns
SLWR to clock setup time10.4–ns
Clock to SLWR hold time0–ns
FIFO data to clock setup time9.2–ns
Clock to FIFO data hold time0–ns
Clock to FLAGS output propagation time–9.5ns
[21]
ParameterDescriptionMinMaxUnit
t
IFCLK
t
SWR
t
WRH
t
SFD
t
FDH
t
XFLG
IFCLK Period20.83200ns
SLWR to clock setup time12.1–ns
Clock to SLWR hold time3.6–ns
FIFO data to clock setup time3.2–ns
Clock to FIFO data hold time4.5–ns
Clock to FLAGS output propagation time–13.5ns
SLWR pulse LOW50–ns
SLWR pulse HIGH70–ns
SL W R to FIFO DATA setup time10–ns
FIFO DATA to SLWR hold time10–ns
SLWR to FLAGS output propagation delay–70ns
9.11 Slave FIFO Synchronous Packet End Strobe
Figure 9-11. Slave FIFO Synchronous Packet End Strobe Timing Diagram
Table 25. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
ParameterDescriptionMinMaxUnit
t
IFCLK
t
SPE
t
PEH
t
XFLG
IFCLK period20.83–ns
PKTEND to clock setup time14.6–ns
Clock to PKTEND hold time0–ns
Clock to FLAGS output propagation delay–9.5ns
[20]
[21]
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
[21]
ParameterDescriptionMinMaxUnit
t
IFCLK
t
SPE
t
PEH
t
XFLG
Document #: 38-08032 Rev. *V Page 47 of 66
IFCLK period20.83200ns
PKTEND to clock setup time8.6–ns
Clock to PKTEND hold time2.5–ns
Clock to FLAGS output propagation delay–13.5ns
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
There is no specific timing requirement that should be met for
IFCLK
SLWR
DATA
t
IFCLK
>= t
SWR
>= t
WRH
X-2
PKTEND
X-3
t
FAH
t
SPE
t
PEH
FIFOADR
t
SFD
t
SFD
t
SFD
X-4
t
FDH
t
FDH
t
FDH
t
SFA
1
X
t
SFD
t
SFD
t
SFD
X-1
t
FDH
t
FDH
t
FDH
At least one IFCLK cycle
FLAGS
t
XFLG
PKTEND
t
PEpwl
t
PEpwh
asserting PKTEND pin to asserting SLWR. PKTEND can be
asserted with the last data value clocked into the FIFOs or
thereafter. The setup time t
met.
and the hold time t
SPE
PEH
must be
Although there are no specific timing requirements for the
PKTEND assertion, there is a specific corner case condition that
needs attention while using the PKTEND to commit a one byte
or word packet. There is an additional timing requirement that
needs to be met when the FIFO is configured to operate in auto
mode and it is required to send two packets back to back: a full
packet (full defined as the number of bytes in the FIFO meeting
the level set in AUTOINLEN register) committed automatically
followed by a short one byte or word packet committed manually
using the PKTEND pin. In this scenario, the user must ensure to
assert PKTEND at least one clock cycle after the rising edge that
Figure 9-12. Slave FIFO Synchronous Write Sequence and Timing Diagram
caused the last byte or word to be clocked into the previous auto
committed packet. Figure 9-12 shows this scenario. X is the
value the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Figure 9-12 shows a scenario where two packets are committed.
The first packet gets committed automatically when the number
of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte/word short packet being
committed manually using PKTEND.
Note that there is at least one IFCLK cycle timing between the
assertion of PKTEND and clocking of the last byte of the previous
packet (causing the packet to be committed automatically).
Failing to adhere to this timing results in the FX2 failing to send
the one byte or word short packet.
[20]
9.12 Slave FIFO Asynchronous Packet End Strobe
Figure 9-13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
Table 27. Slave FIFO Asynchronous Packet End Strobe Parameters
FIFOADR[1:0] to SLRD/SLWR /PKTEND setup time10–ns
RD/WR/PKTEND to FIFOADR[1:0] hold time10–ns
[20]
9.17 Sequence Diagram
9.17.1 Single and Burst Synchronous Read Example
Figure 9-18. Slave FIFO Synchronous Read Sequence and Timing Diagram
[20]
Document #: 38-08032 Rev. *V Page 50 of 66
Figure 9-19. Slave FIFO Synchronous Sequence of Events Diagram
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 9-18 on page 50 shows the timing relationship of the
IFCLK
SLWR
FLAGS
DATA
t
SWR
t
WRH
t
SFD
t
XFLG
t
IFCLK
N
>= t
SWR
>= t
WRH
N+3
PKTEND
N+2
t
XFLG
t
SFA
t
FAH
t
SPE
t
PEH
FIFOADR
SLCS
t
SFD
t
SFD
t
SFD
N+1
t
FDH
t
FDH
t
FDH
t
FDH
t=0
t=1
t=2
t=3
t
SFA
t
FAH
T=1
T=0
T=2
T=5
T=3
T=4
SLAVE FIFO signals during a synchronous FIFO read using
IFCLK as the synchronizing clock. The diagram illustrates a
single read followed by a burst read.
■ At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications). Note
that t
running at 48 MHz, the FIFO address setup time is more than
has a minimum of 25 ns. This means when IFCLK is
SFA
one IFCLK cycle.
■ At t = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that is
driven on the bus is the data that the internal FIFO pointer is
currently pointing to. In this example it is the first data value in
the FIFO. Note: the data is pre-fetched and is driven on the bus
when SLOE is asserted.
■ At t = 2, SLRD is asserted. SLRD must meet the setup time of
t
(time from asserting the SLRD signal to the rising edge of
SRD
the IFCLK) and maintain a minimum hold time of t
from the IFCLK edge to the deassertion of the SLRD signal).
RDH
(time
If the SLCS signal is used, it must be asserted before SLRD is
asserted (The SLCS and SLRD signals must both be asserted
to start a valid read condition).
9.17.2 Single and Burst Synchronous Write
Figure 9-20. Slave FIFO Synchronous Write Sequence and Timing Diagram
■ The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of t
IFCLK) the new data value is present. N is the first data value
(measured from the rising edge of
XFD
read from the FIFO. T o have data on the FIFO data bus, SLOE
MUST also be asserted.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
Note For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is on
the data bus. During the first read cycle, on the rising edge of the
clock the FIFO pointer is updated and increments to point to
address N+1. For each subsequent rising edge of IFCLK, while
the SLRD is asserted, the FIFO pointer is incremented and the
next data value is placed on the data bus.
[20]
Document #: 38-08032 Rev. *V Page 51 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 9-20 shows the timing relationship of the SLAVE FIFO
signals during a synchronous write using IFCLK as the
synchronizing clock. The diagram illustrates a single write
followed by burst write of 3 bytes and committing all 4 bytes as
a short packet using the PKTEND pin.
■ At t = 0 the FIFO address is stable and the signal SLCS is
asserted. (SLCS may be tied low in some applications) Note
that t
running at 48 MHz, the FIFO address setup time is more than
has a minimum of 25 ns. This means when IFCLK is
SFA
one IFCLK cycle.
■ At t = 1, the external master/peripheral must outputs the data
value onto the data bus with a mini mu m set up time of t
before the rising edge of IFCLK.
■ At t = 2, SLWR is asserted. The SLWR must meet the setup
time of t
edge of IFCLK) and maintain a minimum hold time of t
(time from asserting the SLWR signal to the rising
SWR
from the IFCLK edge to the deassertion of the SLWR signal).
WRH
SFD
(time
If the SLCS signal is used, it must be asserted with SLWR or
before SL WR is asserted (The SLCS and SLWR signals must
both be asserted to start a valid write condition).
■ While the SLWR is asserted, data is written to the FIFO and on
the rising edge of the IFCLK, the FIFO pointer is incremented.
The FIFO flag is also updated after a delay of t
rising edge of the clock.
XFLG
from the
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5.
Note For the burst mode, SLWR and SLCS are left asserted for
the entire duration of writing all the required data values. In this
burst write mode, after the SLWR is asserted, the data on the
FIFO data bus is written to the FIFO on every rising edge of
IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In Figure 9-20, after the four bytes are written to the
FIFO, SLWR is deasserted. The short 4 byte packet can be
committed to the host by asserting the PKTEND signal.
There is no specific timing requirement that should be met for
asserting PKTEND signal with regards to asserting the SLWR
signal. PKTEND can be asserted with the last data value or
thereafter. The only requirement is that the setup time t
the hold time t
the number of data values committed includes the last value
must be met. In the scenario of Figure 9-20,
PEH
SPE
and
written to the FIFO. In this example, both the data value and the
PKTEND signal are clocked on the same rising edge of IFCLK.
PKTEND can also be asserted in subsequent clock cycles. The
FIFOADDR lines should be held constant during the PKTEND
assertion.
Although there are no specific timing requirement for the
PKTEND assertion, there is a specific corner case condition that
needs attention while using the PKTEND to commit a one
byte/word packet. Additional timing requirements exists when
the FIFO is configured to operate in auto mode and it is desired
to send two packets: a full packet (full defined as the number of
bytes in the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte or word
packet committed manually using the PKTEND pin.
In this case, the external master must ensure to assert the
PKTEND pin at least one clock cycle after the rising edge that
caused the last byte or word that needs to be clocked into the
previous auto committed packet (the packet with the number of
bytes equal to what is set in the AUTOINLEN register). Refer to
Figure 9-12 on page 48 for further details on this timing.
Document #: 38-08032 Rev. *V Page 52 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.17.3 Sequence Diagram of a Single and Burst Asynchronous Read
SLRD
FLAGS
SLOE
DATA
t
RDpwh
t
RDpwl
t
OEon
t
XFD
t
XFLG
N
Data (X)
t
XFD
N+1
t
XFD
t
OEoff
N+3
N+2
t
OEoff
t
XFLG
t
SFA
t
FAH
FIFOADR
SLCS
Driven
t
XFD
t
OEon
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
FAH
t
SFA
N
t=0
T=0
T=1
T=7
T=2
T=3
T=4
T=5
T=6
t=1
t=2
t=3
t=4
NN
SLOESLRD
FIFO POINTER
N+3
FIFO DATA BUS
Not DrivenDriven: XN Not Driven
SLOE
N
N+2
N+3
SLRD
N
N+1
SLRD
N+1
SLRD
N+1
N+2
SLRD
N+2
SLRD
N+2
N+1
SLOE
Not Driven
SLOE
N
N+1
N+1
Figure 9-21. Slave FIFO Asynchronous Read Sequence and Timing Diagram
Figure 9-22. Slave FIFO Asynchronous Read Sequence of Events Diagram
[20]
Figure 9-21 shows the timing relationship of the SLAVE FIFO
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
■ At t = 0 the FIFO address is stable and the SLCS signal is
■ At t = 1, SLOE is asserted. This results in the data bus being
■ At t = 2, SLRD is asserted. The SLRD must meet the minimum
Document #: 38-08032 Rev. *V Page 53 of 66
■ The data that is driven, after asserting SLRD, is the updated
data from the FIFO. This data is valid after a propagation delay
from the activating edge of SLRD. In Figure 9-21, data
of t
XFD
N is the first valid data read from the FIFO. For data to appear
asserted.
on the data bus during the read cycle (SLRD is asserted), SLOE
must be in an asserted state. SLRD and SLOE can also be tied
together.
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
active pulse of t
t
SLRD is asserted (The SLCS and SLRD signals must both be
. If SLCS is used then, SLCS must be asserted before
RDpwh
and minimum de-active pulse width of
RDpwl
asserted to start a valid read condition.)
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After SLRD is
asserted, the data from the FIFO is driven on the data bus (SLOE
must also be asserted) and then the FIFO pointer is
incremented.
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.17.4 Sequence Diagram of a Single and Burst Asynchronous Write
PKTEND
SLWR
FLAGS
DATA
t
WRpwh
t
WRpwl
t
XFLG
N
t
SFD
N+1
t
XFLG
t
SFA
t
FAH
FIFOADR
SLCS
t
WRpwh
t
WRpwl
t
WRpwh
t
WRpwl
t
WRpwh
t
WRpwl
t
FAH
t
SFA
t
FDH
t
SFD
N+2
t
FDH
t
SFD
N+3
t
FDH
t
SFD
t
FDH
t
PEpwh
t
PEpwl
t=0
t=2
t =1
t=3
T=0
T=2
T=1
T=3
T=6
T=9
T=5
T=8
T=4
T=7
Figure 9-23. Slave FIFO Asynchronous Write Sequence and Timing Diagram
[20]
Figure 9-23 shows the timing relationship of the SLAVE FIFO
write in an asynchronous mode. The diag r am shows a single
write followed by a burst write of 3 bytes and committing the 4
byte short packet using PKTEND.
■ At t = 0 the FIFO address is applied, insuring that it meets the
setup time of t
(SLCS may be tied low in some applications).
■ At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t
t
. If the SLCS is used, it must be asserted with SLWR or
WRpwh
before SLWR is asserted.
■ At t = 2, data must be present on the bus t
deasserting edge of SLWR.
■ At t = 3, deasserting SLWR causes the data to be written from
. If SLCS is used, it must also be asserted
SFA
and minimum de-active pulse width of
WRpwl
before the
SFD
the data bus to the FIFO and then increments the FIFO pointer.
The FIFO flag is also updated after t
edge of SLWR.
from the deasserting
XFLG
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, after SL WR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post
incremented.
In Figure 9-23 after the four bytes are written to the FIFO and
SLWR is deasserted, the short 4 byte packet can be committed
to the host using the PKTEND. The external device should be
designed to not assert SLWR and the PKTEND signal at the
same time. It should be designed to assert the PKTEND after
SLWR is deasserted and met the minimum deasserted pulse
width. The FIFOADDR lines have to held constant during the
PKTEND assertion.
Document #: 38-08032 Rev. *V Page 54 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
10. Ordering Information
Note
24.As UART is not available in the 56-pin package of CY7C68013A, serial port debugging using Keil Monitor is not possible.
Follow these recommendations to ensure reliable high
performance operation:
■ Four layer impedance controlled boards are required to
[25]
maintain signal quality.
■ Specify impedance targets (ask your board vendor what they
can achieve).
■ T o control impedance, maintain trace widths and trace spacing.
■ Minimize stubs to minimize reflected signals.
■ Connections between the USB connector shell and signal
ground must be near the USB connector.
■ Bypass and flyback caps on VBus, near connector, are
recommended.
■ DPLUS and DMINUS trace lengths should be kept to within
2 mm of each other in length, with preferred length of 20 to
30 mm.
■ Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to split under these traces.
■ Do not place vias on the DPLUS or DMINUS trace routing.
■ Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
Document #: 38-08032 Rev. *V Page 61 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
13. Quad Flat Package No Leads (QFN) Package Design Notes
0.017” dia
Solder Mask
Cu Fill
Cu Fill
PCB Material
PCB Material
0.013” dia
Via hole for thermally connecting the
QFN to the circuit board ground plane.
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
Figure 13-2. Plot of the Solder Mask (White Area)
Figure 13-3. X-ray Image of the Assembly
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good thermal
bond to the circuit board. Design a Copper (Cu) fill in the PCB as
a thermal pad under the package. Heat is transferred from the
FX2LP through the device’s metal paddle on the bottom side of
the package. Heat from here is conducted to the PCB at the
thermal pad. It is then conducted from the thermal pad to the
PCB inner ground plane by a 5 × 5 array of via. A via is a plated
through hole in the PCB with a finished diameter of 13 mil. The
QFN’s metal die paddle must be soldered to the PCB’s thermal
pad. Solder mask is placed on the board top side over each via
to resist solder flow into the via. The mask on the top side also
minimizes outgassing during the solder reflow process.
Figure 13-1. Cross-section of the Area Underneath the QFN Package
For further information on this package design refer to
Application Notes for Surface Mount Assembly of Amkor's
MicroLeadFrame (MLF) Packages. You can find this on Amkor's
website http://www.amkor.com.
The application note provides detailed information about board
mounting guidelines, soldering flow, rework process, etc.
Figure 13-1 shows a cross-sectional area underneath the
package. The cross section is of only one via. The solder paste
template should be designed to allow at least 50% solder
coverage. The thickness of the solder paste template should be
5 mil. Use the No Clean type 3 solder paste for mounting the part.
Nitrogen purge is recommended during reflow.
Figure 13-2 is a plot of the solder mask pattern and Figure 13-3
displays an X-Ray image of the assembly (darker areas indicate
solder).
Document #: 38-08032 Rev. *V Page 62 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
AcronymsDocument Conventions
Acronyms Used in this Document
AcronymDescription
ASIC application specific integrated circuit
ATA advanced tech no l o gy at tachment
DID device identifier
DSL digital service line
DSP digital signal processor
ECC error correction code
EEPROM electrically erasable programmable read only
memory
EPP enhanced parallel port
FIFO first in first out
GPIF general programmable interface
GPIO general purpose input output
I/O input output
LAN local area network
MPEG moving picture experts group
PCMCIA personal computer memory card international
association
PID product identifier
PLL phase locked loop
QFN quad flat no leads
RAM random access memory
SIE serial interface engine
SOF start of frame
SSOP super small outlin e package
TQFP thin quad flat pack
USARTS universal serial asynchronous receiver/trans-
mitter
USB universal serial bus
UTOPIA universal test and operations physical-layer
interface
VFBGA very fine ball grid array
VID vendor identifier
Units of Measure
SymbolUnit of Measure
KHz kilohertz
mA milliamperes
Mbps megabits per second
MBPs megabytes per second
MHz megahertz
uA microamperes
V volts
Document #: 38-08032 Rev. *V Page 63 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document History Page
Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB® FX2LP™ USB Microcontroller HighSpeed USB Peripheral Controller
Document Number: 38-08032
Rev . ECN No.
**124316VCS03/17/03New datasheet
*A128461VCS09/02/03Added PN CY7C68015A throughout datasheet
*B130335KKV10/09/03Restored PRELIMINARY to header (had been removed in error from rev. *A)
*C131673KKU02/12/04Section 8.1 changed “certified” to “compliant”
*D230713KKUSee ECNChanged Lead free Marketing part numbers in Table32 as per spec change in 28-00054.
*E242398TMDSee ECNMinor Change: datasheet posted to the web,
*F271169MONSee ECNAdded USB-IF Test ID number
*G 316313MONSee ECNRemoved CY7C68013A-56PVXCT part availability
*H 338901MONSee ECNAdded information about the AUTOPTR1/AUTOPTR2 address timing with regards to data
*I 371097MONSee ECNAdded timing for strobing RD#/WR# signals when using PortC strobe feature (Section 9.5)
*J397239MONSee ECNRemoved XTALINSRC register from register summary.
*K420505MONSee ECNRemove SLCS from figure in Section 9.10.
Orig. of
Change
Submission
Date
Description of Change
Modified Figure 2-1 to add ECC block and fix errors
Removed word “compatible” where associated with I
Corrected grammar and formatting in various locations
Updated Sections 3.2.1, 3.9, 3.11, Table 8, Section 5.0
Added Sections 3.15, 3.18.4, 3.20
Modified Figure 2-5 for clarity
Updated Figure 11-2 to match current spec revision
Table 13 added parameter V
Added Sequence diagrams Section 9.16
Updated Ordering information with lead-free parts
Updated Registry Summary
Section 3.12.4:example changed to column 8 from column 9
Updated Figure 9-3 memory write timing Diagram
Updated section 3.9 (reset)
Updated section 3.15 ECC Generation
Added USB 2.0 logo
Added values for Isusp, Icc, Power Dissipation, Vih_x, Vil_x
Changed VCC from +
Changed PKTEND to FLAGS output propagation delay (asynchronous interface) in
Table 27 from a max value of 70 ns to 115 ns
Added parts ideal for battery powered applications: CY7C68014A, CY7C68016A
Provided additional timing restrictions and requirement about the use of PKETEND pin to
commit a short one byte/word packet subsequent to committing a packet automatically
(when in auto mode).
Added Min Vcc Ramp Up time (0 to 3.3v)
memory read/write timing diagram.
Removed TBD for Min value of Clock to FIFO Data Output Propagation Delay (t
Slave FIFO Synchronous Read
Changed Table 32 to include part CY7C68016A-56LFXC in the part listed for battery
powered applications
Added register GPCR2 in register summary
Changed Vcc margins to +
Added 56-pin VFBGA Pin Package Diagram
Added 56-pin VFBGA definition in pin listing
Added RDK part number to the Ordering Information table
Removed indications that SLRD can be asserted simultaneously with SLCS in Section
9.17.2 and Section 9.17.3
Added Absolute Maximum Temperature Rating for industrial packages in Section 5.
Changed number of packages stated in the description in Section 3. to five.
Added Table 12 on Thermal Coefficients for various packages
10% to + 5%
IH_X
10%
and V
IL_X
2
C
) for
XFD
Document #: 38-08032 Rev. *V Page 64 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB® FX2LP™ USB Microcontroller HighSpeed USB Peripheral Controller
Document Number: 38-08032
*N2727334ODC07/01/09Removed sentence on E-Pad size change from *F revision in the Document History Page
*O 2756202ODC08/26/2009 Updated Ordering Information table and added note 24.
*P2785207ODC10/12/2009 Added information on Pb-free parts in the Ordering information table.
*Q281 1890ODC11/20/2009 Updated Program I/Os for the CY7C68016A-56LTXC and CY7C68016A-56LTXCT parts in
*R2896281ODC03/19/10Removed inactive parts from the ordering information table. Updated package
*S3035980ODC09/22/10Updated template.
*T3161410AAE02/03/2011 Replaced 56-Pin QFN 8 × 8 mm Punch Version Package Diagram (Figure 11.2) and 56-Pin
*U3195232ODC03/14/2011 Updated table numbering.
*V3512313 GAYA02/01/2012 Removed obsolete part CY7C68014A-56BAXC
Orig. of
Change
PYRS
Submission
Date
See ECNChanged TID number
Removed T0OUT and T1OUT from CY7C68015A/16A
Updated t
Updated 56-lead QFN package diagram
Updated ordering information for CY7C68013A-56LTXC, CY7C68013A-56LTXI,
CY7C68014A-56LTXC, CY7C68015A-56LTXC, and CY7C68016A-56LTXC parts.
Updated 56-Pin Sawn Package Diagram
“Ordering Information” on page 55.
diagrams.Updated links in Sales, Solutions and Legal Information.
Changed PPM requirement for the external crystal from +/- 10 ppm to +/- 100 ppm under
Electrical specifications.
Added table of contents, ordering code definitions, acronym table, and units of measure.
QFN 8 × 8 mm Sawn Version Package Diagram (Figure 11.3).
Updated Package Diagrams (Figure 11.4, Figure 11.5).
Added typical values to Table 17 on page 43 and Table 19 on page 44 based on data
obtained from SHAK-63 and SHAK 69.
Updated Table 12, “Thermal Characteristics,” on page 37 (CDT 89510)
Updated package diagram 001-03901 to *D.
Removed pruned part CY7C68016A-56LFXC
Added parts CY7C68013A-56BAXCT and CY7C68013A-56PVXCT
Updated Package Diagrams
Min value in Figure 9-9
SWR
Description of Change
Document #: 38-08032 Rev. *V Page 65 of 66
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotivecypress.com/go/automotive
Clocks & Bufferscypress.com/go/clocks
Interfacecypress.com/go/interface
Lighting & Power Controlcypress.com/go/powerpsoc
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cy press
integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Co de except as speci fied above is pro hibited with out
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cyp ress does not
assume any liability arising out of the applic ation or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot author ize its p roducts fo r use as critical compon ents in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-08032 Rev. *V Revised February 7, 2012Page 66 of 66
>
FX2LP is a trademark and EZ-USB is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these component s in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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