Cypress CY7C68013A User Manual
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
EZ-USB FX2LP™ USB Microcontroller
High-Speed USB Peripheral Controller
1. Features (CY7C68013A/14A/15A/16A)
■ USB 2.0 USB IF high-speed certified (TID # 40460272)
■ Single chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
■ Fit, form and function compatible with the FX2
❐ Pin compatible
❐ Object-code-compatible
❐ Functionally compatible (FX2LP is a superset)
■ Ultra Low power: I
❐ Ideal for bus and battery powered applications
■ Software: 8051 code runs from:
❐ Internal RAM, which is downloaded via USB
❐ Internal RAM, which is loaded from EEPROM
❐ External memory device (128 pin package)
■ 16 KBytes of on-chip Code/Data RAM
■ Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
❐ Buffering options: double, triple, and quad
■ Additional programmable (BULK/INTERRUPT) 64 byte
endpoint
■ 8-bit or 16-bit external data interface
■ Smart Media Standard ECC generation
no more than 85 mA in any mode
CC
■ GPIF (General Programmable Interface)
❐ Enables direct connection to most parallel interfaces
❐ Programmable waveform descriptors and configuration reg-
isters to define waveforms
❐ Supports multiple Ready (RDY) inputs and Control (CTL) out-
puts
■ Integrated, industry standard enhanced 8051
❐ 48 MHz, 24 MHz, or 12 MHz CPU operation
❐ Four clocks per instruction cycle
❐ Two USARTS
❐ Three counter/timers
❐ Expanded interrupt system
❐ Two data poi nters
■ 3.3V operation with 5V tolerant inputs
■ Vectored USB interrupts and GPIF/FIFO interrupts
■ Separate data buffers for the Setup and Data portions of a
CONTROL transfer
■ Integrated I
■ Four integrated FIFOs
❐ Integrated glue logic and FIFOs lower system cost
❐ Automatic conversion to and from 16-bit buses
❐ Master or slave operation
❐ Uses external clock or asynchronous strobes
❐ Easy interface to ASIC and DSP ICs
■ Available in Commercial and Industrial temperature grade (all
2
C controller, runs at 100 or 400 kHz
packages except VFBGA)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 •408-943-2600
Document #: 38-08032 Rev. *L Revised February 8, 2008
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Address (16)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
VCC
1.5k
D+
D–
Address (16) / Data Bus (8)
FX2LP
GPIF
CY
Smart
USB
1.1/2.0
Engine
USB
2.0
XCVR
16 KB
RAM
4 kB
FIFO
Integrated
full-speed and
Additional IOs (24)
ADDR (9)
CTL (6)
RDY (6)
8/16
Data (8)
24 MHz
Ext. XTAL
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Up to 96 MBytes/s
burst rate
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
Abundant IO
including two USART S
High performance micro
using standard tools
with lower-power options
Master
connected for
full-speed
ECC
XCVR
high-speed
Logic Block DiagramLogic Block Diagram
1.1 Features (CY7C68013A/14A only)
■ CY7C68014A: Ideal for battery powered applications
❐ Suspend current: 100 μA (typ)
■ CY7C68013A: Ideal for non-battery powered applicati ons
❐ Suspend current: 300 μA (typ)
■ Available in five lead-free packages with up to 40 GPIOs
❐ 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin
QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VFBGA (24 GPIOs)
1.2 Features (CY7C68015A/16A only)
■ CY7C68016A: Ideal for battery powered applications
❐ Suspend current: 100 μA (typ)
■ CY7C68015A: Ideal for non-battery powered applicati ons
❐ Suspend current: 300 μA (typ)
■ Available in lead-free 56-pin QFN package (26 GPIOs)
❐ 2 more GPIOs than CY7C68013A/14A enabling additional
features in same footprint
Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB
FX2LP™ (CY7C68013A/14A) is a low power version of the
EZ-USB FX2™ (CY7C68013), which is a highly integrated, low
power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip,
Cypress has created a cost effective solution that provides
superior time-to-market advantages with low power to enable
bus powered applications.
The ingenious architecture of FX2LP results in data transfer
rates of over 53 Mbytes per second, the maximum allowable
USB 2.0 bandwidth, while still using a low cost 8051 microcontroller in a package as small as a 56 VFBGA (5mm x 5mm).
Because it incorporates the USB 2.0 transceiver, the FX2LP is
more economical, providing a smaller footprint solution than
USB 2.0 SIE or external transceiver implementations. With
EZ-USB FX2LP, the Cypress Smart SIE handles most of the
USB 1.1 and 2.0 protocol in hardware, freeing the embedded
microcontroller for application specific functions and decreasing
development time to ensure USB compatibility.
The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and
glueless interface to popular interfaces such as
EPP, PCMCIA, and most DSP/processors.
ATA, UTOPIA,
The FX2LP draws less current than the FX2 (CY7C68013), has
double the on-chip code/data RAM, and is fit, form and function
compatible with the 56, 100, and 128 pin FX2.
Five packages are defined for the family: 56VFBGA, 56 SSOP,
56 QFN, 100 TQFP, and 128 TQFP.
Document #: 38-08032 Rev. *L Page 2 of 62
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2. Applications
12 pf
12 pf
24 MHz
20 × PLL
C1
C2
12-pF capacitor values assumes a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
Note
1. 115 KBaud operation is also possible by progr amming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.
■ Portable video recorder
■ MPEG/TV conversion
■ DSL modems
■ ATA interface
■ Memory card readers
■ Legacy conversion devices
■ Cameras
■ Scanners
■ Home PNA
■ Wireless LAN
■ MP3 players
■ Networking
The “Reference Designs” section of the Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Visit the Cypress
web site for more information.
3. Functional Overview
3.1 USB Signaling Speed
FX2LP operates at two of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
■ Full-speed, with a signaling bit rate of 12 Mbps
■ High-speed, with a signaling bit rate of 480 Mbps.
FX2LP does not support the low speed signaling mode of
1.5 Mbps.
3.2 8051 Microprocessor
The 8051 microprocessor embedded in the FX2LP family has
256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
3.2.1 8051 Clock Frequency
FX2LP has an on-chip oscillator circuit that uses an external 24
MHz (±100 ppm) crystal with the following characteristics:
■ Parallel resonant
■ Fundamental mode
■ 500-μW drive level
■ 12-pF (5% tolerance) load capacitors
An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
as required by the transceiver/PHY and internal counters divide
it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically.
Figure 1. Crystal Configuration
The CLKOUT pin, which can be three-stated and inverted using
internal control bits, outputs the 50% duty cycle 8051 clock, at
the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.
3.2.2 USARTS
FX2LP contains two standard 8051 USARTs, addressed via
Special Function Register (SFR) bits. The USART interface pins
are available on separate IO pins, and are not multiplexe d with
port pins.
UART0 and UART1 can operate using an internal clock at
230 KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and 12
MHz) such that it always presents the correct frequency for 230
KBaud operation.
[1]
3.2.3 Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX2LP functions. These SFR additions are
shown in Ta bl e 1 on page 4. Bold type indicates non standard,
enhanced 8051 registers. The two SFR rows that end with “0”
and “8” contain bit addressable registers. The four IO ports A to
D use the SFR addresses used in the standard 8051 for ports 0
to 3, which are not implemented in FX2LP . Because of the faster
and more efficient SFR addressing, the FX2LP IO ports are not
addressable in external RAM space (using the MOVX
instruction).
3.3 I2C Bus
FX2LP supports the I2C bus as a master only at 100-/400- KHz.
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3V, even if no I
2
device is connected.
3.4 Buses
All packages, 8-bit or 16-bit “FIFO” bidirectional data bus, multiplexed on IO ports B and D. 128-pin package: adds 16-bit
output-only 8051 address bus, 8-bit bidirectional data bus.
C
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Table 1. Special Function Registers
Note
2. The I
2
C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
x 8x 9x Ax Bx Cx Dx Ex Fx
0 IOA IOB IOC IOD SCON1 PSW ACC B
1SP EXIF INT2CLR IOE SBUF1
2DPL0 MPAGE
3DPH0 OEB
4 DPL1 OEC
5 DPH1 OED
6 DPS OEE
7PCON
8 TCON SCON0 IE IP T2CON EICON EIE EIP
9 TMOD SBUF0
ATL0AUTOPTRH1 EP2468STAT EP01STAT RCAP2L
BTL1AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H
CTH0reserved EP68FIFOFLGS TL2
DTH1AUTOPTRH2 GPIFSGLDATH TH2
E CKCON AUTOPTRL2 GPIFSGLDA TLX
F reserved AUTOPTRSET-UP GPIFSGLDATLNOX
INT4CLR OEA
3.5 USB Boot Methods
During the power up sequence, internal logic checks the I2C port
for the connection of an EEPROM whose first byte is either 0xC0
or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
in place of the internally stored values (0xC0), or it boot-loads the
EEPROM contents into internal RAM (0xC2). If no EEPROM is
detected, FX2LP enumerates using internally stored descriptors.
The default ID values for FX2LP are VID/PID/DID (0x04B4,
0x8613, 0xAxxx where xxx = Chip revision).
Table 2. Default ID Values for FX2LP
Default VID/PID/DID
Vendor ID 0x04B4 Cypress Semiconductor
Product ID 0x8613 EZ-USB FX2LP
Device release 0xAnnn Depends on chip revision
(nnn = chip revision where first
silicon = 001)
[2]
3.6 ReNumeration™
Because the FX2LP’s configuration is soft, one chip can take on
the identities of multiple distinct USB devices.
When first plugged into USB, the FX2LP enumerates automati cally and downloads firmware and USB descriptor tables over
the USB cable. Next, the FX2LP enumerates again, this time as
a device defined by the downloaded information. This patented
two step process called ReNumeration™ happens instantly when
the device is plugged in, without a hint that the initial download
step has occurred.
Two control bits in the USBCS (USB Control and S tatus) register ,
control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To
reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit
to indicate whether the firmware or the Default USB Device
handles device requests over endpoint zero: if RENUM = 0, the
Default USB Device handles device requests; if RENUM = 1, the
firmware services the requests.
3.7 Bus-powered Applications
The FX2LP fully supports bus powered designs by enumerating
with less than 100 mA as required by the USB 2.0 specification.
3.8 Interrupt System
3.8.1 INT2 Interrupt Request and Enable Registers
FX2LP implements an autovector feature for INT2 and INT4.
There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)
vectors. See EZ-USB Technical Reference Manual (TRM) for
more details.
3.8.2 USB Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that is required to identify the
individual USB interrupt source, the FX2LP provides a second
level of interrupt vectoring, called Autovectoring. When a USB
interrupt is asserted, the FX2LP pushes the program counter
onto its stack then jumps to the address 0x0043 where it expects
to find a “jump” instruction to the USB Interrupt service routine.
Document #: 38-08032 Rev. *L Page 4 of 62
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The FX2LP jump instruction is encoded as follows:
Table 3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority INT2VEC Value Source Notes
1 00 SUDAV Setup Data Available
2 04 SOF Start of Frame (or microframe)
3 08 SUTOK Setup Token Received
4 0C SUSPEND USB Suspend request
5 10 USB RESET Bus reset
6 14 HISPEED Entered high-speed operation
7 18 EP0ACK FX2LP ACK’d the CONTROL Handshake
8 1C reserved
9 20 EP0-IN EP0-IN ready to be loaded with data
10 24 EP0-OUT EP0-OUT has USB data
11 28 EP1-IN EP1-IN ready to be loaded with data
12 2C EP1-OUT EP1-OUT has USB data
13 30 EP2 IN: buffer available. OUT: buffer has data
14 34 EP4 IN: buffer available. OUT: buffer has data
15 38 EP6 IN: buffer available. OUT: buffer has data
16 3C EP8 IN: buffer available. OUT: buffer has data
17 40 IBN IN-Bulk-NAK (any IN endpoint)
18 44 reserved
19 48 EP0PING EP0 OUT was Pinged and it NAK’d
20 4C EP1PING EP1 OUT was Pinged and it NAK’d
21 50 EP2PING EP2 OUT was Pinged and it NAK’d
22 54 EP4PING EP4 OUT was Pinged and it NAK’d
23 58 EP6PING EP6 OUT was Pinged and it NAK’d
24 5C EP8PING EP8 OUT was Pinged and it NAK’d
25 60 ERRLIMIT Bus errors exceeded the programmed limit
26 64
27 68 reserved
28 6C reserved
29 70 EP2ISOERR ISO EP2 OUT PID sequence error
30 74 EP4ISOERR ISO EP4 OUT PID sequence error
31 78 EP6ISOERR ISO EP6 OUT PID sequence error
32 7C EP8ISOERR ISO EP8 OUT PID sequence error
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP
register), the FX2LP substitutes its INT2VEC byte. Therefore, if
the high byte (“page”) of a jump-table address is preloaded at the
location 0x0044, the automatically inserted INT2VEC byte at
0x0045 directs the jump to the correct address out of the 27
addresses within the page.
Document #: 38-08032 Rev. *L Page 5 of 62
3.8.3 FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual USB
interrupt sources, the FIFO/GPIF interrupt is shared among 14
individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the
USB Interrupt, can employ autovectoring. Table4 shows the
priority and INT4VEC values for the 14 FIFO/GPIF interrupt
sources.
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Ta bl e 4. Individ ua l FI FO /GPIF Interrupt Sources
Note
3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 μs.
Priority INT4VEC Value Source Notes
1 80 EP2PF Endpoint 2 Programmable Flag
2 84 EP4PF Endpoint 4 Programmable Flag
3 88 EP6PF Endpoint 6 Programmable Flag
4 8C EP8PF Endpoint 8 Programmable Flag
5 90 EP2EF Endpoint 2 Empty Flag
6 94 EP4EF Endpoint 4 Empty Flag
7 98 EP6EF Endpoint 6 Empty Flag
8 9C EP8EF Endpoint 8 Empty Flag
9 A0 EP2FF Endpoint 2 Full Flag
10 A4 EP4FF Endpoint 4 Full Flag
1 1 A8 EP6FF Endpoint 6 Full Flag
12 AC EP8FF Endpoint 8 Full Flag
13 B0 GPIFDONE GPIF Operation Complete
14 B4 GPIFWF GPIF Waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the FX 2LP substitutes its INT4VEC byte. Therefore, if
the high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically inserted INT4VEC byte at
0x0055 directs the jump to the correct address out of the 14
addresses within the page. When the ISR occurs, the FX2LP
pushes the program counter onto its stack then jumps to address
0x0053, where it expects to find a “jump” instruction to the ISR
Interrupt service routine.
3.9 Reset and Wakeup
3.9.1 Reset Pin
The input pin, RESET#, resets the FX2LP when asserted. This
pin has hysteresis and is active LOW. When a crystal is used with
the CY7C680xxA the reset period must allow for the stabilization
of the crystal and the PLL. This reset period must be approximately 5 ms after VCC reaches 3.0V. If the crystal input pin is
driven by a clock signal the internal PLL stabilizes in 200 μs after
VCC has reached 3.0V.
Figure 2 on page 7 shows a power on reset condition and a reset
applied during operation. A power on reset is defined as the time
reset that is asserted while power is being applied to the circuit.
A powered reset is when the FX2LP powered on and operating
and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation. For more information about reset implementation for the FX2 family of products
visit http://www.cypress.com.
[3]
Document #: 38-08032 Rev. *L Page 6 of 62
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V
IL
0V
3.3V
3.0V
T
RESET
VCC
RESET#
Power on Reset
T
RESET
VCC
RESET#
V
IL
Powered Reset
3.3V
0V
Figure 2. Reset Timing Plots
Table 5. Reset Timing Values
Condition T
RESET
Power on Reset with Crystal 5 ms
Power on Reset with External
200 μs + Clock stability time
Clock
Powered Reset 200 μs
3.9.2 Wakeup Pins
The 8051 puts itself and the rest of the chip into a power down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic the oscillator
restarts after the PLL stabilizes, and the 8051 receives a wakeup
interrupt. This applies whether or not FX2LP is connected to the
USB.
The FX2LP exits the power down (USB suspend) state using one
of the following methods:
■ USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX2LP and initiate a wakeup)
■ External logic asserts the WAKEUP pin
■ External logic asserts the PA3/WU2 pin
The second wakeup pin, WU2, can also be configured as a
general purpose IO pin. This enables a simple external R-C
network to be used as a periodic wakeup source. WAKEUP is by
default active LOW.
3.10 Program/Data RAM
3.10.1 Size
The FX2LP has 16 KBytes of internal program/data RAM, where
PSEN#/RD# signals are internally ORed to enable the 8051 to
access it as both program and data memory. No USB control
registers appear in this space.
Two memory maps are shown in the following diagrams:
Figure 3 on page 8 shows the Internal Code Memory, EA = 0
Figure 4 on page 9 shows the External Code Memory, EA = 1.
3.10.2 Internal Code Memory, EA = 0
This mode implements the internal 16 KByte block of RAM
(starting at 0) as combined code and data memory. When
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside the
chip. This enables the user to connect a 64 KByte memory
without requiring address decodes to keep clear of internal
memory spaces.
Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM
spaces have the following access:
■ USB download
■ USB upload
■ Setup data pointer
2
■ I
C interface boot load.
3.10.3 External Code Memory, EA = 1
The bottom 16 KBytes of program memory is external and
therefore the bottom 16 KBytes of internal RAM is accessible
only as a data memory.
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Figure 3. Internal Code Memory, EA = 0
Inside FX2LP Outside FX2LP
7.5 KBytes
USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KBytes RAM
Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KBytes
External
Data
Memory
(RD#,WR#)
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KBytes RAM
Code and Data
(PSEN#,RD#,WR#)*
48 KBytes
External
Code
Memory
(PSEN#)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
*SUDPTR, USB upload/download, I2C interface boot access
FFFF
E200
E1FF
E000
3FFF
0000
Data Code
Document #: 38-08032 Rev. *L Page 8 of 62
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Figure 4. External Code Memory, EA = 1
Inside FX2LP Outside FX2LP
7.5 KBytes
USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KBytes RAM
Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KBytes
External
Data
Memory
(RD#,WR#)
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KBytes
RAM
Data
(RD#,WR#)*
64 KBytes
External
Code
Memory
(PSEN#)
*SUDPTR, USB upload/download, I2C interface boot access
FFFF
E200
E1FF
E000
3FFF
0000
Data Code
FFFF
E800
E7BF
E740
E73F
E700
E6FF
E500
E4FF
E480
E47F
E400
E200
E1FF
E000
E3FF
EFFF
2 KBytes RESERVED
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addressable Registers
Reserved (128)
128 bytes GPIF Waveforms
512 bytes
8051 xdata RAM
F000
(512)
Reserved (512)
E780
64 Bytes EP1OUT
E77F
64 Bytes EP1IN
E7FF
E7C0
4 KBytes EP2-EP8
buffers
(8 x 512)
3.11 Register Addresses
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3.12 Endpoint RAM
64
64
64
512
512
1024
1024
1024
1024
1024
1024
1024
512
512
512
512
512
512
512
512
512
512
EP2
EP2
EP2
EP6
EP6
EP8
EP8
EP0 IN&OUT
EP1 IN
EP1 OUT
1024
1024
EP6
1024
512
512
EP8
512
512
EP6
512
512
512
512
EP2
512
512
EP4
512
512
EP2
512
512
EP4
512
512
EP2
512
512
EP4
512
512
EP2
512
512
512
512
EP2
512
512
512
512
EP2
512
512
1024
EP2
1024
1024
EP2
1024
1024
EP2
1024
512
512
EP6
1024
1024
EP6
512
512
EP8
512
512
EP6
512
512
512
512
EP6
1024
1024
EP6
512
512
EP8
512
512
EP6
512
512
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
1
2
3
4
5
6
7
8
9
10
11
12
3.12.1 Size
■ 3× 64 bytes (Endpoints 0 and 1)
■ 8 × 512 bytes (Endpoints 2, 4, 6, 8)
3.12.2 Organization
■ EP0
■ Bidirectional endpoint zero, 64 byte buffer
■ EP1IN, EP1OUT
■ 64 byte buffers, bulk or interrupt
■ EP2, 4, 6, 8
■ Eight 512 byte buffers, bulk, interrupt, or isochronous. EP4 and
EP8 can be double buffered; EP2 and 6 can be either double,
triple, or quad buffered. For high-speed endpoint configuration
options, see Figure 5.
Figure 5. Endpoint Configuration
3.12.3 Setup Data Buffer
A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data
from a CONTROL transfer.
3.12.4 Endpoint Configurations (High -speed Mode)
Endpoints 0 and 1 are the same for every configuration. Endpoint
0 is the only CONTROL endpoint, and endpoint 1 can be either
BULK or INTERRUPT.
The endpoint buffers can be configured in any 1 of the 12 configurations shown in the vertical columns. When operating in the
full-speed BULK mode only the first 64 bytes of each buffer are
used. For example, in high-speed, the max packet size is 512
bytes but in full-speed it is 64 bytes. Even though a buffer is
configured to a 512 byte buffer, in full-speed only the first 64
bytes are used. The unused endpoint buffer space is not
available for other operations. An example endpoint configuration is the EP2–1024 double buffered; EP6–512 quad buffered
(column 8).
Document #: 38-08032 Rev. *L Page 10 of 62
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CY7C68015A, CY7C68016A
3.12.5 Default Full-Speed Alternate Settings
Notes
4. “0” means “not implemented.”
5. “2×” means “double buffered.”
6. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Table 6. Default Full-Speed Alternate Settings
[4, 5]
Alternate Setting 0 1 2 3
ep0 64 64 64 64
ep1out 0 64 bulk 64 int 64 int
ep1in 0 64 bulk 64 int 64 int
ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×)
ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
3.12.6 Default High-Speed Alternate Settings
Table 7. Default High-Speed Alternate Settings
[4, 5]
Alternate Setting 0 1 2 3
ep0 64 64 64 64
ep1out 0 512 bulk
ep1in 0 512 bulk
[6]
[6]
64 int 64 int
64 int 64 int
ep2 0 512 bulk out (2×) 512 int out (2×) 512 iso out (2×)
ep4 0 512 bulk out (2×) 512 bulk out (2×) 512 bulk out (2×)
ep6 0 512 bulk in (2×) 512 int in (2×) 512 iso in (2×)
ep8 0 512 bulk in (2×) 512 bulk in (2×) 512 bulk in (2×)
3.13 External FIFO Interface
3.13.1 Architecture
The FX2LP slave FIFO architecture has eight 512 byte blocks in
the endpoint RAM that directly serve as FIFO memories and are
controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from the
SIE, while the others are connected to the IO transfer logic. The
transfer logic takes two forms, the GPIF for internally generated
control signals and the slave FIFO interface for externally
controlled transfers.
3.13.2 Master/Slave Control Signals
The FX2LP endpoint FIFOS are implemented as eight physically
distinct 256x16 RAM blocks. The 8051/SIE can switch any of the
RAM blocks between two domains, the USB (SIE) domain and
the 8051-IO Unit domain. This switching is done virtually instantaneously, giving essentially zero transfer time between “USB
FIFOS” and “Slave FIFOS.” Because they are physically the
same memory no bytes are actually transferred between buffers.
At any given time, some RAM blocks are filling/emptying with
USB data under SIE control, while other RAM blocks are
available to the 8051, the IO control unit or both. The RAM blocks
operate as single port in the USB domain, and dual port i n the
8051-IO domain. The blocks can be configured as single,
double, triple, or quad buffe r ed as previously shown.
The IO control unit implements either an internal master (M for
master) or external master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0]
to select a FIFO. The RDY pins (two in the 56-pin package, six
in the 100-pin and 128-pin packages) can be used as flag inputs
from an external FIFO or other logic if desired. The GPIF can be
run from either an internally derived clock or externally supplied
clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s
(48-MHz IFCLK with 16-bit interface).
In Slave (S) mode, the FX2LP accepts either an internally
derived clock or externally supplied clock (IFCLK, max frequency
48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals
from external logic. When using an external IFCLK, the external
clock must be present before switching to the external clock with
the IFCLKSRC bit. Each endpoint can individually be selected
for byte or word operation by an internal configuration bit and a
Slave FIFO Output Enable signal SLOE enables data of the
selected width. External logic must ensure that the output enable
signal is inactive when writing data to a slave FIFO. The slave
interface can also operate asynchronously, where the SLRD and
SLWR signals act directly as strobes, rather than a clock qualifier
as in synchronous mode. The signals SLRD, SLWR, SLOE and
PKTEND are gated by the signal SLCS#.
Document #: 38-08032 Rev. *L Page 11 of 62
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CY7C68015A, CY7C68016A
3.13.3 GPIF and FIFO Clock Rates
Notes
7. T o use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
8. After the data has been downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory.
An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively,
an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK
pin can be used as the interface clock. IFCLK can be configured
to function as an output clock when the GPIF and FIFOs are
internally clocked. An output enable bit in the IFCONFIG register
turns this clock output off, if desired. Another bit within the
IFCONFIG register inverts the IFCLK signal whether internally or
externally sourced.
3.14 GPIF
The GPIF is a flexible 8-bit or 16-bit parallel interface driven by
a user programmable finite state machine. It enables the
CY7C68013A/15A to perform local bus mastering and can
implement a wide variety of protocols such as ATA interface,
printer parallel port, and Utopia.
The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general-purpose ready
inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF
vector defines the state of the control outputs, and determines
what state a ready input (or multiple inputs) must be before
proceeding. The GPIF vector can be programmed to advance a
FIFO to the next data value, advance an address, etc. A
sequence of the GPIF vectors make up a single waveform that
is executed to perform the desired data move between the
FX2LP and the external device.
3.14.1 Six Control OUT Signals
The 100-pin and 128-pin packages bring out all six Control
Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to
define the CTL waveforms. The 56-pin package brings out three
of these signals, CTL0–CTL2. CTLx waveform edges can be
programmed to make transitions as fast as once per cl ock (20.8
ns using a 48-MHz clock).
3.14.2 Six Ready IN Signals
The 100-pin and 128-pin packages bring out all six Ready inputs
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56-pin package brings out two
of these signals, RDY0–1.
3.14.3 Nine GPIF Address OUT Signals
Nine GPIF address lines are available in the 100-pin and 128-pin
packages, GPIFADR[8..0]. The GPIF address lines enable
indexing through up to a 512 byte block of RAM. If more address
lines are needed IO port pins are used.
3.14.4 Long Transfer Mode
In the master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 2
The GPIF automatically throttles data flow to prevent under or
overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
32
transactions.
3.15 ECC Generation
The EZ-USB can calculate ECCs (Error Correcting Codes) on
data that passes across its GPIF or Slave FIFO interfaces. There
are two ECC configurations: Two ECCs, each calculated over
256 bytes (SmartMedia Standard); and one ECC calculated over
512 bytes.
The ECC can correct any one-bit error or detect any two-bit error.
3.15.1 ECC Implementation
The two ECC configurations are selected by the ECCM bit:
ECCM = 0
Two 3 byte ECCs, each calculated over a 256 byte block of data.
This configuration conforms to the SmartMedia Standard.
Write any value to ECCRESET, then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 256 bytes of data
is calculated and stored in ECC1. The ECC for the next 256 bytes
is stored in ECC2. After the second ECC is calculated, the values
in the ECCx registers do not change until ECCRESET is written
again, even if more data is subsequently passed across the
interface.
ECCM = 1
One 3 byte ECC calculated over a 512 byte block of data.
Write any value to ECCRESET then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 512 bytes of data
is calculated and stored in ECC1; ECC2 is unused. After the
ECC is calculated, the values in ECC1 do not change even if
more data is subsequently passed across the interface, till
ECCRESET is written again.
[7]
3.16 USB Uploads and Downloads
The core has the ability to directly edit the data contents of the
internal 16 KByte RAM and of the internal 512 byte scratch pad
RAM via a vendor specific command. This capability is normally
used when soft downloading user code and is available only to
and from internal RAM, only when the 8051 is held in reset. The
available RAM spaces are 16 KBytes from 0x0000–0x3FFF
(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad
data RAM).
[8]
3.17 Autopointer Access
FX2LP provides two identical autopointers. They are similar to
the internal 8051 data pointers but with an additional feature:
they can optionally increment after every memory access. This
capability is available to and from both internal and external
RAM. The autopointers are available in external FX2LP registers
under control of a mode bit (AUTOPTRSET-UP.0). Using the
external FX2LP autopointer access (at 0xE67B – 0xE67C)
enables the autopointer to access all internal and external RAM
to the part.
Also, the autopointers can point to any FX2LP register or
endpoint buffer space. When autopointer access to external
memory is enabled, location 0xE67B and 0xE67C in XDAT A and
code space cannot be used.
Document #: 38-08032 Rev. *L Page 12 of 62
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CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
3.18 I2C Controller
Note
9. This EEPROM does not have address pins.
FX2LP has one I2C port that is driven by two internal controllers,
one that automatically operates at boot time to load VID/PID/DID
and configuration information, and another that the 8051 uses
when running to control external I
operates in master mode only.
3.18.1 I
The I
2
C Port Pins
2
C pins SCL and SDA must have external 2.2 kΩ pull up
resistors even if no EEPROM is connected to the FX2LP.
External EEPROM device address pins must be configured
properly. See Table 8 for configuring the device address pins.
Table 8. Strap Boot EEPROM Address Lines to These V alues
Bytes Example EEPROM A2 A1 A0
16 24LC00
[9]
128 24LC01 0 0 0
256 24LC02 0 0 0
4K 24LC32 0 0 1
8K 24LC64 0 0 1
16K 24LC128 0 0 1
2
C devices. The I2C port
N/A N/A N/A
3.18.2 I
At power on reset the I
VID/PID/DID configuration bytes and up to 16 KBytes of
program/data. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051
is in reset. I
reset.
3.18.3 I
The 8051 can control peripherals connected to the I
the I
control only, it is never an I
3.19 Compatible with Previous Generation
The EZ-USB FX2LP is form, fit and with minor exceptions
functionally compatible with its predecessor, the EZ-USB FX2.
This makes for an easy transition for designers wanting to
upgrade their systems from the FX2 to the FX2LP. The pinout
and package selection are identical and a vast majority of
firmware previously developed for the FX2 functions in the
FX2LP.
For designers migrating from the FX2 to the FX2LP a change in
2
C Interface Boot Load Access
2
C interface boot loader loads the
2
C interface boot loads only occur after power on
2
C Interface General-Purpose Access
2
CTL and I2DAT registers. FX2LP provides I2C master
2
C slave.
EZ-USB FX2
the bill of material and review of the memory allocation (due to
increased internal memory) is required. For more information
about migrating from EZ-USB FX2 to EZ-USB FX2LP, see the
application note titled Migrating from EZ-USB FX2 to EZ-USB
FX2LP available in the Cypress web site.
Table 9. Part Number Conversion Table
EZ-USB FX2
Part Number
EZ-USB FX2LP
Part Number
Package Description
CY7C68013-56PVC CY7C68013A-56PVXC or CY7C68014A-56PVXC 56-pin SSOP
CY7C68013-56PVCT CY7C68013A-56PVXCT or CY7C68014A-56PVXCT 56-pin SSOP – Tape and Reel
CY7C68013-56LFC CY7C68013A-56LFXC or CY7C68014A-56LFXC 56-pin QFN
CY7C68013-100AC CY7C68013A-100AXC or CY7C68014A-100AXC 100-pin TQFP
CY7C68013-128AC CY7C68013A-128AXC or CY7C68014A-128AXC 128-pin TQFP
2
C bus using
Document #: 38-08032 Rev. *L Page 13 of 62
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CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
3.20 CY7C68013A/14A and CY7C68015A/16A Differences
CY7C68013A is identical to CY7C68014A in form, fit, and
functionality. CY7C68015A is identical to CY7C68016A in form,
fit, and functionality. CY7C68014A and CY7C68016A have a
lower suspend current than CY7C68013A and CY7C68015A
respectively and are ideal for power sensitive battery applications.
CY7C68015A and CY7C68016A are available in 56-pin QFN
package only. Two additional GPIO signals are available on the
CY7C68015A and CY7C68016A to provide more flexibility when
neither IFCLK or CLKOUT are needed in the 56-pin package.
USB developers wanting to convert their FX2 56-pin application
to a bus-powered system directly benefit from these additional
signals. The two GPIOs give developers the signals they n eed
for the power control circuitry of their bus-powered application
without pushing them to a high pincount version of FX2LP.
The CY7C68015A is only available in the 56-pin QFN package
Table 10. CY7C68013A/14A and CY7C68015A/16A Pin Differences
CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A
IFCLK PE0
CLKOUT PE1
4. Pin Assignments
Figure 6 on page 15 identifies all signals for the five package
types. The following pages illustrate the individual pin diagrams,
plus a combination diagram showing which of the full set of
signals are available in the 128-pin, 100-pin, and 56-pin
packages.
The signals on the left edge of the 56-pin package in Figure 6
on page 15 are common to all versions in the FX2LP family with
the noted differences between the CY7C68013A/14A and the
CY7C68015A/16A.
Three modes are available in all package versions: Port, GPIF
master, and Slave FIFO. These modes define the signals on the
right edge of the diagram. The 8051 selects the interface mode
using the IFCONFIG[1:0] register bits. Port mode is the power on
default configuration.
The 100-pin package adds functionality to the 56-pin package by
adding these pins:
■ PORTC or alternate GPIFADR[7:0] address signals
■ PORTE or alternate GPIFADR[8] address signal and seven
additional 8051 signals
■ Three GPIF Control signals
■ Four GPIF Ready signals
■ Nine 8051 signals (two USART s, three timer inputs, INT4,and
INT5#)
■ BKPT, RD#, WR#.
The 128-pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100-pin version.
In the 100-pin and 128-pin versions, an 8051 control bit can be
set to pulse the RD# and WR# pins when the 8051 reads
from/writes to PORTC. This feature is enabled by setting
PORTCSTB bit in CPUCS register.
Section 10.5 displays the timing diagram of the read and w rite
strobing function on accessing PORTC.
Document #: 38-08032 Rev. *L Page 14 of 62
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CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 6. Signal
RDY0
RDY1
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
56
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
T2
T1
T0
100
D7
D6
D5
D4
D3
D2
D1
D0
EA
128
RD#
WR#
CS#
OE#
PSEN#
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
**PE0
**PE1
IFCLK
CLKOUT
DPLUS
DMINUS
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
Port GPIF Master Slave FIFO
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
**PE0 replaces IFCLK
on CY7C68015A/16A
& PE1 replaces CLKOUT
Document #: 38-08032 Rev. *L Page 15 of 62
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CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
EA
SCL
SDA
OE#
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
A3
A2
A1
A0
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
D6
D5
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
GND
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
A4
A5
A6
A7
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
A8
A9
A10
CY7C68013A/CY7C68014A
128-pin TQFP
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
D4
D3
D2
D1
D0
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
CS#
WR#
RD#
PSEN#
* denotes programmable polarity
Figure 7. CY7C68013A/CY7C68014A 128-pin TQFP Pin Assignment
Document #: 38-08032 Rev. *L Page 16 of 62
[+] Feedback [+] Feedback
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
CY7C68013A/CY7C68014A
100-pin TQFP
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
WR#
RD#
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
SCL
SDA
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
* denotes programmable polarity
Figure 8. CY7C68013A/CY7C68014A 100-pin TQFP Pin Assignment
Document #: 38-08032 Rev. *L Page 17 of 62
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CY7C68015A, CY7C68016A
Figure 9. CY7C68013A/CY7C68014A 56-pin SSOP Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK
RESERVED
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
RESET#
GND
PA7/*FLAGD/SLCS#
PA6/PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
CY7C68013A/CY7C68014A
56-pin SSOP
* denotes programmable polarity
Document #: 38-08032 Rev. *L Page 18 of 62
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CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 10. CY7C68013A/14A/15A/16A 56-pin QFN Pin Assignment
28
27
26
25
24
23
22
21
20
19
18
17
16
15
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
* denotes programmable polarity
RESET#
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK/**PE0
RESERVED
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
SDA
SCL
CY7C68013A/CY7C68014A
&
CY7C68015A/CY7C68016A
56-pin QFN
** denotes CY7C68015A/CY7C68016A pinout
VCC
*WAKEUP
PD0/FD8
PD1/FD9
PD2/FD10
PD3/FD11
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT/**PE1
VCC
GND
Document #: 38-08032 Rev. *L Page 19 of 62
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