Cypress CY7C68013A User Manual

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
EZ-USB FX2LP™ USB Microcontroller
High-Speed USB Peripheral Controller

1. Features (CY7C68013A/14A/15A/16A)

USB 2.0 USB IF high-speed certified (TID # 40460272)
enhanced 8051 microprocessor
Fit, form and function compatible with the FX2Pin compatibleObject-code-compatible
Functionally compatible (FX2LP is a superset)
Ultra Low power: IIdeal for bus and battery powered applications
Software: 8051 code runs from:Internal RAM, which is downloaded via USB
Internal RAM, which is loaded from EEPROMExternal memory device (128 pin package)
16 KBytes of on-chip Code/Data RAM
Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
Buffering options: double, triple, and quad
Additional programmable (BULK/INTERRUPT) 64 byte
endpoint
8-bit or 16-bit external data interface
Smart Media Standard ECC generation
no more than 85 mA in any mode
CC
GPIF (General Programmable Interface)Enables direct connection to most parallel interfacesProgrammable waveform descriptors and configuration reg-
isters to define waveforms
Supports multiple Ready (RDY) inputs and Control (CTL) out-
puts
Integrated, industry standard enhanced 805148 MHz, 24 MHz, or 12 MHz CPU operation
Four clocks per instruction cycleTwo USARTSThree counter/timersExpanded interrupt systemTwo data poi nters
3.3V operation with 5V tolerant inputs
Vectored USB interrupts and GPIF/FIFO interrupts
Separate data buffers for the Setup and Data portions of a
CONTROL transfer
Integrated I
Four integrated FIFOsIntegrated glue logic and FIFOs lower system cost
Automatic conversion to and from 16-bit busesMaster or slave operationUses external clock or asynchronous strobesEasy interface to ASIC and DSP ICs
Available in Commercial and Industrial temperature grade (all
2
C controller, runs at 100 or 400 kHz
packages except VFBGA)
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 •408-943-2600 Document #: 38-08032 Rev. *L Revised February 8, 2008
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Address (16)
x20 PLL
/0.5 /1.0 /2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
VCC
1.5k
D+
D–
Address (16) / Data Bus (8)
FX2LP
GPIF
CY
Smart
USB
1.1/2.0
Engine
USB
2.0
XCVR
16 KB
RAM
4 kB
FIFO
Integrated
full-speed and
Additional IOs (24)
ADDR (9)
CTL (6)
RDY (6)
8/16
Data (8)
24 MHz Ext. XTAL
Enhanced USB core Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory (master or slave operation)
Up to 96 MBytes/s
burst rate
General programmable I/F to ASIC/DSP or bus
standards such as ATAPI, EPP, etc.
Abundant IO
including two USART S
High performance micro using standard tools with lower-power options
Master
connected for full-speed
ECC
XCVR
high-speed

Logic Block DiagramLogic Block Diagram

1.1 Features (CY7C68013A/14A only)

CY7C68014A: Ideal for battery powered applicationsSuspend current: 100 μA (typ)
CY7C68013A: Ideal for non-battery powered applicati onsSuspend current: 300 μA (typ)
Available in five lead-free packages with up to 40 GPIOs128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin
QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VF­BGA (24 GPIOs)

1.2 Features (CY7C68015A/16A only)

CY7C68016A: Ideal for battery powered applicationsSuspend current: 100 μA (typ)
CY7C68015A: Ideal for non-battery powered applicati onsSuspend current: 300 μA (typ)
Available in lead-free 56-pin QFN package (26 GPIOs)2 more GPIOs than CY7C68013A/14A enabling additional
features in same footprint
Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB FX2LP (CY7C68013A/14A) is a low power version of the EZ-USB FX2(CY7C68013), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.0 trans­ceiver, serial interface engine (SIE), enhanced 8051 microcon­troller, and a programmable peripheral interface in a single chip,
Cypress has created a cost effective solution that provides superior time-to-market advantages with low power to enable bus powered applications.
The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low cost 8051 microcon­troller in a package as small as a 56 VFBGA (5mm x 5mm). Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application specific functions and decreasing development time to ensure USB compatibility.
The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as EPP, PCMCIA, and most DSP/processors.
ATA, UTOPIA,
The FX2LP draws less current than the FX2 (CY7C68013), has double the on-chip code/data RAM, and is fit, form and function compatible with the 56, 100, and 128 pin FX2.
Five packages are defined for the family: 56VFBGA, 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.
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2. Applications

12 pf
12 pf
24 MHz
20 × PLL
C1
C2
12-pF capacitor values assumes a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
Note
1. 115 KBaud operation is also possible by progr amming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.
Portable video recorder
MPEG/TV conversion
DSL modems
ATA interface
Memory card readers
Legacy conversion devices
Cameras
Scanners
Home PNA
Wireless LAN
MP3 players
Networking
The “Reference Designs” section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Visit the Cypress
web site for more information.

3. Functional Overview

3.1 USB Signaling Speed

FX2LP operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000:
Full-speed, with a signaling bit rate of 12 Mbps
High-speed, with a signaling bit rate of 480 Mbps.
FX2LP does not support the low speed signaling mode of
1.5 Mbps.

3.2 8051 Microprocessor

The 8051 microprocessor embedded in the FX2LP family has 256 bytes of register RAM, an expanded interrupt system, three timer/counters, and two USARTs.

3.2.1 8051 Clock Frequency

FX2LP has an on-chip oscillator circuit that uses an external 24 MHz (±100 ppm) crystal with the following characteristics:
Parallel resonant
Fundamental mode
500-μW drive level
12-pF (5% tolerance) load capacitors
An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz, as required by the transceiver/PHY and internal counters divide it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically.
Figure 1. Crystal Configuration
The CLKOUT pin, which can be three-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.

3.2.2 USARTS

FX2LP contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins are available on separate IO pins, and are not multiplexe d with port pins.
UART0 and UART1 can operate using an internal clock at 230 KBaud with no more than 1% baud rate error. 230 KBaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and 12 MHz) such that it always presents the correct frequency for 230 KBaud operation.
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3.2.3 Special Function Registers

Certain 8051 SFR addresses are populated to provide fast access to critical FX2LP functions. These SFR additions are shown in Ta bl e 1 on page 4. Bold type indicates non standard, enhanced 8051 registers. The two SFR rows that end with “0” and “8” contain bit addressable registers. The four IO ports A to D use the SFR addresses used in the standard 8051 for ports 0 to 3, which are not implemented in FX2LP . Because of the faster and more efficient SFR addressing, the FX2LP IO ports are not addressable in external RAM space (using the MOVX instruction).

3.3 I2C Bus

FX2LP supports the I2C bus as a master only at 100-/400- KHz. SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to 3.3V, even if no I
2
device is connected.

3.4 Buses

All packages, 8-bit or 16-bit “FIFO” bidirectional data bus, multi­plexed on IO ports B and D. 128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus.
C
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Table 1. Special Function Registers
Note
2. The I
2
C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
x 8x 9x Ax Bx Cx Dx Ex Fx
0 IOA IOB IOC IOD SCON1 PSW ACC B 1SP EXIF INT2CLR IOE SBUF1 2DPL0 MPAGE 3DPH0 OEB 4 DPL1 OEC 5 DPH1 OED 6 DPS OEE 7PCON 8 TCON SCON0 IE IP T2CON EICON EIE EIP
9 TMOD SBUF0 ATL0AUTOPTRH1 EP2468STAT EP01STAT RCAP2L BTL1AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H CTH0reserved EP68FIFOFLGS TL2 DTH1AUTOPTRH2 GPIFSGLDATH TH2 E CKCON AUTOPTRL2 GPIFSGLDA TLX F reserved AUTOPTRSET-UP GPIFSGLDATLNOX
INT4CLR OEA

3.5 USB Boot Methods

During the power up sequence, internal logic checks the I2C port for the connection of an EEPROM whose first byte is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0), or it boot-loads the EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2LP enumerates using internally stored descriptors. The default ID values for FX2LP are VID/PID/DID (0x04B4, 0x8613, 0xAxxx where xxx = Chip revision).
Table 2. Default ID Values for FX2LP
Default VID/PID/DID
Vendor ID 0x04B4 Cypress Semiconductor Product ID 0x8613 EZ-USB FX2LP Device release 0xAnnn Depends on chip revision
(nnn = chip revision where first silicon = 001)
[2]

3.6 ReNumeration™

Because the FX2LP’s configuration is soft, one chip can take on the identities of multiple distinct USB devices.
When first plugged into USB, the FX2LP enumerates automati ­cally and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2LP enumerates again, this time as a device defined by the downloaded information. This patented two step process called ReNumeration happens instantly when the device is plugged in, without a hint that the initial download step has occurred.
Two control bits in the USBCS (USB Control and S tatus) register , control the ReNumeration process: DISCON and RENUM. To simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device handles device requests over endpoint zero: if RENUM = 0, the Default USB Device handles device requests; if RENUM = 1, the firmware services the requests.

3.7 Bus-powered Applications

The FX2LP fully supports bus powered designs by enumerating with less than 100 mA as required by the USB 2.0 specification.

3.8 Interrupt System

3.8.1 INT2 Interrupt Request and Enable Registers

FX2LP implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See EZ-USB Technical Reference Manual (TRM) for more details.

3.8.2 USB Interrupt Autovectors

The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that is required to identify the individual USB interrupt source, the FX2LP provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter onto its stack then jumps to the address 0x0043 where it expects to find a “jump” instruction to the USB Interrupt service routine.
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The FX2LP jump instruction is encoded as follows:
Table 3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority INT2VEC Value Source Notes
1 00 SUDAV Setup Data Available 2 04 SOF Start of Frame (or microframe) 3 08 SUTOK Setup Token Received 4 0C SUSPEND USB Suspend request 5 10 USB RESET Bus reset 6 14 HISPEED Entered high-speed operation 7 18 EP0ACK FX2LP ACK’d the CONTROL Handshake 8 1C reserved
9 20 EP0-IN EP0-IN ready to be loaded with data 10 24 EP0-OUT EP0-OUT has USB data 11 28 EP1-IN EP1-IN ready to be loaded with data 12 2C EP1-OUT EP1-OUT has USB data 13 30 EP2 IN: buffer available. OUT: buffer has data 14 34 EP4 IN: buffer available. OUT: buffer has data 15 38 EP6 IN: buffer available. OUT: buffer has data 16 3C EP8 IN: buffer available. OUT: buffer has data 17 40 IBN IN-Bulk-NAK (any IN endpoint) 18 44 reserved 19 48 EP0PING EP0 OUT was Pinged and it NAK’d 20 4C EP1PING EP1 OUT was Pinged and it NAK’d 21 50 EP2PING EP2 OUT was Pinged and it NAK’d 22 54 EP4PING EP4 OUT was Pinged and it NAK’d 23 58 EP6PING EP6 OUT was Pinged and it NAK’d 24 5C EP8PING EP8 OUT was Pinged and it NAK’d 25 60 ERRLIMIT Bus errors exceeded the programmed limit 26 64 27 68 reserved 28 6C reserved 29 70 EP2ISOERR ISO EP2 OUT PID sequence error 30 74 EP4ISOERR ISO EP4 OUT PID sequence error 31 78 EP6ISOERR ISO EP6 OUT PID sequence error 32 7C EP8ISOERR ISO EP8 OUT PID sequence error
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page.
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3.8.3 FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.
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Ta bl e 4. Individ ua l FI FO /GPIF Interrupt Sources
Note
3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 μs.
Priority INT4VEC Value Source Notes
1 80 EP2PF Endpoint 2 Programmable Flag 2 84 EP4PF Endpoint 4 Programmable Flag 3 88 EP6PF Endpoint 6 Programmable Flag 4 8C EP8PF Endpoint 8 Programmable Flag 5 90 EP2EF Endpoint 2 Empty Flag 6 94 EP4EF Endpoint 4 Empty Flag 7 98 EP6EF Endpoint 6 Empty Flag 8 9C EP8EF Endpoint 8 Empty Flag
9 A0 EP2FF Endpoint 2 Full Flag 10 A4 EP4FF Endpoint 4 Full Flag 1 1 A8 EP6FF Endpoint 6 Full Flag 12 AC EP8FF Endpoint 8 Full Flag 13 B0 GPIFDONE GPIF Operation Complete 14 B4 GPIFWF GPIF Waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP register), the FX 2LP substitutes its INT4VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0054, the automatically inserted INT4VEC byte at 0x0055 directs the jump to the correct address out of the 14 addresses within the page. When the ISR occurs, the FX2LP pushes the program counter onto its stack then jumps to address 0x0053, where it expects to find a “jump” instruction to the ISR Interrupt service routine.

3.9 Reset and Wakeup

3.9.1 Reset Pin

The input pin, RESET#, resets the FX2LP when asserted. This pin has hysteresis and is active LOW. When a crystal is used with
the CY7C680xxA the reset period must allow for the stabilization of the crystal and the PLL. This reset period must be approxi­mately 5 ms after VCC reaches 3.0V. If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 μs after VCC has reached 3.0V.
Figure 2 on page 7 shows a power on reset condition and a reset
applied during operation. A power on reset is defined as the time reset that is asserted while power is being applied to the circuit. A powered reset is when the FX2LP powered on and operating and the RESET# pin is asserted.
Cypress provides an application note which describes and recommends power on reset implementation. For more infor­mation about reset implementation for the FX2 family of products visit http://www.cypress.com.
[3]
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V
IL
0V
3.3V
3.0V
T
RESET
VCC
RESET#
Power on Reset
T
RESET
VCC
RESET#
V
IL
Powered Reset
3.3V
0V
Figure 2. Reset Timing Plots
Table 5. Reset Timing Values
Condition T
RESET
Power on Reset with Crystal 5 ms Power on Reset with External
200 μs + Clock stability time
Clock Powered Reset 200 μs

3.9.2 Wakeup Pins

The 8051 puts itself and the rest of the chip into a power down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic the oscillator restarts after the PLL stabilizes, and the 8051 receives a wakeup interrupt. This applies whether or not FX2LP is connected to the USB.
The FX2LP exits the power down (USB suspend) state using one of the following methods:
USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX2LP and initiate a wakeup)
External logic asserts the WAKEUP pin
External logic asserts the PA3/WU2 pin
The second wakeup pin, WU2, can also be configured as a general purpose IO pin. This enables a simple external R-C network to be used as a periodic wakeup source. WAKEUP is by default active LOW.

3.10 Program/Data RAM

3.10.1 Size

The FX2LP has 16 KBytes of internal program/data RAM, where PSEN#/RD# signals are internally ORed to enable the 8051 to access it as both program and data memory. No USB control registers appear in this space.
Two memory maps are shown in the following diagrams:
Figure 3 on page 8 shows the Internal Code Memory, EA = 0 Figure 4 on page 9 shows the External Code Memory, EA = 1.

3.10.2 Internal Code Memory, EA = 0

This mode implements the internal 16 KByte block of RAM (starting at 0) as combined code and data memory. When external RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This enables the user to connect a 64 KByte memory without requiring address decodes to keep clear of internal memory spaces.
Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM spaces have the following access:
USB download
USB upload
Setup data pointer
2
I
C interface boot load.

3.10.3 External Code Memory, EA = 1

The bottom 16 KBytes of program memory is external and therefore the bottom 16 KBytes of internal RAM is accessible only as a data memory.
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Figure 3. Internal Code Memory, EA = 0
Inside FX2LP Outside FX2LP
7.5 KBytes USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KBytes RAM
Data (RD#,WR#)*
(OK to populate data memory here—RD#/WR# strobes are not active)
40 KBytes External Data Memory (RD#,WR#)
(Ok to populate data memory here—RD#/WR# strobes are not active)
16 KBytes RAM Code and Data (PSEN#,RD#,WR#)*
48 KBytes External Code Memory (PSEN#)
(OK to populate program memory here— PSEN# strobe is not active)
*SUDPTR, USB upload/download, I2C interface boot access
FFFF
E200 E1FF
E000
3FFF
0000
Data Code
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Figure 4. External Code Memory, EA = 1
Inside FX2LP Outside FX2LP
7.5 KBytes USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KBytes RAM
Data (RD#,WR#)*
(OK to populate data memory here—RD#/WR# strobes are not active)
40 KBytes External Data Memory (RD#,WR#)
(Ok to populate data memory here—RD#/WR# strobes are not active)
16 KBytes RAM Data (RD#,WR#)*
64 KBytes External Code Memory (PSEN#)
*SUDPTR, USB upload/download, I2C interface boot access
FFFF
E200 E1FF
E000
3FFF
0000
Data Code
FFFF
E800
E7BF
E740
E73F
E700 E6FF
E500 E4FF E480 E47F
E400
E200
E1FF
E000
E3FF
EFFF
2 KBytes RESERVED
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addressable Registers
Reserved (128)
128 bytes GPIF Waveforms
512 bytes
8051 xdata RAM
F000
(512)
Reserved (512)
E780
64 Bytes EP1OUT
E77F
64 Bytes EP1IN
E7FF E7C0
4 KBytes EP2-EP8
buffers
(8 x 512)

3.11 Register Addresses

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3.12 Endpoint RAM

64 64 64
512
512
1024
1024
1024
1024
1024
1024
1024
512
512
512 512
512
512
512
512
512 512
EP2
EP2
EP2
EP6
EP6
EP8
EP8
EP0 IN&OUT
EP1 IN
EP1 OUT
1024
1024
EP6
1024
512
512
EP8
512 512
EP6
512
512
512
512
EP2
512
512
EP4
512 512
EP2
512 512
EP4
512
512
EP2
512
512
EP4
512 512
EP2
512 512
512 512
EP2
512 512
512
512
EP2
512 512
1024
EP2
1024
1024
EP2
1024
1024
EP2
1024
512
512
EP6
1024
1024
EP6
512 512
EP8
512 512
EP6
512
512
512 512
EP6
1024
1024
EP6
512 512
EP8
512 512
EP6
512 512
64 64 64
64 64 64
64 64 64
64 64 64
64 64 64
64 64 64
64 64 64
64 64 64
64 64 64
64 64 64
64 64 64
1
2
3
4
5
6
7
8
9
10
11
12

3.12.1 Size

3× 64 bytes (Endpoints 0 and 1)
8 × 512 bytes (Endpoints 2, 4, 6, 8)

3.12.2 Organization

EP0
Bidirectional endpoint zero, 64 byte buffer
EP1IN, EP1OUT
64 byte buffers, bulk or interrupt
EP2, 4, 6, 8
Eight 512 byte buffers, bulk, interrupt, or isochronous. EP4 and
EP8 can be double buffered; EP2 and 6 can be either double, triple, or quad buffered. For high-speed endpoint configuration options, see Figure 5.
Figure 5. Endpoint Configuration

3.12.3 Setup Data Buffer

A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data from a CONTROL transfer.

3.12.4 Endpoint Configurations (High -speed Mode)

Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT.
The endpoint buffers can be configured in any 1 of the 12 config­urations shown in the vertical columns. When operating in the full-speed BULK mode only the first 64 bytes of each buffer are used. For example, in high-speed, the max packet size is 512 bytes but in full-speed it is 64 bytes. Even though a buffer is configured to a 512 byte buffer, in full-speed only the first 64 bytes are used. The unused endpoint buffer space is not available for other operations. An example endpoint configu­ration is the EP2–1024 double buffered; EP6–512 quad buffered (column 8).
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3.12.5 Default Full-Speed Alternate Settings

Notes
4. “0” means “not implemented.”
5. “2×” means “double buffered.”
6. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Table 6. Default Full-Speed Alternate Settings
[4, 5]
Alternate Setting 0 1 2 3
ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×) ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×) ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×) ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)

3.12.6 Default High-Speed Alternate Settings

Table 7. Default High-Speed Alternate Settings
[4, 5]
Alternate Setting 0 1 2 3
ep0 64 64 64 64 ep1out 0 512 bulk ep1in 0 512 bulk
[6] [6]
64 int 64 int
64 int 64 int ep2 0 512 bulk out (2×) 512 int out (2×) 512 iso out (2×) ep4 0 512 bulk out (2×) 512 bulk out (2×) 512 bulk out (2×) ep6 0 512 bulk in (2×) 512 int in (2×) 512 iso in (2×) ep8 0 512 bulk in (2×) 512 bulk in (2×) 512 bulk in (2×)

3.13 External FIFO Interface

3.13.1 Architecture

The FX2LP slave FIFO architecture has eight 512 byte blocks in the endpoint RAM that directly serve as FIFO memories and are controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the IO transfer logic. The transfer logic takes two forms, the GPIF for internally generated control signals and the slave FIFO interface for externally controlled transfers.

3.13.2 Master/Slave Control Signals

The FX2LP endpoint FIFOS are implemented as eight physically distinct 256x16 RAM blocks. The 8051/SIE can switch any of the RAM blocks between two domains, the USB (SIE) domain and the 8051-IO Unit domain. This switching is done virtually instan­taneously, giving essentially zero transfer time between “USB FIFOS” and “Slave FIFOS.” Because they are physically the same memory no bytes are actually transferred between buffers.
At any given time, some RAM blocks are filling/emptying with USB data under SIE control, while other RAM blocks are available to the 8051, the IO control unit or both. The RAM blocks operate as single port in the USB domain, and dual port i n the
8051-IO domain. The blocks can be configured as single, double, triple, or quad buffe r ed as previously shown.
The IO control unit implements either an internal master (M for master) or external master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-pin package, six in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s (48-MHz IFCLK with 16-bit interface).
In Slave (S) mode, the FX2LP accepts either an internally derived clock or externally supplied clock (IFCLK, max frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. When using an external IFCLK, the external clock must be present before switching to the external clock with the IFCLKSRC bit. Each endpoint can individually be selected for byte or word operation by an internal configuration bit and a Slave FIFO Output Enable signal SLOE enables data of the selected width. External logic must ensure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#.
Document #: 38-08032 Rev. *L Page 11 of 62
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3.13.3 GPIF and FIFO Clock Rates

Notes
7. T o use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
8. After the data has been downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory.
An 8051 register bit selects one of two frequencies for the inter­nally supplied interface clock: 30 MHz and 48 MHz. Alternatively, an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register turns this clock output off, if desired. Another bit within the IFCONFIG register inverts the IFCLK signal whether internally or externally sourced.

3.14 GPIF

The GPIF is a flexible 8-bit or 16-bit parallel interface driven by a user programmable finite state machine. It enables the CY7C68013A/15A to perform local bus mastering and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia.
The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, etc. A sequence of the GPIF vectors make up a single waveform that is executed to perform the desired data move between the FX2LP and the external device.

3.14.1 Six Control OUT Signals

The 100-pin and 128-pin packages bring out all six Control Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to define the CTL waveforms. The 56-pin package brings out three of these signals, CTL0–CTL2. CTLx waveform edges can be programmed to make transitions as fast as once per cl ock (20.8 ns using a 48-MHz clock).

3.14.2 Six Ready IN Signals

The 100-pin and 128-pin packages bring out all six Ready inputs (RDY0–RDY5). The 8051 programs the GPIF unit to test the RDY pins for GPIF branching. The 56-pin package brings out two of these signals, RDY0–1.

3.14.3 Nine GPIF Address OUT Signals

Nine GPIF address lines are available in the 100-pin and 128-pin packages, GPIFADR[8..0]. The GPIF address lines enable indexing through up to a 512 byte block of RAM. If more address lines are needed IO port pins are used.

3.14.4 Long Transfer Mode

In the master mode, the 8051 appropriately sets GPIF trans­action count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or GPIFTCB0) for unattended transfers of up to 2 The GPIF automatically throttles data flow to prevent under or overflow until the full number of requested transactions complete. The GPIF decrements the value in these registers to represent the current status of the transaction.
32
transactions.
3.15 ECC Generation
The EZ-USB can calculate ECCs (Error Correcting Codes) on data that passes across its GPIF or Slave FIFO interfaces. There are two ECC configurations: Two ECCs, each calculated over 256 bytes (SmartMedia Standard); and one ECC calculated over 512 bytes.
The ECC can correct any one-bit error or detect any two-bit error.

3.15.1 ECC Implementation

The two ECC configurations are selected by the ECCM bit:
ECCM = 0
Two 3 byte ECCs, each calculated over a 256 byte block of data. This configuration conforms to the SmartMedia Standard.
Write any value to ECCRESET, then pass data across the GPIF or Slave FIFO interface. The ECC for the first 256 bytes of data is calculated and stored in ECC1. The ECC for the next 256 bytes is stored in ECC2. After the second ECC is calculated, the values in the ECCx registers do not change until ECCRESET is written again, even if more data is subsequently passed across the interface.
ECCM = 1
One 3 byte ECC calculated over a 512 byte block of data. Write any value to ECCRESET then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 512 bytes of data is calculated and stored in ECC1; ECC2 is unused. After the ECC is calculated, the values in ECC1 do not change even if more data is subsequently passed across the interface, till ECCRESET is written again.
[7]

3.16 USB Uploads and Downloads

The core has the ability to directly edit the data contents of the internal 16 KByte RAM and of the internal 512 byte scratch pad RAM via a vendor specific command. This capability is normally used when soft downloading user code and is available only to and from internal RAM, only when the 8051 is held in reset. The available RAM spaces are 16 KBytes from 0x0000–0x3FFF (code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad data RAM).
[8]

3.17 Autopointer Access

FX2LP provides two identical autopointers. They are similar to the internal 8051 data pointers but with an additional feature: they can optionally increment after every memory access. This capability is available to and from both internal and external RAM. The autopointers are available in external FX2LP registers under control of a mode bit (AUTOPTRSET-UP.0). Using the external FX2LP autopointer access (at 0xE67B – 0xE67C) enables the autopointer to access all internal and external RAM to the part.
Also, the autopointers can point to any FX2LP register or endpoint buffer space. When autopointer access to external memory is enabled, location 0xE67B and 0xE67C in XDAT A and code space cannot be used.
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3.18 I2C Controller

Note
9. This EEPROM does not have address pins.
FX2LP has one I2C port that is driven by two internal controllers, one that automatically operates at boot time to load VID/PID/DID and configuration information, and another that the 8051 uses when running to control external I operates in master mode only.
3.18.1 I
The I
2
C Port Pins
2
C pins SCL and SDA must have external 2.2 kΩ pull up resistors even if no EEPROM is connected to the FX2LP. External EEPROM device address pins must be configured properly. See Table 8 for configuring the device address pins.
Table 8. Strap Boot EEPROM Address Lines to These V alues
Bytes Example EEPROM A2 A1 A0
16 24LC00
[9]
128 24LC01 0 0 0 256 24LC02 0 0 0 4K 24LC32 0 0 1 8K 24LC64 0 0 1 16K 24LC128 0 0 1
2
C devices. The I2C port
N/A N/A N/A
3.18.2 I
At power on reset the I VID/PID/DID configuration bytes and up to 16 KBytes of program/data. The available RAM spaces are 16 KBytes from 0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051 is in reset. I reset.
3.18.3 I
The 8051 can control peripherals connected to the I the I control only, it is never an I
3.19 Compatible with Previous Generation
The EZ-USB FX2LP is form, fit and with minor exceptions functionally compatible with its predecessor, the EZ-USB FX2. This makes for an easy transition for designers wanting to upgrade their systems from the FX2 to the FX2LP. The pinout and package selection are identical and a vast majority of firmware previously developed for the FX2 functions in the FX2LP.
For designers migrating from the FX2 to the FX2LP a change in
2
C Interface Boot Load Access
2
C interface boot loader loads the
2
C interface boot loads only occur after power on
2
C Interface General-Purpose Access
2
CTL and I2DAT registers. FX2LP provides I2C master
2
C slave.
EZ-USB FX2
the bill of material and review of the memory allocation (due to increased internal memory) is required. For more information about migrating from EZ-USB FX2 to EZ-USB FX2LP, see the application note titled Migrating from EZ-USB FX2 to EZ-USB FX2LP available in the Cypress web site.
Table 9. Part Number Conversion Table
EZ-USB FX2
Part Number
EZ-USB FX2LP
Part Number
Package Description
CY7C68013-56PVC CY7C68013A-56PVXC or CY7C68014A-56PVXC 56-pin SSOP
CY7C68013-56PVCT CY7C68013A-56PVXCT or CY7C68014A-56PVXCT 56-pin SSOP – Tape and Reel
CY7C68013-56LFC CY7C68013A-56LFXC or CY7C68014A-56LFXC 56-pin QFN CY7C68013-100AC CY7C68013A-100AXC or CY7C68014A-100AXC 100-pin TQFP CY7C68013-128AC CY7C68013A-128AXC or CY7C68014A-128AXC 128-pin TQFP
2
C bus using
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3.20 CY7C68013A/14A and CY7C68015A/16A Differences

CY7C68013A is identical to CY7C68014A in form, fit, and functionality. CY7C68015A is identical to CY7C68016A in form, fit, and functionality. CY7C68014A and CY7C68016A have a lower suspend current than CY7C68013A and CY7C68015A respectively and are ideal for power sensitive battery applica­tions.
CY7C68015A and CY7C68016A are available in 56-pin QFN package only. Two additional GPIO signals are available on the CY7C68015A and CY7C68016A to provide more flexibility when neither IFCLK or CLKOUT are needed in the 56-pin package.
USB developers wanting to convert their FX2 56-pin application to a bus-powered system directly benefit from these additional signals. The two GPIOs give developers the signals they n eed for the power control circuitry of their bus-powered application without pushing them to a high pincount version of FX2LP.
The CY7C68015A is only available in the 56-pin QFN package
Table 10. CY7C68013A/14A and CY7C68015A/16A Pin Dif­ferences
CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A
IFCLK PE0
CLKOUT PE1

4. Pin Assignments

Figure 6 on page 15 identifies all signals for the five package
types. The following pages illustrate the individual pin diagrams, plus a combination diagram showing which of the full set of signals are available in the 128-pin, 100-pin, and 56-pin packages.
The signals on the left edge of the 56-pin package in Figure 6 on page 15 are common to all versions in the FX2LP family with the noted differences between the CY7C68013A/14A and the CY7C68015A/16A.
Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power on default configuration.
The 100-pin package adds functionality to the 56-pin package by adding these pins:
PORTC or alternate GPIFADR[7:0] address signals
PORTE or alternate GPIFADR[8] address signal and seven
additional 8051 signals
Three GPIF Control signals
Four GPIF Ready signals
Nine 8051 signals (two USART s, three timer inputs, INT4,and
INT5#)
BKPT, RD#, WR#.
The 128-pin package adds the 8051 address and data buses plus control signals. Note that two of the required signals, RD# and WR#, are present in the 100-pin version.
In the 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from/writes to PORTC. This feature is enabled by setting PORTCSTB bit in CPUCS register.
Section 10.5 displays the timing diagram of the read and w rite
strobing function on accessing PORTC.
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Figure 6. Signal
RDY0 RDY1
CTL0 CTL1 CTL2
INT0#/PA0 INT1#/PA1 PA2 WU2/PA3 PA4 PA5 PA6 PA7
56
BKPT PORTC7/GPIFADR7
PORTC6/GPIFADR6 PORTC5/GPIFADR5 PORTC4/GPIFADR4 PORTC3/GPIFADR3 PORTC2/GPIFADR2 PORTC1/GPIFADR1 PORTC0/GPIFADR0
PE7/GPIFADR8 PE6/T2EX PE5/INT6 PE4/RxD1OUT PE3/RxD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
T2 T1 T0
100
D7 D6 D5 D4 D3 D2 D1 D0
EA
128
RD#
WR#
CS# OE#
PSEN#
A15 A14 A13 A12 A11 A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
XTALIN XTALOUT RESET# WAKEUP#
SCL SDA
**PE0 **PE1
IFCLK CLKOUT
DPLUS DMINUS
FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0]
SLRD SLWR
FLAGA FLAGB FLAGC
INT0#/ PA0 INT1#/ PA1 SLOE WU2/PA3 FIFOADR0 FIFOADR1 PKTEND PA7/FLAGD/SLCS#
FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0]
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
INT0#/PA0 INT1#/PA1
PA2
WU2/PA3
PA4 PA5 PA6 PA7
Port GPIF Master Slave FIFO
CTL3 CTL4 CTL5 RDY2 RDY3 RDY4 RDY5
**PE0 replaces IFCLK
on CY7C68015A/16A
& PE1 replaces CLKOUT
Document #: 38-08032 Rev. *L Page 15 of 62
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
CLKOUT VCC GND RDY0/*SLRD RDY1/*SLWR RDY2 RDY3 RDY4 RDY5 AVCC XTALOUT XTALIN AGND NC NC NC AVCC DPLUS DMINUS AGND A11 A12 A13 A14 A15 VCC GND INT4 T0 T1 T2 *IFCLK RESERVED BKPT EA SCL SDA OE#
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
A3 A2 A1 A0
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0
D7 D6 D5
PA3/*WU2
PA2/*SLOE
PA1/INT1# PA0/INT0#
VCC
GND PC7/GPIFADR7 PC6/GPIFADR6 PC5/GPIFADR5 PC4/GPIFADR4 PC3/GPIFADR3 PC2/GPIFADR2 PC1/GPIFADR1 PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB CTL0/*FLAGA
VCC CTL4 CTL3
GND
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
A4
A5
A6
A7
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
A8
A9
A10
CY7C68013A/CY7C68014A
128-pin TQFP
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VCC
D4
D3
D2
D1
D0
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
CS#
WR#
RD#
PSEN#
* denotes programmable polarity
Figure 7. CY7C68013A/CY7C68014A 128-pin TQFP Pin Assignment
Document #: 38-08032 Rev. *L Page 16 of 62
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1# PA0/INT0#
VCC
GND PC7/GPIFADR7 PC6/GPIFADR6 PC5/GPIFADR5 PC4/GPIFADR4 PC3/GPIFADR3 PC2/GPIFADR2 PC1/GPIFADR1 PC0/GPIFADR0
CTL2/*FLAGC CTL1/*FLAGB CTL0/*FLAGA
VCC CTL4 CTL3
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
CY7C68013A/CY7C68014A
100-pin TQFP
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
WR#
RD#
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VCC GND RDY0/*SLRD RDY1/*SLWR RDY2 RDY3 RDY4 RDY5 AVCC XTALOUT XTALIN AGND NC NC NC AVCC DPLUS DMINUS AGND VCC GND INT4 T0 T1 T2 *IFCLK RESERVED BKPT SCL SDA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
* denotes programmable polarity
Figure 8. CY7C68013A/CY7C68014A 100-pin TQFP Pin Assignment
Document #: 38-08032 Rev. *L Page 17 of 62
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Figure 9. CY7C68013A/CY7C68014A 56-pin SSOP Pin Assignment
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PD5/FD13 PD6/FD14 PD7/FD15 GND CLKOUT VCC GND RDY0/*SLRD RDY1/*SLWR AVCC XTALOUT XTALIN AGND AVCC DPLUS DMINUS AGND VCC GND *IFCLK RESERVED SCL SDA VCC PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PD4/FD12 PD3/FD11 PD2/FD10
PD1/FD9 PD0/FD8
*WAKEUP
VCC
RESET#
GND
PA7/*FLAGD/SLCS#
PA6/PKTEND PA5/FIFOADR1 PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1# PA0/INT0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB CTL0/*FLAGA
GND
VCC
GND PB7/FD7 PB6/FD6 PB5/FD5 PB4/FD4
CY7C68013A/CY7C68014A
56-pin SSOP
* denotes programmable polarity
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Figure 10. CY7C68013A/14A/15A/16A 56-pin QFN Pin Assignment
28
27
26
25
24
23
22
21
20
19
18
17
16
15
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1 2 3 4 5 6 7 8
9 10 11 12 13 14
42 41 40 39 38 37 36 35 34 33 32 31 30
29
* denotes programmable polarity
RESET# GND PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/*WU2 PA2/*SLOE PA1/INT1# PA0/INT0# VCC CTL2/*FLAGC CTL1/*FLAGB CTL0/*FLAGA
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK/**PE0
RESERVED
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
SDA
SCL
CY7C68013A/CY7C68014A
&
CY7C68015A/CY7C68016A
56-pin QFN
** denotes CY7C68015A/CY7C68016A pinout
VCC
*WAKEUP
PD0/FD8
PD1/FD9
PD2/FD10
PD3/FD11
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT/**PE1
VCC
GND
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Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment - Top View
12345678
A
B
C
D
E
F
G
H
1A 2A 3A 4A 5A 6A 7A 8A
1B 2B 3B 4B 5B 6B 7B 8B
1C 2C 3C 4C 5C 6C 7C 8C
1D 2D 7D 8D
1E 2E 7E 8E
1F 2F 3F 4F 5F 6F 7F 8F
1G 2G 3G 4G 5G 6G 7G 8G
1H 2H 3H 4H 5H 6H 7H 8H
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4.1 CY7C68013A/15A Pin Descriptions

56 VF-
BGA
[10]
Name Type Default Description
This signal provides power to the analog section of the chip.
This signal provides power to the analog section of the chip.
as possible.
as possible.
When the 8051 is addressing internal RAM it reflects the internal address.
impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend.
indicates an 8051 code fetch from external memory. It is active for program memory fetches from 0x4000–0xFFFF when the EA pin is LOW, or from 0x0000–0xFFFF when the EA pin is HIGH.
The FX2LP Pin Descriptions follows.
Table 11. FX2LP Pin Descriptions
128
TQFP
Note
100
TQFP
10 9 10 3 2D AVCC Power N/A Analog VCC. Connect this pin to 3.3V power source.
17 16 14 7 1D AVCC Power N/A Analog VCC. Connect this pin to 3.3V power source.
13 12 13 6 2F AGND Ground N/A Analog Ground. Connect to ground with as short a path
20 19 17 10 1F AGND Ground N/A Analog Ground. Connect to ground with as short a path
19 18 16 9 1E DMINUS IO/Z Z USB D– Signal. Connect to the USB D– signal. 18 17 15 8 2E DPLUS IO/Z Z USB D+ Signal. Connect to the USB D+ signal. 94 A0 Output L 8051 Address Bus. This bus is driven at all times. 95 A1 Output L 96 A2 Output L
97 A3 Output L 1 17 A4 Output L 1 18 A5 Output L 1 19 A6 Output L 120 A7 Output L 126 A8 Output L 127 A9 Output L 128 A10 Output L
21 A11 Output L
22 A12 Output L
23 A13 Output L
24 A14 Output L
25 A15 Output L
59 D0 IO/Z Z 8051 Data Bus. This bidirectional bus is high
60 D1 IO/Z Z
61 D2 IO/Z Z
62 D3 IO/Z Z
63 D4 IO/Z Z
86 D5 IO/Z Z
87 D6 IO/Z Z
88 D7 IO/Z Z
39 PSEN# Output H Program Store Enable. This active-LOW signal
10.Unused inputs must not be left floating. Tie eithe r HIGH or LO W as appro priate. Outpu t s should o nly be pulled up or do wn to ensure sign als at power up and i n standby . Note also that no pins should be driven while the device is powered down.
56
SSOP
56
QFN
Document #: 38-08032 Rev. *L Page 21 of 62
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
Table 11. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
34 28 BKPT Output L Breakpoint. This pin goes active (HIGH) when the 8051
99 77 49 42 8B RESET# Input N/A Active LOW Reset. Resets the entire chip. See section
35 EA Input N/A External Access. This pin determines where the 8051
12 11 12 5 1C XTALIN Input N/A Crystal Input. Connect this signal to a 24-MHz
11 10 11 4 2C XTALOUT Output N/A Crystal Output. Connect this signal to a 24-MHz
1 100 5 54 2B CLKOUT on
Port A
82 67 40 33 8G PA0 or
83 68 41 34 6G PA1 or
84 69 42 35 8F PA2 or
56
SSOP
56
QFN
56 VF-
BGA
Name Type Default Description
address bus matches the BPADDRH/L registers and breakpoints are enabled in the BREAKPT register (BPEN = 1). If the BPPULSE bit in the BREAKPT register is HIGH, this signal pulses HIGH for eight 12-/24-/48-MHz clocks. If the BPPULSE bit is LOW, the signal remains HIGH until the 8051 clears the BREAK bit (by writing 1 to it) in the BREAKPT register.
3.9 ”Reset and Wakeup” on page 6 for more details.
fetches code between addresses 0x0000 and 0x3FFF. If EA = 0 the 8051 fetches this code from its internal RAM. IF EA = 1 the 8051 fetches this code from external memory.
parallel-resonant, fundamental mode crystal and load capacitor to GND. It is also correct to drive XTALIN with an external 24-MHz square wave derived from another clock source. When driving from an external source, the driving signal should be a 3.3V square wave.
parallel-resonant, fundamental mode crystal and load capacitor to GND. If an external clock is used to drive XTALIN, leave this pin open.
CY7C68013A and CY7C68014A
-----------------­PE1 on CY7C68015A and CY7C68016A
INT0#
INT1#
SLOE or
O/Z
----------­IO/Z
IO/Z I
IO/Z I
IO/Z I
12 MHz
---------­I
(PA0)
(PA1)
(PA2)
CLKOUT: 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input clock. The 8051 defaults to 12-MHz operation. The 8051 may three-state this output by setting CPUCS.1 = 1.
-----------------------------------------------------------------------­PE1 is a bidirectional IO port pin.
Multiplexed pin whose function is selected by PORTACFG.0
PA0 is a bidirecti onal IO port pin. INT0# is the active-LOW 8051 INT0 interrupt input
signal, which is either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
Multiplexed pin whose function is selected by: PORTACFG.1
PA1 is a bidirecti onal IO port pin. INT1# is the active-LOW 8051 INT1 interrupt input
signal, which is either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
Multiplexed pin whose function is selected by two bits: IFCONFIG[1:0].
PA2 is a bidirecti onal IO port pin. SLOE is an input-only output enable with program-
mable polarity (FIFOPINPOLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0].
Document #: 38-08032 Rev. *L Page 22 of 62
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Table 11. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
85 70 43 36 7F PA3 or
89 71 44 37 6F PA4 or
90 72 45 38 8C PA5 or
91 73 46 39 7C PA6 or
92 74 47 40 6C PA7 or
Port B
44 34 25 18 3H PB0 or
45 35 26 19 4F PB1 or
46 36 27 20 4H PB2 or
47 37 28 21 4G PB3 or
54 44 29 22 5H PB4 or
56
SSOP
56
QFN
56 VF-
BGA
Name Type Default Description
WU2
FIFOADR0
FIFOADR1
PKTEND
FLAGD or SLCS#
FD[0]
FD[1]
FD[2]
FD[3]
FD[4]
IO/Z I
(PA3)
IO/Z I
(PA4)
IO/Z I
(PA5)
IO/Z I
(PA6)
IO/Z I
(PA7)
IO/Z I
(PB0)
IO/Z I
(PB1)
IO/Z I
(PB2)
IO/Z I
(PB3)
IO/Z I
(PB4)
Multiplexed pin whose function is selected by: WAKEUP.7 and OEA.3
PA3 is a bidirecti onal IO port pin. WU2 is an alternate source for USB Wakeup, enabled
by WU2EN bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in suspend and WU2EN = 1, a transition on this pin starts up the oscil­lator and interrupts the 8051 to enable it to exit the suspend mode. Asserting this pin inhibits the chip from suspending, if WU2EN = 1.
Multiplexed pin whose function is selected by: IFCONFIG[1..0].
PA4 is a bidirecti onal IO port pin. FIFOADR0 is an input-only address select for the slave
FIFOs connected to FD[7..0] or FD[15..0]. Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirecti onal IO port pin. FIFOADR1 is an input-only address select for the slave
FIFOs connected to FD[7..0] or FD[15..0]. Multiplexed pin whose function is selected by the
IFCONFIG[1:0] bits.
PA6 is a bidirecti onal IO port pin. PKTEND is an input used to commit the FIFO packet
data to the endpoint and whose polarity is program­mable via FIFOPINPOLAR.5.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and PORTACFG.7 bits.
PA7 is a bidirecti onal IO port pin. FLAGD is a programmable slave-FIFO output status
flag signal. SLCS# gates all other slave FIFO enable/strobes
Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0].
PB0 is a bidirectional IO port pin. FD[0] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0].
PB1 is a bidirectional IO port pin. FD[1] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0].
PB2 is a bidirectional IO port pin. FD[2] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0].
PB3 is a bidirectional IO port pin. FD[3]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0].
PB4 is a bidirectional IO port pin. FD[4] is the bidirectional FIFO/GPIF data bus.
Document #: 38-08032 Rev. *L Page 23 of 62
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
Table 11. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
55 45 30 23 5G PB5 or
56 46 31 24 5F PB6 or
57 47 32 25 6H PB7 or
PORT C
72 57 PC0 or
73 58 PC1 or
74 59 PC2 or
75 60 PC3 or
76 61 PC4 or
77 62 PC5 or
78 63 PC6 or
79 64 PC7 or
PORT D
102 80 52 45 8A PD0 or
103 81 53 46 7A PD1 or
56
SSOP
56
QFN
56 VF-
BGA
Name Type Default Description
FD[5]
FD[6]
FD[7]
GPIFADR0
GPIFADR1
GPIFADR2
GPIFADR3
GPIFADR4
GPIFADR5
GPIFADR6
GPIFADR7
FD[8]
FD[9]
IO/Z I
(PB5)
IO/Z I
(PB6)
IO/Z I
(PB7)
IO/Z I
(PC0)
IO/Z I
(PC1)
IO/Z I
(PC2)
IO/Z I
(PC3)
IO/Z I
(PC4)
IO/Z I
(PC5)
IO/Z I
(PC6)
IO/Z I
(PC7)
IO/Z I
(PD0)
IO/Z I
(PD1)
Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0].
PB5 is a bidirectional IO port pin. FD[5] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0].
PB6 is a bidirectional IO port pin. FD[6] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0].
PB7 is a bidirectional IO port pin. FD[7] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by PORTCCFG.0
PC0 is a bidirectional IO port pin. GPIFADR0 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.1
PC1 is a bidirectional IO port pin. GPIFADR1 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.2
PC2 is a bidirectional IO port pin. GPIFADR2 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.3
PC3 is a bidirectional IO port pin. GPIFADR3 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.4
PC4 is a bidirectional IO port pin. GPIFADR4 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.5
PC5 is a bidirectional IO port pin. GPIFADR5 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.6
PC6 is a bidirectional IO port pin. GPIFADR6 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.7
PC7 is a bidirectional IO port pin. GPIFADR7 is a GPIF address output pin.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus.
Document #: 38-08032 Rev. *L Page 24 of 62
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Table 11. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
104 82 54 47 6B PD2 or
105 83 55 48 6A PD3 or
121 95 56 49 3B PD4 or
122 96 1 50 3A PD5 or
123 97 2 51 3C PD6 or
124 98 3 52 2A PD7 or
Port E
108 86 PE0 or
109 87 PE1 or
110 88 PE2 or
111 89 PE3 or
56
SSOP
56
QFN
56 VF-
BGA
Name Type Default Description
FD[10]
FD[11]
FD[12]
FD[13]
FD[14]
FD[15]
T0OUT
T1OUT
T2OUT
RXD0OUT
IO/Z I
(PD2)
IO/Z I
(PD3)
IO/Z I
(PD4)
IO/Z I
(PD5)
IO/Z I
(PD6)
IO/Z I
(PD7)
IO/Z I
(PE0)
IO/Z I
(PE1)
IO/Z I
(PE2)
IO/Z I
(PE3)
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[10] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[11] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[12] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[13] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[14] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[15] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the PORTECFG.0 bit.
PE0 is a bidirectional IO port pin. T0OUT is an active-HIGH signal from 8051
Timer-counter0. T0OUT outputs a high level for one CLKOUT clock cycle when Timer0 overflows. If Timer0 is operated in Mode 3 (two separate timer/counters), T0OUT is active when the low byte timer/counter overflows.
Multiplexed pin whose function is selected by the PORTECFG.1 bit.
PE1 is a bidirectional IO port pin. T1OUT is an active-HIGH signal from 8051
Timer-counter1. T1OUT outputs a high level for one CLKOUT clock cycle when Timer1 overflows. If Timer1 is operated in Mode 3 (two separate timer/counters), T1OUT is active when the low byte timer/counter overflows.
Multiplexed pin whose function is selected by the PORTECFG.2 bit.
PE2 is a bidirectional IO port pin. T2OUT is the active-HIGH output signal from 8051
Timer2. T2OUT is active (HIGH) for one clock cycle when Timer/Counter 2 overflows.
Multiplexed pin whose function is selected by the PORTECFG.3 bit.
PE3 is a bidirectional IO port pin. RXD0OUT is an active-HIGH signal from 8051 UART0.
If RXD0OUT is selected and UART0 is in Mode 0, this pin provides the output data for UART0 only when it is in sync mode. Otherwise it is a 1.
Document #: 38-08032 Rev. *L Page 25 of 62
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Table 11. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
112 90 PE4 or
113 91 PE5 or
114 92 PE6 or
115 93 PE7 or
56
SSOP
56
QFN
56 VF-
BGA
Name Type Default Description
RXD1OUT
INT6
T2EX
GPIFADR8
IO/Z I
(PE4)
IO/Z I
(PE5)
IO/Z I
(PE6)
IO/Z I
(PE7)
Multiplexed pin whose function is selected by the PORTECFG.4 bit.
PE4 is a bidirectional IO port pin. RXD1OUT is an active-HIGH output from 8051 UART1.
When RXD1OUT is selected and UART1 is in Mode 0, this pin provides the output data for UART1 only when it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.
Multiplexed pin whose function is selected by the PORTECFG.5 bit.
PE5 is a bidirectional IO port pin. INT6 is the 8051 INT6 interrupt request input signal. The
INT6 pin is edge-sensitive, active HIGH. Multiplexed pin whose function is selected by the
PORTECFG.6 bit.
PE6 is a bidirectional IO port pin. T2EX is an active-HIGH input signal to the 8051 Timer2.
T2EX reloads timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set in T2CON.
Multiplexed pin whose function is selected by the PORTECFG.7 bit.
PE7 is a bidirectional IO port pin. GPIFADR8 is a GPIF address output pin.
4 3 8 1 1A RDY0 or
SLRD
5 4 9 2 1B RDY1 or
SL WR
6 5 RDY2 Input N/A RDY2 is a GPIF input signal. 7 6 RDY3 Input N/A RDY3 is a GPIF input signal. 8 7 RDY4 Input N/A RDY4 is a GPIF input signal. 9 8 RDY5 Input N/A RDY5 is a GPIF input signal.
69 54 36 29 7H CTL0 or
FLAGA
Input N/A Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
RDY0 is a GPIF input signal. SLRD is the input-only read strobe with programmable
polarity (FIFOPINPOLAR.3) for the slave FIFOs connected to FD[7..0] or FD[15..0].
Input N/A Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
RDY1 is a GPIF input signal. SLWR is the input-only write strobe with programmable
polarity (FIFOPINPOLAR.2) for the slave FIFOs connected to FD[7..0] or FD[15..0].
O/Z H Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status
flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins.
Document #: 38-08032 Rev. *L Page 26 of 62
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Table 11. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
70 55 37 30 7G CTL1 or
71 56 38 31 8H CTL2 or
66 51 CTL3 O/Z H CTL3 is a GPIF control output. 67 52 CTL4 Output H CTL4 is a GPIF control output. 98 76 CTL5 Output H CTL5 is a GPIF control output. 32 26 20 13 2G IFCLK on
28 22 INT4 Input N/A INT4 is the 8051 INT4 interrupt request input signal. The
106 84 INT5# Input N/A INT5# is the 8051 INT5 interrupt request input signal.
31 25 T2 Input N/A T2 is the active-HIGH T2 input signal to 8051 Timer2,
30 24 T1 Input N/A T1 is the active-HIGH T1 signal for 8051 Timer1, which
29 23 T0 Input N/A T0 is the active-HIGH T0 signal for 8051 Timer0, which
53 43 RXD1 Input N/A RXD1is an active-HIGH input signal for 8051 UART1,
52 42 TXD1 Output H TXD1is an active-HIGH output pin from 8051 UART1,
51 41 RXD0 Input N/A RXD0 is the active-HIGH RXD0 input to 8051 UART0,
56
SSOP
56
QFN
56 VF-
BGA
Name Type Default Description
O/Z H Multiplexed pin whose function is selected by the
FLAGB
FLAGC
CY7C68013A and CY7C68014A
-----------------­PE0 on CY7C68015A and CY7C68016A
O/Z H Multiplexed pin whose function is selected by the
IO/Z
----------­IO/Z
----------
following bits: IFCONFIG[1..0].
CTL1 is a GPIF control output. FLAGB is a programmable slave-FIFO output status
flag signal. Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
following bits: IFCONFIG[1..0].
CTL2 is a GPIF control output. FLAGC is a programmable slave-FIFO output status
flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
Z
Interface Clock, used for synchronously clocking data into or out of the slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals and GPIF . When internal clocking is used (IFCONFIG.7= 1) the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether internally or externally sourced, by setting the bit IFCONFIG.4 =1.
----------------------------------------------------------------------­PE0 is a bidirectional IO port pin.
I
INT4 pin is edge-sensitive, active HIGH.
The INT5 pin is edge-sensitive, active LOW.
which provides the input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2 does not use this pin.
provides the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use this bit.
provides the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use this bit.
which provides data to the UART in all modes.
which provides the output clock in sync mode, and the output data in async mode.
which provides data to the UART in all modes.
Document #: 38-08032 Rev. *L Page 27 of 62
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Table 11. FX2LP Pin Descriptions (continued)
128
TQFP
100
TQFP
56
SSOP
56
QFN
56 VF-
BGA
Name Type Default Description
50 40 TXD0 Output H TXD0 is the active-HIGH TXD0 output from 8051
UART0, which provides the output clock in sync mode,
and the output data in async mode. 42 CS# Output H CS# is the active-LOW chip select for external memory. 41 32 WR# Output H WR# is the active-LOW write strobe output for external
memory. 40 31 RD# Output H RD# is the active-LOW read strobe output for external
memory. 38 OE# Output H OE# is the active-LOW output enable for external
memory.
33 27 21 14 2H Reserved Input N/A Reserved. Connect to ground.
101 79 51 44 7B WAKEUP Input N/A USB Wakeup. If the 8051 is in suspend, asserting this
pin starts up the oscillator and interrupts the 8051 to
enable it to exit the suspend mode. Holding WAKEUP
asserted inhibits the EZ-USB
®
chip from suspending.
This pin has programmable polarity (WAKEUP.4). 36 29 22 15 3F SCL OD Z Clock for the I
resistor, even if no I 37 30 23 16 3G SDA OD Z Data for I
with a 2.2K resistor, even if no I
2
C interface. Connect to VCC with a 2.2K
2
C peripheral is attached.
2
C-compatible interface. Connect to VCC
2
C-compatible
peripheral is attached.
216555AVCC PowerN/AVCC. Connect to 3.3V power source. 26 20 18 11 1G VCC Power N/A VCC. Connect to 3.3V power source. 43 33 24 17 7E VCC Power N/A VCC. Connect to 3.3V power source. 48 38 VCC Power N/A VCC. Connect to 3.3V power source. 64 49 34 27 8E VCC Power N/A VCC. Connect to 3.3V power source. 68 53 VCC Power N/A VCC. Connect to 3.3V power source. 81 66 39 32 5C VCC Power N/A VCC. Connect to 3.3V power source.
100 78 50 43 5B VCC Power N/A VCC. Connect to 3.3V power source. 107 85 VCC Power N/A VCC. Connect to 3.3V power source.
3 2 7 56 4B GND Ground N/A Ground. 27 21 19 12 1H GND Ground N/A Ground. 49 39 GND Ground N/A Ground. 58 48 33 26 7D GND Ground N/A Ground. 65 50 35 28 8D GND Ground N/A Ground. 80 65 GND Ground N/A Ground. 93 75 48 41 4C GND Ground N/A Ground.
1 16 94 GND Ground N/A Ground. 125 99 4 53 4A GND Ground N/A Ground.
14 13 NC N/A N/A No Connect. This pin must be left open. 15 14 NC N/A N/A No Connect. This pin must be left open. 16 15 NC N/A N/A No Connect. This pin must be left open.
Document #: 38-08032 Rev. *L Page 28 of 62
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5. Register Summary

FX2LP register bit definitions are described in the FX2LP TRM in greater detail.
Table 12. FX2LP Register Summary
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
E400 128 WAVEDATA GPIF Waveform
E480 128 reserved
E50D GPCR2 General Purpose Configu-
E600 1 CPUCS CPU Cont r o l & Status 0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr E601 1 IFCONFIG Interface Configuration
E602 1 PINFLAGSAB
E603 1 PINFLAGSCD
E604 1 FIFORESET
E605 1 BREAKPT Breakpoint Control 0 0 0 0 BREAK BPPULSE BPEN 0 00000000 rrrrbbbr E606 1 BPADDRH Breakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW E607 1 BPADDRL Breakpoint Address L A7 A6 A5 A4 A3 A2 A1 A0 xxxxxxxx RW E608 1 UART230 230 Kbaud internally
E609 1 FIFOPINPOLAR
E60A 1 REVID Chip Revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 RevA
E60B 1 REVCTL
E60C 1 GPIFHOLDAMOUNT MSTB Hold Time
E610 1 EP1OUTCFG Endpoint 1-OU T
E611 1 EP1INCFG Endpoint 1-IN
E612 1 EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 10100010 bbbbbrbb E613 1 EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 10100000 bbbbrrrr E614 1 EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 11100010 bbbbbrbb E615 1 EP8CFG Endpoint 8 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 11100000 bbbbrrrr
E618 1 EP2FIFOCFG
E619 1 EP4FIFOCFG
E61A 1 EP6FIFOCFG
E61B 1 EP8FIFOCFG
E61C 4 reserved E620 1 EP2AUTOINLENH
E621 1 EP2AUTOINLENL
E622 1 EP4AUTOINLENH
E623 1 EP4AUTOINLENL
E624 1 EP6AUTOINLENH
E625 1 EP6AUTOINLENL
E626 1 EP8AUTOINLENH
E627 1 EP8AUTOINLENL
E628 1 ECCCFG ECC Configuration 0 0 0 0 0 0 0 ECCM 00000000 rrrrrrrb E629 1 ECCRESET ECC Reset x x x x x x x x 00000000 W E62A 1 ECC1B0 ECC1 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R
GPIF Waveform Memories
GENERAL CONFIGURATION
UDMA
3 reserved
ENDPOINT CONFIGUR ATION
2 reserved
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
Descriptor 0, 1, 2, 3 data
ration Register 2
(Ports, GPIF , slave FIFOs) Slave FIFO FLAGA and
FLAGB Pin Configuration
Slave FIFO FLAGC and
FLAGD Pin Configuration Restore FIFOS to default
state
generated ref. clock Slave FIFO Interface pins
polarity
Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb
(for UDMA)
Configuration
Configuration
Endpoint 2 / slave FIFO configuration
Endpoint 4 / slave FIFO configuration
Endpoint 6 / slave FIFO configuration
Endpoint 8 / slave FIFO configuration
[11
Endpoint 2 AUTOIN
Packet Length H
[11]
Endpoint 2 AUTOIN Packet Length L
[11]
Endpoint 4 AUTOIN Packet Length H
[11]
Endpoint 4 AUTOIN Packet Length L
[11]
Endpoint 6 AUTOIN Packet Length H
[11]
Endpoint 6 AUTOIN Packet Length L
[11]
Endpoint 8 AUTOIN Packet Length H
[11]
Endpoint 8 AUTOIN Packet Length L
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
reserved reserved reserved FULL_SPEE
IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW
FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000 RW
FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0 00000000 RW
NAKALL 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
0 0 0 0 0 0 230UART1 230UART0 00000000 rrrrrrbb
0 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb
0 0 0 0 0 0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
D_ONLY
reserved reserved reserved reserved 00000000 R
00000001
R
Note
11.Read and writes to these registers may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
Document #: 38-08032 Rev. *L Page 29 of 62
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E62B 1 ECC1B1 ECC1 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 00000000 R E62C 1 ECC1B2 ECC1 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 00000000 R E62D 1 ECC2B0 ECC2 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R E62E 1 ECC2B1 ECC2 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 00000000 R E62F 1 ECC2B2 ECC2 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 0 0 00000000 R E630
1 EP2FIFOPFH
H.S. E630
F.S. E631
H.S. E631
F.S E632
H.S. E632
F.S E633
H.S. E633
F.S E634
H.S. E634
F.S E635
H.S. E635
F.S E636
H.S. E636
F.S E637
H.S. E637
F.S
1 EP2FIFOPFH
1 EP2FIFOPFL
1 EP2FIFOPFL
1 EP4FIFOPFH
1 EP4FIFOPFH
1 EP4FIFOPFL
1 EP4FIFOPFL
1 EP6FIFOPFH
1 EP6FIFOPFH
1 EP6FIFOPFL
1 EP6FIFOPFL
1 EP8FIFOPFH
1 EP8FIFOPFH
1 EP8FIFOPFL
1 EP8FIFOPFL
8 reserved
E640 1 EP2ISOINPKTS EP2 (if ISO) IN Packets
E641 1 EP4ISOINPKTS EP4 (if ISO) IN Packets
E642 1 EP6ISOINPKTS EP6 (if ISO) IN Packets
E643 1 EP8ISOINPKTS EP8 (if ISO) IN Packets
E644 4 reserved E648 1 INPKTEND E649 7 OUTPKTEND
INTERRUPTS
E650 1 EP2FIFOIE
E651 1 EP2FIFOIRQ
E652 1 EP4FIFOIE
E653 1 EP4FIFOIRQ
E654 1 EP6FIFOIE
E655 1 EP6FIFOIRQ
E656 1 EP8FIFOIE
E657 1 EP8FIFOIRQ
E658 1 IBNIE IN-BULK-NAK Interrupt
E659 1 IBNIRQ
E65A 1 NAKIE Endpoint Ping-NAK / IBN
E65B 1 NAKIRQ
E65C 1 USBIE USB Int Enables 0 EP0ACK HSGRANT URES SUSP SUTOK SOF SUDAV 00000000 RW
[11]
Endpoint 2 / slave FIFO Programmable Flag H
[11]
Endpoint 2 / slave FIFO Programmable Flag H
[11]
Endpoint 2 / slave FIFO Programmable Flag L
[11]
Endpoint 2 / slave FIFO Programmable Flag L
[11]
Endpoint 4 / slave FIFO Programmable Flag H
[11]
Endpoint 4 / slave FIFO Programmable Flag H
[11]
Endpoint 4 / slave FIFO Programmable Flag L
[11]
Endpoint 4 / slave FIFO Programmable Flag L
[11]
Endpoint 6 / slave FIFO Programmable Flag H
[11]
Endpoint 6 / slave FIFO Programmable Flag H
[11]
Endpoint 6 / slave FIFO Programmable Flag L
[11]
Endpoint 6 / slave FIFO Programmable Flag L
[11]
Endpoint 8 / slave FIFO Programmable Flag H
[11]
Endpoint 8 / slave FIFO Programmable Flag H
[11]
Endpoint 8 / slave FIFO Programmable Flag L
[11]
Endpoint 8 / slave FIFO Programmable Flag L
per frame (1-3)
per frame (1-3)
per frame (1-3)
per frame (1-3)
[11]
Force IN Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
[11]
Force OUT Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
[11]
Endpoint 2 slave FIFO Flag Interrupt Enable
[11,12]
Endpoint 2 slave FIFO Flag Interrupt Request
[11]
Endpoint 4 slave FIFO Flag Interrupt Enable
[11,12]
Endpoint 4 slave FIFO Flag Interrupt Request
[11]
Endpoint 6 slave FIFO Flag Interrupt Enable
[11,12]
Endpoint 6 slave FIFO Flag Interrupt Request
[11]
Endpoint 8 slave FIFO Flag Interrupt Enable
[11,12]
Endpoint 8 slave FIFO Flag Interrupt Request
[12]
[12]
Enable IN-BULK-NAK interrupt
Request
Interrupt Enable Endpoint Ping-NAK / IBN
Interrupt Request
DECIS PKTSTAT IN:PKTS[2]
OUT:PFC12
DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0 PFC9 IN:PKTS[2]
IN:PKTS[1] OUT:PFC11
IN:PKTS[0] OUT:PFC10
0 PFC9 PFC8 10001000 bbbbbrbb
OUT:PFC8
PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
IN:PKTS[1] OUT:PFC7
DECIS PKTSTAT 0 IN: PKTS[1]
IN:PKTS[0] OUT:PFC6
PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
OUT:PFC10
IN: PKTS[0] OUT:PFC9
0 0 PFC8 10001000 bbrbbrrb
DECIS PKTSTAT 0 OUT:PFC10 OUT:PFC9 0 0 PFC8 10001000 bbrbbrrb
PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
IN: PKTS[1] OUT:PFC7
DECIS PKTSTAT IN:PKTS[2]
DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0 PFC9 IN:PKTS[2]
IN: PKTS[0] OUT:PFC6
PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
OUT:PFC12
IN:PKTS[1] OUT:PFC11
IN:PKTS[0] OUT:PFC10
0 PFC9 PFC8 00001000 bbbbbrbb
OUT:PFC8
PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
IN:PKTS[1] OUT:PFC7
DECIS PKTSTAT 0 IN: PKTS[1]
IN:PKTS[0] OUT:PFC6
PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
OUT:PFC10
IN: PKTS[0] OUT:PFC9
0 0 PFC8 00001000 bbrbbrrb
DECIS PKTSTAT 0 OUT:PFC10 OUT:PFC9 0 0 PFC8 00001000 bbrbbrrb
PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
IN: PKTS[1] OUT:PFC7
IN: PKTS[0] OUT:PFC6
PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrbb
AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrrr
AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrbb
AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrrr
0 0 0 0 EDGEPF PF EF FF 00000000 RW
0 0 0 0 0 PF EF FF 00000000 rrrrrbbb
0 0 0 0 EDGEPF PF EF FF 00000000 RW
0 0 0 0 0 PF EF FF 00000000 rrrrrbbb
0 0 0 0 EDGEPF PF EF FF 00000000 RW
0 0 0 0 0 PF EF FF 00000000 rrrrrbbb
0 0 0 0 EDGEPF PF EF FF 00000000 RW
0 0 0 0 0 PF EF FF 00000000 rrrrrbbb
0 0 EP8 EP6 EP4 EP2 EP1 EP0 00000000 RW
0 0 EP8 EP6 EP4 EP2 EP1 EP0 00xxxxxx rrbbbbbb
EP8 EP6 EP4 EP2 EP1 EP0 0 IBN 00000000 RW
EP8 EP6 EP4 EP2 EP1 EP0 0 IBN xxxxxx0x bbbbbbrb
10001000 bbbbbrbb
00001000 bbbbbrbb
Note
12.The register can only be reset, it cannot be set.
Document #: 38-08032 Rev. *L Page 30 of 62
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E65D 1 USBIRQ E65E 1 EPIE Endpoint Interrupt
E65F 1 EPIRQ
E660 1 GPIFIE E661 1 GPIFIRQ E662 1 USBERRIE USB Error Interrupt
E663 1 USBERRIRQ
E664 1 ERRCNTLIM USB Error counter and
E665 1 CLRERRCNT Clear Error Counter EC3:0 x x x x x x x x xxxxxxxx W E666 1 INT2IVEC Interrupt 2 (USB)
E667 1 INT4IVEC Interrupt 4 (slave FIFO &
E668 1 INTSET-UP Interrupt 2&4 setup 0 0 0 0 AV2EN 0 INT4SRC AV4EN 00000000 RW E669 7 reserved
E670 1 PORTACFG IO PORTA Alternate
E671 1 PORTCCFG IO PORTC Alternate
E672 1 PORTECFG IO PORTE Alternate
E673 4 reserved E677 1 reserved E678 1 I2CS I²C Bus
E679 1 I2DAT I²C Bus
E67A 1 I2CTL I²C Bus
E67B 1 XAUTODAT1 Autoptr1 MOVX access,
E67C 1 XAUTODAT2 Autoptr2 MOVX access,
E67D 1 UDMACRCH E67E 1 UDMACRCL E67F 1 UDMACRC-
E680 1 USBCS USB Control & Status HSM 0 0 0 DISCON NOSYNSOF RENUM SIGRSUME x0000000 rrrrbbbb E681 1 SUSPEND Put chip into suspend x x x x x x x x xxxxxxxx W E682 1 WAKEUPCS Wakeup Control & Status WU2 WU WU2POL WUPOL 0 DPEN WU2EN WUEN xx000101 bbbbrbbb E683 1 TOGCTL Toggle Con trol Q S R IO EP3 EP2 EP1 EP0 x0000000 rrrbbbbb E684 1 USBFRAMEH USB Frame count H 0 0 0 0 0 FC10 FC9 FC8 00000xxx R E685 1 USBFRAMEL USB Frame count L FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 xxxxxxxx R E686 1 MICROFRAME Microframe count, 0-7 0 0 0 0 0 MF2 MF1 MF0 00000xxx R E687 1 FNADDR USB Function address 0 FA6 FA5 FA4 FA3 FA2 FA1 FA0 0xxxxxxx R E688 2 reserved
E68A 1 EP0BCH E68B 1 EP0BCL E68C 1 reserved E68D 1 EP1OUTBC Endpoint 1 OUT Byte
E68E 1 reserved E68F 1 EP1INBC Endpoint 1 IN Byte Count 0 BC6 BC5 BC4 BC3 BC2 BC1 BC0 0xxxxxxx RW E690 1 EP2BCH E691 1 EP2BCL E692 2 reserved E694 1 EP4BCH E695 1 EP4BCL E696 2 reserved E698 1 EP6BCH E699 1 EP6BCL E69A 2 reserved E69C 1 EP8BCH
[12]
[12]
[11]
GPIF Interrupt Enable 0 0 0 0 0 0 GPIFWF GPIFDONE 00000000 RW
[11]
INPUT / OUTPUT
UDMA CRC
QUALIFIER USB CONTROL
ENDPOINTS
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
USB Interrupt Requests 0 EP0ACK HSGRANT URES SUSP SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb
Enables Endpoint Interrupt
Requests
GPIF Interrupt Request 0 0 0 0 0 0 GPIFWF GPIFDONE 000000xx RW
Enables
[12]
USB Error Interrupt Requests
limit
Autovector
GPIF) Autovector
Configuration
Configuration
Configuration
Control & Status
Data
Control
when APTREN=1
when APTREN=1
[11]
UDMA CRC MSB CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8 01001010 RW
[11]
UDMA CRC LSB CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 10111010 RW UDMA CRC Qualifier QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb
Endpoint 0 Byte Count H (BC15) (BC14) (BC13) (BC12) (BC11) (BC10) (BC9) (BC8) xxxxxxxx RW Endpoint 0 Byte Count L (BC7) BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
Count
Endpoint 2 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 00000xxx RW
Endpoint 2 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
Endpoint 4 Byte Count H 0 0 0 0 0 0 BC9 BC8 000000xx RW
Endpoint 4 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
Endpoint 6 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 00000xxx RW
Endpoint 6 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
Endpoint 8 Byte Count H 0 0 0 0 0 0 BC9 BC8 000000xx RW
EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 00000000 RW
EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 0 RW
ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 00000000 RW
ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 0000000x bbbbrrrb
EC3 EC2 EC1 EC0 LIMIT3 LIMIT2 LIMIT1 LIMIT0 xxxx0100 rrrrbbbb
0 I2V4 I2V3 I2V2 I2V1 I2V0 0 0 00000000 R
1 0 I4V3 I4V2 I4V1 I4V0 0 0 10000000 R
FLAGD SLCS 0 0 0 0 INT1 INT0 00000000 RW
GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW
GPIFA8 T2EX INT6 RXD1OUT RXD0OUT T2OUT T1OUT T0OUT 00000000 RW
START STOP LASTRD ID1 ID0 BERR ACK DONE 000xx000 bbbrrrrr
d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx RW
0 0 0 0 0 0 STOPIE 400KHZ 00000000 RW
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
0 BC6 BC5 BC4 BC3 BC2 BC1 BC0 0xxxxxxx RW
Document #: 38-08032 Rev. *L Page 31 of 62
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Table 12. FX2LP Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E69D 1 EP8BCL E69E 2 reserved E6A0 1 EP0CS Endpoint 0 Control and
E6A1 1 EP1OUTCS Endpoint 1 OUT Control
E6A2 1 EP1INCS Endpoint 1 IN Control and
E6A3 1 EP2CS Endpoint 2 Control and
E6A4 1 EP4CS Endpoint 4 Control and
E6A5 1 EP6CS Endpoint 6 Control and
E6A6 1 EP8CS Endpoint 8 Control and
E6A7 1 EP2FIFOFLGS Endpoint 2 slave FIFO
E6A8 1 EP4FIFOFLGS Endpoint 4 slave FIFO
E6A9 1 EP6FIFOFLGS Endpoint 6 slave FIFO
E6AA 1 EP8FIFOFLGS Endpoint 8 slave FIFO
E6AB 1 EP2FIFOBCH Endpoint 2 slave FIFO
E6AC 1 EP2FIFOBCL Endpoint 2 slave FIFO
E6AD 1 EP4FIFOBCH Endpoint 4 slave FIFO
E6AE 1 EP4FIFOBCL Endpoint 4 slave FIFO
E6AF 1 EP6FIFOBCH Endpoint 6 slave FIFO
E6B0 1 EP6FIFOBCL Endpoint 6 slave FIFO
E6B1 1 EP8FIFOBCH Endpoint 8 slave FIFO
E6B2 1 EP8FIFOBCL Endpoint 8 slave FIFO
E6B3 1 SUDPTRH Setup Data Pointer high
E6B4 1 SUDPTRL Setup Data Pointer low ad-
E6B5 1 SUDPTRCTL Setup Data Pointer Auto
2 reserved
E6B8 8 SET-UPDAT 8 bytes of se tup data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
E6C0 1 GPIFWFSELECT Waveform Selector SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0 FIFORD1 FIFORD0 11100100 RW E6C1 1 GPIFIDLECS GPIF Done, GPIF IDLE
E6C2 1 GPIFIDLECTL Inactive Bus, CTL states 0 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 11111111 RW E6C3 1 GPIFCTLCFG CTL Drive Type TRICTL 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 00000000RW E6C4 1 GPIFADRH E6C5 1 GPIFADRL
E6C6 1 FLOWSTATE Flowstate Enable and
E6C7 1 FLOWLOGIC Flowstate Logic LFUNC1 LFUNC0 TERMA2 TERMA1 TERMA0 TERMB2 TERMB1 TERMB0 00000000 RW E6C8 1 FLOWEQ0CTL CTL-Pin States in
E6C9 1 FLOWEQ1CTL CTL-Pin States in Flow-
E6CA 1 FLOWHOLDOFF Holdoff Configuration HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0HOSTATE HOCTL2 HOCTL1 HOCTL0 00010010 RW
[11]
GPIF
FLOWSTATE
Endpoint 8 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
Status
and Status
Status
Status
Status
Status
Status
Flags
Flags
Flags
Flags
total byte count H
total byte count L
total byte count H
total byte count L
total byte count H
total byte count L
total byte count H
total byte count L
address byte
dress byte
Mode
SET-UPDAT[0] = bmRequestType
SET-UPDAT[1] = bmRequest
SET-UPDA T[2:3] = wVal­ue
SET-UPDAT[4:5] = wInd­ex
SET-UPDA T[6:7] = wLength
drive mode
[11]
GPIF Address H 0 0 0 0 0 0 0 GPIFA8 00000000 RW
[11]
GPIF Address L GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW
Selector
Flowstate (when Logic = 0)
state (when Logic = 1)
HSNAK 0 0 0 0 0 BUSY STALL 10000000 bbbbbbrb
0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb
0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb
0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL 00101000 rrrrrrrb
0 0 NPAK1 NPAK0 FULL EMPTY 0 STALL 00101000 rrrrrrrb
0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL 00000100 rrrrrrrb
0 0 NPAK1 NPAK0 FULL EMPTY 0 STALL 00000100 rrrrrrrb
0 0 0 0 0 PF EF FF 00000010 R
0 0 0 0 0 PF EF FF 00000010 R
0 0 0 0 0 PF EF FF 00000110 R
0 0 0 0 0 PF EF FF 00000110 R
0 0 0 BC12 BC11 BC10 BC9 BC8 00000000 R
BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
0 0 0 0 0 BC10 BC9 BC8 00000000 R
BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
0 0 0 0 BC11 BC10 BC9 BC8 00000000 R
BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
0 0 0 0 0 BC10 BC9 BC8 00000000 R
BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
A7 A6 A5 A4 A3 A2 A1 0 xxxxxxx0 bbbbbbbr
0 0 0 0 0 0 0 SDPAUTO 00000001 RW
DONE 0 0 0 0 0 0 IDLEDRV 10000000 RW
FSE 0 0 0 0 FS2 FS1 FS0 00000000 brrrrbbb
CTL0E3 CTL0E2 CTL0E1/
CTL0E3 CTL0E2 CTL0E1/
CTL5
CTL5
CTL0E0/ CTL4
CTL0E0/ CTL4
CTL3 CTL2 CTL1 CTL0 00000000 RW
CTL3 CTL2 CTL1 CTL0 00000000 RW
Document #: 38-08032 Rev. *L Page 32 of 62
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Table 12. FX2LP Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E6CB 1 FLOWSTB Flowstate Strobe
E6CC 1 FLOWSTBEDGE Flowstate Rising/Falling
E6CD 1 FLOWSTBPERIOD Master-Strobe Half-Period D7 D6 D5 D4 D3 D2 D1 D0 00000010 RW E6CE 1 GPIFTCB3
E6CF 1 GPIFTCB2
E6D0 1 GPIFTCB1
E6D1 1 GPIFTCB0
2 reserved 00000000 RW
reserved
E6D2 1 EP2GPIFFLGSEL
E6D3 1 EP2GPIFPFSTOP Endpoint 2 GPIF stop
E6D4 1 EP2GPIFTRIG
E6DA 1 EP4GPIFFLGSEL
E6DB 1 EP4GPIFPFSTOP Endpoint 4 GPIF stop
E6DC 1 EP4GPIFTRIG
E6E2 1 EP6GPIFFLGSEL
E6E3 1 EP6GPIFPFSTOP Endpoint 6 GPIF stop
E6E4 1 EP6GPIFTRIG
E6EA 1 EP8GPIFFLGSEL
E6EB 1 EP8GPIFPFSTOP Endpoint 8 GPIF stop
E6EC 1 EP8GPIFTRIG
E6F0 1 XGPIFSGLDATH GPIF Data H
E6F1 1 XGPIFSGLDATLX Read/Write GPIF Data L &
E6F2 1 XGPIFSGLDATL-
E6F3 1 GPIFREADYCFG Internal RDY, Sync/Async,
reserved
3 reserved
reserved reserved
3 reserved
reserved reserved
3 reserved
reserved reserved
3 reserved
NOX
Configuration
Edge Configuration
[11]
GPIF Transaction Count Byte 3
[11]
GPIF Transaction Count Byte 2
[11]
GPIF Transaction Count Byte 1
[11]
GPIF Transaction Count Byte 0
[11]
Endpoint 2 GPIF Flag select
transaction on prog. flag
[11]
Endpoint 2 GPIF Trigger x x x x x x x x xxxxxxxx W
[11]
Endpoint 4 GPIF Flag select
transaction on GPIF Flag
[11]
Endpoint 4 GPIF Trigger x x x x x x x x xxxxxxxx W
[11]
Endpoint 6 GPIF Flag select
transaction on prog. flag
[11]
Endpoint 6 GPIF Trigger x x x x x x x x xxxxxxxx W
[11]
Endpoint 8 GPIF Flag select
transaction on prog. flag
[11]
Endpoint 8 GPIF Trigger x x x x x x x x xxxxxxxx W
(16-bit mode only)
trigger transaction Read GPIF Data L, no
transaction trigger
RDY pin states
SLAVE RDYASYNC CTLTOGL SUSTAIN 0 MSTB2 MSTB1 MSTB0 00100000 RW
0 0 0 0 0 0 FALLING RISING 00000001 rrrrrrbb
TC31 TC30 TC29 TC28 TC27 TC26 TC25 TC24 00000000 RW
TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000 RW
TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 00000000 RW
TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 00000001 RW
0 0 0 0 0 0 FS1 FS0 00000000 RW
0 0 0 0 0 0 0 FIFO2FLAG 00000000 RW
0 0 0 0 0 0 FS1 FS0 00000000 RW
0 0 0 0 0 0 0 FIFO4FLAG 00000000 RW
0 0 0 0 0 0 FS1 FS0 00000000 RW
0 0 0 0 0 0 0 FIFO6FLAG 00000000 RW
0 0 0 0 0 0 FS1 FS0 00000000 RW
0 0 0 0 0 0 0 FIFO8FLAG 00000000 RW
D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
INTRDY SAS TCXRDY5 0 0 0 0 0 00000000 bbbrrrrr
E6F4 1 GPIFREADYSTAT GPIF Ready Status 0 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 00xxxxxx R E6F5 1 GPIFABORT Abort GPIF Waveforms x x x x x x x x xxxxxxxx W E6F6 2 reserved
E740 64 EP0BUF EP0-IN/-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW E780 64 EP10UTBUF EP1-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW E7C0 64 EP1INBUF EP1-IN buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW E800 2048 reserved RW F000 1024 EP2FIFOBUF 512/1024 byte EP 2 / slave
F400 512 EP4FIFOBUF 512 byte EP 4 / slave FIFO
F600 512 reserved F800 1024 EP6FIFOBUF 512/1024 byte EP 6 / slave
FC00 512 EP8FIFOBUF 512 byte EP 8 / slave FIFO
FE00 512 reserved
Document #: 38-08032 Rev. *L Page 33 of 62
ENDPOINT BUFFERS
FIFO buffer (IN or OUT)
buffer (IN or OUT)
FIFO buffer (IN or OUT)
buffer (IN or OUT)
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
[+] Feedback [+] Feedback
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access xxxx I²C Configuration Byte 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx
Special Function Registers (SFRs)
80 1 IOA
[13]
Port A (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW 81 1 SP Stack Pointer D7 D6 D5 D4 D3 D2 D1 D0 00000111 RW 82 1 DPL0 Data Pointer 0 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW 83 1 DPH0 Data Pointer 0 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW 84 1 DPL1 85 1 DPH1 86 1 DPS
[13]
[13]
[13]
Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
Data Pointer 1 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
Data Pointer 0/1 select 0 0 0 0 0 0 0 SEL 00000000 RW 87 1 PCON Power Control SMOD0 x 1 1 x x x IDLE 00110000 RW 88 1 TCON Timer/Counter Control
89 1 TMOD Timer/Counter Mode
(bit addressable)
Control
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 RW
GATE CT M1 M0 GATE CT M1 M0 00000000 RW
8A 1 TL0 Timer 0 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW 8B 1 TL1 Timer 1 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW 8C 1 TH0 Timer 0 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW 8D 1 TH1 Timer 1 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW 8E 1 CKCON 8F 1 reserved 90 1 IOB 91 1 EXIF 92 1 MPAGE
[13]
[13]
[13]
[13]
Clock Control x x T2M T1M T0M MD2 MD1 MD0 00000001 RW
Port B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
External Interrupt Flag(s) IE5 IE4 I²CINT USBNT 1 0 0 0 00001000 RW
Upper Addr Byte of MOVX
using @R0 / @R1
A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
93 5 reserved 98 1 SCON0 Serial Port 0 Control
99 1 SBUF0 Serial Port 0 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW 9A 1 AUTOPTRH1 9B 1 AUTOPTRL1 9C 1 reserved 9D 1 AUTOPTRH2 9E 1 AUTOPTRL2 9F 1 reserved A0 1 IOC A1 1 INT2CLR A2 1 INT4CLR
[13]
[13] [13]
(bit addressable)
[13]
Autopointer 1 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
[13]
Autopointer 1 Address L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
[13]
Autopointer 2 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
[13]
Autopointer 2 Address L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
Port C (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
Interrupt 2 clear x x x x x x x x xxxxxxxx W
Interrupt 4 clear x x x x x x x x xxxxxxxx W
SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00000000 RW
A3 5 reserved A8 1 IE Interrupt Enable
A9 1 reserved AA 1 EP2468STAT
AB 1 EP24FIFOFLGS
AC 1 EP68FIFOFLGS
[13]
[13]
AD 2 reserved AF 1 AUTOPTRSETUP B0 1 IOD B1 1 IOE
B2 1 OEA B3 1 OEB B4 1 OEC B5 1 OED B6 1 OEE
[13]
[13]
[13] [13] [13] [13] [13]
(bit addressable)
[13]
Endpoint 2,4,6,8 status
flags
Endpoint 2,4 slave FIFO
status flags
Endpoint 6,8 slave FIFO
status flags
[13]
Autopointer 1&2 setup 0 0 0 0 0 APTR2INC APTR1INC APTREN 00000110 RW
Port D (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
Port E
(NOT bit addressable)
Port A Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
Port B Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
Port C Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
Port D Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
Port E Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00000000 RW
EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E 01011010 R
0 EP4PF EP4EF EP4FF 0 EP2PF EP2EF EP2FF 00100010 R
0 EP8PF EP8EF EP8FF 0 EP6PF EP6EF EP6FF 01100110 R
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
B7 1 reserved B8 1 IP Interrupt Priority (bit ad-
B9 1 reserved BA 1 EP01STAT
BB 1 GPIFTRIG
[13, 11]
BC 1 reserved BD 1 GPIFSGLDATH
Note
13.SFRs not part of the standard 8051 architecture.
dressable)
[13]
Endpoint 0&1 Status 0 0 0 0 0 EP1INBSY EP1OUTBSYEP0BSY 00000000 R
Endpoint 2,4,6,8 GPIF
slave FIFO Trigger
[13]
GPIF Data H (16-bit mode
only)
1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 10000000 RW
DONE 0 0 0 0 RW EP1 EP0 10000xxx brrrrbbb
D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW
14.If no EEPROM is detected by the SIE then the default is 00000000.
n/a
[14]
Document #: 38-08032 Rev. *L Page 34 of 62
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Table 12. FX2LP Register Summary (continued)
r = read-only bit w = write-only bit b = both read/write bit
R = all bits read-only W = all bits write-only
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access BE 1 GPIFSGLDATLX BF 1 GPIFSGLDATL-
C0 1 SCON1
C1 1 SBUF1 C2 6 reserved C8 1 T2CON T imer/Counter 2 Control
C9 1 reserved CA 1 RCAP2L Capture for Timer 2, au-
CB 1 RCAP2H Capture for Timer 2, au-
CC 1 TL2 Timer 2 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW CD 1 TH2 Timer 2 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW CE 2 reserved D0 1 PSW Program Status Word (bit
D1 7 reserved D8 1 EICON D9 7 reserved E0 1 ACC Accumulato r (bit address-
E1 7 reserved E8 1 EIE
E9 7 reserved F0 1 B B (bit addr essable) D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW F1 7 reserved F8 1 EIP
F9 7 reserved
NOX
[13]
[13]
[13]
[13]
GPIF Data L w/ Trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
GPIF Data L w/ No TriggerD7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
[13]
[13]
[13]
Serial Port 1 Control (bit
addressable)
Serial Port 1 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
(bit addressable)
to-reload, up-counter
to-reload, up-counter
addressable)
External Interrupt Control SMOD1 1 ERESI RESI INT6 0 0 0 01000000 RW
able)
External Interrupt En-
able(s)
External Interrupt Priority
Control
SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00000000 RW
TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 00000000 RW
D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
CY AC F0 RS1 RS0 OV F1 P 00000000 RW
D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
1 1 1 EX6 EX5 EX4 EI²C EUSB 11100000 RW
1 1 1 PX6 PX5 PX4 PI²C PUSB 11100000 RW
Document #: 38-08032 Rev. *L Page 35 of 62
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6. Absolute Maximum Ratings

Note
15.Do not power IO with chip power off.
Storage Temperature..................................................................................................... .. ..............................................65°C to +150°C
Ambient Temperature with Power Supplied (Commercial)................................................................................................0°C to +70°C
Ambient Temperature with Power Supplied (Industrial).............................................................................................. –40°C to +105°C
Supply Voltage to Ground Potential................................................................................................................................–0.5V to +4.0V
DC Input Voltage to Any Input Pin
DC Voltage Applied to Outputs in High Z State.................................................................................................... –0.5V to VCC + 0.5V
Power Dissipation................................................................................................................................... ... ................................300 mW
Static Disc harge Voltage............................................................................ ... ..............................................................................>2000V
Max Output Current, per IO port...................................................................................................................................................10 mA
Max Output Current, all five IO ports (128- and 100-pin packages).............................................................................................50 mA
[15]
............................................................................................................................................5.25V

7. Operating Conditions

TA (Ambient Temperature Under Bias) Commercial.................................. ....................................................................... 0°C to +70°C
T
(Ambient Temperature Under Bias) Industrial.........................................................................................................–40°C to +105°C
A
Supply Voltage............................................................................................................................... ... ..........................+3.00V to +3.60V
Ground Voltage...................................................... .. .......................................... .................................................................................0V
F
(Oscillator or Crystal Frequency)........................................... ... .. .......................................24 MHz ± 100 ppm, Parallel Resonant
OSC

8. Thermal Characteristics

The following table displays the thermal characteristics of various packages:
Table 13. Thermal Characteristics
Package
56 SSOP 70 24.4 23.3 47.7 100 TQFP 70 11.9 34.0 45.9 128 TQFP 70 15.5 27.7 43.2 56 QFN 70 10.6 14.6 25.2 56 VFBGA 70 30.9 27.7 58.6
Ambient Temperature
(°C)
θa
θJc
Junction to Case
Temperature
(°C/W)
θCa
Case to Ambient
Temperature
(°C/W)
Junction to Ambient Temperature
θJa
θJc + θCa
(°C/W)
The Junction Te mperature where, P = Power
θJa = Junction to Ambient T emperature (θJc + θCa) θa = Ambient Temperature (70 C)
The Case Temp erature where, P = Power
θCa = Case to Ambient Temperature θa = Ambient Temperature (70 C)
Document #: 38-08032 Rev. *L Page 36 of 62
θj, can be calculated using the following equation: θj = P*θJa + θa
θc, can be calculated using the following equation: θc = P*θCa + θa
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9. DC Characteristics

Note
16.Measured at Max VCC, 25°C.
Table 14. DC Characteristics
Parameter Description Conditions Min Typ Max Unit
VCC Supply V oltage 3.00 3.3 3.60 V VCC Ramp Up 0 to 3.3V 200 μs V
IH
V
IL
V
IH_X
V
IL_X
I
I
V
OH
V
OL
I
OH
I
OL
C
IN
I
SUSP
I
CC
T
RESET
Input HIGH Voltage 2 5.25 V Input LOW Voltage –0.5 0.8 V Crystal Input HIGH Vo ltage 2 5.25 V Crystal Input LOW Voltage –0.5 0.8 V Input Leakage Current 0< VIN < VCC ±10 μA Output Voltage HIGH I Output LOW Voltage I
= 4 mA 2.4 V
OUT
= –4 mA 0.4 V
OUT
Output Current HIGH 4mA Output Current LOW 4mA Input Pin Capacitance Except D+/D– 10 pF
D+/D– 15 pF Suspend Current Conne cted 300 380 CY7C68014/CY7C68016 Disconnected 100 150 Suspend Current Connected 0.5 1.2 CY7C68013/CY7C68015 Disconnected 0.3 1.0
[16]
[16] [16] [16]
Supply Current 8051 running, connected to USB HS 50 85 mA
8051 running, connected to USB FS 35 65 mA Reset Time after Valid Power VCC min = 3.0V 5.0 mS Pin Reset after powered on 200 μS
μA μA
mA mA

9.1 USB Transceiver

USB 2.0 compliant in full-speed and high-speed modes.

10. AC Electrical Characteristics

10.1 USB Transceiver

USB 2.0 compliant in full-speed and high-speed modes.
Document #: 38-08032 Rev. *L Page 37 of 62
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10.2 Program Memory Read

t
CL
t
DH
t
SOEL
t
SCSL
PSEN#
D[7..0]
OE#
A[15..0]
CS#
t
STBL
data in
t
ACC1
t
AV
t
STBH
t
AV
CLKOUT
[17]
[18]
Notes
17.CLKOUT is shown with positive polarity.
18.t
ACC1
is computed from the above parameters as follows:
t
ACC1
(24 MHz) = 3*tCL – tAV – t
DSU
= 106 ns
t
ACC1
(48 MHz) = 3*tCL – tAV – t
DSU
= 43 ns.
Figure 12. Program Memory Read Timing Diagram
Table 15. Program Memory Read Parameters
Parameter Description Min Typ Max Unit Notes
t
CL
t
AV
t
STBL
t
STBH
t
SOEL
t
SCSL
t
DSU
t
DH
1/CLKOUT Frequency 20.83 ns 48 MHz
41.66 ns 24 MHz
83.2 ns 12 MHz Delay from Clock to Valid Address 0 10.7 ns Clock to PSEN Low 0 8 ns Clock to PSEN High 0 8 ns Clock to OE Low 11.1 ns Clock to CS Low 13 ns Data Setup to Clock 9.6 ns Data Hold Time 0 ns
Document #: 38-08032 Rev. *L Page 38 of 62
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10.3 Data Memory Read

data in
t
CL
A[15..0]
t
AV
t
AV
RD#
t
STBL
t
STBH
t
DH
D[7..0]
data in
t
ACC1
[19]
t
DSU
Stretch = 0
Stretch = 1
t
CL
A[15..0]
t
AV
RD#
t
DH
D[7..0]
t
ACC1
t
DSU
CS#
CS#
t
SCSL
OE#
t
SOEL
CLKOUT
[17]
CLKOUT
[17]
[19]
Figure 13. Data Memory Read Timing Diagram
Table 16. Data Memory Read Parameters
Parameter Description Min Typ Max Unit Notes
t
CL
t
AV
t
STBL
t
STBH
t
SCSL
t
SOEL
t
DSU
t
DH
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOP TR1 is only active while either RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is based on the stretch value
Note
Document #: 38-08032 Rev. *L Page 39 of 62
and t
19.t
ACC2
(24 MHz) = 3*tCL – tAV –t
t
ACC2
t
(48 MHz) = 3*tCL – tAV – t
ACC2
t
(24 MHz) = 5*tCL – tAV –t
ACC3
(48 MHz) = 5*tCL – tAV – t
t
ACC3
1/CLKOUT Frequency 20.83 ns 48 MHz
Delay from Clock to Valid Address 10.7 ns Clock to RD LOW 11 ns Clock to RD HIGH 11 ns Clock to CS LOW 13 ns
DSU
DSU
DSU
DSU
= 106 ns
= 43 ns
= 190 ns
= 86 ns.
Clock to OE LOW 11.1 ns Data Setup to Clock 9.6 ns Data Hold Time 0 ns
are computed from the above parameters as follows:
ACC3
41.66 ns 24 MHz
83.2 ns 12 MHz
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10.4 Data Memory Write

t
OFF1
CLKOUT
A[15..0]
WR#
t
AV
D[7..0]
t
CL
t
STBL
t
STBH
data out
t
OFF1
CLKOUT
A[15..0]
WR#
t
AV
D[7..0]
t
CL
data out
Stretch = 1
t
ON1
t
SCSL
t
AV
CS#
t
ON1
CS#
Figure 14. Data Memory Write Timing Diagram
Table 17. Data Memory Write Parameters
t
AV
t
STBL
t
STBH
t
SCSL
t
ON1
t
OFF1
Parameter Description Min Max Unit Notes
Delay from Clock to Valid Address 0 10.7 ns Clock to WR Pulse LOW 0 11.2 ns Clock to WR Pulse HIGH 0 11.2 ns Clock to CS Pulse LOW 13.0 ns Clock to Data Turn-on 0 13.1 ns Clock to Data Hold Time 0 13.1 ns
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is based on the stretch value.
Document #: 38-08032 Rev. *L Page 40 of 62
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10.5 PORTC Strobe Feature Timings

CLKOUT
WR#
t
CLKOUT
PORTC IS UPDATED
t
STBL
t
STBH
CLKOUT
t
CLKOUT
DATA MUST BE HELD FOR 3 CLK CYLCES
DATA CAN BE UPDATED BY EXTERNAL LOGIC
8051 READS PORTC
RD#
t
STBL
t
STBH
The RD# and WR# are present in the 100-pin ve rsion and the 128-pin package. In these 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from or writes to PORTC. This feature is enabled by setting PORTCSTB bit in CPUCS register.
The RD# and WR# strobes are asserted for two CLKOUT cycles when PORTC is accessed.
The WR# strobe is asserted two clock cycles after PORTC is updated and is active for two clock cycles after that, as shown in
Figure 15.
As for read, the value of PORTC three clock cycles before the assertion of RD# is the value that the 8051 reads in. The RD# is pulsed for 2 clock cycles after 3 clock cycles from the point when the 8051 has performed a read function on PORTC.
Figure 15. WR# Strobe Function when PORTC is Accessed by 8051
The RD# signal prompts the external logic to prepare the next data byte. Nothing gets sampled internally on assertion of the RD# signal itself, it is just a prefetch type signal to get the next data byte prepared. So, using it with that in mind easily meets the setup time to the next read.
The purpose of this pulsing of RD# is to allow the external peripheral to know that the 8051 is done reading PORTC and the data was latched into PORTC three CLKOUT cycles before asserting the RD# signal. After the RD# is pulsed, the external logic can update the data on PORTC.
Following is the timing diagram of the read and write strobing function on accessing PORTC. Refer to Section 10.3 and
Section 10.4 for details on propagation delay of RD# and WR#
signals.
Document #: 38-08032 Rev. *L Page 41 of 62
Figure 16. RD# Strobe Function when PORTC is Accessed by 8051
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10.6 GPIF Synchronous Signals

DATA(output)
t
XGD
IFCLK
RDY
X
DATA(input)
valid
t
SRY
t
RYH
t
IFCLK
t
SGD
CTL
X
t
XCTL
t
DAH
N
N+1
GPIFADR[8:0]
t
SGA
Figure 17. GPIF Synchronous Signals Timing Diagram
[20]
Table 18. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
[20, 21]
Parameter Description Min Max Unit
t
IFCLK
t
SRY
t
RYH
t
SGD
t
DAH
t
SGA
t
XGD
t
XCTL
Table 19. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
IFCLK Period 20.83 ns RDYX to Clock Setup Time 8.9 ns Clock to RDYX 0ns GPIF Data to Clock Setup Time 9.2 ns GPIF Data Hold Time 0 ns Clock to GPIF Address Propagation Delay 7.5 ns Clock to GPIF Data Output Propagation Delay 11 ns Clock to CTLX Output Propagation Delay 6.7 ns
[21]
Parameter Description Min. Max. Unit
t
IFCLK
t
SRY
t
RYH
t
SGD
t
DAH
t
SGA
t
XGD
t
XCTL
Notes
20.Dashed lines denote signals with programmable polarity.
21.GPIF asynchronous RDY
22.IFCLK must not exceed 48 MHz.
Document #: 38-08032 Rev. *L Page 42 of 62
IFCLK Period RDYX to Clock Setup Time 2.9 ns Clock to RDYX 3.7 ns GPIF Data to Clock Setup Time 3.2 ns GPIF Data Hold Time 4.5 ns Clock to GPIF Address Propagation Delay 11.5 ns Clock to GPIF Data Output Propagation Delay 15 ns Clock to CTLX Output Propagation Delay 10.7 ns
signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
x
[22]
20.83 200 ns
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10.7 Slave FIFO Synchronous Read

IFCLK
SLRD
FLAGS
SLOE
t
SRD
t
RDH
t
OEon
t
XFD
t
XFLG
DATA
t
IFCLK
N+1
t
OEoff
N
Figure 18. Slave FIFO Synchronous Read Timing Diagram
[20]
Table 20. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
[21]
Parameter Description Min Max Unit
t
IFCLK
t
SRD
t
RDH
t
OEon
t
OEoff
t
XFLG
t
XFD
Table 21. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
IFCLK Period 20.83 ns SLRD to Clock Setup Time 18.7 ns Clock to SLRD Hold Time 0 ns SLOE Turn-on to FIFO Data Valid 10.5 ns SLOE Turn-off to FIFO Data Hold 10.5 ns Clock to FLAGS Output Propagation Delay 9.5 ns Clock to FIFO Data Output Propagation Delay 11 ns
[21]
Parameter Description Min. Max. Unit
t
IFCLK
t
SRD
t
RDH
t
OEon
t
OEoff
t
XFLG
t
XFD
IFCLK Period 20.83 200 ns SLRD to Clock Setup Time 12.7 ns Clock to SLRD Hold Time 3.7 ns SLOE Turn-on to FIFO Data Valid 10.5 ns SLOE Turn-off to FIFO Data Hold 10.5 ns Clock to FLAGS Output Propagation Delay 13.5 ns Clock to FIFO Data Output Propagation Delay 15 ns
Document #: 38-08032 Rev. *L Page 43 of 62
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10.8 Slave FIFO Asynchronous Read

SLRD
FLAGS
t
RDpwl
t
RDpwh
SLOE
t
XFLG
t
XFD
DATA
t
OEon
t
OEoff
N+1
N
Note
23.Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Figure 19. Slave FIFO Asynchronous Read Timing Diagram
[20]
Table 22. Slave FIFO Asynchronous Read Parameters
[23]
Parameter Description Min Max Unit
t
RDpwl
t
RDpwh
t
XFLG
t
XFD
t
OEon
t
OEoff
SLRD Pulse Width LOW 50 ns SLRD Pulse Width HIGH 50 ns SLRD to FLAGS Output Propagation Delay 70 ns SLRD to FIFO Data Output Propagation Delay 15 ns SLOE Turn-on to FIFO Data Valid 10.5 ns SLOE Turn-off to FIFO Data Hold 10.5 ns
Document #: 38-08032 Rev. *L Page 44 of 62
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10.9 Slave FIFO Synchronous Write

Z
Z
t
SFDtFDH
DATA
IFCLK
SLWR
FLAGS
t
WRH
t
XFLG
t
IFCLK
t
SWR
N
Figure 20. Slave FIFO Synchronous Write Timing Diagram
[20]
Table 23. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
[21]
Parameter Description Min Max Unit
t
IFCLK
t
SWR
t
WRH
t
SFD
t
FDH
t
XFLG
Table 24. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK
IFCLK Period 20.83 ns SLWR to Clock Setup Time 10.4 ns Clock to SLWR Hold Time 0 ns FIFO Data to Clock Setup Time 9.2 ns Clock to FIFO Data Hold Time 0 ns Clock to FLAGS Output Propagation Time 9.5 ns
[21]
Parameter Description Min Max Unit
t
IFCLK
t
SWR
t
WRH
t
SFD
t
FDH
t
XFLG
IFCLK Period 20.83 200 ns SLWR to Clock Setup Time 12.1 ns Clock to SLWR Hold Time 3.6 ns FIFO Data to Clock Setup Time 3.2 ns Clock to FIFO Data Hold Time 4.5 ns Clock to FLAGS Output Propagation Time 13.5 ns
Document #: 38-08032 Rev. *L Page 45 of 62
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10.10 Slave FIFO Asynchronous Write

DATA
t
SFD
t
FDH
FLAGS
t
XFD
SLWR/SLCS#
t
WRpwh
t
WRpwl
SLWR
FLAGS
t
XFLG
IFCLK
PKTEND
t
SPE
t
PEH
Figure 21. Slave FIFO Asynchronous Write Timing Diagram
[20]
Table 25. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
[23]
Parameter Description Min Max Unit
t
WRpwl
t
WRpwh
t
SFD
t
FDH
t
XFD
SLWR Pulse LOW 50 ns SLWR Pulse HIGH 70 ns SL W R to FIFO DATA Setup Time 10 ns FIFO DATA to SLWR Hold Time 10 ns SLWR to FLAGS Output Propagation Delay 70 ns

10.11 Slave FIFO Synchronous Packet End Strobe

Figure 22. Slave FIFO Synchronous Packet End Strobe Timing Diagram
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Parameter Description Min Max Unit
t
IFCLK
t
SPE
t
PEH
t
XFLG
IFCLK Period 20.83 ns PKTEND to Clock Setup Time 14.6 ns Clock to PKTEND Hold Time 0 ns Clock to FLAGS Output Propagation Delay 9.5 ns
[20]
[21]
Table 27. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
[21]
Parameter Description Min Max Unit
t
IFCLK
t
SPE
t
PEH
t
XFLG
Document #: 38-08032 Rev. *L Page 46 of 62
IFCLK Period 20.83 200 ns PKTEND to Clock Setup Time 8.6 ns Clock to PKTEND Hold Time 2.5 ns Clock to FLAGS Output Propagation Delay 13.5 ns
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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
There is no specific timing requirement that should be met for
IFCLK
SLWR
DATA
t
IFCLK
>= t
SWR
>= t
WRH
X-2
PKTEND
X-3
t
FAH
t
SPE
t
PEH
FIFOADR
t
SFD
t
SFD
t
SFD
X-4
t
FDH
t
FDH
t
FDH
t
SFA
1
X
t
SFD
t
SFD
t
SFD
X-1
t
FDH
t
FDH
t
FDH
At least one IFCLK cycle
FLAGS
t
XFLG
PKTEND
t
PEpwl
t
PEpwh
asserting PKTEND pin to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or there­after. The setup time t
and the hold time t
SPE
must be met.
PEH
Although there are no specific timing requirements for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte or word packet. There is an additional timing requirement that needs to be met when the FIFO is configured to operate in auto mode and it is required to send two packets back to back: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte or word packet committed manually using the PKTEND pin. In this scenario, the us er must ensure to assert PKTEND at least one clock cycle after the rising edge that
Figure 23. Slave FIFO Synchronous Write Sequence and Timing Diagram
caused the last byte or word to be clocked into the previous auto committed packet. Figure 23 shows this scenario. X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode.
Figure 23 shows a scenario where two packets are committed.
The first packet gets committed automatically when the number of bytes in the FIFO reaches X (value set in AUTOINLEN register) and the second one byte/word short packet being committed manually using PKTEND.
Note that there is at least one IFCLK cycle timing between the assertion of PKTEND and clocking of the last byte of the previous packet (causing the packet to be committed automatically). Failing to adhere to this timing results in the FX2 failing to send the one byte or word short packet.
[20]

10.12 Slave FIFO Asynchronous Packet End Strobe

Figure 24. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
[23]
Table 28. Slave FIFO Asynchronous Packet End Strobe Parameters
Parameter Description Min Max Unit
t
PEpwl
t
PWpwh
t
XFLG
PKTEND Pulse Width LOW 50 ns PKTEND Pulse Width HIGH 50 ns PKTEND to FLAGS Output Propagation Delay 115 ns
Document #: 38-08032 Rev. *L Page 47 of 62
[20]
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10.13 Slave FIFO Output Enable

SLOE
DATA
t
OEon
t
OEoff
FIFOADR [1.0]
DATA
t
XFLG
t
XFD
FLAGS
NN+1
Figure 25. Slave FIFO Output Enable Timing Diagram
Table 29. Slave FIFO Output Enable Parameters
Parameter Description Min Max Unit
t
OEon
t
OEoff
SLOE Assert to FIFO DATA Output 10.5 ns SLOE Deassert to FIFO DATA Hold 10.5 ns
[20]

10.14 Slave FIFO Address to Flags/Data

Figure 26. Slave FIFO Address to Flags/Data Timing Diagram
[20]
Table 30. Slave FIFO Address to Flags/Data Parameters
Parameter Description Min Max Unit
t
XFLG
t
XFD
FIFOADR[1:0] to FLAGS Output Propagation Delay 10.7 ns FIFOADR[1:0] to FIFODATA O utput Propagation Delay 14.3 ns
Document #: 38-08032 Rev. *L Page 48 of 62
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10.15 Slave FIFO Synchronous Address

IFCLK
SLCS/FIFOADR [1:0]
t
SFAtFAH
SLRD/SLWR/PKTEND
SLCS/FIFOADR [1:0]
t
SFA
t
FAH
Figure 27. Slave FIFO Synchronous Address Timing Diagram
[20]
Table 31. Slave FIFO Synchronous Address Parameters
[21]
Parameter Description Min Max Unit
t
IFCLK
t
SFA
t
FAH
Interface Clock Period 20.83 200 ns FIFOADR[1:0] to Clock Setup Time 25 ns Clock to FIFOADR[1:0] Hold Time 10 ns

10.16 Slave FIFO Asynchronous Address

Figure 28. Slave FIFO Asynchronous Address Timing Diagram
Table 32. Slave FIFO Asynchronous Address Parameters
[23]
Parameter Description Min Max Unit
t
SFA
t
FAH
FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time 10 ns RD/WR/PKTEND to FIFOADR[1:0] Hold Time 10 ns
[20]
Document #: 38-08032 Rev. *L Page 49 of 62
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10.17 Sequence Diagram

IFCLK
SLRD
FLAGS
SLOE
DATA
t
SRD
t
RDH
t
OEon
t
XFD
t
XFLG
t
IFCLK
N+1
Data Driven: N
>= t
SRD
t
OEon
t
XFD
N+2
t
XFD
t
XFD
>= t
RDH
t
OEoff
N+4
N+3
t
OEoff
t
SFA
t
FAH
FIFOADR
SLCS
t=0
N+1
t=1
t=2
t=3
t=4
t
FAH
T=0
t
SFA
T=1
T=2
T=3
T=4
NNN+1 N+2
FIFO POINTER
N+3
FIFO DATA BUS
N+4
Not Driven Driven: N
SLOE
SLRD
N+1 N+2
N+3
Not Driven
SLRD
SLOE
IFCLK
IFCLK IFCLK
IFCLK IFCLK
N+4
N+4
IFCLK IFCLK
IFCLK IFCLK
SLRD
N+1
SLRD
N+1
N+1
SLOE
Not Driven
N+4
N+4
IFCLK
SLOE

10.17.1 Single and Burst Synchronous Read Example

Figure 29. Slave FIFO Synchronous Read Sequence and Timing Diagram
[20]
Figure 29 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the synchronizing clock. The diagram illustrates a single read followed by a burst read.
At t = 0 the FIFO address is stable and the signal SLCS is
At t = 1, SLOE is asserted. SLOE is an output enable only,
At t = 2, SLRD is asserted. SLRD must meet the setup time of
Document #: 38-08032 Rev. *L Page 50 of 62
Figure 30. Slave FIFO Synchronous Sequence of Events Diagram
asserted (SLCS may be tied low in some applications). Note that t running at 48 MHz, the FIFO address setup time is more than one IFCLK cycle.
whose sole function is to drive the data bus. The data that is
has a minimum of 25 ns. This means when IFCLK is
SFA
driven on the bus is the data that the internal FIFO pointer is currently pointing to. In this example it is the first data value in the FIFO. Note: the data is pre-fetched and is driven on the bus when SLOE is asserted.
(time from asserting the SLRD signal to the rising edge of
t
SRD
the IFCLK) and maintain a minimum hold time of t from the IFCLK edge to the deassertion of the SLRD signal).
RDH
(time
If the SLCS signal is used, it must be asserted before SLRD is asserted (The SLCS and SLRD signals must both be asserted to start a valid read condition).
The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data from the newly addressed location to the data bus. After a propagation delay of t IFCLK) the new data value is present. N is the first data value read from the FIFO. T o have data on the FIFO data bus, SLOE
(measured from the rising edge of
XFD
MUST also be asserted.
The same sequence of events are shown for a burst read and are marked with the time indicators of T = 0 through 5.
Note For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle, on the rising edge of the clock the FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus.
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10.17.2 Single and Burst Synchronous Write

IFCLK
SLWR
FLAGS
DATA
t
SWR
t
WRH
t
SFD
t
XFLG
t
IFCLK
N
>= t
SWR
>= t
WRH
N+3
PKTEND
N+2
t
XFLG
t
SFA
t
FAH
t
SPE
t
PEH
FIFOADR
SLCS
t
SFD
t
SFD
t
SFD
N+1
t
FDH
t
FDH
t
FDH
t
FDH
t=0
t=1
t=2
t=3
t
SFA
t
FAH
T=1
T=0
T=2
T=5
T=3
T=4
Figure 31. Slave FIFO Synchronous Write Sequence and Timing Diagram
[20]
The Figure 31 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchro­nizing clock. The diagram illustrates a single write followed b y burst write of 3 bytes and committing all 4 bytes as a short packet using the PKTEND pin.
At t = 0 the FIFO address is stable and the signal SLCS is
asserted. (SLCS may be tied low in some applications) Note that t running at 48 MHz, the FIFO address setup time is more than
has a minimum of 25 ns. This means when IFCLK is
SFA
one IFCLK cycle.
At t = 1, the external master/peripheral must outputs the data
value onto the data bus with a mini mu m set up time of t before the rising edge of IFCLK.
At t = 2, SLWR is asserted. The SLWR must meet the setup
time of t edge of IFCLK) and maintain a minimum hold time of t
(time from asserting the SLWR signal to the rising
SWR
from the IFCLK edge to the deassertion of the SLWR signal). If the SLCS signal is used, it must be asserted with SLWR or before SL WR is asserted (The SLCS and SLWR signals must
SFD
WRH
(time
both be asserted to start a valid write condition).
While the SLWR is asserted, data is written to the FIFO and on
the rising edge of the IFCLK, the FIFO pointer is incremented. The FIFO flag is also updated after a delay of t rising edge of the clock.
The same sequence of events are also shown for a burst write and are marked with the time indicators of T = 0 through 5.
XFLG
from the
Note For the burst mode, SLWR and SLCS are left asserted for the entire duration of writing all the required data values. In this burst write mode, after the SLWR is asserted, the data on the
Document #: 38-08032 Rev. *L Page 51 of 62
FIFO data bus is written to the FIFO on every rising edge of IFCLK. The FIFO pointer is updated on each rising edge of IFCLK. In Figure 31, after the four bytes are written to the FIFO, SLWR is deasserted. The short 4 byte packet can be committed to the host by asserting the PKTEND signal.
There is no specific timing requirement that should be met for asserting PKTEND signal with regards to asserting the SLWR signal. PKTEND can be asserted with the last data value or thereafter. The only requirement is that the setup time t the hold time t number of data values committed includes the last value written to the FIFO. In this example, both the data value and the PKTEND signal are clocked on the same rising edge of IFCLK.
must be met. In the scenario of Figure 31, the
PEH
PKTEND can also be asserted in subsequent clock cycles. The FIFOADDR lines should be held constant during the PKTEND assertion.
Although there are no specific timing requirement for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte/word packet. Additional timing requirements exists when the FIFO is configured to operate in auto mode and it is desired to send two packets: a full packet (full defined as the number of bytes in the FIFO meeting t he l evel set in AUTOINLEN registe r ) committed automatically followed by a short one byte or word packet committed manually using the PKTEND pin.
In this case, the external master must ensure to assert the PKTEND pin at least one clock cycle after the rising edge that caused the last byte or word that needs to be clocked into the previous auto committed packet (the packet with the number of bytes equa l to what is set i n the AUTOINLEN register). Refer to
Figure 23 for further details on this timing.
SPE
and
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10.17.3 Sequence Diagram of a Single and Burst Asynchronous Read

SLRD
FLAGS
SLOE
DATA
t
RDpwh
t
RDpwl
t
OEon
t
XFD
t
XFLG
N
Data (X)
t
XFD
N+1
t
XFD
t
OEoff
N+3
N+2
t
OEoff
t
XFLG
t
SFA
t
FAH
FIFOADR
SLCS
Driven
t
XFD
t
OEon
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
FAH
t
SFA
N
t=0
T=0
T=1
T=7
T=2
T=3
T=4
T=5
T=6
t=1
t=2
t=3
t=4
NN
SLOE SLRD
FIFO POINTER
N+3
FIFO DATA BUS
Not Driven Driven: X N Not Driven
SLOE
N
N+2
N+3
SLRD
N
N+1
SLRD
N+1
SLRD
N+1
N+2
SLRD
N+2
SLRD
N+2
N+1
SLOE
Not Driven
SLOE
N
N+1
N+1
Figure 32. Slave FIFO Asynchronous Read Sequence and Timing Diagram
[20]
Figure 32 shows the timing relationship of the SLAVE FIFO
signals during an asynchronous FIFO read. It shows a single read followed by a burst read.
At t = 0 the FIFO address is stable and the SLCS signal is
At t = 1, SLOE is asserted. This results in the data bus being
At t = 2, SLRD is asserted. The SLRD must meet the minimum
Document #: 38-08032 Rev. *L Page 52 of 62
Figure 33. Slave FIFO Asynchronous Read Sequence of Events Diagram
The data that is driven, after asserting SLRD, is the updated
data from the FIFO. This data is valid after a propagation delay of t
from the activating edge of SLRD. In Figure 32, data N
XFD
asserted.
is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle (SLRD is asserted), SLOE must be in an asserted state. SLRD and SLOE can also be tied together.
driven. The data that is driven on to the bus is previous data, it data that was in the FIFO from a prior read cycle.
active pulse of t t
RDpwh
SLRD is asserted (The SLCS and SLRD signals must both be
. If SLCS is used then, SLCS must be asserted before
and minimum de-active pulse width of
RDpwl
asserted to start a valid read condition.)
The same sequence of events is also shown for a burst read marked with T = 0 through 5.
Note In burst read mode, during SLOE is assertion, the data bus is in a driven state and outputs the previous data. After SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incre­mented.
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10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write

PKTEND
SLWR
FLAGS
DATA
t
WRpwh
t
WRpwl
t
XFLG
N
t
SFD
N+1
t
XFLG
t
SFA
t
FAH
FIFOADR
SLCS
t
WRpwh
t
WRpwl
t
WRpwh
t
WRpwl
t
WRpwh
t
WRpwl
t
FAH
t
SFA
t
FDH
t
SFD
N+2
t
FDH
t
SFD
N+3
t
FDH
t
SFD
t
FDH
t
PEpwh
t
PEpwl
t=0
t=2
t =1
t=3
T=0
T=2
T=1
T=3
T=6
T=9
T=5
T=8
T=4
T=7
Figure 34. Slave FIFO Asynchronous Write Sequence and Timing Diagram
[20]
Figure 34 shows the timing relationship of the SLAVE FIFO write
in an asynchronous mode. The diagram shows a single wri te followed by a burst write of 3 bytes and committing the 4 byte short packet using PKTEND.
At t = 0 the FIFO address is applied, insuring that it meets the
setup time of t (SLCS may be tied low in some applications).
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t t
. If the SLCS is used, it must be asserted with SLWR or
WRpwh
before SLWR is asserted.
At t = 2, data must be present on the bus t
deasserting edge of SLWR.
At t = 3, deasserting SLWR causes the data to be written from
. If SLCS is used, it must also be asserted
SFA
and minimum de-active pulse width of
WRpwl
before the
SFD
the data bus to the FIFO and then increments the FIFO pointer.
The FIFO flag is also updated after t edge of SLWR.
from the deasserting
XFLG
The same sequence of events are shown for a burst write and is indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, after SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incre­mented.
In Figure 34 after the four bytes are written to the FIFO and SLWR is deasserted, the short 4 byte packet can be committed to the host using the PKTEND. The external device should be designed to not assert SLWR and the PKTEND signal at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The FIFOADDR lines have to held constant during the PKTEND assertion.
Document #: 38-08032 Rev. *L Page 53 of 62
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11. Ordering Information

Table 33. Ordering Information
Ordering Code Package Type RAM Size # Prog IOs
Ideal for battery powered applications
CY7C68014A-128AXC 128 TQFP – Lead-Free 16K 40 16/8 bit CY7C68014A-100AXC 100 TQFP – Lead-Free 16K 40 – CY7C68014A-56PVXC 56 SSOP – Lead-Free 16K 24 – CY7C68014A-56LFXC 56 QFN – Lead-Free 16K 24 – CY7C68014A-56BAXC 56 VFBGA – Lead-Free 16K 24 – CY7C68016A-56LFXC 56 QFN – Lead-Free 16K 26
Ideal for non-battery powered applications
CY7C68013A-128AXC 128 TQFP – Lead-Free 16K 40 16/8 bit CY7C68013A-128AXI 128 TQFP – Lead-Free (Industrial) 16K 40 16/8 bit CY7C68013A-100AXC 100 TQFP – Lead-Free 16K 40 – CY7C68013A-100AXI 100 TQFP – Lead-Free (Industrial) 16K 40 – CY7C68013A-56PVXC 56 SSOP – Lead-Free 16K 24 – CY7C68013A-56PVXI 56 SSOP – Lead-Free (Industrial) 16K 24 – CY7C68013A-56LFXC 56 QFN – Lead-Free 16K 24 – CY7C68013A-56LFXI 56 QFN – Lead-Free (Industrial) 16K 24 – CY7C68015A-56LFXC 56 QFN – Lead-Free 16K 26 – CY7C68013A-56BAXC 56 VFBGA – Lead-Free 16K 24
8051 Address
/Data Busses
Development Tool Kit
CY3684 EZ-USB FX2LP Development Kit
Reference Design Kit
CY4611B USB 2.0 to ATA/ATAPI Reference Design using EZ-USB FX2LP
Document #: 38-08032 Rev. *L Page 54 of 62
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12. Package Diagrams

51-85062-*C
Figure 35. 56-lead Shrunk Small Outline Package O56 (51-85062)
The FX2LP is available in five packages:
56-pin SSOP
56-pin QFN
100-pin TQFP
128-pin TQFP
56-ball VFBGA
Package Diagrams
Document #: 38-08032 Rev. *L Page 55 of 62
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Package Diagrams (continued)
51-85144-*D
Figure 36. 56-Lead QFN 8 x 8 mm LF56A (51-85144)
TOP VIEW
0.80[0.031]
7.70[0.303]
7.90[0.311]
A
C
1.00[0.03 9] MAX.
N
BOTTOM VIEW
SEATING PLANE
N
2
0.18[0.007]
0.50[0.020]
1
1
0.08[0.003]
0.50[0.020]
0.05[0.002] MAX.
2
SIDE VIEW
(4X)
C
0.24[0.009]
0.20[0.008] REF.
0.80[0.031] MAX.
PIN1 ID
0°-12°
6.45[0.254]
8.10[0.319]
7.80[0.307]
6.55[0.258]
0.45[0.018]
0.20[0.008] R.
8.10[0.319]
7.90[0.311]
7.80[0.307]
7.70[0.303]
DIA.
0.28[0.011]
0.30[0.012]
6.55[0.258]
6.45[0.254]
0.60[0.024]
1. HATCH AREA IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
NOTES
:
PART #
PB-FREE
STANDARD
LY56
5. PACKAGE CODE DESCRIPTION
3. PACKAGE WEIGHT: 0.162g
LF56
SOLDERABLE
EXPOSED
PAD
(SUBCON PUNCH TYPE PKG with 6.1 x 6.1 EPAD)
6.1
6.1
51-85144-*G
Document #: 38-08032 Rev. *L Page 56 of 62
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Package Diagrams (continued)
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
3. DIMENSIONS IN MILLIMETERS
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
0.30±0.08
0.65
20.00±0.10
22.00±0.20
1.40±0.05
12°±1°
1.60 MAX.
0.05 MIN.
0.60±0.15
0° MIN.
0.25
0°-7°
(8X)
STAND-OFF
R 0.08 MIN.
TYP.
0.20 MAX.
0.15 MAX.
0.20 MAX.
R 0.08 MIN.
0.20 MAX.
14.00±0.10
16.00±0.20
0.10
SEE DETAIL
A
DETAIL
A
1
100
30
31 50
51
80
81
GAUGE PLANE
1.00 REF.
0.20 MIN.
SEATING PLANE
51-85050-*B
Figure 37. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A100RA (51-85050)
Document #: 38-08032 Rev. *L Page 57 of 62
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Package Diagrams (continued)
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
3. DIMENSIONS IN MILLIMETERS
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
0.22±0.05
0.50
20.00±0.10
22.00±0.20
1.40±0.05
12°±1°
1.60 MAX.
0.05 MIN.
0.60±0.15
0° MIN.
0.25
0°-7°
(8X)
STAND-OFF
R 0.08 MIN.
TYP.
0.20 MAX.
0.15 MAX.
0.20 MAX.
R 0.08 MIN.
0.20 MAX.
14.00±0.10
16.00±0.20
0.08
SEE DETAIL
A
DETAIL
A
128
GAUGE PLANE
1.00 REF.
0.20 MIN.
SEATING PLANE
1
51-85101-*C
Figure 38. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128 (51-85101)
Document #: 38-08032 Rev. *L Page 58 of 62
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Package Diagrams (continued)
TOP VIEW
PIN A1 CORNER
0.50
3.50
5.00±0.10
BOTTOM VIEW
0.10(4X)
3.50
5.00±0.10
0.50
Ø0.15 M C A B
Ø0.05 M C
Ø0.30±0.05(56X)
A1 CORNER
-B-
-A-
1.0 max
0.160 ~0.260
0.080 C
0.45
SEATING PLANE
0.21
0.10 C
-C-
SIDE VIEW
5.00±0.10
5.00±0.10
REFERENCE JEDEC: MO-195C
PACKAGE WEIGHT: 0.02 grams
E
G H
F
D
C
B
A
13265486
7856 2341
E
G H
F
D
C
B
A
001-03901-*B
Figure 39. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 (001-03901)
Note
24.Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High-Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.

13. PCB Layout Recommendations

Follow these recommendations to ensure reliable high perfor­mance operation:
Four layer impedance controlled boards are required to
maintain signal quality.
Specify impedance targets (ask your board vendor what they
[24]
can achieve).
T o control impedance, maintain trace widths and trace spacing.
Minimize stubs to minimize reflected signals.
Connections between the USB connector shell and signal
ground must be near the USB connector.
Bypass and flyback caps on VBus, near connector, are recom-
mended.
DPLUS and DMINUS trace lengths should be kept to within 2
mm of each other in length, with preferred length of 20 to 30 mm.
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to split under these traces.
Do not place vias on the DPLUS or DMINUS trace routing.
Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
Document #: 38-08032 Rev. *L Page 59 of 62
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14. Quad Flat Package No Leads (QFN) Package Design Notes

0.017” dia
Solder Mask
Cu Fill
Cu Fill
PCB Material
PCB Material
0.013” dia
Via hole for thermally connecting the QFN to the circuit board ground plane.
This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane
Figure 41. Plot of the Solder Mask (White Area)
Figure 42. X-ray Image of the Assembly
Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. Design a Copper (Cu) fill in the PCB as a thermal pad under the package. Heat is transferred from the FX2LP through the device’s metal paddle on the bottom side of the package. Heat from here is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via. A via is a plated through hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process.
Figure 40. Cross-section of the Area Underneath the QFN Package
For further information on this package design refer to Appli­cation Notes for Surface Mount Assembly of Amkor's MicroLead­Frame (MLF) Packages. You can find this on Amkor's website http://www.amkor.com.
The application note provides detailed information about board mounting guidelines, soldering flow, rework process, etc.
Figure 40 shows a cross-sectional area underneath the
package. The cross section is of only one via. The solder paste template should be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. Use the No Clean type 3 solder paste for mounting the part. Nitrogen purge is recommended during reflow.
Figure 41 is a plot of the solder mask pattern and Figure 42
displays an X-Ray image of the assembly (darker areas indicate solder).
Document #: 38-08032 Rev. *L Page 60 of 62
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Document History Page
Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller Document Number: 38-08032
REV . ECN NO.
** 124316 03/17/03 VCS New data sheet
*A 128461 09/02/03 VCS Added PN CY7C68015A throughout data sheet
*B 130335 10/09/03 KKV Restored PRELIMINARY to header (had been removed in error from rev. *A) *C 131673 02/12/04 KKU Section 8.1 changed “certified” to “compliant”
*D 230713 See ECN KKU Changed Lead free Marketing part numbers in Table 33 as per spec change in 28-00054. *E 242398 See ECN TMD Minor Change: data sheet posted to the web, *F 271169 See ECN MON Added USB-IF Test ID number
*G 316313 See ECN MON Removed CY7C68013A-56PVXCT part availability
*H 338901 See ECN MON Added information about the AUTOPTR1/AUTOPTR2 address timing with regards to data
*I 371097 See ECN MON Added timing for strobing RD#/WR# signals when using PortC strobe feature (Section 10.5)
*J 397239 See ECN MON Removed XTALINSRC register from register summary.
Issue
Date
Orig. of Change
Description of Change
Modified Figure 1 to add ECC block and fix errors Removed word “compatible” where associated with I Corrected grammar and formatting in various locations Updated Sections 3.2.1, 3.9, 3.11, Table 9, Section 5.0 Added Sections 3.15, 3.18.4, 3.20 Modified Figure 5 for clarity Updated Figure 36 to match current spec revision
Table 14 added parameter V
Added Sequence diagrams Section 9.16 Updated Ordering information with lead-free parts Updated Registry Summary Section 3.12.4:example changed to column 8 from column 9 Updated Figure 14 memory write timing Diagram Updated section 3.9 (reset) Updated section 3.15 ECC Generation
Added USB 2.0 logo Added values for Isusp, Icc, Power Dissipation, Vih_x, Vil_x Changed VCC from + Changed E-Pad size to 4.3 mm x 5.0 mm Changed PKTEND to FLAGS output propagation delay (asynchronous interface) in
Table 28 from a max value of 70 ns to 115 ns
Added parts ideal for battery powered applications: CY7C68014A, CY7C68016A Provided additional timing restrictions and requirement about the use of PKETEND pin to commit a short one byte/word packet subsequent to committing a packet automatically (when in auto mode). Added Min Vcc Ramp Up time (0 to 3.3v)
memory read/write timing diagram. Removed TBD for Min value of Clock to FIFO Data Output Propagation Delay (t Slave FIFO Synchronous Read Changed Table 33 to include part CY7C68016A-56LFXC in the part listed for battery powered applications Added register GPCR2 in register summary
Changed Vcc margins to + Added 56-pin VFBGA Pin Package Diagram Added 56-pin VFBGA definition in pin listing Added RDK part number to the Ordering Information table
10% to + 5%
IH_X
10%
and V
IL_X
2
C
) for
XFD
Document #: 38-08032 Rev. *L Page 61 of 62
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Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller Document Number: 38-08032
REV . ECN NO.
Issue
Date
Orig. of Change
Description of Change
*K 420505 See ECN MON Remove SLCS from figure in Section 10.10.
Removed indications that SLRD can be asserted simultaneously with SLCS in Section
10.17.2 and Section 10.17.3 Added Absolute Maximum Temperature Rating for industrial packages in Section 6. Changed number of packages stated in the description in Section 4. to five. Added Table 13 on Thermal Coefficients for various packages
*L 2064406 See ECN CMCC/
PYRS
Changed TID number Removed T0OUT and T1OUT from CY7C68015A/16A Updated t Updated 56-lead QFN package diagram
Min value in Figure 20
SWR
© Cypress Semiconductor Corporation, 2003- 2008. The infor mation cont ain ed herein is subj ect to change wi thout notice. C ypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warrant ed no r int e nded to be used fo r medical, life support, life saving, critica l contr o l or safety applications, unless pursuant to an express writte n agreement with Cypress. Furthermore, Cypress does not authorize it s pr o ducts for use as critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the us er . The inclu sion of Cypress p roducts in life -support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cyp ress does not assume any liability arising out of the app licati on or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot auth orize its p roducts fo r use as critical compon ents in life-su pport systems whe re a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-08032 Rev. *L Revised February 8, 2008 Page 62 of 62
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philip s. EZ- USB FX2LP, EZ-USB FX2 and ReNumeration are trademarks, and EZ-U SB is a regi stered trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
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