CYPRESS CY7C68001 User Manual
e
CY7C6800
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EZ-USB SX2™ High-Speed USB Interface Devic
1.0 EZ-USB SX2™ Features
• USB 2.0-certified compliant
—On the USB-IF Integrators List: T est I D Number
40000713
• Operates at high (480 Mbps) or full (12 Mbps) speed
• Supports Control Endpoint 0:
—Used for handling USB device requests
• Supports four configurable endpoints that share a 4-
KB FIFO space
—Endpoints 2, 4, 6, 8 for appl ication-specific control
and data
• Standard 8- or 16-bit external master interface
—Glueless interface to most standard microproces-
sors DSPs, ASICs, and FPGAs
—Synchronous or Asynchronous interface
• Integrated phase-locked loop (PLL)
• 3.3V operation, 5V tolerant I/Os
• 56-pin SSOP and QFN package
• Complies with most device class specificati ons
2.1 Block Diagram
2.0 Applications
• DSL modems
• AT A interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Home PNA
• Wireless LAN
• MP3 players
•Networking
•Printers
The “Reference Designs” section of the Cypress web site
provides additional tools for typical USB applications. Each
reference design comes complete with firmware source code
and object code, schematic s, and documenta ti on. Please see
the Cypress web site at www.cypress. com .
24 MHz
XTAL
DPLUS
DMINUS
VCC
1.5K
USB 2.0 XCVR
SCL
SDA
PLL
I2C Bus
Controller
(Master On l y )
SX2 Internal Logic
CY Smart USB
FS/HS Engine
RESET#
WAKEUP*
4 KB
FIFO
Figure 2-1. Block Diagram
IFCLK*
Read*, Write*, OE*, PKTEND *, CS#
Interrupt#, Ready
Flags (3/4)
Address (3)
Control
FIFO
Data
8/16-Bit Data
Bus
Data
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-08013 Rev. *E Revised July 13, 2004
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2.2 Introduction
The EZ-USB SX2™ USB interf ace device is designed to wo rk
with any external master, such as standard microprocessors,
DSPs, ASICs, and FPGAs to enable USB 2.0 support for any
peripheral design. SX2 has a built-in USB transceiver and
Serial Interface Engine (SIE), along with a command dec oder
for sending and receiving USB data. The controller has four
endpoints that share a 4-KB FIFO space for maximum flexibility and throughput, as well as Control Endpoint 0. SX2 has
three address pins and a selectable 8- or 16- bit data bus for
command and data input or out put.
2.3 System Diagram
Windows/USB Capable Host
USB Cable
USB Connection
Cypress
SX2
RAM/ROM
Device CPU Application
Figure 2-2. Example USB System Diagram
EEPROM
3.3 Boot Methods
During the power-up sequence, internal logic of the SX2
checks for the presence of an I
EEPROM, it will boot off the EEPROM. When the presence of
an EEPROM is detected, the SX2 checks the value of first
byte. If the first byte is found to be a 0xC4, the SX2 loads the
next two bytes into the IFCONFIG and POLAR registers,
respectively. If the fourth byte is also 0xC4, the SX2
enumerates using t he descriptor i n the EEPROM, then signal s
to the external master when enumeration is complete via an
ENUMOK interrupt (Section 3.4). If no EEPROM is detected,
the SX2 relies o n the extern al master f or the descr iptors. Once
this descriptor infor mation i s recei ve from the exte rnal mast er,
the SX2 will connect to the USB bus and enumerate.
3.3.1 EEPROM Organization
The valid sequence of bytes in the EEPROM are displayed
below
T able 3-1. Descriptor Lengt h Set to 0x06:
Default Enumeration
Byte Index Description
00xC4
1 IFCONFIG
2POLAR
30xC4
4 Descriptor Length (LSB):0x06
5 Descriptor Length (MSB): 0x00
6 VID (LSB)
7 VID (MSB)
8 PID (LSB)
9 PID (MSB)
10 DID (LSB)
1 1 DID (MSB)
2
C EEPROM.
[1,2]
If it finds an
3.0 Functional Overview
T able 3-2. Descriptor Length Not Set to 0x06
3.1 USB Signaling Speed
SX2 operates at two of the three rates def ined in the Universal
Serial Bus Specification Revision 2.0, dated April 27, 2000:
• Full-speed, with a signaling bit rate of 12 Mbits/s
• High-speed, with a signal ing bit rate of 480 Mbits/s.
SX2 does not support the low-speed signaling rate of 1.5
Mbits/s.
3.2 Buses
SX2 features:
• A selectable 8- or 16-bit bidirectional data bus
• An address bus for selecting the FIFO or Command Interface.
Notes:
1. Because there is no direct way to detect which EEPROM type (single or double address) is connected, SX2 uses the EEPROM address pins A2, A1, and A0
to determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and doublebyte EEPROMs (24LC64, etc.) should be strapped to address 001.
2. The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull-up values are 2.2K – 10K
Ohms.
Document #: 38-08013 Rev. *E Page 2 of 42
Byte Index Description
00xC4
1IFCONFIG
2POLAR
30xC4
4 Descriptor Length (L SB)
5 Descriptor Length (MSB
6 Descriptor[0]
7 Descriptor[1]
8 Descriptor[2]
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• 0xC4: This initial byte tells the SX2 that this is a valid EEPROM with configuration information.
• IFCONFIG: The IFCONFIG byte contains the settings for
the IFCONFIG regi ster . The IFCONFI G register bi ts are defined in Section 7. 1. If the external master requires an interface configu ration different from the def ault, that interface
can be specified by this byte.
• POLAR: The Polar byte contains the polarity of the FIFO
flag pin signals. The POLAR register bits are defined in
Section 7.3. If th e external master requires signal polarity
differ ent from the default, the polari ty can be specified by
this byte.
• Descriptor: The Descriptor byte determines if the SX2
loads the desc riptor from the EEPROM. If this byt e = 0xC4,
the SX2 will l oad the descript or starting with the next byte.
If this byte does not equal 0xC4, the SX2 will wait for descriptor information from the external master.
• Descriptor Length: The Descriptor l ength is within the next
two bytes and i ndicate the length o f the descriptor con tained
within the EEPROM. The l ength is loaded least significant
byte (LSB) first, then most significant byte (MSB).
• Byte 7 Starts Descri ptor Inform ation: The descript or can
be a maximum of 500 bytes.
3.3.2 Default Enumeration
An optional d efault descr iptor can be used t o si mplif y enumeration. Onl y the V endor ID (VID), Product ID (PID), and Device
ID (DID) need t o b e loaded b y the SX2 f or i t to en umerate wi th
this default set-up. This information is either loaded from an
EEPROM in the case when the presence of an EEPROM
(Table 3-1) is detected, or the ext ernal master m ay simply l oad
a VID, PID, and DID when no EEPROM is present. In this
default enumeration, the SX2 uses the in-built default
descriptor (refer to Section 12.0).
If the descript or length loaded from the EEPROM is 6, SX2 will
load a VID, PID, and DID from the EEPROM and enumerate.
The VID, PID, and DID are loaded LSB, then MSB. For
example, if the VID, PID, and DID are 0x0547, 0x1002, and
0x0001, respectively, then the bytes should be stored as:
• 0x47, 0x05, 0x02, 0x10, 0x01, 0x00.
If there is no EEPROM, SX2 will wait for the external master
to provide the descriptor information. To use the default
descriptor, the external master must write to the appropriate
register (0x30) with descriptor length equal to 6 followed by the
VID, PID, and DID. Refer to Secti on 4.2 for fur ther info rmatio n
on how the external mast er may load the values.
The default descriptor enumerates four endpoints as listed in
the following page:
• Endpoint 2: Bulk out, 512 bytes in high-speed mode, 64
bytes in full-s peed m ode
• Endpoint 4: Bulk out, 512 bytes in high-speed mode, 64
bytes in full-s peed m ode
• Endpoint 6: Bulk in, 512 byt es in high-speed mode, 64 bytes
in full-speed mode
• Endpoint 8: Bulk in, 512 byt es in high-speed mode, 64 bytes
in full-speed mode.
The entire default descriptor is listed in Section 12.0 of this
data sheet.
3.4 Interrupt System
3.4.1 Architecture
The SX2 provides an output signal that indicates to the
external mast er t hat the SX2 has an inter rupt condi tion, or that
the data from a register re ad reques t is avail able. The SX2 has
six interrupt sources: SETUP, EP0BUF, FLAGS, ENUMOK,
BUSACTIVITY, and READY . Eac h interrup t can be enab led or
disabled by setting or clearing the corresponding bit in the
INTENABLE register.
When an interrupt occurs, the INT# pin will be asserted, and
the corresponding bit will be set in the Interrupt Status Byte.
The external master reads the Interrupt Status Byte by
strobing SLRD/SLOE. This presents the Interrupt Status Byte
on the lower portion of the data bus (FD[7:0]). Reading the
Interrupt Status Byte automatically clears the interrupt. Only
one interrupt request will occur at a time; the SX2 buffers
multiple pending interrupts.
If the ext ernal master has initiated a register read request, the
SX2 will buffer inte rrupts unt il the external master has read the
data. This insures that after a read sequence has begun, the
next interrupt that is received from the SX2 will indicate that
the corresponding data is available. Followi ng is a description
of this INTENABLE register.
3.4.2 INTENABLE Register Bit Definition
Bit 7: SETUP
If this interrupt is enabled, and the SX2 receives a set-up
packet from the USB host, the SX2 asserts the INT# pin and
sets bit 7 in the Int errupt St atus Byte. Th is inter rupt onl y occurs
if the set-up request is not one that the SX2 automatically
handles. For complete details on how to handle the SETUP
interr up t , re fe r to S ec ti o n 5 .0 of this data sheet .
Bit 6: EP0BUF
If this interrupt is enabl ed, and the Endpoi nt 0 buff er becomes
available to the external master for read or write operations,
the SX2 asserts the INT# pin and sets bit 6 in the Interrupt
Status Byte. This in terrupt i s used for handlin g the data ph ase
of a set-up req uest. Fo r comple te de tails on h ow to handle t he
EP0BUF interrupt, refer t o Secti on 5.0 of this data sheet.
Bit 5: FLAGS
If this int errupt is e nabled, and any O UT endpoi nt FIF O’ s stat e
changes from empty to not-empty, the SX2 asserts the INT#
pin and sets bit 5 in the Interrupt Status Byte. This is an
alternate way to monitor the status of OUT endpoint FIFOs
instead of using the FLAGA-FLAGD pins, and can be used to
indicate when an OUT packet has been received from the
host.
Bit 2: ENUMOK
If this interrupt is enabled and the SX2 receives a
SET_CONFIGURATION request from the USB host, the SX2
asserts the I NT# pin and sets bi t 2 i n the Int errup t Stat us Byte .
This event signals the completion of the SX2 enumeration
process.
Bit 1: BUSACTIVITY
If this interrupt is enabled, and the SX2 detects either an
absence or resumption of activity on the USB bus, the SX2
asserts the I NT# pin and sets bi t 1 i n the Int errup t Stat us Byte .
This usually indicates that the USB host is either suspending
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or resuming or that a self-powered device has been plugged
in or unplugged. If the SX2 is bus-powered, the external
master must put the SX2 into a low-power mode after
detecting a USB suspend condition to be USB-compliant.
Bit 0: READY
If this interrupt is enabled, bit 0 in the Interrupt Status Byte is
set when the SX2 has powered up and performed a self-test.
The external master should always wait for this interrupt
before trying to read or write to the SX2, unless an external
EEPROM with a valid descriptor is present. If an external
EEPROM with a valid descriptor is present, the ENUMOK
interrupt will occur instead of the READY interrupt after power
up. A READY interrupt will also occur if the SX2 is awakened
from a low-power mode via the WAKEUP pin. This READY
interrupt i ndicates that the SX2 is ready for commands or data.
Although it is true that all interrupts will be buffered once a
command read request has been initiated, in very rare conditions, there might be a situation when there is a pending
interrupt already, when a read request is initiated by the
external master. In this case it is the interrupt status byte that
will be output when the external master asserts the SLRD. So,
a condition exists wher e the Int errup t Statu s Data Byt e can be
mistaken for t he resul t of a command re gister read requ est . In
order to get around this possible race condition, the first thing
that the external master must do on getting an interrupt from
the SX2 is check the status of the READY pin. If the READY
is low at the time the INT# was asserted, the data that will be
output when the external master strobes the SLRD is the
interrupt status byte (not the actual data requested). If the
READY pin is high at the time when the interrupt is asserted,
the data output on strobing the SLRD is the actual data byte
requested by the external master. So it is important that the
state of the READY pin be checked at the time the INT# is
asserted to ascertain the cause of the interrupt.
3.5 Resets and Wakeup
3.5.1 Reset
An input pi n (RESET#) reset s the chi p. The i nternal PLL s tabilizes af ter V
network (R = 100 K Ohms, C = 0.1 uf) is used to provide the
has reached 3.3V. Typically, an external RC
CC
RESET# signal. Th e Clock must be in a st able sta te for at l east
200 us before the RESET is released.
3.5.2 USB Reset When the SX2 detect s a USB Reset condi tion on the USB bus,
SX2 handles it like any other enumeration sequence. This
means that SX2 will enumerate again and assert the
ENUMOK interrupt to let the external master know that it has
enumerated. The external master will then be responsible for
configuring the SX2 for the application. The external master
should also check whether SX2 enumerated at High or Full
speed in order to adjust the EPxPKTLENH/L register values
accordingly. The last initialization task is for the external
master to flush all of the SX2 FIFOs .
3.5.3 Wakeup
The SX2 exits its low-power state when one of the following
events occur:
• USB bus signals a res um e. The SX2 will assert a BUSACTIVITY interrupt.
• The external master asserts the W AKEUP pin. The SX2 wi ll
assert a READY interrupt
[3]
.
3.6 Endpoint RAM
3.6.1 Size
• Control endpoint: 64 Bytes: 1 × 64 bytes (Endpoint 0).
• FIFO Endpoints: 409 6 Bytes: 8 × 51 2 by tes (E ndpoi nt 2, 4,
6, 8).
3.6.2 Organization
• EP0–Bidirectional Endpoint 0, 64-byte buff er.
• EP2, 4, 6, 8–Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2 and EP6 can be either double-, triple-, or
quad-buffer ed. EP4 and EP8 c an only be do ubl e-buf fere d.
For high-speed endpoint configuration options, see
Figure 3-1.
Note:
3. if the descriptor loaded is set for remote wakeup enabled and the host does a set feature remote wakeup enabled, then the SX2 logic will perform RESUME
signalling after a WAKEUP interrupt.
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3.6.3 Endpoi nt Configurations (Hig h-speed Mode)
EP0 IN&OUT 64 64 64 64 64 64
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Group A
EP2
EP4
512
512
EP2
512
512
512
1024
512
EP2
512
1024
512
Group B
512
EP6
512
EP6
512
EP8
512
512
1024
512
EP6
512
1024
512
Figure 3-1. Endpoint Configuration
Endpoint 0 is the same for every configuration as it serves as
the CONTROL end point. For Endpoints 2, 4, 6, and 8, refer to
Figure 3-1. Endpoints 2, 4, 6, and 8 may be configured by
choosing eith er:
• One configuration from Group A and one from Group B
• One configuration from Group C.
Some example endpoi nt configurations are as foll ows.
• EP2: 1024 bytes double-buffered, EP6: 512 bytes quadbuffered.
• EP2: 512 bytes double-buffered, EP4: 512 bytes doublebuffered , EP6: 512 bytes doubl e-buf fere d, EP8: 512 bytes
double buffered.
• EP2: 1024 bytes quad-buf fered.
3.6.4 Default Endpoint Memory Configuration
At power-on-reset, the endpoint memories are configured as
follows:
• EP2: Bulk OUT, 512 bytes/packet, 2x buffered.
• EP4: Bulk OUT, 512 bytes/packet, 2x buffered.
• EP6: Bulk IN, 512 bytes/packet, 2x buffered.
• EP8: Bulk IN, 512 bytes/packet, 2x buffered.
3.7 External Interface
The SX2 presents two interfaces to the external master.
1. A FIFO interface thr ough which EP2, 4, 6, an d 8 data flows.
2. A command interf ace, which is used to set up the SX2, read
status, load descriptors, and access Endpoint 0.
Group C
EP2
EP6
EP8
512
512
512
EP2
512
512
512
512
EP8
512
1024
1024
1024
512
512
1024
1024
EP2
1024
1024
3.7.1 Architecture
The SX2 slave FIFO archit ecture has eight 512-byte blocks in
the endpoint RAM that directly serve as FIFO memories and
are controlled by FIFO control signals (IFCLK, CS#, SLRD,
SL WR, SLOE, PKTEND, and FIFOADR[2 :0]).
The SX2 command interface is used to set up the SX2, read
status, load descriptors, and access Endpoint 0. The
command interface has its own READY signal for gating
writes, and an INT# signa l to ind icate that the SX2 has data to
be read, or that an inter rupt event has occurred. The command
interface uses the same control signals (IFCLK, CS#, SLRD,
SLWR, SLOE, and FIFOADR[2:0]) as the FIFO interface,
except for PKTEND.
3.7.2 Control Signals
3.7.2.1 FIFOADDR Lines
The SX2 has three address pins that are used to select either
the FIFOs or the command interface. The addresses correspond to the following table.
Table 3-3. FIFO Address Lines Setting
Address/Selection FIFOADR2 FIFOADR1 FIFOADR0
FIFO2 0 0 0
FIFO4 0 0 1
FIFO6 0 1 0
FIFO8 0 1 1
COMMAND 1 0 0
RESERVED 1 0 1
RESERVED 1 1 0
RESERVED 1 1 1
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The SX2 accepts either an internally derived clock (30 or 48
MHz) or externally supplied clock (IFCLK, 5-50 MHz), and
SLRD, SLWR, SLOE, PKTEND, CS#, FIFOADR[2:0] signals
from an external master. The interface can be selected for 8or 16- bit operation by an internal configuration bit, and an
Output Enable si gnal SLOE enabl es the dat a bus dr iver of th e
selected width. The external master must ensure that the
output enable signal is inactive when writing data to the SX2.
The interface can operate either asynchronously where the
SLRD and SLWR signals act directly as strobes, or synchronously where the SLRD and SL W R act as clock quali fiers. The
optional CS# sig nal wi ll trista te t he d ata bu s a nd ign ore SLRD,
SL W R, PKTEND.
The external master reads from OUT endpoints and writes to
IN endpoints, and reads from or writes to the command
interface.
3.7.2.2 Read: SLOE and SLRD
In synchronous mode, the FIFO pointer is incremented on
each rising edge of IFCLK while SLRD is asserted. In
asynchronous mo de, the FIFO pointer i s incremented on each
asserted-to-deasserted transit ion of SLRD.
SLOE is a d ata bus dr iver enable. When SLOE i s asserte d, the
data bus is driven by the SX2.
3.7.2.3 Write: SLWR
In synchronous mode, data on the FD bus is written to the
FIFO (and the FIFO pointer is incremented) on each rising
edge of IFCLK while SLWR is asserted. In asynchronous
mode, data on t he FD bus i s writ ten t o the F IFO (and th e FIFO
pointer is incremented) on each asserted-to-deasserted
transition of SLWR.
3.7.2.4 PKTEND
PKTEND commits the current buffer to USB. To send a short
IN packet (one which has not been filled to max packet size
determined by the value of PL[X:0] in EPxPKTLENH/L), the
external maste r st robes the PKTEND pin.
All these interface signals have a default polarity of low. In
order to change the polarity of PKTEND pin, the master may
write to the POLAR register anytime. In order to switch the
polarity of the SLWR/SLRD/SLOE, the master must set the
appropriate bit s 2, 3 and 4 respectively in th e FIFOPINPOLAR
register locat ed at XDATA space 0xE609. Please note that the
SX2 powers up with the polarities set to low. Section 7.3
provides further information on how to access this register
located at XDATA space.
3.7.3 IFCLK
The IFCLK pin can be c onfigured to be either an i nput (def ault)
or an output interface clock. Bits IFCONFIG[7:4] define the
behavior of the interface clock. To use the SX2’s intern allyderived 30- or 48-MHz clock, set IFCONFIG.7 to 1 and set
IFCONFIG.6 to 0 (30 MHz) or to 1 (48 MHz). T o use an externally supplied clock, set IFCONFIG.7=0 and drive the IFCLK
pin (5 MHz – 50 MHz). The input or output IFCLK signal can
be inverted by setting IFCONFIG.4=1.
3.7.4 FIFO Access
An external master can access the slave FIFOs either
asynchronously or synchronously :
• Asynchronous–SLRD, SLWR, and PKTEND pins are
strobes.
• Synchronous–SLRD, SLWR, and PKTEND pins are enables for the IFCLK clock pi n.
An external master accesses the FIFOs throu gh the data bus,
FD [15:0]. This bus can be either 8- or 16-bits wide; the width
is selected via the WORDWIDE bit in the EPxPKTLENH/L
registers. The data bus is bidirectional, with its output drivers
controlled by the SLOE pin. The FIFOADR[2:0] pins select
which of the four FIFOs is connected to the FD [15:0] bus, or
if the command interface is selected.
3.7.5 FIFO Flag Pins Configurat ion
The FIFO flags are FLAGA, FLAGB, FLAGC, and FLAGD.
These FLAGx pins report the status of the FIFO selected by
the FIFOADR[2:0] pins. At reset , the se pins are configured to
report the status of the following:
• FLAGA reports the stat us of the programmable flag.
• FLAGB reports the stat us of the full flag.
• FLAGC reports the status of the empty flag.
• FLAGD defaults to the CS# function.
The FIFO flags can either be indexed or fixed. Fixed flags
report the status of a particular FIFO regardless of the value
on the FIFOADR [2:0] pins. Indexed flags report the status of
the FIFO selected by the FIFOADR [2:0] pins.
[4]
3.7.6 Default FIFO Programmab le Fl ag Set- up
By default, FLAGA is the Programmable Flag (PF) for the
endpoint being pointed to by the FIFOADR[2:0] pins. For EP2
and EP4, the default endpoint configuration is BULK, OUT,
512, 2x, and the PF pin asserts when the entire FIFO has
greater than/equal to 512 b yte s. For EP6 a nd EP8, the defaul t
endpoint configuration is BULK, IN, 512, 2x, and the PF pin
asserts when t he entir e FIFO has less than /equal t o 512 by tes.
In other words, EP6/8 report a half-empty state, and EP2/4
report a half-full state. The polarity of the programmable flag
is set to active low and cannot be altered.
3.7.7 FIFO Programmable Flag (PF) Set-up
Each FIFO’s programmable-level flag (PF) asserts when the
FIFO reaches a user-defined fullness threshold. That
threshold is configured as follows:
1. For OUT packets: The thres hold i s sto red in PFC12 :0. Th e
PF is asserted when the number o f bytes i n the entire FI FO
is less than/equal to (DECIS = 0) or greater than/equal to
(DECIS = 1) the threshold.
2. For IN packets, with PKTSTAT = 1: The th reshol d is st ored
in PFC9:0. The PF is asserted when the number of bytes
written into the current packet in the FIFO i s less than/equa l
to (DECIS = 0) or greater than/equal to ( D ECIS = 1) the
threshold.
3. For IN packets, with PKTSTAT = 0: The th reshol d is st ored
in two parts: PKTS2:0 holds the numbe r of committed packets, and PFC9:0 holds the number of bytes in the current
packet. The PF is asserted when the FIFO is at or less full
than (DECIS = 0), or at or more full than (DE C IS = 1), the
threshold.
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3.7.8 Command Protocol
An address of [1 0 0] on FIFOADR [2:0] will select the
command interface. The command interface is used to write
to and read from the SX2 registers and the Endpoint 0 buffer,
as well a s the des criptor RAM. Command read and write t ransactions occur over FD[7:0] only. Each byte written to the SX2
is either an address or a data byte, as determined by bit7. If
bit7 = 1, then the byte i s considered an address byte. If bit7 =
0, then the byte is considered a data byte. If bit7 = 1, then bit6
determines whether the address byte is a read request or a
write request. If bit6 = 1, then the byte is considered a read
request. If bit 6 = 0 then the byte is co nsider ed a write r equest.
Bits [5:0] hold the register address of the request. The format
of the command addre ss byte is shown in Table 3-4.
T able 3-4. Command Address Byte
Address/
Data#
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read/
Write# A5 A4 A3 A2 A1 A0
Each Write request is followed by two or more data bytes. If
another address byte is received before both data bytes are
received, t he SX2 ignores the first addr ess and any incompl ete
data transfers. The format for the data bytes is shown in
Table 3-5 and Table 3-6. Some registers take a series of byt es.
Each byte is transferred using the same protocol.
T able 3-5. Command Data Byte One
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 X X X D7 D6 D5 D4
T able 3-6. Command Data Byte T wo
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 X X X D3 D2 D1 D0
The first com mand data byt e contain s the upper nibble of data,
and the second command byte contains the lower nibble of
data.
3.7.8.1 Write Reques t Example
Prior to writing to a register, two conditions must be met:
FIFOADR[2:0] must hold [1 0 0], and the Ready line must be
HIGH. The external master should not initiate a command if
the READY pin is not in a HIgh state.
Example: to write the byte <10110000> into the IFCONFIG
register (0x01) , first send a command address byte as fol lows.
T able 3-7. Command Address Write Byte
Address/
Data#
Read/
Write# A5 A4 A3 A2 A1 A0
1 0000001
• The next six bits represent the register address (000001
binary = 0x01 hex).
Once the byte has been received the SX2 pulls the REA DY
pin low to inform the external master not to send any more
information. When the SX2 is ready to receive the next byte,
the SX2 pulls the READY pin high again. This next byte, the
upper nibble o f the d ata byt e, is writ ten to the SX2 as follows.
Table 3-8. Command Data Write Byte One
Address/
Data#
Don’t
Don’t
Care
0 XXX1011
Don’t
Care
Care D7 D6 D5 D4
• The first bit signifies that this is a data trans fer.
• The next three are don’t care bits.
• The next four bits hold th e upper nibble of the transferred
byte.
Once the byte has been received the SX2 pulls the REA DY
pin low to inform the external master not to send any more
information. When the SX2 is ready to receive the next byte,
the SX2 pulls the READY pin high again. This next byte, the
lower nibble of the data byte is written to the SX2.
Table 3-9. Command Data Write Byte Two
Address/
Data#
Don’t
Don’t
Care
0 XXX0000
Don’t
Care
Care D3 D2 D1 D0
At this point the entire byte <101 10000> has been transferred
to register 0x01 and the write sequence is complete.
3.7.8.2 Read Request Example
The Read cycle is simpler t han the write cycle. Th e Read cycl e
consists of a read reques t from the external master to t he SX2.
For example, to read the contents of register 0x01, a
command address byte is written to the SX2 as follows.
Table 3-10. Command Address Read Byte
Address/
Data#
Read/
Write# A5 A4 A3 A2 A1 A0
1 1000001
When the data is ready to be read, the SX2 asserts the INT#
pin to tell the external master that the data it requested is
waiting on FD[7:0].
[5]
• The first bit signifies an address transfer.
• The second bit signifie s that this is a write command.
Note:
4. In indexed mode, the value of the FLAGx pins is indeterminate except when addressing a FIFO (FIFOADR[2:0]={000,001,010,011}).
5. An important note: Once the SX2 receives a Read request, the SX2 allocates the interrupt line solely for the read request. If one of the six interrupt sources
described in Section 3.4 is asserted, the SX2 will buffer that interrupt until the read request completes.
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4.0 Enumeration
The SX2 has two modes of enumeration. The first mode is
automatic through EEPROM boot load, as described in
Section 3.3. The second method is a manual load of the
descriptor or VID, PID, and DID as described below.
4.1 Standard Enumeratio n
The SX2 has 500 bytes of descriptor RAM into which the
external master may write its descriptor. The descriptor RAM
is accessed through register 0x30. To load a descriptor, the
external maste r does the following:
• Initiate a Write Request to register 0x30.
• Write two bytes (four command data transf ers) that define
the length of the entire descriptor about to be transferred.
The LSB is written first , fo llowed by the MSB.
• Write the descriptor, one byte at a time until complete.
Note: the register address is only written once .
After the entire descriptor has been transferred, the SX2 will
float the pull-up resistor connected to D+, and parse through
the descriptor to locate the individual descriptors. After the
SX2 has parsed the e ntir e desc ript or , the SX2 wi ll con nect th e
pull-up resistor and enumerate automatically. When enumeration is complete, the SX2 will notify the external master with
an ENUMOK interrupt.
The format and order of the descriptor should be as follows
(see Section 12.0 for an example):
• Device.
• Device qualifier.
• High-speed configuration, high-speed interface, highspeed endpoints.
• Full-speed configuration, full-speed interface, full-speed
endpoints.
• String.
4.2 Default Enumeration
The external master may si mply l oad a VI D, PID, and DID an d
use the defau lt des cript or bui lt i nto t he SX2. To use the default
descriptor, the descriptor length described above must equal
6. After the external master has written the length, the VID,
PID, and DID must be written LSB, t hen MSB. For example, if
the VID, PID, and DID are 0x04B4, 0x1002, and 0x0001
respectively, then the external master does the following:
• Initiates a Writ e Request to register 0x30.
• Writes two byte s (four command d ata transf ers) that define
the length of the entire descriptor about to be transferred.
In this case, the length is always six.
• Writes the V ID, PID, and DID bytes: 0xB4, 0x04, 0x02, 0x10,
0x01, 0x00 (in nibble format per the command protocol).
The default descriptor is listed in Section 12.0. The default
descriptor can be used as a starting point for a custom
descriptor.
Note:
6. These and all other data bytes must conform to the command protocol.
[6]
[6]
5.0 Endpoint 0
The SX2 wi ll automatica lly respon d to USB chapter 9 request s
without any external master intervention. If the SX2 receives
a request to which it cannot respond automatically, the SX2
will notify the external master. The external master then has
the choice of respond ing to the request or stalling.
After the SX2 receives a set-up packet to which it cannot
respond automatically, the SX2 will assert a SETUP interrupt.
After the external master reads the Interrupt Status Byte to
determine that the interrupt source was the SETUP interrupt,
it can initiate a read request to the SETUP register, 0x32.
When the SX2 sees a read request for the SETUP register, it
will present the first byte of set- up data to the external mast er.
Each additional read request will present the next byte of setup data, until all eight bytes have been read.
The external master can stall this request at this or any other
time. To stall a request, the external master initiates a write
request for the SETUP regi ster , 0x32, an d writes any non-zer o
value to the register.
If this set-up request has a data phase, the SX2 will then
interrupt the external master with an EP0BUF interrupt when
the buffer becomes available. The SX2 determines the
direction of the set -up request and interrupts when either:
• IN: the Endpoint 0 buff er becomes available to write to, or
• OUT : the Endpoint 0 buf fer r eceives a pac ket from the USB
host.
For an IN set-u p transaction, the external master can write up
to 64 bytes at a time for the data phase. The steps to write a
packet are as follows:
1. Wait for a n EP0BUF inte rrupt , indicat ing t hat the b uff er is
available.
2. Initiate a write request for register 0x31.
3. Write one data byte .
4. Repeat steps 2 and 3 until either all the data or 64 bytes
have been written, whichever is less.
5. Write the numbe r of byt es i n thi s packet to the b yt e count
register, 0x33.
T o se nd more than 64 byt es, the pr ocess is rep eated. The SX2
internally stores the length of the data phase that was
specified in the wLength field (bytes 6,7) of the set-up packet .
To send less than the requested amount of data, the external
master writes a packet that is less than 64 bytes, or if a multi ple
of 64, the external master follows the data with a zero-length
packet. When the SX2 sees a short or zero-length packet, it
will complete the set-up transfer by automatically completing
the handshake phase. The SX2 will not allow more data than
the wLength field specified in the set-up packet. Note: the
PKTEND pin does not apply to Endpoint 0. The only way to
send a short or zero length packet is by writing to the byte
count register with the appropriate value.
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For an OUT set-up transaction, the external master can read
each packet received from the USB host during the data
phase. The steps to re ad a packet are as follows:
1. Wait f or an EP0BUF inte rrupt, indicati ng that a pac ket was
received from the US B host i nto the buffer.
2. Initiate a read re quest for the byte count regis ter, 0x33.
This indicates the amount of data received from the host.
3. Initiate a read re quest for register 0x31.
4. Read one byte.
5. Repeat steps 3 and 4 until the number of b ytes specified
in the byte count register has been read.
To receive more than 64 bytes, the process is repeated. The
SX2 internally stores the length of the data phase that was
specified in the wLength field of the set-up packet (bytes 6,7 ).
When the SX2 sees that the specified number of bytes have
been received, it will complete the set-up transfer by automatically comple ting the handshake phase. If the external master
does not wish to receive the entire transfer, it can stall the
transfer.
If the SX2 receives another set-up packet before the current
transfer has complet ed, it will int errupt the external master wi th
another SETUP in te rrupt. If the SX2 receives a set-up packet
with no data phase, the externa l master can accept the packet
and complete the handshak e pha se b y writ ing z ero t o the b yt e
count register.
The SX2 auto maticall y responds to all USB standard requests
covered in chapter 9 of the
USB 2.0 specification except the
Set/Clear F eature Endpoint r equests. When the host issues a
Set Feature or a Clear feature request, the SX2 will trigger a
SETUP interrupt to the external master. The USB spec
requires that the device respond to the Set endpoint feature
request by doing the fol lowing:
• Set the STALL condition on that endpoin t.
The USB spec requires that the device respond to the Clear
endpoint feature request by doing the following:
• Reset the Data Toggle for that endpoint
• Clear the STALL condition of that end point.
The register that is used to reset the data toggle TOGCTL
(located at XDATA location 0xE683) is not an index register
that can be addressed by the command protocol presented in
Section 3.7.8. The following section provides further information on this register bits and how to reset the data toggle
accordingly using a different set of command protocol
sequence.
5.1 Resetting Data Toggle
Following is the bi t def inition of the TOGCTL regis ter:
TOGCTL
Bit #
Bit Name Q S R I/O EP3 EP2 EP1 EP0
Read/Write R W W R/W R/W R/W R/W R/W
Default 00110010
7 6 5 4 3 2 1 0
Bit 7: Q, Data Toggle Value
Q=0 indicates DATA0 and Q=1 indicates DATA1, for the
endpoint sele cted by the I/O and EP3:0 bit s. Write the endpoi nt
select bits (IO and EP3: 0), before reading this value.
0xE683
Bit 6: S, Set Data Toggle to DATA1
After selecting the desired endpoint by writing the endpoint
select bits (IO and EP3:0), set S=1 to set the data toggle to
DATA1. The endpoint selection bits should not be changed
while thi s bit is wr itt e n.
Bit 5: R, Set Data Toggle to DATA0
Set R=1 to set the data toggle to DATA0. The endpoint
selection bits should not be changed while this bit is written.
Bit 4: IO , Select IN or OUT Endpoint
Set this bit to sel ect an endpoint direction prior to sett ing its R
or S bit. IO=0 selects an OUT endpoint, IO = 1 selects an IN
endpoint.
Bit 3-0: EP3:0, Select Endpoint
Set these bits to select an endpoint prior to setting its R or S
bit. Valid values are 0, 1, 2, , 6, and 8.
A two-step process is employed to clear an endpoint data
toggle bit to 0. First, write to the TOGCTL register with an
endpoint address (EP3 :EP0) plus a dire ction bit (IO ). Keeping
the endpoint and direction bits the same, write a “1” to the R
(reset) bit. For example, to clear the data toggle for EP6
configured as an “IN” endpoint, write the following values
sequentially to TOGCTL:
00010110b
00110110b
Following is the sequence of events that the master should
perform to set this register to 0x16:
(1) Send Low Byte of the Register (0x83)
• Command address write of address 0x3A
• Command data writ e of upper nibble of the Low Byte of
Register Address (0x08)
• Command data writ e of l ower nibble of the Low Byte of
Register Address (0x03)
(2) Send High Byte of the Register (0xE6)
• Command address write of address 0x3B
• Command data writ e of upper nibble of the High Byte of
Register Address (0x0E)
• Command data write of l ower nibble of the High Byte of
Register Address (0x06)
(3) Send the actual value to write to the register Register (in
this case 0x16)
• Command address write of address0x3C
• Command data writ e of upper nibble of the High Byte of
Register Address (0x01)
• Command data writ e of l ower nibble of the High Byte of
Register Address (0x06)
The same command sequence needs to be followed to set
TOGCTL register to 0x36. The same command protocol
sequence can be used to reset the data toggle for the other
endpoints. In order to read the status of this register, the
external master must do the following sequence of event s:
(1) Send Low Byte of the Register (0x83)
• Command address write of 0x3A
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• Command data write of upper nibble of the Low Byte of
Register Address (0x08)
• Command data write of lower nibble of the Low Byte of
Register Address (0x03)
(2) Send High Byte of the Register (0xE6)
• Command address writ e of address 0x3B
• Command data write of upper nibble of the High Byte of
Register Address (0x0E)
• Command data write of lowe r ni bble of the High Byte of
Register Address (0x06)
(3) Get the actual value from the TOGCTL regist er (0x16)
• Command address READ of 0x3C
6.0 Pin Assignments
6.1 56-pin SSOP
CY7C6800
1
FD13
2
FD14
3
FD15
4
GND
5
NC
6
VCC
7
GND
8
*SLRD
9
*SLWR
10
AVCC
11
XTALOUT
12
XTALIN
13
AGND
14
VCC
15
DPLUS
16
DMINUS
17
GND
18
VCC
19
GND
20
*IFCLK
21
RESERVED
22
SCL
23
SDA
24
VCC
25
FD0
26
FD1
27
FD2
28
FD3
*WAKEUP
*FLAGD/CS#
FIFOADR1
FIFOADR0
FIFOADR2
CY7C68001
56-pin SSOP
FD12
FD11
FD10
FD9
FD8
VCC
RESET#
GND
*PKTEND
*SLOE
INT#
READY
VCC
*FLAGC
*FLAGB
*FLAGA
GND
VCC
GND
FD7
FD6
FD5
FD4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Figure 6-1. CY7C68001 56-pin SSOP Pin Assignment
Note:
7. A * denotes programmable polarity.
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6.2 56-pin QFN
GND
56
VCC
55
FOR
FOR
CY7C6800
*
WAKEUP
FD15
FD14
FD13
FD12
FD11
NC
54
GND
53
52
51
50
49
FD10
484547
FD9
46
44
VCC
43
FD8
SLRD
*
SLW R
*
AVCC
XTAL O U T
XTAL IN
AGND
VCC
DPLUS
DMINUS
GND
VCC
GND
IFCLK
*
RESERVED
10
11
12
13
14
1
2
3
4
5
6
7
8
9
17
15
SCL
16
SDA
18
VCC
FD0
CY7C68001
56-pin Q FN
19
202721
FD1
FD2
FD3
22
FD4
23
FD5
24
FD6
25
FD7
26
GND
28
VCC
GND
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RESET#
GND
FLAGD/CS#
*
PKTEND
*
FIFOAD R1
FIFOAD R0
FIFOAD R2
SLOE
*
INT#
READY
VCC
FLAGC
*
FLAGB
*
FLAGA
*
Figure 6-2. CY7C68001 56-pi n QF N Assignment
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6.3 CY7C68001 Pin Definitions
T able 6-1. SX2 Pin Definitions
QFN
SSOP
Pin
Pin Name Type Default Description
3 10 AVCC Power N/A Analog V
6 13 AGND Power N/A Analog Ground. Connect to ground with as short a path as possible.
9 16 DMINUS I/O/Z Z USB D– Signal. Connect to the USB D– signal.
815DPLUSI/O/Z ZUSB D+ Signal. Connect to the USB D+ signal.
42 49 RESET# Input N/A Active LOW Reset. Rese ts the entire chip. This pin is normally tied to V
through a 100K resi stor, and to GND through a 0.1-µF capacitor.
5 12 XTALIN Input N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental
mode crys tal and 20-pF capacitor to GND. It is also correct to drive XTALIN with
an external 24- MHz square wave derived from anothe r cl ock source.
4 11 XTALOUT Output N/A Crystal Output. Conn ect this signa l to a 24 -MHz parall el-reso nant , fun dament al
mode crystal and 20- pF capacitor to GND. If an external clock is used to drive
XTALIN, leave this pin open.
54 5 NC Output O No Connect. This pin must be left unconnected.
. This signal provi des power to the analog section of the chip.
CC
CC
33 40 READY Output L READY is an output-only ready that gates external command reads and writes.
Active High.
34 41 INT# Output H INT# is an output-only external interrupt signal. Active Low.
35 42 SLOE Input I SLOE is an input-onl y output enable with programmable polarity (POLAR.4) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
36 43 FIFOADR2 Input I FIFOADR2 is an input-only address select for the slav e FIFOs connected to
FD[7:0] o r FD [ 1 5: 0 ].
37 44 FIFOADR0 Input I FIFOADR0 is an input-only address select for the slav e FIFOs connected to
FD[7:0] o r FD [ 1 5: 0 ].
38 45 FIFOADR1 Input I FIFOADR1 is an input-only address select for the slav e FIFOs connected to
FD[7:0] o r FD [ 1 5: 0 ].
39 46 PKTEND Input I PKTEND is an input-only packet end with programmable polari ty (POLAR.5) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
40 47 FLAGD/CS#CS#:I
FLAGD:O
I FLAGD is a programmable slave- FIFO output status f lag signal. CS# is a mast er
chip select (default).
18 25 FD[0] I/O/Z I FD[0] is the bidirectional FIFO/Command data bus.
19 26 FD[1] I/O/Z I FD[1] is the bidirectional FIFO/Command data bus.
20 27 FD[2] I/O/Z I FD[2] is the bidirectional FIFO/Command data bus.
21 28 FD[3] I/O/Z I FD[3] is the bidirectional FIFO/Command data bus.
22 29 FD[4] I/O/Z I FD[4] is the bidirectional FIFO/Command data bus.
23 30 FD[5] I/O/Z I FD[5] is the bidirectional FIFO/Command data bus.
24 31 FD[6] I/O/Z I FD[6] is the bidirectional FIFO/Command data bus.
25 32 FD[7] I/O/Z I FD[7] is the bidirectional FIFO/Command data bus.
45 52 FD[8] I/O/Z I FD[8] is the bidirectional FIFO data bus.
46 53 FD[9] I/O/Z I FD[9] is the bidirectional FIFO data bus.
47 54 FD[10] I/O/Z I FD[10] is the bidir ectional FIFO data bus.
48 55 FD[11] I/O/Z I FD[11] is the bidirectional FIFO data bus.
49 56 FD[12] I/O/Z I FD[12] is the bidir ectional FIFO data bus.
50 1 FD[13] I/O/Z I FD[13] is the bidirectional FIFO data bus.
51 2 FD[14] I/O/Z I FD[14] is the bidirectional FIFO data bus.
52 3 FD[15] I/O/Z I FD[15] is the bidirectional FIFO data bus.
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T able 6-1. SX2 Pin Definitions (continued)
QFN
SSOP
Pin
Pin Name Type Default Description
1 8 SLRD Input N/A SLRD is the input-only re ad strobe with programmable polari ty (POLAR.3) for the
slave FIFOs connected to FD[7:0] or FD[15:0].
2 9 SLWR Input N/A SLWR is the input-only write strobe with programmable polarity (POLAR.2) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
29 36 FLAGA Output H FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to PF for the FIFO se lected by th e FIFOADR [2:0] pins.
30 37 FLAGB Output H FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[2:0] pins.
31 38 FLAGC Output H FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[2:0] pins.
13 20 IFCLK I/O/Z Z Interface Clock, used for synchronously clocking data into or out of the slave
FIFOs. IFCLK al so serves as a tim ing referenc e for all slave FI FO control signals.
When using the internal clock reference (IFCONFIG.7=1) the IFCLK pin can be
configured to outp ut 30/48 MHz by setting bits IFCONFIG.5 and IFCONFIG.6.
IFCLK may be inver ted by se ttin g the bit IFCONFIG. 4=1. Pro grammable po lari ty.
14 21 Reserved Input N/A Reserved. Must be connected to ground.
44 51 WAKEUP Input N/A USB Wakeup. If th e SX2 is in suspend, asserting thi s pin starts up the oscill ator
15 22 SCL OD Z I
16 23 SDA OD Z I
and interrup ts t he SX2 to al low i t to exit the suspend mode. During normal
operation, ho lding W AKEUP asserted inhi bits the SX2 chip fro m suspending. This
pin has programmable polarity (POLAR.7).
2
C Clock. Connec t to V
EEPROM is attached.
2
C Data. Connect to V
is attached.
with a 2.2K-10 K Ohms resistor, even if no I2C
CC
with a 2. 2K-10 K Ohms res istor , even if no I2C EEPROM
CC
55 6 V
714 V
11 18 V
17 24 V
27 34 V
32 39 V
43 50 V
CC
CC
CC
CC
CC
CC
CC
Power N/A VCC. Connect to 3.3V power source.
Power N/A VCC. Connect to 3.3V power source.
Power N/A VCC. Connect to 3.3V power source.
Power N/A VCC. Connect to 3.3V power source.
Power N/A VCC. Connect to 3.3V power source.
Power N/A VCC. Connect to 3.3V power source.
Power N/A VCC. Connect to 3.3V power source.
53 4 GND Ground N/A Connect to ground.
56 7 GND Ground N/A Connect to ground.
10 17 GND Ground N/A Connect to ground.
12 19 GND Ground N/A Connect to ground.
26 33 GND Ground N/A Connect to ground.
28 35 GND Ground N/A Connect to ground.
41 48 GND Ground N/A Connect to ground.
Document #: 38-08013 Rev. *E Page 13 of 42
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