Cypress CY7C68000A User Manual
CY7C68000A
MoBL-USB™ TX2 USB 2.0 UTMI
Transceiver
MoBL-USB™ TX2 Features
Tri_state
Logic Block Diagram
■ UTMI-compliant and USB 2.0 certified for device operation
■ Operates in both USB 2.0 High Speed (HS), 480 Mbits/second,
and Full Speed (FS), 12 Mbits/second
■ Optimized for Seamless Interface with Intel
cations Processors
■ Tri-state Mode enables sharing of UTMI Bus with other devices
■ Serial-to-Parallel and Parallel-to-Serial Conversions
■ 8-bit Unidirectional, 8-bit Bidirectional, or 16-bit Bidirectional
External Data Interface
■ Synchronous Field and EOP Detection on Receive Packets
■ Synchronous Field and EOP Generation on Transmit Packets
■ Data and Clock Recovery from the USB Serial Stream
■ Bit stuffing and unstuffing; Bit Stuff Error Detection
■ Staging Register to manage Data Rate variation due to Bit
stuffing and unstuffing
■ 16-bit 30 MHz and 8-bit 60 MHz Parallel Interface
■ Ability to switch between FS and HS terminations and signaling
■ Supports detection of USB Reset, Suspend, and Resume
■ Supports HS identification and detection as defined by the USB
2.0 Specification
®
Monahans Appli-
■ Supports transmission of Resume Signaling
■ 3.3V Operation
■ Two package options: 56-pin QFN and 56-pin VFBGA
■ All required terminations, including 1.5 Kohm pull up on
DPLUS, are internal to chip
■ Supports USB 2.0 Test Modes
The Cypress MoBL-USB TX2 is a Universal Serial Bus (USB)
specification revision 2.0 transceiver, serial and deserializer, to a
parallel interface of either 16 bits at 30 MHz or eight bits at 60
MHz. The MoBL-USB TX2 provides a high speed physical layer
interface that operates at the maximum allowable USB 2.0
bandwidth. This enables the system designer to keep the
complex high speed analog USB components external to the
digital ASIC. This decreases development time and associated
risk. A standard USB 2.0-certified interface is provided and is
compliant with Transceiver Macrocell Interface (UTMI) specification version 1.05 dated 3/29/2001.
This product is also optimized to seamlessly interface with
Monahans -P & -L applications processors. It has been characterized by Intel and is recommended as the USB 2.0 UTMI transceiver of choice for its Monahans processors. It is also capable
of tri-stating the UTMI bus, while suspended, to enable the bus
to be shared with other devices.
Two packages are defined for the family: 56-pin QFN and 56-pin
VFBGA.
The functional block diagram follows.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08052 Rev. *G Revised October 5, 2008
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Applications
Mobile Applications
■ Smart Phones
■ PDA Phones
■ Gaming Phones
■ MP3 players
■ Portable Media Players (PMP)
■ GPS Tracking Devices
Consumer Applications
■ Cameras
■ Scanners
■ DSL Modems
■ Memory Card Readers
Non-Consumer Applications
■ Networking
■ Wireless LAN
■ Home PNA
Functional Overview
The functionality of this chip is described in the following
sections:
USB Signaling Speed
The MoBL-USB TX2 operates at two of the rates defined in the
USB Specification 2.0, dated 4/27/2000.
■ Full speed, with a signaling bit rate of 12 Mbps
■ High speed, with a signaling bit rate of 480 Mbps
The MoBL-USB TX2 does not support the LS signaling rate of
1.5 Mbps.
Transceiver Clock Frequency
The MoBL-USB TX2 has an on-chip oscillator circuit that uses
an external 24 MHz (±100 ppm) crystal with the following characteristics:
■ Parallel resonant
■ Fundamental mode
■ 500 μW drive level
■ 27 to 33 pF (5% tolerance) load capacitors
An on-chip phase-locked loop (PLL) multiplies the 24 MHz oscillator up to 30 or 60 MHz, as required by the transceiver parallel
data bus. The default UTMI interface clock (CLK) frequency is
determined by the DataBus16_8 pin.
Buses
The two packages enable a 8- or 16-bit bidirectional data bus for
data transfers to a controlling unit.
Suspend and Tri-state Modes
When the MoBL-USB TX2 is not in use, the processor reduces
power consumption by putting it into Suspend mode using the
Suspend pin.
While in Suspend mode, Tri-state mode may be enabled, which
tri-states all outputs and IOs, enabling the UTMI interface pins to
be shared with other devices. This is valuable in mobile handset
applications, where GPIOs are at a premium. The outputs and
IOs are tri-stated ~50ns when Tri-state mode is enabled, and are
driven ~50ns when Tri-state mode is disabled. All inputs must not
be left floating while in Tri-state mode.
When resuming after a suspend, the PLL stabilizes approximately 200 μs after the suspend pin goes high.
Reset Pin
An input pin (Reset) resets the chip. This pin has hysteresis and
is active HIGH according to the UTMI specification. The internal
PLL stabilizes approximately 200 μs after V
has reached 3.3V.
CC
Line State
The Line State output pins LineState[1:0] are driven by combinational logic and may be toggling between the ‘J’ and the ‘K’
states. They are synchronized to the CLK signal for a valid
signal. On the CLK edge, the state of these lines reflect the state
of the USB data lines. Upon the clock edge the ‘0’ bit of the
LineState pins is the state of the DPLUS line and the ‘1’ bit of
LineState is the DMINUS line. When synchronized, the setup
and hold timing of the LineState is identical to the parallel data
bus.
Full-speed versus High-speed Select
The FS versus HS is done through the use of both XcvrSelect
and the TermSelect input signals. The TermSelect signal enables
the 1.5 Kohm pull up on to the DPLUS pin. When TermSelect is
driven LOW, a SE0 is asserted on the USB providing the HS
termination and generating the HS Idle state on the bus. The
XcvrSelect signal is the control that selects either the FS transceivers or the HS transceivers. By setting this pin to a ‘0’ the HS
transceivers are selected and by setting this bit to a’1’ the FS
transceivers are selected.
Document #: 38-08052 Rev. *G Page 2 of 15
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Operational Modes
The operational modes are controlled by the OpMode signals.
The OpMode signals are capable of inhibiting normal operation
of the transceiver and evoking special test
take effect immediately and take precedence over any pending
data operations. The transmission data rate when in OpMode
depends on the state of the XcvrSelect input.
OpMode[1:0] Mode Description
00 0 Normal operation
01 1 Non-driving
10 2 Disable Bit Stuffing and NRZI
encoding
11 3 Reserved
modes. These modes
Mode 0 enables the transceiver to operate with normal USB data
decoding and encoding.
Mode 1 enables the transceiver logic to support a soft disconnect
feature that tri-states both the HS and FS transmitters, and
removes any termination from the USB, making it appear to an
upstream port that the device is disconnected from the bus.
Mode 2 disables Bit Stuff and NRZI encoding logic so ‘1’s loaded
from the data bus becomes ‘J’s on the DPLUS/DMINUS lines
and ‘0’s become ‘K’s.
DPLUS/DMINUS Impedance Termination
The CY7C68000A does not require external resistors for USB
data line impedance termination or an external pull up resistor on
the DPLUS line. These resistors are incorporated into the part.
They are factory trimmed to meet the requirements of USB 2.0.
Incorporating these resistors also reduces the pin count on the
part.
Document #: 38-08052 Rev. *G Page 3 of 15
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Pin Configurations
D4
D3
V
CC
D2
Reserved
D1
D0
CLK
DataBus16_8
Uni_bidi
GND
TXValid
V
CC
ValidH
28
27
26
25
24
23
22
21
20
19
18
17
16
15
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
D5
Reserved
D6
D7
D8
D9
Reserved
D10
D11
V
CC
D12
GND
D13
TXReady
Suspend
Reset
AV
CC
XTALOUT
XTALIN
AGND
AV
CC
DPLUS
DMINUS
AGND
XcvrSelect
TermSelect
OpMode0
V
CC
D14
D15
Reserved
Tri_state
RXError
RXActive
RXValid
GND
LineState1
LineState0
V
CC
GND
OpMode1
CY7C68000A
56-pin QFN
The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin VFBGA packages.
The packages offered use either an 8-bit (60 MHz) or 16-bit (30 MHz) bus interface.
Figure 1. CY7C68000A 56-pin QFN Pin Assignment
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Figure 2. CY7C68000A 56-pin VFBGA Pin Assignment
12345678
A
B
C
D
E
F
G
H
1A 2A 3A 4A 5A 6A 7A 8A
1B 2B 3B 4B 5B 6B 7B 8B
1C 2C 3C 4C 5C 6C 7C 8C
1D 2D 7D 8D
1E 2E 7E 8E
1F 2F 3F 4F 5F 6F 7F 8F
1G 2G 3G 4G 5G 6G 7G 8G
1H 2H 3H 4H 5H 6H 7H 8H
Document #: 38-08052 Rev. *G Page 5 of 15
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