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CY7C6800 0
CY7C6800
TX2™ USB 2.0 UTMI Transceiv
1.0 EZ-USB TX2™ Features
The Cypress EZ-USB TX2™ is a Universal Serial Bus (USB)
specifica tion revisi on 2.0 tran sceiver, serial/d eserializer, to a
parallel interface of either 16 bits at 30 MHz or ei ght bits at 60
MHz. The TX2 provides a high-speed physical layer interface
that operates at the maximum allowable USB 2.0 bandwidth.
This allows the system designer to keep the complex highspeed analog USB components external to the digital ASIC
which decreases development time and associated risk. A
standard interface is provided that is USB 2.0-certified and is
compliant with Transceiver Macrocell Interface (UTMI) specification version 1.05 dated 3/29/01.
Two p ackages are defi ned for the fami ly: 56-pin SSOP and 56pin QFN.
The function block diagram is shown in Figure 1-1. The
features of the EX-USB TX2 are:
• UTMI-compliant/USB-2.0-certified for device operation
• Operates in both USB 2.0 high speed (HS), 480
Mbits/second, and full speed (FS), 12 Mbits/second
• Serial-to-parallel and parallel-to-serial conversions
• 8-bit unidirectional, 8-bit bidirectional, or 16-bit
bidirectional external data interface
CY7C68000
• Synchronous field and EOP detection on receive
packets
• Synchronous field and EOP generation on transmit
packets
• Data and clock recovery from the USB serial stream
• Bit stuffing/unstuffing; bit stuff error detection
• Staging register to manage data rate variation due to
bit stuffing/unstuffing
• 16-bit 30-MHz, and 8-bit 60-MHz parallel interface
• Ability to switch betwee n F S an d HS te rmin ation s a nd
signaling
• Supports detec tion of USB reset, suspend, and resume
• Supports HS identification and de tection as defined by
the USB 2.0 Specification
• Supports transmission of resume signaling
• 3.3 V operation
• Two package options—56-pin QFN, and 56-pin SSOP
• All required terminations, including 1.5K-ohm pull up
on DPLUS, are internal to the chip
• Supports USB 2.0 test modes
XTALIN/
OUT
USB
OSC
USB
2.0
XCVR
20X
PLL
Full-Speed Rx
High-Speed Rx
High-Speed Tx
PLL_480
Traffic
Sync
Elasticity
Buffer
Fast
Digital
Rx
Fast
UTMI CLK
Digital
Rx
UTMI CLK
UTMI Rx Ctl
UTMI Rx Data 8/16
BIDI Option
Also
Digital
Full-Speed Tx
Tx
Digital
Tx
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08016 Rev. *H Revised May 2, 2006
Tx
UTMI Rx Data 8/16
UTMI Tx Ctl
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CY7C6800
2.0 Applications
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Home PNA
• Wireless LAN
• MP3 players
•Networking
3.0 Functional Overview
3.1 USB Signaling Speed
TX2 operates at two of the rates defined in the USB Specification 2.0, dated April 27, 2000:
• Full speed, with a signaling bit rate of 12 Mbps
• High speed, with a signaling bit rate of 480 Mbps
TX2 does not support the lo w-sp eed (LS) si gnalin g rate of 1.5
Mbps.
3.2 Transceiver Clock Frequency
TX2 has an on-chip oscillator circuit that uses an external 24MHz (±100-ppm) crystal with the following characteristics:
• Parallel resonant
• Fundamental mode
•500-μW drive lev el
• 27–33 pF (5% tolerance) load capacitors
An on-chip phase-locked loop (PLL) multiplies the 24-MHz
oscillator up to 30/60 MHz, as required by the transceiver
parallel data bus. The default UTMI interface clock (CLK)
frequency is determined by the DataBus16_8 pin.
3.3 Buses
The two packages allow for 8/16-bit bidirectional data bus for
data transfe rs to a controlling unit.
3.4 Reset Pin
An input pin (Reset) resets the chip. This pin has hysteresis
and is active HIGH according to the UTMI specification. The
internal PLL stabilizes approximately 200 μs after V
reached 3.3V.
3.5 Line State
The Line S tat e output pins Line S t ate[1:0] ar e driven by com binational logic and may be toggling between the J and the K
states. They are synchronized to the CLK signal for a valid
CC
has
signal. On the CLK edge the state of these lines reflect the
state of the USB data lines. Upon the clock edge the 0-bit of
the LineState pins is the state of the DPLUS line and the one
bit of Lin eState is the DMINU S li ne. Wh en syn chron ized, the
set up and hold timing of the LineState is identical to the
parallel data bus.
3.6 Full-speed vs. High-speed Select
The FS vs. HS is done through the use of bo th XcvrSelect and
the TermSelect input signals. The TermSelect signal enables
the 1.5 K ohm pull up on to the D PLUS pin . When TermSele ct
is driven LOW , a SE0 is asserted on the USB provi ding the HS
termination and generating the HS Idle state on the bus. The
XcvrSelect signal is the control which selects either the FS
transceivers or the HS transceivers. To select the HS transceivers, set this pin to ‘0’. To select the FS transceivers, set
this pin to ‘1’.
3.7 Operational Modes
The operational m odes ar e controll ed by the O pMode sign als.
The OpMode signals are capable of inhibiting normal
operation of the transceiver and evoking special test
These modes take effect immediately and take precedence
over any pending dat a op eration s. The tran smissi on dat a rate
when in OpMode depends on the state of the XcvrSelect
input.
OpMode[1:0] Mode Description
00 0 Normal operation
01 1 Non-driving
10 2 Disable Bit Stuffing and
11 3 Reserved
Mode 0 allows the transceiver to operate with normal USB
data decoding and encoding.
Mode 1 allows the transceiver logic to support a soft
disconnect feature which three-states both the HS and FS
transmitters, and removes any termination from the USB,
making it appear t o an up stream port that th e device h as been
disconnected from the bus.
Mode 2 disables Bit Stuff and NRZI encoding logic so 1s
loaded from the dat a bus becomes Js on the DPLUS/DMINUS
lines and 0s become Ks.
NRZI encoding
modes.
4.0 DPLUS/DMINUS Impedance Termination
The CY7C68000 does not require external resistors for USB
data line i mpedanc e term inati on or an e xternal pul l up resistor
on the DPLUS line. These resistors are incorporated into the
part. They are factory trimmed to meet the requirements of
USB 2.0. Incorporating these resistors also reduces the pin
count on the part.
Document #: 38-08016 Rev. *H Page 2 of 14
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CY7C6800
5.0 Pin Assignments
The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin SSOP packages.
The packages offered use either an 8-bit (60-MHz) or 16-bit (30-MHz) bus interface.
56-pin QFN
DataBus16_8
TXReady
Suspend
Reset
AV
CC
XTALOUT
XTALIN
AGND
AV
CC
DPLUS
DMINUS
AGND
XcvrSelect
10
11
12
V
CC
55
TXValid
54
ValidH
56
1
2
3
4
5
6
7
8
9
GND
53
Uni_bidi
51
52
CY7C68000
56-pin QFN
CLK
50
D0
49
D1
48
Reserved
47
D2
46
V
CC
45
D3
44
D4
43
42
41
40
39
38
37
36
35
34
33
32
31
GND
D5
Reserved
D6
D7
D8
D9
Reserved
D10
D11
V
CC
D12
TermSelect
OpMode0
Document #: 38-08016 Rev. *H Page 3 of 14
13
14
25
24
23
22
21
20
19
18
17
16
15
Reserved
Reserved
RXError
RXActive
RXValid
GND
LineState1
LineState0
V
GND
OpMode1
CC
Figure 5-1. CY7C68000 56-pin QFN Pin Assignment
26
D15
27
D14
28
V
CC
30
29
GND
D13
0
56-pin SSOP
CY7C6800
1
CLK
2
DataBus16_8
3
Uni_Bidi
4
GND
5
TXValid
6
V
7
ValidH
8
TXReady
9
Suspend
10
Reset
11
AVCC
12
XTALOUT
13
XTALIN
14
AGND
15
AVCC
DPLUS
16
DMINUS
17
AGND
18
XcvrSelect
19
TermSelect
20
21
OpMode0
22
OpMode1
23
GND
24
V
LineState0
25
LineState1
26
GND
27
RXValid
28
56
D0
55
D1
V
GND
D10
D11
V
D12
GND
D13
V
D14
D15
54
53
D2
52
CC
51
D3
50
D4
49
48
D5
47
46
D6
45
D7
44
D8
43
D9
42
41
40
39
CC
38
37
36
35
CC
34
33
32
31
30
29
Reserved
CC
Reserved
Reserved
CC
Reserved
Reserved
RXError
RXActive
Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment
5.1 CY7C68000 Pin Descriptions
Table 5-1. Pin Descriptions
SSOP QFN Name Type Default Description
11 4 AVCC Power N/A Analog V
15 8 AVCC Power N/A Analog V
14 7 AGND Power N/A Analog Ground. Connect to ground with as short a path as possible.
18 11 AGND Power N/A Analog Ground. Connect to ground with as short a path as possible.
16 9 DPLUS I/O/Z Z USB DPLUS Signal. Connect to the USB DPLUS signal.
17 10 DMINUS I/O/Z Z USB DMINUS Signal. Connect to the USB DMINUS signal.
Note:
1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure
signals at power-up and in standby.
Document #: 38-08016 Rev. *H Page 4 of 14
[1]
. This signal provides power to the analog section of the chip.
CC
. This signal provides power to the analog section of the chip.
CC
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CY7C6800
Table 5-1. Pin Descriptions (continued)
SSOP QFN Name Type Default Description
56 49 D0 I/O Bidirectional Data Bus. This bidirectional bus is used as the entire data
55 48 D1 I/O
53 46 D2 I/O
51 44 D3 I/O
50 43 D4 I/O
48 41 D5 I/O
46 39 D6 I/O
45 38 D7 I/O
44 37 D8 I/O Bidirectional Data Bus. This bidirectional bus is used as the upper eight
43 36 D9 I/O
41 34 D10 I/O
40 33 D11 I/O
38 31 D12 I/O
36 29 D13 I/O
34 27 D14 I/O
33 26 D15 I/O
1 50 CLK Output Clock. This output is used for clocki ng the receive and transmit paralle l data
10 3 Reset Input N/A Active HIGH Reset. Resets the entire chip. This pin can be tied to V
19 12 XcvrSelect Input N/A T ransceiver Select. This signal selects between the Full Speed (FS) and
20 13 TermSelect Input N/A Termination Select. This signal selects between the between the Full
9 2 Suspend Input N/A Suspend. Places the CY7C68000 in a mod e that draws minimal power from
26 19 LineState1 Output Line State. These signals reflect the current state of the single-ended
25 18 LineState0 Output Line State. These signals reflect the current state of the single-ended
[1]
bus in the 8-bit bi direction al mode or th e least sig nificant eig ht bits i n the 16bit mode or under the 8-b it unidirectional mode these bits are us ed as inputs
for data, selected by the RxValid signal.
bits of the d ata bu s when i n the 16-bit m ode, and not use d when in the 8-bi t
bidirectional mode . Un der th e 8-b it un idir ectio nal mod e the se b its are used
as outputs for data, selected by the TxValid signal.
on the D[15:0] bus.
through a 0.1 μF capacitor and to GN D through a 100 K resistor for a 10
msec RC time constant.
the High Speed (HS) transceivers:
0: HS transceiver enabled
1: FS transceiver enabled
Speed (FS) and the High Speed (HS) terminations:
0: HS termination
1: FS termination
supplies. Shuts down all bloc ks not nec essary for Susp end/Resum e operations. While susp ended, TermSelect must always be in FS mode to ensure
that the 1.5 K ohm pull-up on DPLUS remains powered.
0: CY7C68000 circuitry drawing suspend current
1: CY7C68000 circuitry drawing normal current
receivers. They are combi natorial until a “usable” CLK is available then they
are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
0 0 0: SE0
0 1 1: ‘J’ State
1 0 2: ‘K’ State
1 1 3: SE1
receivers. They ar e combinatoria l until a ‘u sable’ CL K is available then they
are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
00–0: SE0
01–1: ‘J’ St ate
10–2: ‘K’ Sta t e
11–3: SE1.
CC
Document #: 38-08016 Rev. *H Page 5 of 14
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