0
CY7C68000
CY7C6800
TX2™ USB 2.0 UTMI Transceiver
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-08016 Rev. *D Revised June 23, 2003
0
TABLE OF CONTENTS
1.0 EZ-USB TX2 FEATURES ............................................. .. .. .. ............................. .. ..............................4
2.0 APPLICATIONS ...............................................................................................................................5
3.0 FUNCTIONAL OVERVIEW ........................................... .. .. .... .. ...................................... .. .................5
3.1 USB Signaling Speed .......................................................................................... .. .....................5
3.2 Transceiver Clock Frequency ......... .................................... ........................................................5
3.3 Buses ..........................................................................................................................................5
3.4 Reset Pin ....................................................................................................................................5
3.5 Line State ....................................................................................................................................5
3.6 Full-speed vs. High-speed Select .............. ............................................ .....................................5
3.7 Operational Modes ........... .................. ................... .................................. ................... .................5
4.0 DPLUS/DMINUS IMPEDANCE TERMINATION ..............................................................................6
5.0 PIN ASSIGNMENTS ............................................................................... .........................................6
5.1 CY7C68000 Pin Descriptions .................................... .................................................................7
6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................12
7.0 OPERATING CONDITIONS ............................... ........................ .............................................. ......12
8.0 DC CHARACTERISTICS ........................ .. .. .. .. .. ................................. ............................................12
8.1 USB 2.0 Transceiver .................................................................................................................13
CY7C6800
9.0 AC ELECTRICAL CHARACTERISTICS ..................................... .. ...................... .. ...................... ..13
9.1 USB 2.0 Transceiver .................................................................................................................13
9.2 Timing Dia g ra m .......... .. .............. .. .. ............. ... ............. .. .. ............. ... ............. .. .............. .............13
9.2.1 HS/FS Interface Timing–60 MHz ..................................................................................................13
9.2.2 HS/FS Interface Timing–30 MHz ....................................................................................................13
10.0 ORDERING INFORMATION ................................ .. .. .. ..................................................................14
11.0 PACKAGE DIAGRAMS ..................................... .. .... .. ...................................... .... ........................14
12.0 PCB LAYOUT RECOMMENDATIONS............... .. .... .. ................................ .. .... .. .. ........................15
13.0 QUAD FLAT PACKAGE NO LEADS (QFN) PACKAGE DESIGN NOTES .................. .. .............16
Document #: 38-08016 Rev. *D Page 2 of 17
0
LIST OF FIGURES
Figure 1-1. Blo c k Di a gr a m .......................... .. ... ............. .. ............. .. ........................... .. .............................4
Figure 5-1. CY7C68000 56-pin QFN Pin Assignment.............................................................................7
Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment...........................................................................8
Figure 9-1. 60 -M Hz Interface Timing Constra i n t s........... ............. .. ... ............. .. ............. ... ............. .. .......13
Figure 9-2. 30 -M Hz Timing Int e rf ac e T im in g C o n straints... ... ............. .. ............. ... ............. .. ............. .. ... 13
Figure 11-1. 56-lead Shrunk Small Outline Package O56.....................................................................14
Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 x 8 mm) LF56.............................................15
Figure 13-1. Cross-Section of the area underneath the QFN package.................................................16
Figure 13-2. P lo t of th e so l de r m as k........... .. .............. .. .. ............. .. .............. .. .. ............. ... ......................16
LIST OF TABLES
CY7C6800
Table 5-1.
Table 8-1.
Table 9-1. 60-MHz Interface Timing Constraints Parameters ..............................................................13
Table 9-2. 30 MHz Timing Interface Timing Constraints Parameters ...................................................13
Table 10-1. Ordering Info rm a t io n .................... .. ............. .. ........................... .. ............. .. .............. .. .. .......14
Pin Descriptions ...................... ......... ...... ......... ......... ......... ...... ......... ......... ....... ......... ........ .....8
DC Characteristics ...............................................................................................................12
Document #: 38-08016 Rev. *D Page 3 of 17
0
CY7C6800 0
CY7C6800
1.0 EZ-USB TX2 Features
The Cypress EZ-USB TX2 i s a Universal Serial Bus (USB) specificatio n revision 2.0 trans ceiver , serial /deserializ er , to a paralle l
interface of eit her 16 bi ts at 30 MHz or eight bits at 60 MHz. T he TX2 pro vides a high-sp eed physi cal layer interface that ope rates
at the maximum allowable USB 2.0 bandwidth. This allows the system designer to keep the complex high-speed analog USB
components ex ternal to the di gital ASIC whi ch decr eases d evelopment time and a ssociated risk. A stand ard interfac e is p rovided
that is USB 2.0-certified and is compliant with Transceiver Macrocell Interface (UTMI) specification version 1.05 dated 3/29/01.
Two packages are defined for the family: 56-pin SSOP and 56-pin QFN.
The function block diagram is shown in Figure 1-1.
CY7C68000
XTALIN/
OUT
USB
OSC
USB
2.0
XCVR
20X
PLL
Full-Speed Rx
High-Speed Rx
High-Speed Tx
PLL_480
Traffic
Sync
Elasticity
Buffer
Fast
Digital
Rx
Fast
UTMI CLK
Digital
Rx
Digital
Full-Speed Tx
Tx
Digital
Tx
Figure 1-1. Block Diagram
• UTMI-compliant/USB-2.0-certified for device operation
• Operates in both USB 2.0 high speed (HS), 480 Mbits/second, and full speed (FS), 12 Mbits/second
• Serial-to-parallel and parallel-to-serial conversions
• 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirectional external data interface
• Synchronous field and EOP detection on receive packets
• Synchronous field and EOP generation on transmit packets
• Data and clock recovery from the USB serial stream
• Bit stuffing/unstuffing; bit stuff error detection
• Staging register to manage data rate variation due to bit stuffing/unstuffing
• 16-bit 30-MHz, and 8-bit 60-MHz parallel interface
• Ability to switch between FS and HS terminations and signaling
• Supports detection of USB reset, suspend, and resume
• Supports HS identification and detection as defined by the USB 2.0 Specification
• Supports transmission of resume signaling
• 3.3V operation
• Two package options—56-pin QFN, and 56-pin SSOP
• All required terminations, including 1.5-K ohm pull-up on DPLUS, are internal to chip
• Supports USB 2.0 test modes.
UTMI CLK
UTMI Rx Ctl
UTMI Rx Data 8/16
BIDI Option
Also
UTMI Rx Data 8/16
UTMI Tx Ctl
Document #: 38-08016 Rev. *D Page 4 of 17
0
CY7C6800
2.0 Applications
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
•Home PNA
• Wireless LAN
• MP3 players
• Networking.
3.0 Functional Overview
3.1 USB Signaling Speed
TX2 operates at two of the rates defined in the USB Specification 2.0, dated April 27, 2000:
• Full speed, with a signaling bit rate of 12 Mbps
• High speed, with a signaling bit rate of 480 Mbps.
TX2 does not support the low-speed (LS) signaling rate of 1.5 Mbps.
3.2 Transceiver Clock Frequency
TX2 has an on-chip oscillator circuit that uses an external 24-MHz (±100-ppm) crystal with the following characteristics:
• Parallel resonant
• Fundamental mode
• 500-µW drive level
• 27–33 pF (5% tolerance) load capacitors.
An on-chip phase-lock ed loop (PLL) m ultiplies the 24- MHz oscilla tor up to 30/60 M Hz, as required by the trans ceiver paral lel data
bus. The default UTMI interface clock (CLK) frequency is determined by the DataBus16_8 pin.
3.3 Buses
The two packages allow for 8/16-bit bidirectional data bus for data transfers to a controlling unit.
3.4 Reset Pin
An input pin (Rese t) reset s t he ch ip. This pin ha s hyst eres is and is a ctive HIGH ac cordi ng to the U TMI s pecifica tion. T he internal
PLL stabilizes approximately 200 µs after V
has reached 3.3V.
CC
3.5 Line State
The Line State output pins LineState[1:0] are driven by combinational logic and may be toggling between the “J” and the “K”
states. They are synchronized to the CLK signal for a valid signal. On the CLK edge the state of these lines reflect the state of
the USB data lines. Upon the clock edg e the 0-bit of the Li neS tat e pins is the s tate of the DP LUS line and the one bit of LineState
is the DMINUS line. When synchronized, the set-up and hold timing of the LineState is identical to the parallel data bus.
3.6 Full-speed vs. High-speed Select
The FS vs. HS is done through the u se of bot h Xcv rSel ec t and the TermSelect input signals . The TermSelect signal enables th e
1.5 K ohm pull-up on to the DPLUS pin. When TermSelect is driven LOW, a SE0 is asserted on the USB providing the HS
termination and generating the HS Idle state on the bus. The XcvrSelect signal is the control which selects either the FS transceivers or the HS transceive rs. By sett ing this pin to a “0” the HS tran sc ei vers are s ele ct ed an d by setti ng this bit to a “1 ” the FS
transceiver s are selected.
3.7 Operational Modes
The operational modes are controlled by the OpMode signals. The OpMode signals are c apabl e of inhi biti ng n orm al op erat ion
of the transceiver an d evo king s pecial test modes. These mo des t ake ef fect im medi ately and t a ke prec edenc e ove r any pen ding
data operations. The transmission data rate when in OpMode depends on the state of the XcvrSelect input.
Document #: 38-08016 Rev. *D Page 5 of 17
0
OpMode[1:0] Mode Description
00 0 Normal operation
01 1 Non-driving
10 2 Disable Bit Stuffing and NRZI encoding
11 3 Reserved
Mode 0 allows the transceiver to operate with normal USB data decoding and encoding.
Mode 1 allows the transc eive r logic to su pport a soft d isconne ct feat ure which t hree-states both the HS and F S transm itters , an d
removes any t ermination from the USB, making it appear to an upstream port that the device has been disconnected from the bus.
Mode 2 disables Bit Stuff and NRZI encoding logic so 1s loaded from the data bus becomes Js on the DPLUS/DMINUS lines
and 0s become Ks.
CY7C6800
4.0 DPLUS/DMINUS Impedance Termination
The CY7C68000 does not require external resistors for USB data line impedance termination or an external pull up resistor on
the DPLUS line. These resistors are incorporated into the part. They are factory trimmed to meet the requirements of USB 2.0.
Incorporating these resistors also reduces the pin count on the part.
Document #: 38-08016 Rev. *D Page 6 of 17
Loading...