CYPRESS CY7C67200 User Manual
EZ-OTG™
CY7C67200
Programmable USB On-The-Go
Host/Peripheral Controller
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-08014 Rev. *E Revised September 16, 2003
CY7C67200
TABLE OF CONTENTS
1.0 INTRODUCTION ..............................................................................................................................9
1.1 EZ-OTG Features .......................................................................................................................9
2.0 TYPICAL APPLICATIONS .............................................................................................................10
3.0 FUNCTIONAL OVERVIEW ............................................................................................................10
3.1 Processor Core .........................................................................................................................10
3.1.1 Processor ........................................................................................................................................ 10
3.1.2 Clocking ..........................................................................................................................................10
3.1.3 Memory ...........................................................................................................................................10
3.1.4 Interrupts ......................................................................................................................................... 10
3.1.5 General Timers and Watchdog Timer ............................................................................................. 10
3.1.6 Power Management ........................................................................................................................10
4.0 INTERFACE DESCRIPTIONS .......................................................................................................11
4.1 USB Interface ............................................................................................................................11
4.1.1 USB Features ..................................................................................................................................12
4.1.2 USB Pins. ........................................................................................................................................ 12
4.2 OTG Interface ...........................................................................................................................12
4.2.1 OTG Features ................................................................................................................................. 12
4.2.2 OTG Pins. ....................................................................................................................................... 13
4.3 General Purpose I/O Interface ..................................................................................................13
4.3.1 GPIO Description ............................................................................................................................13
4.3.2 Unused Pin Descriptions ................................................................................................................. 13
4.4 UART Interface .........................................................................................................................13
4.4.1 UART Features ...............................................................................................................................13
4.4.2 UART Pins. ..................................................................................................................................... 13
4.5 I2C EEPROM Interface .............................................................................................................13
4.5.1 I2C EEPROM Features ................................................................................................................... 13
4.5.2 I2C EEPROM Pins. ......................................................................................................................... 14
4.6 Serial Peripheral Interface ........................................................................................................14
4.6.1 SPI Features ...................................................................................................................................14
4.6.2 SPI Pins ..........................................................................................................................................14
4.7 High-Speed Serial Interface ......................................................................................................14
4.7.1 HSS Features ..................................................................................................................................14
4.7.2 HSS Pins ......................................................................................................................................... 15
4.8 Host Port Interface (HPI) ...........................................................................................................15
4.8.1 HPI Features ...................................................................................................................................15
4.8.2 HPI Pins ..........................................................................................................................................15
4.9 Charge Pump Interface .............................................................................................................16
4.9.1 Charge Pump Features ................................................................................................................... 16
4.9.2 Charge Pump Pins ..........................................................................................................................17
4.10 Booster Interface .....................................................................................................................17
4.10.1 Booster Pins. .................................................................................................................................18
4.11 Crystal Interface ......................................................................................................................18
4.11.1 Crystal Pins. .................................................................................................................................. 18
4.12 Boot Configuration Interface ...................................................................................................18
4.13 Operational Modes ..................................................................................................................19
4.13.1 Coprocessor Mode ........................................................................................................................ 19
4.13.2 Stand-alone Mode ......................................................................................................................... 19
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CY7C67200
TABLE OF CONTENTS (continued)
5.0 POWER SAVINGS AND RESET DESCRIPTION ..........................................................................20
5.1 Power Savings Mode Description .............................................................................................20
5.2 Sleep .........................................................................................................................................20
5.3 External (Remote) wakeup Source ...........................................................................................20
5.4 Power-On Reset (POR) Description .........................................................................................21
5.5 Reset Pin .................................................................................................................................. 21
5.6 USB Reset ................................................................................................................................21
6.0 MEMORY MAP ...............................................................................................................................21
6.1 Mapping ....................................................................................................................................21
6.2 Internal Memory ........................................................................................................................21
7.0 REGISTERS ...................................................................................................................................23
7.1 Processor Control Registers .....................................................................................................23
7.1.1 CPU Flags Register [0xC000] [R] .................................................................................................23
7.1.2 Bank Register [0xC002] [R/W] ...................................................................................................... 24
7.1.3 Hardware Revision Register [0xC004] [R] .................................................................................... 25
7.1.4 CPU Speed Register [0xC008] [R/W] ........................................................................................... 25
7.1.5 Power Control Register [0xC00A] [R/W] .......................................................................................26
7.1.6 Interrupt Enable Register [0xC00E] [R/W] .................................................................................... 28
7.1.7 Breakpoint Register [0xC014] [R/W] .............................................................................................29
7.1.8 USB Diagnostic Register [0xC03C] [R/W] .....................................................................................30
7.2 Timer Registers ......................................................................................................................... 31
7.2.1 Watchdog Timer Register [0xC00C] [R/W] ................................................................................... 31
7.2.2 Timer n Register [R/W] ....................................................................................................................32
7.3 General USB Registers ............................................................................................................. 32
7.3.1 USB n Control Register [R/W] ......................................................................................................... 32
7.4 USB Host Only Registers ..........................................................................................................34
7.4.1 Host n Control Register [R/W] .........................................................................................................35
7.4.2 Host n Address Register [R/W] .......................................................................................................35
7.4.3 Host n Count Register [R/W] ........................................................................................................... 36
7.4.4 Host n Endpoint Status Register [R] ............................................................................................... 36
7.4.5 Host n PID Register [W] .................................................................................................................. 38
7.4.6 Host n Count Result Register [R] ....................................................................................................39
7.4.7 Host n Device Address Register [W] ............................................................................................... 39
7.4.8 Host n Interrupt Enable Register [R/W] ........................................................................................... 40
7.4.9 Host n Status Register [R/W] .......................................................................................................... 41
7.4.10 Host n SOF/EOP Count Register [R/W] ........................................................................................ 42
7.4.11 Host n SOF/EOP Counter Register [R] .........................................................................................42
7.4.12 Host n Frame Register [R] ............................................................................................................ 43
7.5 USB Device Only Registers ......................................................................................................43
7.5.1 Device n Endpoint n Control Register [R/W] ...................................................................................44
7.5.2 Device n Endpoint n Address Register [R/W] ................................................................................. 45
7.5.3 Device n Endpoint n Count Register [R/W] .....................................................................................46
7.5.4 Device n Endpoint n Status Register [R/W] ....................................................................................46
7.5.5 Device n Endpoint n Count Result Register [R/W] ..........................................................................48
7.5.6 Device n Interrupt Enable Register [R/W] .......................................................................................49
7.5.7 Device n Address Register [W] .......................................................................................................51
7.5.8 Device n Status Register [R/W] .......................................................................................................52
7.5.9 Device n Frame Number Register [R] .............................................................................................54
7.5.10 Device n SOF/EOP Count Register [W] ........................................................................................ 54
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CY7C67200
TABLE OF CONTENTS (continued)
7.6 OTG Control Registers .............................................................................................................55
7.6.1 OTG Control Register [0xC098] [R/W] .......................................................................................... 55
7.7 GPIO Registers .........................................................................................................................56
7.7.1 GPIO Control Register [0xC006] [R/W] ......................................................................................... 57
7.7.2 GPIO 0 Output Data Register [0xC01E] [R/W] ................................................................................58
7.7.3 GPIO 1 Output Data Register [0xC024] [R/W] ................................................................................59
7.7.4 GPIO 0 Input Data Register [0xC020] [R] .....................................................................................59
7.7.5 GPIO 1 Input Data Register [0xC026] [R] .......................................................................................59
7.7.6 GPIO 0 Direction Register [0xC022] [R/W] ................................................................................... 60
7.7.7 GPIO 1 Direction Register [0xC028] [R/W] ................................................................................... 60
7.8 HSS Registers .......................................................................................................................... 61
7.8.1 HSS Control Register [0xC070] [R/W] .......................................................................................... 61
7.8.2 HSS Baud Rate Register [0xC072] [R/W] .....................................................................................63
7.8.3 HSS Transmit Gap Register [0xC074] [R/W] ..................................................................................63
7.8.4 HSS Data Register [0xC076] [R/W] ..............................................................................................64
7.8.5 HSS Receive Address Register [0xC078] [R/W] ............................................................................. 64
7.8.6 HSS Receive Counter Register [0xC07A] [R/W] ........................................................................... 65
7.8.7 HSS Transmit Address Register [0xC07C] [R/W] .........................................................................65
7.8.8 HSS Transmit Counter Register [0xC07E] [R/W] .......................................................................... 66
7.9 HPI Registers ............................................................................................................................66
7.9.1 HPI Breakpoint Register [0x0140] [R] ............................................................................................. 66
7.9.2 Interrupt Routing Register [0x0142] [R] ...........................................................................................67
7.9.3 SIEXmsg Register [W] .................................................................................................................... 68
7.9.4 HPI Mailbox Register [0xC0C6] [R/W] .......................................................................................... 69
7.9.5 HPI Status Port [] [HPI: R] ...............................................................................................................70
7.10 SPI Registers .......................................................................................................................... 72
7.10.1 SPI Configuration Register [0xC0C8] [R/W] ................................................................................72
7.10.2 SPI Control Register [0xC0CA] [R/W] .........................................................................................74
7.10.3 SPI Interrupt Enable Register [0xC0CC] [R/W] ........................................................................... 75
7.10.4 SPI Status Register [0xC0CE] [R] ............................................................................................... 76
7.10.5 SPI Interrupt Clear Register [0xC0D0] [W] ....................................................................................77
7.10.6 SPI CRC Control Register [0xC0D2] [R/W] .................................................................................77
7.10.7 SPI CRC Value Register [0xC0D4] [R/W] ...................................................................................78
7.10.8 SPI Data Register [0xC0D6] [R/W] ............................................................................................. 79
7.10.9 SPI Transmit Address Register [0xC0D8] [R/W] ......................................................................... 79
7.10.10 SPI Transmit Count Register [0xC0DA] [R/W] ............................................................................79
7.10.11 SPI Receive Address Register [0xC0DC [R/W] ........................................................................80
7.10.12 SPI Receive Count Register [0xC0DE] [R/W] ........................................................................... 80
7.11 UART Registers ......................................................................................................................81
7.11.1 UART Control Register [0xC0E0] [R/W] ......................................................................................81
7.11.2 UART Status Register [0xC0E2] [R] ........................................................................................... 82
7.11.3 UART Data Register [0xC0E4] [R/W] ..........................................................................................82
8.0 PIN DIAGRAM ................................................................................................................................ 83
9.0 PIN DESCRIPTIONS ......................................................................................................................84
10.0 ABSOLUTE MAXIMUM RATINGS ..............................................................................................85
11.0 OPERATING CONDITIONS .........................................................................................................85
12.0 CRYSTAL REQUIREMENTS (XTALIN, XTALOUT) ...................................................................86
13.0 DC CHARACTERISTICS ...........................................................................................................86
13.1 USB Transceiver .....................................................................................................................87
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CY7C67200
TABLE OF CONTENTS (continued)
14.0 AC TIMING CHARACTERISTICS ................................................................................................87
14.1 Reset Timing ...........................................................................................................................87
14.2 Clock Timing ...........................................................................................................................88
14.3 I2C EEPROM Timing ..............................................................................................................88
14.4 HPI (Host Port Interface) Write Cycle Timing .........................................................................89
14.5 HPI (Host Port Interface) Read Cycle Timing ......................................................................... 90
14.6 HSS BYTE Mode Transmit .....................................................................................................91
14.7 HSS Block Mode Transmit ......................................................................................................91
14.8 HSS BYTE and BLOCK Mode Receive ..................................................................................91
14.9 Hardware CTS/RTS Handshake .............................................................................................92
15.0 REGISTER SUMMARY ................................................................................................................93
16.0 ORDERING INFORMATION ........................................................................................................97
17.0 PACKAGE DIAGRAMS ...............................................................................................................97
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CY7C67200
LIST OF FIGURES
Figure 1-1. Block Diagram .......................................................................................................................9
Figure 4-1. Charge Pump ...................................................................................................................... 16
Figure 4-2. Power Supply Connection With Booster ............................................................................. 17
Figure 4-3. Power Supply Connection Without Booster ........................................................................ 17
Figure 4-4. Crystal Interface .................................................................................................................. 18
Figure 4-5. Minimum Standalone Hardware Configuration – Peripheral Only.......................................20
Figure 6-1. Memory Map .......................................................................................................................22
Figure 7-1. Processor Control Registers ............................................................................................... 23
Figure 7-2. CPU Flags Register.............................................................................................................23
Figure 7-3. Bank Register...................................................................................................................... 24
Figure 7-4. Revision Register ................................................................................................................ 25
Figure 7-5. CPU Speed Register ...........................................................................................................25
Figure 7-6. Power Control Register ....................................................................................................... 26
Figure 7-7. Interrupt Enable Register .................................................................................................... 28
Figure 7-8. Breakpoint Register............................................................................................................. 29
Figure 7-9. USB Diagnostic Register..................................................................................................... 30
Figure 7-10. Timer Registers .................................................................................................................31
Figure 7-11. Watchdog Timer Register..................................................................................................31
Figure 7-12. Timer n Register................................................................................................................ 32
Figure 7-13. USB Registers................................................................................................................... 32
Figure 7-14. USB n Control Register .....................................................................................................33
Figure 7-15. USB Host Only Register.................................................................................................... 34
Figure 7-16. Host n Control Register .....................................................................................................35
Figure 7-17. Host n Address Register ................................................................................................... 36
Figure 7-18. Host n Count Register .......................................................................................................36
Figure 7-19. Host n Endpoint Status Register ....................................................................................... 37
Figure 7-20. Host n PID Register...........................................................................................................38
Figure 7-21. Host n Count Result Register............................................................................................ 39
Figure 7-22. Host n Device Address Register ....................................................................................... 39
Figure 7-23. Host n Interrupt Enable Register .......................................................................................40
Figure 7-24. Host n Status Register ...................................................................................................... 41
Figure 7-25. Host n SOF/EOP Count Register ......................................................................................42
Figure 7-26. Host n SOF/EOP Counter Register................................................................................... 43
Figure 7-27. Host n Frame Register ...................................................................................................... 43
Figure 7-28. USB Device Only Registers .............................................................................................. 43
Figure 7-29. Device n Endpoint n Control Register ...............................................................................44
Figure 7-30. Device n Endpoint n Address Register..............................................................................45
Figure 7-31. Device n Endpoint n Count Register .................................................................................46
Figure 7-32. Device n Endpoint n Status Register................................................................................. 47
Figure 7-33. Device n Endpoint n Count Result Register ...................................................................... 49
Figure 7-34. Device n Interrupt Enable Register ................................................................................... 49
Figure 7-35. Device n Address Register................................................................................................ 51
Figure 7-36. Device n Status Register................................................................................................... 52
Figure 7-37. Device n Frame Number Register.....................................................................................54
Figure 7-38. Device n SOF/EOP Count Register .................................................................................. 54
Figure 7-39. OTG Registers ..................................................................................................................55
Figure 7-40. OTG Control Register........................................................................................................55
Figure 7-41. GPIO Registers ................................................................................................................. 56
Figure 7-42. GPIO Control Register ...................................................................................................... 57
Figure 7-43. GPIO 0 Output Data Register............................................................................................58
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CY7C67200
LIST OF FIGURES (continued)
Figure 7-44. GPIO n Output Data Register............................................................................................59
Figure 7-45. GPIO 0 Input Data Register .............................................................................................. 59
Figure 7-46. GPIO 1 Input Data Register .............................................................................................. 59
Figure 7-47. GPIO 0 Direction Register................................................................................................. 60
Figure 7-48. GPIO 1 Direction Register................................................................................................. 60
Figure 7-49. HSS Registers................................................................................................................... 61
Figure 7-50. HSS Control Register ........................................................................................................61
Figure 7-51. HSS Baud Rate Register...................................................................................................63
Figure 7-52. HSS Transmit Gap Register.............................................................................................. 63
Figure 7-53. HSS Data Register ............................................................................................................64
Figure 7-54. HSS Receive Address Register ........................................................................................ 64
Figure 7-55. HSS Receive Counter Register......................................................................................... 65
Figure 7-56. HSS Transmit Address Register ....................................................................................... 65
Figure 7-57. HSS Transmit Counter Register........................................................................................ 66
Figure 7-58. HPI Registers .................................................................................................................... 66
Figure 7-59. HPI Breakpoint Register.................................................................................................... 66
Figure 7-60. Interrupt Routing Register ................................................................................................. 67
Figure 7-61. SIEXmsg Register .............................................................................................................69
Figure 7-62. HPI Mailbox Register.........................................................................................................69
Figure 7-63. HPI Status Port..................................................................................................................70
Figure 7-64. SPI Registers .................................................................................................................... 72
Figure 7-65. SPI Configuration Register................................................................................................ 72
Figure 7-66. SPI Control Register..........................................................................................................74
Figure 7-67. SPI Interrupt Enable Register............................................................................................75
Figure 7-68. SPI Status Register ...........................................................................................................76
Figure 7-69. SPI Interrupt Clear Register .............................................................................................. 77
Figure 7-70. SPI CRC Control Register................................................................................................. 77
Figure 7-71. SPI CRC Value Register ................................................................................................... 78
Figure 7-72. SPI Data Register..............................................................................................................79
Figure 7-73. SPI Transmit Address Register .........................................................................................79
Figure 7-74. SPI Transmit Count Register.............................................................................................79
Figure 7-75. SPI Receive Address Register ..........................................................................................80
Figure 7-76. SPI Receive Count Register..............................................................................................80
Figure 7-77. UART Registers ................................................................................................................ 81
Figure 7-78. UART Control Register...................................................................................................... 81
Figure 7-79. UART Status Register .......................................................................................................82
Figure 7-80. UART Data Register..........................................................................................................82
Figure 8-1. EZ-OTG Pin Diagram ..........................................................................................................83
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CY7C67200
LIST OF TABLES
Table 4-1. Interface Options for GPIO Pins ..........................................................................................11
Table 4-2. USB Port Configuration Options ..........................................................................................12
Table 4-3. USB Interface Pins ..............................................................................................................12
Table 4-4. OTG Interface Pins ..............................................................................................................13
Table 4-5. UART Interface Pins ............................................................................................................13
Table 4-6. I2C EEPROM Interface Pins ...............................................................................................14
Table 4-7. SPI Interface Pins ................................................................................................................14
Table 4-8. HSS Interface Pins ..............................................................................................................15
Table 4-9. HPI Interface Pins ................................................................................................................15
Table 4-10. HPI Addressing ..................................................................................................................16
Table 4-11. Charge Pump Interface Pins .............................................................................................17
Table 4-12. Charge Pump Interface Pins .............................................................................................18
Table 4-13. Crystal Pins .......................................................................................................................18
Table 4-14. Boot Configuration Interface ..............................................................................................18
Table 5-1. wakeup Sources
Table 7-1. Bank Register Example .......................................................................................................24
Table 7-2. CPU Speed Definition ..........................................................................................................25
Table 7-3. Force Select Definition ........................................................................................................30
Table 7-4. Period Select Definition .......................................................................................................31
Table 7-5. USB Data Line Pull-Up and Pull-Down Resistors ................................................................33
Table 7-6. Port A Force D± State .........................................................................................................34
Table 7-7. PID Select Definition ............................................................................................................38
Table 7-8. Mode Select Definition .........................................................................................................57
Table 7-9. Scale Select Field Definition for SCK Frequency ................................................................ 73
Table 7-10. CRC Mode Definition .........................................................................................................77
Table 7-11. UART Baud Select Definition ............................................................................................81
Table 9-1. Pin Descriptions ...................................................................................................................84
Table 12-1. Crystal Requirements ........................................................................................................86
Table 13-1. DC Characteristics..............................................................................................................86
Table 13-2. DC Characteristics: Charge Pump ....................................................................................86
Table 15-1. Register Summary .............................................................................................................93
Table 16-1. Ordering Information ..........................................................................................................97
..................................................................................................................21
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CY7C67200
1.0 INTRODUCTION
EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is
designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-OTG has its own 16-bit RISC
processor to act as a coprocessor or operate in standalone mode. EZ-OTG also has a programmable I/O interface block allowing
a wide range of interface options.
CY7C67200
nRESET
Control
Watchdog
Timer 0 Timer 1
UART I/F
CY16
HOST/
Peripheral
USB Ports
Vbus, ID
D+,D-
D+,D-
16-bit RISC CORE
OTG
X1
X2
PLL
USB-A
SIE1
USB-A
SIE2
Mobile
Power
Booster
4Kx16
ROM BIOS
8Kx16
RAM
I2C
EEPROM I/F
HSS I/F
SPI I/F
HPI I/F
GPIO
GPIO [24:0]
SHARED INPUT/OUTPUT PINS
Figure 1-1. Block Diagram
1.1 EZ-OTG Features
• Single-chip programmable USB dual role (Host/Peripheral) controller with two configurable Serial Interface Engines
(SIEs) and two USB ports
• Support for USB OTG protocol
• On-chip 48-MHz 16-bit processor with dynamically switchable clock speed
• Configurable I/O block supporting a variety of I/O options or up to 25 bits of General Purpose I/O (GPIO)
• 4K × 16 internal mask ROM containing built-in BIOS that supports a communication-ready state with access to I2C
EEPROM interface, external ROM, UART, or USB
• 8K x 16 internal RAM for code and data buffering
• 16-bit parallel host port interface (HPI) with DMA/Mailbox data path for an external processor to directly access all
on-chip memory and control on-chip SIEs
• Fast serial port supports from 9600 baud to 2.0 Mbaud
• SPI supporting both master and slave
• Supports 12-MHz external crystal or clock
• Power consumption: 50 mA operational; 30 mA standby
• 2.7V to 3.6V power supply voltage
• Package option — 48-pin FBGA
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CY7C67200
2.0 Typical Applications
EZ-OTG is a very powerful and flexible dual-role USB controller that supports a wide variety of applications. It is primarily intended
to enable USB OTG capability in applications such as:
• Cellular phones
• PDAs and pocket PCs
• Video and digital still cameras
• MP3 players
• Mass storage devices.
3.0 Functional Overview
3.1 Processor Core
3.1.1 Processor
EZ-OTG has a general-purpose 16-bit embedded RISC processor that runs at 48 MHz.
3.1.2 Clocking
EZ-OTG requires a 12-MHz source for clocking. Either an external crystal or TTL-level oscillator may be used. EZ-OTG has an
internal PLL that produces a 48-MHz internal clock from the 12-MHz source.
3.1.3 Memory
EZ-OTG has a built-in 4K × 16 masked ROM and a 8K × 16 internal RAM. The masked ROM contains the EZ-OTG BIOS. The
internal RAM can be used for program code or data.
3.1.4 Interrupts
EZ-OTG provides 128 interrupt vectors. The first 48 vectors are hardware interrupts and the following 80 vectors are software
interrupts.
3.1.5 General Timers and Watchdog Timer
EZ-OTG has two built-in programmable timers and a Watchdog timer. All three timers can generate an interrupt to the EZ-OTG.
3.1.6 Power Management
EZ-OTG has one main power-saving mode, Sleep. Sleep mode pauses all operations and provides the lowest power state.
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CY7C67200
4.0 Interface Descriptions
EZ-OTG has a variety of interface options for connectivity, with several interface options available. See Ta bl e 4-1 to understand
how the interfaces share pins and can coexist. Below are some general guidelines:
•I2C EEPROM and OTG do not conflict with any interfaces
• HPI is mutually exclusive to: HSS, SPI, and UART.
Table 4-1. Interface Options for GPIO Pins
GPIO Pins HPI HSS SPI UART I2C OTG
GPIO31 SCL/SDA
GPIO30 SCL/SDA
GPIO29 OTGID
GPIO24 INT
GPIO23 nRD
GPIO22 nWR
GPIO21 nCS
GPIO20 A1
GPIO19 A0
GPIO15 D15 CTS
GPIO14 D14 RTS
GPIO13 D13 RXD
GPIO12 D12 TXD
GPIO11 D11 MOSI
GPIO10 D10 SCK
GPIO9 D9 nSSI
GPIO8 D8 MISO
GPIO7 D7 TX
GPIO6 D6 RX
GPIO5 D5
GPIO4 D4
GPIO3 D3
GPIO2 D2
GPIO1 D1
GPIO0 D0
4.1 USB Interface
EZ-OTG has two built-in Host/Peripheral SIEs that each have a single USB transceiver, meeting the USB 2.0 specification
requirements for full- and low-speed (high-speed is not supported). In Host mode, EZ-OTG supports two downstream ports, each
support control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-OTG supports one peripheral port with eight
endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints
1 though 7 support Interrupt, Bulk (up to 64 Bytes/packet), or Isochronous transfers (up to 1023 Bytes/packet size). EZ-OTG also
supports a combination of Host and Peripheral ports simultaneously. EZ-OTG also supports a combination of Host and Peripheral
ports simultaneously as shown in Table 4-2.
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Table 4-2. USB Port Configuration Options
Port Configurations Port 1A Port 2A
OTG OTG –
OTG + 1 Host OTG Host
OTG + 1 Peripheral OTG Peripheral
1 Host + 1 Peripheral Host Peripheral
1 Host + 1 Peripheral Peripheral Host
2 Hosts Host Host
1 Host Host –
1 Host – Host
2 Peripherals Peripheral Peripheral
1 Peripheral Peripheral –
1 Peripheral – Peripheral
4.1.1 USB Features
• USB 2.0-compatible for full and low speed
• Up to two downstream USB host ports
• Up to two upstream USB peripheral ports
• Configurable endpoint buffers (pointer and length), must reside in internal RAM
• Up to eight available peripheral endpoints (1 control endpoint)
• Supports Control, Interrupt, Bulk, and Isochronous transfers
• Internal DMA channels for each endpoint
• Internal pull-up and pull-down resistors
• Internal Series termination resistors on USB data lines
CY7C67200
4.1.2 USB Pins.
Table 4-3. USB Interface Pins
Pin Name Pin Number
DM1A F2
DP1A E3
DM2A C2
DP2A D3
4.2 OTG Interface
EZ-OTG has one USB port that is compatible with the USB On-The-Go supplement to the USB 2.0 specification. The USB OTG
port has a various hardware features to support Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). OTG is
only supported on USB PORT 1A.
4.2.1 OTG Features
• Internal Charge Pump to supply and control VBUS
• VBUS Valid Status (above 4.4V)
• VBUS Status for 2.4V< VBUS <0.8V
• ID Pin Status
• Switchable 2KΩ internal discharge resistor on VBUS
• Switchable 500Ω internal Pull-up resistor on VBUS
• Individually switchable internal Pull-up and Pull-down resistors on the USB Data Lines
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CY7C67200
4.2.2 OTG Pins.
Table 4-4. OTG Interface Pins
Pin Name Pin Number
DM1A F2
DP1A E3
OTGVBUS C1
OTGID F4
CSwitchA D1
CSwitchB D2
4.3 General Purpose I/O Interface
EZ-OTG has up to 25 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overall
number of available GPIOs.
4.3.1 GPIO Description
All Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48-MHZ clock cycles. GPIO pins are
latched directly into registers, a single flip-flop.
4.3.2 Unused Pin Descriptions
Unused USB pins should be tri-stated with the D+ line pulled high through the internal pull-up resistor and the D- line pulled low
through the internal pull-down resistor.
Unused GPIO pins should be configured as outputs and driven low.
4.4 UART Interface
EZ-OTG has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as a
development port or for other interface requirements. The UART interface is exposed through GPIO pins.
4.4.1 UART Features
• Supports baud rates of 900 to 115.2K
• 8-N-1
4.4.2 UART Pins.
Table 4-5. UART Interface Pins
Pin Name Pin Number
TX B5
RX B4
4.5 I2C EEPROM Interface
EZ-OTG provides a master only I2C interface for external serial EEPROMs. The serial EEPROM can be used to store application
specific code and data. This I
2
The I
C EEPROM interface is a BIOS implementation and is exposed through GPIO pins. Please refer to the BIOS documentation
for additional details on this interface.
4.5.1 I
• Supports EEPROMs up to 64 KB (512K bit)
• Auto-detection of EEPROM size
2
C EEPROM Features
2
C interface is only to be used for loading code out of EEPROM, it is not a general I2C interface.
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4.5.2 I2C EEPROM Pins.
2
Table 4-6. I
4.6 Serial Peripheral Interface
EZ-OTG provides a SPI interface for added connectivity. EZ-OTG may be configured as either an SPI master or SPI slave. The
SPI interface can be exposed through GPIO pins or the External Memory port.
4.6.1 SPI Features
• Master or slave mode operation
• DMA block transfer and PIO byte transfer modes
• Full duplex or half duplex data communication
• 8-byte receive FIFO and 8-byte transmit FIFO
• Selectable master SPI clock rates from 250 KHz to 12 MHz
• Selectable master SPI clock phase and polarity
• Slave SPI signaling synchronization and filtering
• Slave SPI clock rates up to 2 MHz
• Maskable interrupts for block and byte transfer modes
• Individual bit transfer for non-byte aligned serial communication in PIO mode
• Programmable delay timing for the active/in-active master SPI clock
• Auto or manual control for master mode slave select signal
• Complete access to internal memory
C EEPROM Interface Pins
Pin Name Pin Number
SMALL EEPROM
SCK H3
SDA F3
LARGE EEPROM
SCK F3
SDA H3
4.6.2 SPI Pins
The SPI port has a few different pin location options as shown in Table 4-7. The pin location is selectable via the GPIO Control
Register [0xC006].
Table 4-7. SPI Interface Pins
Pin Name Pin Number
nSSI F6 or C6
SCK D5
MOSI D4
MISO C5
4.7 High-Speed Serial Interface
EZ-OTG provides an HSS interface. The HSS interface is a programmable serial connection with baud rate from 9600 baud to
2 Mbaud. The HSS interface supports both byte and block mode operations as well as hardware and software handshaking.
Complete control of EZ-OTG can be accomplished through this interface via an extensible API and communication protocol. The
HSS interface can be exposed through GPIO pins or the External Memory port.
4.7.1 HSS Features
• 8-bit, no parity code
• Programmable baud rate from 9600 baud to 2 Mbaud
• Selectable 1- or 2-stop bit on transmit
• Programmable inter-character gap timing for Block Transmit
• 8-byte receive FIFO
• Glitch filter on receive
• Block mode transfer directly to/from EZ-OTG internal memory (DMA transfer)
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• Selectable CTS/RTS hardware signal handshake protocol
• Selectable XON/XOFF software handshake protocol
• Programmable Receive interrupt, Block Transfer Done interrupts
• Complete access to internal memory
4.7.2 HSS Pins
Table 4-8. HSS Interface Pins
Pin Name Pin Number
CTS F6
RTS E4
RX E5
TX E6
4.8 Host Port Interface (HPI)
EZ-OTG has an HPI interface. The HPI interface provides DMA access to the EZ-OTG internal memory by an external host, plus
a bidirectional mailbox register for supporting high-level communication protocols. This port is designed to be the primary highspeed connection to a host processor. Complete control of EZ-OTG can be accomplished through this interface via an extensible
API and communication protocol. Other than the HW communication protocols, a host processor has identical control over
EZ-Host whether connecting to the HPI or HSS port. The HPI interface is exposed through GPIO pins.
4.8.1 HPI Features
• 16-bit data bus Interface
• 16 MB/s throughput
• Auto-Increment of address pointer for fast block mode transfers
• Direct memory access (DMA) to internal memory
• Bidirectional Mailbox register
• Byte Swapping
• Complete access to internal memory
• Complete control of SIEs through HPI
• Dedicated HPI Status Register
4.8.2 HPI Pins
Table 4-9. HPI Interface Pins
[1, 2]
Pin Name Pin Number
INT H4
nRD G4
nWR H5
nCS G5
A1 H6
A0 F5
D15 F6
D14 E4
D13 E5
D12 E6
D11 D4
D10 D5
D9 C6
D8 C5
D7 B5
Notes:
1. HPI_INT is for the Outgoing Mailbox Interrupt.
2. HPI strobes are negative logic sampled on rising edge.
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Table 4-9. HPI Interface Pins (continued)
D6 B4
D5 C4
D4 B3
D3 A3
D2 C3
D1 A2
D0 B2
The two HPI address pins are used to address one of four possible HPI port registers as shown in Ta bl e 4 -1 0 below.
Table 4-10. HPI Addressing
HPI A[1:0] A1 A0
HPI Data 0 0
HPI Mailbox 0 1
HPI Address 1 0
HPI Status 1 1
[1, 2]
4.9 Charge Pump Interface
VBUS for the USB On-The-Go (OTG) port can be produced by EZ-OTG using its built-in charge pump and some external
components. The circuit connections should look similar to the diagram below.
D1
D2
CSWITCHA
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CSWITCHB
C1
VBUS
OTGVBUS
C2
Figure 4-1. Charge Pump
Component details:
• D1 and D2: Schottky diodes with a current rating greater than 60 mA
• C1: Ceramic capacitor with a capacitance of 0.1 uF
• C2: Capacitor value should be no more that 6.5 uF since that is the maximum capacitance allowed by the USB OTG spec for
a dual-role device. The minimum value of C2 is 1 uF. There are no restrictions on the type of capacitor for C2.
If the VBUS charge pump circuit is not to be used, CSWITCHA, CSWITCHB, and OTGVBUS can be left unconnected.
4.9.1 Charge Pump Features
• Meets OTG Supplement Requirements, see the DC Characteristics: Charge Pump Table 13-2.
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p
4.9.2 Charge Pump Pins
Table 4-11. Charge Pump Interface Pins
Pin Name Pin Number
OTGVBUS C1
CSwitchA D1
CSwitchB D2
4.10 Booster Interface
EZ-OTG has an on-chip power booster circuit for use with power supplies that range between 2.7V and 3.6V. The booster circuit
boosts the power to 3.3V nominal to supply power for the entire chip. The booster circuit requires an external inductor, diode, and
capacitor. During power down mode, the circuit is disabled to save power. Figure 4-2 shows how to connect the booster circuit.
BOOSTVcc
2.7V to 3.6V
L1
VSWITCH
D1
power supply
3.3V
AVCC
C1 VCC
Figure 4-2. Power Supply Connection With Booster
Component details:
• L1: Inductor with inductance of 10 uH and a current rating of at least 250 mA
• D1: Schottky diode with a current rating of at least 250 mA
• C1: Tantalum or ceramic capacitor with a capacitance of at least 2.2 uF.
Figure 4-3 shows how to connect the power supply when the booster circuit is not being used.
BOOSTVcc
3.0V to 3.6V
ower supply
VSWITCH
VCC
AVCC
Figure 4-3. Power Supply Connection Without Booster
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4.10.1 Booster Pins.
Table 4-12. Charge Pump Interface Pins
Pin Name Pin Number
BOOSTVcc F1
VSWITCH E2
4.11 Crystal Interface
The recommended crystal circuit to be used with EZ-OTG is shown in Figure 4-4. If an oscillator is used instead of a crystal circuit,
connect it to XTALIN and leave XTALOUT unconnected. For further information on the crystal requirements, see Crystal Requirements Table 12-1.
XTALIN
C1 = 22 pF
Y1
12MHz
Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
C2 = 22 pF
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XTALOUT
Figure 4-4. Crystal Interface
4.11.1 Crystal Pins.
Table 4-13. Crystal Pins
Pin Name Pin Number
XTALIN G3
XTALOUT G2
4.12 Boot Configuration Interface
EZ-OTG can boot into any one of four modes. The mode it boots into is determined by the TTL voltage level of GPIO[31:30] at
the time nRESET is deasserted. The table below shows the different boot pin combinations possible. After a reset pin event
occurs, the BIOS bootup procedure executes for up to 3 ms. GPIO[31:30] are sampled by the BIOS during bootup only. After
bootup these pins are available to the application as GPIOs.
Table 4-14. Boot Configuration Interface
GPIO31 (Pin 39) GPIO30 (Pin 40) Boot Mode
0 0 Host Port Interface (HPI)
0 1 High Speed Serial (HSS)
1 0 Serial Peripheral Interface (SPI, slave mode)
11I
2
C EEPROM (Standalone Mode)
GPIO[31:30] should be pulled high or low as needed using resistors tied to VCC or GND with resistor values between 5KΩ and
15KΩ. GPIO[31:30] should not be tied directly to VCC or GND. Note that in Standalone mode, the pull-ups on those two pins are
used for the serial I
2
C EEPROM (if implemented). The resistors used for these pull-ups should conform to the serial EEPROM
manufacturer's requirements.
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If any mode other then standalone is chosen, EZ-OTG will be in coprocessor mode. The device will power up with the appropriate
communication interface enabled according to its boot pins and wait idle until a coprocessor communicates with it. See the BIOS
documentation for greater detail on the boot process.
4.13 Operational Modes
4.13.1 Coprocessor Mode
EZ-OTG can act as a coprocessor to an external host processor. In this mode, an external host processor drives EZ-OTG and
is the main processor rather then EZ-OTG’s own 16-bit internal CPU. An external host processor may interface to EZ-OTG
through one of the following three interfaces in coprocessor mode:
• HPI mode, a 16-bit parallel interface with up to 16MBytes transfer rate
• HSS mode, a serial interface with up to 2 MBaud transfer rate
• SPI mode, a serial interface with up to 2 Mbits/s transfer rate.
At bootup GPIO[31:30] determine which of these three interfaces are used for coprocessor mode. Please refer to Table 4-14 for
details. Bootloading begins from the selected interface after POR + 3 ms of BIOS bootup.
4.13.2 Stand-alone Mode
In stand-alone mode, there is no external processor connected to EZ-OTG. Instead, EZ-OTG’s own internal 16-bit CPU is the
main processor and firmware is typically downloaded from an EEPROM. Optionally, firmware may also be downloaded via USB.
Please refer to Ta bl e 4-1 4 for booting into stand-alone mode.
After booting into stand-alone mode (GPIO[31:30] = ‘11’), the following pins are affected:
• GPIO[31:20] are configured as output pins to examine the EEPROM contents
• GPIO[28:27] are enabled for debug UART mode
• GPIO[29] is configured for as OTGID for OTG applications on PORT1A
— If OTGID is logic 1 then PORT1A (OTG) is configured as a USB peripheral
— If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host
• Ports 1B, 2A, and 2B default as USB peripheral ports
• All other pins remain INPUT pins.
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4.13.2.1 Minimum Hardware Requirements for Stand-alone Mode – Peripheral Only
Minimum Standalone Hardware Configuration - Peripheral Only
EZ-OTG
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VReg
VBus
Up to 64k x8
EEPROM
D+
DGND
SHIELD
VCC
VCC
WP
SCL
SDA
Bootstrap Options
Vcc
Vcc
10k
10k
Bootloading Firmware
GPIO[30]
GPIO[31]
Standard-B
or Mini-B
A0
A1
A2
GND
*Bootloading begins after POR + 3ms BIOS bootup
*GPIO[31:30] 31 30
Up to 2k x8 SCL SDA
>2k x8 to 64k x8 SDA SCL
VCC, AVCC,
BoostVCC
DPlus
DMinus
SCL*
SDA*
Reserved
GND, AGND,
BoostGND
Figure 4-5. Minimum Standalone Hardware Configuration – Peripheral Only
nRESET
Int. 16k x8
Code / Data
XOUT
XIN
*
Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
12MHz
Reset
Logic
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22pf
22pf
5.0 Power Savings and Reset Description
5.1 Power Savings Mode Description
EZ-OTG has one main power savings mode, Sleep. For detailed information on Sleep mode please see section 5.2.
Sleep mode is used for USB applications to support USB suspend and non USB applications as the main chip power down mode.
In addition, EZ-OTG is capable of slowing down the CPU clock speed through the CPU Speed Register [0xC008] without affecting
other peripheral timing. Reducing the CPU clock speed from 48 MHz to 24 MHz will reduce the overall current draw by around
8mA while reducing it from 48 MHz to 3 MHz will reduce the overall current draw by approximately 15 mA.
5.2 Sleep
Sleep mode is the main chip power down mode and is also used for USB suspend. Sleep mode is entered by setting the Sleep
Enable (bit 1) of the Power Control Register [0xC00A]. During Sleep mode (USB Suspend) the following events and states are
true:
• GPIO pins maintain their configuration during sleep (in suspend)
• External Memory Address pins are driven low
• XTALOUT will be turned off
• Internal PLL will be turned off
• Firmware should disable the charge pump (OTG Control Register [0xC098]) causing OTGVBUS to drop below 0.2V. Otherwise
OTGVBUS will only drop to V
• Booster circuit will be turned off
• USB transceivers will be turned off
• CPU will suspend until a programmable wakeup event.
5.3 External (Remote) wakeup Source
There are several possible events available to wake EZ-OTG from Sleep mode as shown in Tab le 5 -1 . These may also be used
as remote wakeup options for USB applications. Please see the Power Down Control Register [0xC00A] for details.
– (2 schottky diode drops)
CC
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Upon wakeup, code will begin executing within 200 ms, the time it takes the PLL to stabilize.
Table 5-1. wakeup Sources
wakeup Source
(if enabled) Event
USB Resume D+/D- Signaling
OTGVBUS Level
OTGID Any Edge
HPI Read
HSS Read
SPI Read
IRQ0 (GPIO 24) Any Edge
5.4 Power-On Reset (POR) Description
The length of the power-on-reset event can be defined by (VCC ramp to valid) + (Crystal start up). A typical application might
utilize a 12-ms power-on-reset event = ~7 ms + ~5 ms, respectively.
5.5 Reset Pin
The Reset pin is active low and requires a minimum pulse duration of 16 12-MHz clock cycles (1.3 ms). A reset event will restore
all registers to their default POR settings. Code execution will then begin 200 ms later at 0xFF00 with an immediate jump to
0xE000, the start of BIOS.
It should be noted that for up to 3 ms after BIOS starts executing, GPIO[24:19] and GPIO[15:8] will be driven as outputs for a test
mode. If these pins need to be used as inputs, a series resistor is required (10Ω-48Ω is recommended). Please refer to BIOS
documentation for addition details.
[3, 4]
5.6 USB Reset
A USB Reset will affect registers 0xC090 and 0xC0B0, all other registers remain unchanged.
6.0 Memory Map
6.1 Mapping
The EZ-OTG has just over 24 KB of addressable memory mapped from 0x0000 to 0xFFFF. This 24 KB contains both program
and data space and is byte addressable. Figure 6-1. shows the various memory region address locations.
6.2 Internal Memory
Of the internal memory, 15 KB is allocated for user’s program and data code. The lower memory space from 0x0000 to 0x04A2
is reserved for interrupt vectors, general purpose registers, USB control registers, the stack, and other BIOS variables. The upper
internal memory space contains EZ-OTG control registers from 0xC000 to 0xC0FF and the BIOS ROM itself from 0xE000 to
0xFFFF. For more information on the reserved lower memory or the BIOS ROM, please refer to the Programmers documentation
and the BIOS documentation.
During development with the EZ-OTG toolset, the lower area of User's space (0x04A4 to 0x1000) should be left available to load
the GDB stub. The GDB stub is required to allow the toolset debug access into EZ-OTG.
Notes:
3. Read data will be discarded (dummy data).
4. HPI_INT will assert on a USB Resume.
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Internal Memory
HW INT's
0x0000 - 0x00FF
SW INT's
0x0100 - 0x011F
0x0120 - 0x013F
0x0140 - 0x0148
0x014A - 0x01FF
Primary Registers
Swap Registers
HPI Int / Mailbox
LCP Variables
0x0200- 0x02FF
0x0300- 0x030F
0x0310- 0x03FF
0x0400- 0x04A2
0x04A4- 0x3FFF
0xC000- 0xC0FF
USB Registers
Slave Setup Packet
BIOS Stack
USB Slave & OTG
USER SPACE
~15K
Control Registers
0xE000- 0xFFFF
Figure 6-1. Memory Map
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7.0 Registers
Some registers have different functions for a read vs. a write access or USB host vs. USB device mode. Therefore, registers of
this type will have multiple definitions for the same address.
The default register values listed in this data sheet may get altered to some other value during BIOS initialization. Please refer
to the BIOS documentation for Register initialization information.
7.1 Processor Control Registers
There are eight registers dedicated to general processor control. Each of these registers is covered in this section and is summarized in Figure 7-1.
Register Name Address R/W
CPU Flags Register 0xC000 R
Register Bank Register 0xC002 R/W
Hardware Revision Register 0xC004 R
CPU Speed Register 0xC008 R/W
Power Control Register 0xC00A R/W
Interrupt Enable Register 0xC00E R/W
Breakpoint Register 0xC014 R/W
USB Diagnostic Register 0xC03C W
Figure 7-1. Processor Control Registers
7.1.1 CPU Flags Register [0xC000] [R]
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Global
Read/Write - - - R R R R R
Default 0 0 0 X X X X X
Interrupt
Enable
Negative
Flag
Overflow
Flag
Carry
Flag
Figure 7-2. CPU Flags Register
Register Description
The CPU Flags Register is a read-only register that gives processor flags status.
Global Interrupt Enable (Bit 4)
The Global Interrupt Enable bit indicates if the Global Interrupts are enabled.
1: Enabled
0: Disabled
Negative Flag (Bit 3)
The Negative Flag bit indicates if an arithmetic operation results in a negative answer.
1: MS result bit is ‘1’
0: MS result bit is not ‘1’
Zero
Flag
Overflow Flag (Bit 2)
The Overflow Flag bit indicates if an overflow condition has occurred. An overflow condition can occur if an arithmetic result was
either larger than the destination operand size (for addition) or smaller than the destination operand should allow for subtraction.
1: Overflow occurred
0: Overflow did not occur
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Carry Flag (Bit 1)
The Carry Flag bit indicates if an arithmetic operation resulted in a carry for addition, or borrow for subtraction.
1: Carry/Borrow occurred
0: Carry/Borrow did not occur
Zero Flag (Bit 0)
The Zero Flag bit indicates if an instruction execution resulted in a ‘0’.
1: Zero occurred
0: Zero did not occur
7.1.2 Bank Register [0xC002] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 1
Bit # 7 6 5 4 3 2 1 0
Field ...Address Reserved
Read/Write R/W R/W R/W - - - - -
Default 0 0 0 X X X X X
Figure 7-3. Bank Register
Register Description
The Bank Register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers
R0–R15. A register address is automatically generated by:
a. Shifting the four LSBs of the register address left by 1.
b. ORing the four shifted bits of the register address with the 12 MSBs of the Bank Register.
c. Force the LSB to zero.
For example, if the Bank Register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 will be
read. See Table 7-1 for details.
Table 7-1. Bank Register Example
Register Hex Value Binary Value
Bank 0x0100 0000 0001 0000 0000
R14 0x000E << 1 = 0x001C 0000 0000 0001 1100
RAM Location 0x011C 0000 0001 0001 1100
Address (Bits [15:4])
The Address field is used as a base address for all register addresses to start from.
Reserved
All reserved bits should be written as ‘0’.
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7.1.3 Hardware Revision Register [0xC004] [R]
Bit # 15 14 13 12 11 10 9 8
Field Revision...
Read/Write R R R R R R R R
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field ...Revision
Read/Write R R R R R R R R
Default X X X X X X X X
Figure 7-4. Revision Register
Register Description
The Hardware Revision Register is a read only register that indicates the silicon revision number. The first silicon revision is
represented by 0x0101. This number will be increased by one for each new silicon revision.
Revision (Bits [15:0])
The Revision field contains the silicon revision number.
7.1.4 CPU Speed Register [0xC008] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved CPU Speed
Read/Write - - - - R/W R/W R/W R/W
Default 0 0 0 0 1 1 1 1
Figure 7-5. CPU Speed Register
Register Description
The CPU Speed Register allows the processor to operate at a user selected speed. This register will only affect the CPU, all other
peripheral timing is still based on the 48-MHz system clock (unless otherwise noted).
CPU Speed (Bits[3:0])
The CPU Speed field is a divisor that selects the operating speed of the processor as defined in Ta bl e 7-2 .
Table 7-2. CPU Speed Definition
CPU Speed [3:0] Processor Speed
0000 48 MHz/1
0001 48 MHz/2
0010 48 MHz/3
0011 48 MHz/4
0100 48 MHz/5
0101 48 MHz/6
0110 48 MHz/7
0111 48 MH z/8
1000 48 MHz/9
1001 48 MHz/10
1010 48 MHz/11
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Table 7-2. CPU Speed Definition (continued)
CPU Speed [3:0] Processor Speed
1011 48 MHz/12
1100 48 MHz/13
1101 48 MHz/14
1110 48 MHz/15
1111 48 MHz /1 6
Reserved
All reserved bits should be written as ‘0’.
7.1.5 Power Control Register [0xC00A] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved Host/Device 2
Read/Write - R/W - R/W R/W - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field HPI
Wake Enable
Read/Write R/W - - R/W - R R/W R/W
Default 0 0 0 0 0 0 0 0
Wake Enable
Reserved Host/Device 1
Reserved GPI
Wake Enable
Wake Enable
OTG
Wake Enable
Reserved
Reserved HSS
Boost 3V
OK
Wake Enable
Sleep
Enable
Wake Enable
SPI
Halt
Enable
Figure 7-6. Power Control Register
Register Description
The Power Control Register controls the power-down and wakeup options. Either the sleep mode or the halt mode options can
be selected. All other writable bits in this register can be used as a wakeup source while in sleep mode.
Host/Device 2 Wake Enable (Bit 14)
The Host/Device 2 Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 2 transition. This wake
up from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wakeup on Host/Device 2 transition.
0: Disable wakeup on Host/Device 2 transition.
Host/Device 1 Wake Enable (Bit 12)
The Host/Device 1 Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 1 transition. This wakeup
from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wakeup on Host/Device 1 transition
0: Disable wakeup on Host/Device 1 transition
OTG Wake Enable (Bit 11)
The OTG Wake Enable bit enables or disables a wakeup condition to occur on either an OTG VBUS_Valid or OTG ID transition
(IRQ20).
1: Enable wakeup on OTG VBUS valid or OTG ID transition
0: Disable wakeup on OTG VBUS valid or OTG ID transition
HSS Wake Enable (Bit 9)
The HSS Wake Enable bit enables or disables a wakeup condition to occur on an HSS Rx serial input transition. The processor
may take several hundreds of microseconds before being operational after wakeup. Therefore, the incoming data byte that causes
the wakeup will be discarded.
1: Enable wakeup on HSS Rx serial input transition
0: Disable wakeup on HSS Rx serial input transition
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SPI Wake Enable (Bit 8)
The SPI Wake Enable bit enables or disables a wakeup condition to occur on a falling SPI_nSS input transition. The processor
may take several hundreds of microseconds before being operational after wakeup. Therefore, the incoming data byte that causes
the wakeup will be discarded.
1: Enable wakeup on falling SPI nSS input transition
0: Disable SPI_nSS interrupt
HPI Wake Enable (Bit 7)
The HPI Wake Enable bit enables or disables a wakeup condition to occur on an HPI interface read.
1: Enable wakeup on HPI interface read
0: Disable wakeup on HPI interface read
GPI Wake Enable (Bit 4)
The GPI Wake Enable bit enables or disables a wakeup condition to occur on a GPIO(25:24) transition.
1: Enable wakeup on GPIO(25:24) transition
0: Disable wakeup on GPIO(25:24) transition
Boost 3V OK (Bit 2)
The Boost 3V OK bit is a read only bit that returns the status of the OTG Boost circuit.
1: Boost circuit not ok and internal voltage rails are below 3.0V
0: Boost circuit ok and internal voltage rails are at or above 3.0V
Sleep Enable (Bit 1)
Setting this bit to ‘1’ will immediately initiate SLEEP mode. While in SLEEP mode, the entire chip is paused achieving the lowest
standby power state. All operations are paused, the internal clock is stopped, the booster circuit and OTG VBUS charge pump
are all powered down, and the USB transceivers are powered down. All counters and timers are paused but will retain their values.
SLEEP mode exits by any activity selected in this register. When SLEEP mode ends, instruction execution will resume within
0.5 ms.
1: Enable Sleep Mode
0: No Function
Halt Enable (Bit 0)
Setting this bit to ‘1’ will immediately initiate HALT mode. While in HALT mode, only the CPU is stopped. The internal clock still
runs and all peripherals still operate, including the USB engines. The power savings using HALT is most cases will be minimal,
but in applications that are very CPU intensive the incremental savings may provide some benefit.
The HALT state is exited when any enabled interrupt is triggered. Upon exiting the HALT state, one or two instructions immediately
following the HALT instruction may get executed before the waking interrupt is serviced (you may want to follow the HALT
instruction with two NOPs).
1: Enable Halt Mode
0: No Function
Reserved
All reserved bits should be written as ‘0’.
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7.1.6 Interrupt Enable Register [0xC00E] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved OTG
Read/Write - - - R/W R/W - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field HSS
Read/Write R/W R/W R/W - R/W R/W R/W R/W
Default 0 0 0 1 0 0 0 0
Interrupt
Enable
In Mailbox
Interrupt
Enable
Out Mailbox
Interrupt
Enable
Interrupt
Enable
Reserved UART
Figure 7-7. Interrupt Enable Register
Register Description
The Interrupt Enable Register allows control of the hardware interrupt vectors.
OTG Interrupt Enable (Bit 12)
The OTG Interrupt Enable bit enables or disables the OTG ID / OTG4.4V Valid hardware interrupt.
1: Enable OTG interrupt
0: Disable OTG interrupt
SPI
Interrupt
Enable
Interrupt
Enable
Reserved Host/Device 2
GPIO
Interrupt
Enable
Interrupt
Enable
Timer 1
Interrupt
Enable
Host/Device 1
Interrupt
Enable
Timer 0
Interrupt
Enable
SPI Interrupt Enable (Bit 11)
The SPI Interrupt Enable bit enables or disables the following three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA Block
Done.
1: Enable SPI interrupt
0: Disable SPI interrupt
Host/Device 2 Interrupt Enable (Bit 9)
The Host/Device 2 Interrupt Enable bit enables or disables all of the following Host/Device 2 hardware interrupts: Host 2 USB
Done, Host 2 USB SOF/EOP, Host 2 WakeUp/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB, Device
2 Endpoint n.
1: Enable Host 2 and Device 2 interrupt
0: Disable Host 2 and Device 2 interrupt
Host/Device 1 Interrupt Enable (Bit 8)
The Host/Device 1 Interrupt Enable bit enables or disables all of the following Host/Device 1 hardware interrupts: Host 1 USB
Done, Host 1 USB SOF/EOP, Host 1 WakeUp/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device
1Endpoint n.
1: Enable Host 2 and Device 2 interrupt
0: Disable Host 2 and Device 2 interrupt
HSS Interrupt Enable (Bit 7)
The HSS Interrupt Enable bit enables or disables the following High-speed Serial Interface hardware interrupts: HSS Block Done,
and HSS RX Full.
1: Enable HSS interrupt
0: Disable HSS interrupt
In Mailbox Interrupt Enable (Bit 6)
The In Mailbox Interrupt Enable bit enables or disables the HPI: Incoming Mailbox hardware interrupt.
1: Enable MBXI interrupt
0: Disable MBXI interrupt
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Out Mailbox Interrupt Enable (Bit 5)
The Out Mailbox Interrupt Enable bit enables or disables the HPI: Outgoing Mailbox hardware interrupt.
1: Enable MBXO interrupt
0: Disable MBXO interrupt
UART Interrupt Enable (Bit 3)
The UART Interrupt Enable bit enables or disables the following UART hardware interrupts: UART TX, and UART RX.
1: Enable UART interrupt
0: Disable UART interrupt
GPIO Interrupt Enable (Bit 2)
The GPIO Interrupt Enable bit enables or disables the General Purpose I/O Pins Interrupt (See the GPIO Control Register). When
GPIO bit is reset, all pending GPIO interrupts are also cleared.
1: Enable GPIO interrupt
0: Disable GPIO interrupt
Timer 1 Interrupt Enable (Bit 1)
The Timer 1 Interrupt Enable bit enables or disables the TImer1 Interrupt Enable. When this bit is reset, all pending Timer 1
interrupts are cleared.
1: Enable TM1interrupt
0: Disable TM1 interrupt
Timer 0 Interrupt Enable (Bit 0)
The Timer 0 Interrupt Enable bit enables or disables the TImer0 Interrupt Enable. When this bit is reset, all pending Timer 0
interrupts are cleared.
1: Enable TM0 interrupt
0: Disable TM0 interrupt
Reserved
All reserved bits should be written as ‘0’.
7.1.7 Breakpoint Register [0xC014] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-8. Breakpoint Register
Register Description
The Breakpoint Register holds the breakpoint address. When the program counter match this address, the INT127 interrupt
occurs. To clear this interrupt, a zero value should be written to this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
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7.1.8 USB Diagnostic Register [0xC03C] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved Port 2A
Read/Write - R/W - R/W - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Pull-down
Read/Write - R/W R/W R/W - R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Diagnostic
Enable
Enable
Register Description
The USB Diagnostic Register provides control of diagnostic modes. It is intended for use by device characterization tests, not for
normal operations. This register is Read/Write by the on-chip CPU but is write only via the HPI port.
Port 2A Diagnostic Enable (Bit 15)
The Port 2A Diagnostic Enable bit enables or disables Port 2A for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD
0: Do not apply test conditions
Reserved Port 1A
LS Pull-up
Enable
Diagnostic
Enable
FS Pull-up
Enable
Reserved Force Select
Figure 7-9. USB Diagnostic Register
Reserved...
Port 1A Diagnostic Enable (Bit 15)
The Port 1A Diagnostic Enable bit enables or disables Port 1A for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD
0: Do not apply test conditions
Pull-down Enable (Bit 6)
The Pull-down Enable bit enables or disables full-speed pull-down resistors (pull-down on both D+ and D–) for testing.
1: Enable pull-down resistors on both D+ and D–
0: Disable pull-down resistors on both D+ and D–
LS Pull-up Enable (Bit 5)
The LS Pull-up Enable bit enables or disables a low-speed pull-up resistor (pull-up on D–) for testing.
1: Enable low-speed pull-up resistor on D–
0: Pull-up resistor is not connected on D–
FS Pull-up Enable (Bit 4)
The FS Pull-up Enable bit enables or disables a full-speed pull-up resistor (pull-up on D+) for testing.
1: Enable full-speed pull-up resistor on D+
0: Pull-up resistor is not connected on D+
Force Select (Bits [2:0])
The Force Select field bit selects several different test condition states on the data lines (D+/D–). See Tab le 7 -3 for details.
Table 7-3. Force Select Definition
Force Select [2:0] Data Line State
1xx Assert SE0
01x Toggle JK
001 Assert J
000 Assert K
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