EZ-OTG™
CY7C67200
Programmable USB On-The-Go
Host/Peripheral Controller
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-08014 Rev. *E Revised September 16, 2003
CY7C67200
TABLE OF CONTENTS
1.0 INTRODUCTION ..............................................................................................................................9
1.1 EZ-OTG Features .......................................................................................................................9
2.0 TYPICAL APPLICATIONS .............................................................................................................10
3.0 FUNCTIONAL OVERVIEW ............................................................................................................10
3.1 Processor Core .........................................................................................................................10
3.1.1 Processor ........................................................................................................................................ 10
3.1.2 Clocking ..........................................................................................................................................10
3.1.3 Memory ...........................................................................................................................................10
3.1.4 Interrupts ......................................................................................................................................... 10
3.1.5 General Timers and Watchdog Timer ............................................................................................. 10
3.1.6 Power Management ........................................................................................................................10
4.0 INTERFACE DESCRIPTIONS .......................................................................................................11
4.1 USB Interface ............................................................................................................................11
4.1.1 USB Features ..................................................................................................................................12
4.1.2 USB Pins. ........................................................................................................................................ 12
4.2 OTG Interface ...........................................................................................................................12
4.2.1 OTG Features ................................................................................................................................. 12
4.2.2 OTG Pins. ....................................................................................................................................... 13
4.3 General Purpose I/O Interface ..................................................................................................13
4.3.1 GPIO Description ............................................................................................................................13
4.3.2 Unused Pin Descriptions ................................................................................................................. 13
4.4 UART Interface .........................................................................................................................13
4.4.1 UART Features ...............................................................................................................................13
4.4.2 UART Pins. ..................................................................................................................................... 13
4.5 I2C EEPROM Interface .............................................................................................................13
4.5.1 I2C EEPROM Features ................................................................................................................... 13
4.5.2 I2C EEPROM Pins. ......................................................................................................................... 14
4.6 Serial Peripheral Interface ........................................................................................................14
4.6.1 SPI Features ...................................................................................................................................14
4.6.2 SPI Pins ..........................................................................................................................................14
4.7 High-Speed Serial Interface ......................................................................................................14
4.7.1 HSS Features ..................................................................................................................................14
4.7.2 HSS Pins ......................................................................................................................................... 15
4.8 Host Port Interface (HPI) ...........................................................................................................15
4.8.1 HPI Features ...................................................................................................................................15
4.8.2 HPI Pins ..........................................................................................................................................15
4.9 Charge Pump Interface .............................................................................................................16
4.9.1 Charge Pump Features ................................................................................................................... 16
4.9.2 Charge Pump Pins ..........................................................................................................................17
4.10 Booster Interface .....................................................................................................................17
4.10.1 Booster Pins. .................................................................................................................................18
4.11 Crystal Interface ......................................................................................................................18
4.11.1 Crystal Pins. .................................................................................................................................. 18
4.12 Boot Configuration Interface ...................................................................................................18
4.13 Operational Modes ..................................................................................................................19
4.13.1 Coprocessor Mode ........................................................................................................................ 19
4.13.2 Stand-alone Mode ......................................................................................................................... 19
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CY7C67200
TABLE OF CONTENTS (continued)
5.0 POWER SAVINGS AND RESET DESCRIPTION ..........................................................................20
5.1 Power Savings Mode Description .............................................................................................20
5.2 Sleep .........................................................................................................................................20
5.3 External (Remote) wakeup Source ...........................................................................................20
5.4 Power-On Reset (POR) Description .........................................................................................21
5.5 Reset Pin .................................................................................................................................. 21
5.6 USB Reset ................................................................................................................................21
6.0 MEMORY MAP ...............................................................................................................................21
6.1 Mapping ....................................................................................................................................21
6.2 Internal Memory ........................................................................................................................21
7.0 REGISTERS ...................................................................................................................................23
7.1 Processor Control Registers .....................................................................................................23
7.1.1 CPU Flags Register [0xC000] [R] .................................................................................................23
7.1.2 Bank Register [0xC002] [R/W] ...................................................................................................... 24
7.1.3 Hardware Revision Register [0xC004] [R] .................................................................................... 25
7.1.4 CPU Speed Register [0xC008] [R/W] ........................................................................................... 25
7.1.5 Power Control Register [0xC00A] [R/W] .......................................................................................26
7.1.6 Interrupt Enable Register [0xC00E] [R/W] .................................................................................... 28
7.1.7 Breakpoint Register [0xC014] [R/W] .............................................................................................29
7.1.8 USB Diagnostic Register [0xC03C] [R/W] .....................................................................................30
7.2 Timer Registers ......................................................................................................................... 31
7.2.1 Watchdog Timer Register [0xC00C] [R/W] ................................................................................... 31
7.2.2 Timer n Register [R/W] ....................................................................................................................32
7.3 General USB Registers ............................................................................................................. 32
7.3.1 USB n Control Register [R/W] ......................................................................................................... 32
7.4 USB Host Only Registers ..........................................................................................................34
7.4.1 Host n Control Register [R/W] .........................................................................................................35
7.4.2 Host n Address Register [R/W] .......................................................................................................35
7.4.3 Host n Count Register [R/W] ........................................................................................................... 36
7.4.4 Host n Endpoint Status Register [R] ............................................................................................... 36
7.4.5 Host n PID Register [W] .................................................................................................................. 38
7.4.6 Host n Count Result Register [R] ....................................................................................................39
7.4.7 Host n Device Address Register [W] ............................................................................................... 39
7.4.8 Host n Interrupt Enable Register [R/W] ........................................................................................... 40
7.4.9 Host n Status Register [R/W] .......................................................................................................... 41
7.4.10 Host n SOF/EOP Count Register [R/W] ........................................................................................ 42
7.4.11 Host n SOF/EOP Counter Register [R] .........................................................................................42
7.4.12 Host n Frame Register [R] ............................................................................................................ 43
7.5 USB Device Only Registers ......................................................................................................43
7.5.1 Device n Endpoint n Control Register [R/W] ...................................................................................44
7.5.2 Device n Endpoint n Address Register [R/W] ................................................................................. 45
7.5.3 Device n Endpoint n Count Register [R/W] .....................................................................................46
7.5.4 Device n Endpoint n Status Register [R/W] ....................................................................................46
7.5.5 Device n Endpoint n Count Result Register [R/W] ..........................................................................48
7.5.6 Device n Interrupt Enable Register [R/W] .......................................................................................49
7.5.7 Device n Address Register [W] .......................................................................................................51
7.5.8 Device n Status Register [R/W] .......................................................................................................52
7.5.9 Device n Frame Number Register [R] .............................................................................................54
7.5.10 Device n SOF/EOP Count Register [W] ........................................................................................ 54
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CY7C67200
TABLE OF CONTENTS (continued)
7.6 OTG Control Registers .............................................................................................................55
7.6.1 OTG Control Register [0xC098] [R/W] .......................................................................................... 55
7.7 GPIO Registers .........................................................................................................................56
7.7.1 GPIO Control Register [0xC006] [R/W] ......................................................................................... 57
7.7.2 GPIO 0 Output Data Register [0xC01E] [R/W] ................................................................................58
7.7.3 GPIO 1 Output Data Register [0xC024] [R/W] ................................................................................59
7.7.4 GPIO 0 Input Data Register [0xC020] [R] .....................................................................................59
7.7.5 GPIO 1 Input Data Register [0xC026] [R] .......................................................................................59
7.7.6 GPIO 0 Direction Register [0xC022] [R/W] ................................................................................... 60
7.7.7 GPIO 1 Direction Register [0xC028] [R/W] ................................................................................... 60
7.8 HSS Registers .......................................................................................................................... 61
7.8.1 HSS Control Register [0xC070] [R/W] .......................................................................................... 61
7.8.2 HSS Baud Rate Register [0xC072] [R/W] .....................................................................................63
7.8.3 HSS Transmit Gap Register [0xC074] [R/W] ..................................................................................63
7.8.4 HSS Data Register [0xC076] [R/W] ..............................................................................................64
7.8.5 HSS Receive Address Register [0xC078] [R/W] ............................................................................. 64
7.8.6 HSS Receive Counter Register [0xC07A] [R/W] ........................................................................... 65
7.8.7 HSS Transmit Address Register [0xC07C] [R/W] .........................................................................65
7.8.8 HSS Transmit Counter Register [0xC07E] [R/W] .......................................................................... 66
7.9 HPI Registers ............................................................................................................................66
7.9.1 HPI Breakpoint Register [0x0140] [R] ............................................................................................. 66
7.9.2 Interrupt Routing Register [0x0142] [R] ...........................................................................................67
7.9.3 SIEXmsg Register [W] .................................................................................................................... 68
7.9.4 HPI Mailbox Register [0xC0C6] [R/W] .......................................................................................... 69
7.9.5 HPI Status Port [] [HPI: R] ...............................................................................................................70
7.10 SPI Registers .......................................................................................................................... 72
7.10.1 SPI Configuration Register [0xC0C8] [R/W] ................................................................................72
7.10.2 SPI Control Register [0xC0CA] [R/W] .........................................................................................74
7.10.3 SPI Interrupt Enable Register [0xC0CC] [R/W] ........................................................................... 75
7.10.4 SPI Status Register [0xC0CE] [R] ............................................................................................... 76
7.10.5 SPI Interrupt Clear Register [0xC0D0] [W] ....................................................................................77
7.10.6 SPI CRC Control Register [0xC0D2] [R/W] .................................................................................77
7.10.7 SPI CRC Value Register [0xC0D4] [R/W] ...................................................................................78
7.10.8 SPI Data Register [0xC0D6] [R/W] ............................................................................................. 79
7.10.9 SPI Transmit Address Register [0xC0D8] [R/W] ......................................................................... 79
7.10.10 SPI Transmit Count Register [0xC0DA] [R/W] ............................................................................79
7.10.11 SPI Receive Address Register [0xC0DC [R/W] ........................................................................80
7.10.12 SPI Receive Count Register [0xC0DE] [R/W] ........................................................................... 80
7.11 UART Registers ......................................................................................................................81
7.11.1 UART Control Register [0xC0E0] [R/W] ......................................................................................81
7.11.2 UART Status Register [0xC0E2] [R] ........................................................................................... 82
7.11.3 UART Data Register [0xC0E4] [R/W] ..........................................................................................82
8.0 PIN DIAGRAM ................................................................................................................................ 83
9.0 PIN DESCRIPTIONS ......................................................................................................................84
10.0 ABSOLUTE MAXIMUM RATINGS ..............................................................................................85
11.0 OPERATING CONDITIONS .........................................................................................................85
12.0 CRYSTAL REQUIREMENTS (XTALIN, XTALOUT) ...................................................................86
13.0 DC CHARACTERISTICS ...........................................................................................................86
13.1 USB Transceiver .....................................................................................................................87
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CY7C67200
TABLE OF CONTENTS (continued)
14.0 AC TIMING CHARACTERISTICS ................................................................................................87
14.1 Reset Timing ...........................................................................................................................87
14.2 Clock Timing ...........................................................................................................................88
14.3 I2C EEPROM Timing ..............................................................................................................88
14.4 HPI (Host Port Interface) Write Cycle Timing .........................................................................89
14.5 HPI (Host Port Interface) Read Cycle Timing ......................................................................... 90
14.6 HSS BYTE Mode Transmit .....................................................................................................91
14.7 HSS Block Mode Transmit ......................................................................................................91
14.8 HSS BYTE and BLOCK Mode Receive ..................................................................................91
14.9 Hardware CTS/RTS Handshake .............................................................................................92
15.0 REGISTER SUMMARY ................................................................................................................93
16.0 ORDERING INFORMATION ........................................................................................................97
17.0 PACKAGE DIAGRAMS ...............................................................................................................97
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CY7C67200
LIST OF FIGURES
Figure 1-1. Block Diagram .......................................................................................................................9
Figure 4-1. Charge Pump ...................................................................................................................... 16
Figure 4-2. Power Supply Connection With Booster ............................................................................. 17
Figure 4-3. Power Supply Connection Without Booster ........................................................................ 17
Figure 4-4. Crystal Interface .................................................................................................................. 18
Figure 4-5. Minimum Standalone Hardware Configuration – Peripheral Only.......................................20
Figure 6-1. Memory Map .......................................................................................................................22
Figure 7-1. Processor Control Registers ............................................................................................... 23
Figure 7-2. CPU Flags Register.............................................................................................................23
Figure 7-3. Bank Register...................................................................................................................... 24
Figure 7-4. Revision Register ................................................................................................................ 25
Figure 7-5. CPU Speed Register ...........................................................................................................25
Figure 7-6. Power Control Register ....................................................................................................... 26
Figure 7-7. Interrupt Enable Register .................................................................................................... 28
Figure 7-8. Breakpoint Register............................................................................................................. 29
Figure 7-9. USB Diagnostic Register..................................................................................................... 30
Figure 7-10. Timer Registers .................................................................................................................31
Figure 7-11. Watchdog Timer Register..................................................................................................31
Figure 7-12. Timer n Register................................................................................................................ 32
Figure 7-13. USB Registers................................................................................................................... 32
Figure 7-14. USB n Control Register .....................................................................................................33
Figure 7-15. USB Host Only Register.................................................................................................... 34
Figure 7-16. Host n Control Register .....................................................................................................35
Figure 7-17. Host n Address Register ................................................................................................... 36
Figure 7-18. Host n Count Register .......................................................................................................36
Figure 7-19. Host n Endpoint Status Register ....................................................................................... 37
Figure 7-20. Host n PID Register...........................................................................................................38
Figure 7-21. Host n Count Result Register............................................................................................ 39
Figure 7-22. Host n Device Address Register ....................................................................................... 39
Figure 7-23. Host n Interrupt Enable Register .......................................................................................40
Figure 7-24. Host n Status Register ...................................................................................................... 41
Figure 7-25. Host n SOF/EOP Count Register ......................................................................................42
Figure 7-26. Host n SOF/EOP Counter Register................................................................................... 43
Figure 7-27. Host n Frame Register ...................................................................................................... 43
Figure 7-28. USB Device Only Registers .............................................................................................. 43
Figure 7-29. Device n Endpoint n Control Register ...............................................................................44
Figure 7-30. Device n Endpoint n Address Register..............................................................................45
Figure 7-31. Device n Endpoint n Count Register .................................................................................46
Figure 7-32. Device n Endpoint n Status Register................................................................................. 47
Figure 7-33. Device n Endpoint n Count Result Register ...................................................................... 49
Figure 7-34. Device n Interrupt Enable Register ................................................................................... 49
Figure 7-35. Device n Address Register................................................................................................ 51
Figure 7-36. Device n Status Register................................................................................................... 52
Figure 7-37. Device n Frame Number Register.....................................................................................54
Figure 7-38. Device n SOF/EOP Count Register .................................................................................. 54
Figure 7-39. OTG Registers ..................................................................................................................55
Figure 7-40. OTG Control Register........................................................................................................55
Figure 7-41. GPIO Registers ................................................................................................................. 56
Figure 7-42. GPIO Control Register ...................................................................................................... 57
Figure 7-43. GPIO 0 Output Data Register............................................................................................58
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CY7C67200
LIST OF FIGURES (continued)
Figure 7-44. GPIO n Output Data Register............................................................................................59
Figure 7-45. GPIO 0 Input Data Register .............................................................................................. 59
Figure 7-46. GPIO 1 Input Data Register .............................................................................................. 59
Figure 7-47. GPIO 0 Direction Register................................................................................................. 60
Figure 7-48. GPIO 1 Direction Register................................................................................................. 60
Figure 7-49. HSS Registers................................................................................................................... 61
Figure 7-50. HSS Control Register ........................................................................................................61
Figure 7-51. HSS Baud Rate Register...................................................................................................63
Figure 7-52. HSS Transmit Gap Register.............................................................................................. 63
Figure 7-53. HSS Data Register ............................................................................................................64
Figure 7-54. HSS Receive Address Register ........................................................................................ 64
Figure 7-55. HSS Receive Counter Register......................................................................................... 65
Figure 7-56. HSS Transmit Address Register ....................................................................................... 65
Figure 7-57. HSS Transmit Counter Register........................................................................................ 66
Figure 7-58. HPI Registers .................................................................................................................... 66
Figure 7-59. HPI Breakpoint Register.................................................................................................... 66
Figure 7-60. Interrupt Routing Register ................................................................................................. 67
Figure 7-61. SIEXmsg Register .............................................................................................................69
Figure 7-62. HPI Mailbox Register.........................................................................................................69
Figure 7-63. HPI Status Port..................................................................................................................70
Figure 7-64. SPI Registers .................................................................................................................... 72
Figure 7-65. SPI Configuration Register................................................................................................ 72
Figure 7-66. SPI Control Register..........................................................................................................74
Figure 7-67. SPI Interrupt Enable Register............................................................................................75
Figure 7-68. SPI Status Register ...........................................................................................................76
Figure 7-69. SPI Interrupt Clear Register .............................................................................................. 77
Figure 7-70. SPI CRC Control Register................................................................................................. 77
Figure 7-71. SPI CRC Value Register ................................................................................................... 78
Figure 7-72. SPI Data Register..............................................................................................................79
Figure 7-73. SPI Transmit Address Register .........................................................................................79
Figure 7-74. SPI Transmit Count Register.............................................................................................79
Figure 7-75. SPI Receive Address Register ..........................................................................................80
Figure 7-76. SPI Receive Count Register..............................................................................................80
Figure 7-77. UART Registers ................................................................................................................ 81
Figure 7-78. UART Control Register...................................................................................................... 81
Figure 7-79. UART Status Register .......................................................................................................82
Figure 7-80. UART Data Register..........................................................................................................82
Figure 8-1. EZ-OTG Pin Diagram ..........................................................................................................83
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CY7C67200
LIST OF TABLES
Table 4-1. Interface Options for GPIO Pins ..........................................................................................11
Table 4-2. USB Port Configuration Options ..........................................................................................12
Table 4-3. USB Interface Pins ..............................................................................................................12
Table 4-4. OTG Interface Pins ..............................................................................................................13
Table 4-5. UART Interface Pins ............................................................................................................13
Table 4-6. I2C EEPROM Interface Pins ...............................................................................................14
Table 4-7. SPI Interface Pins ................................................................................................................14
Table 4-8. HSS Interface Pins ..............................................................................................................15
Table 4-9. HPI Interface Pins ................................................................................................................15
Table 4-10. HPI Addressing ..................................................................................................................16
Table 4-11. Charge Pump Interface Pins .............................................................................................17
Table 4-12. Charge Pump Interface Pins .............................................................................................18
Table 4-13. Crystal Pins .......................................................................................................................18
Table 4-14. Boot Configuration Interface ..............................................................................................18
Table 5-1. wakeup Sources
Table 7-1. Bank Register Example .......................................................................................................24
Table 7-2. CPU Speed Definition ..........................................................................................................25
Table 7-3. Force Select Definition ........................................................................................................30
Table 7-4. Period Select Definition .......................................................................................................31
Table 7-5. USB Data Line Pull-Up and Pull-Down Resistors ................................................................33
Table 7-6. Port A Force D± State .........................................................................................................34
Table 7-7. PID Select Definition ............................................................................................................38
Table 7-8. Mode Select Definition .........................................................................................................57
Table 7-9. Scale Select Field Definition for SCK Frequency ................................................................ 73
Table 7-10. CRC Mode Definition .........................................................................................................77
Table 7-11. UART Baud Select Definition ............................................................................................81
Table 9-1. Pin Descriptions ...................................................................................................................84
Table 12-1. Crystal Requirements ........................................................................................................86
Table 13-1. DC Characteristics..............................................................................................................86
Table 13-2. DC Characteristics: Charge Pump ....................................................................................86
Table 15-1. Register Summary .............................................................................................................93
Table 16-1. Ordering Information ..........................................................................................................97
..................................................................................................................21
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CY7C67200
1.0 INTRODUCTION
EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is
designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-OTG has its own 16-bit RISC
processor to act as a coprocessor or operate in standalone mode. EZ-OTG also has a programmable I/O interface block allowing
a wide range of interface options.
CY7C67200
nRESET
Control
Watchdog
Timer 0 Timer 1
UART I/F
CY16
HOST/
Peripheral
USB Ports
Vbus, ID
D+,D-
D+,D-
16-bit RISC CORE
OTG
X1
X2
PLL
USB-A
SIE1
USB-A
SIE2
Mobile
Power
Booster
4Kx16
ROM BIOS
8Kx16
RAM
I2C
EEPROM I/F
HSS I/F
SPI I/F
HPI I/F
GPIO
GPIO [24:0]
SHARED INPUT/OUTPUT PINS
Figure 1-1. Block Diagram
1.1 EZ-OTG Features
• Single-chip programmable USB dual role (Host/Peripheral) controller with two configurable Serial Interface Engines
(SIEs) and two USB ports
• Support for USB OTG protocol
• On-chip 48-MHz 16-bit processor with dynamically switchable clock speed
• Configurable I/O block supporting a variety of I/O options or up to 25 bits of General Purpose I/O (GPIO)
• 4K × 16 internal mask ROM containing built-in BIOS that supports a communication-ready state with access to I2C
EEPROM interface, external ROM, UART, or USB
• 8K x 16 internal RAM for code and data buffering
• 16-bit parallel host port interface (HPI) with DMA/Mailbox data path for an external processor to directly access all
on-chip memory and control on-chip SIEs
• Fast serial port supports from 9600 baud to 2.0 Mbaud
• SPI supporting both master and slave
• Supports 12-MHz external crystal or clock
• Power consumption: 50 mA operational; 30 mA standby
• 2.7V to 3.6V power supply voltage
• Package option — 48-pin FBGA
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CY7C67200
2.0 Typical Applications
EZ-OTG is a very powerful and flexible dual-role USB controller that supports a wide variety of applications. It is primarily intended
to enable USB OTG capability in applications such as:
• Cellular phones
• PDAs and pocket PCs
• Video and digital still cameras
• MP3 players
• Mass storage devices.
3.0 Functional Overview
3.1 Processor Core
3.1.1 Processor
EZ-OTG has a general-purpose 16-bit embedded RISC processor that runs at 48 MHz.
3.1.2 Clocking
EZ-OTG requires a 12-MHz source for clocking. Either an external crystal or TTL-level oscillator may be used. EZ-OTG has an
internal PLL that produces a 48-MHz internal clock from the 12-MHz source.
3.1.3 Memory
EZ-OTG has a built-in 4K × 16 masked ROM and a 8K × 16 internal RAM. The masked ROM contains the EZ-OTG BIOS. The
internal RAM can be used for program code or data.
3.1.4 Interrupts
EZ-OTG provides 128 interrupt vectors. The first 48 vectors are hardware interrupts and the following 80 vectors are software
interrupts.
3.1.5 General Timers and Watchdog Timer
EZ-OTG has two built-in programmable timers and a Watchdog timer. All three timers can generate an interrupt to the EZ-OTG.
3.1.6 Power Management
EZ-OTG has one main power-saving mode, Sleep. Sleep mode pauses all operations and provides the lowest power state.
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CY7C67200
4.0 Interface Descriptions
EZ-OTG has a variety of interface options for connectivity, with several interface options available. See Ta bl e 4-1 to understand
how the interfaces share pins and can coexist. Below are some general guidelines:
•I2C EEPROM and OTG do not conflict with any interfaces
• HPI is mutually exclusive to: HSS, SPI, and UART.
Table 4-1. Interface Options for GPIO Pins
GPIO Pins HPI HSS SPI UART I2C OTG
GPIO31 SCL/SDA
GPIO30 SCL/SDA
GPIO29 OTGID
GPIO24 INT
GPIO23 nRD
GPIO22 nWR
GPIO21 nCS
GPIO20 A1
GPIO19 A0
GPIO15 D15 CTS
GPIO14 D14 RTS
GPIO13 D13 RXD
GPIO12 D12 TXD
GPIO11 D11 MOSI
GPIO10 D10 SCK
GPIO9 D9 nSSI
GPIO8 D8 MISO
GPIO7 D7 TX
GPIO6 D6 RX
GPIO5 D5
GPIO4 D4
GPIO3 D3
GPIO2 D2
GPIO1 D1
GPIO0 D0
4.1 USB Interface
EZ-OTG has two built-in Host/Peripheral SIEs that each have a single USB transceiver, meeting the USB 2.0 specification
requirements for full- and low-speed (high-speed is not supported). In Host mode, EZ-OTG supports two downstream ports, each
support control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-OTG supports one peripheral port with eight
endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints
1 though 7 support Interrupt, Bulk (up to 64 Bytes/packet), or Isochronous transfers (up to 1023 Bytes/packet size). EZ-OTG also
supports a combination of Host and Peripheral ports simultaneously. EZ-OTG also supports a combination of Host and Peripheral
ports simultaneously as shown in Table 4-2.
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Table 4-2. USB Port Configuration Options
Port Configurations Port 1A Port 2A
OTG OTG –
OTG + 1 Host OTG Host
OTG + 1 Peripheral OTG Peripheral
1 Host + 1 Peripheral Host Peripheral
1 Host + 1 Peripheral Peripheral Host
2 Hosts Host Host
1 Host Host –
1 Host – Host
2 Peripherals Peripheral Peripheral
1 Peripheral Peripheral –
1 Peripheral – Peripheral
4.1.1 USB Features
• USB 2.0-compatible for full and low speed
• Up to two downstream USB host ports
• Up to two upstream USB peripheral ports
• Configurable endpoint buffers (pointer and length), must reside in internal RAM
• Up to eight available peripheral endpoints (1 control endpoint)
• Supports Control, Interrupt, Bulk, and Isochronous transfers
• Internal DMA channels for each endpoint
• Internal pull-up and pull-down resistors
• Internal Series termination resistors on USB data lines
CY7C67200
4.1.2 USB Pins.
Table 4-3. USB Interface Pins
Pin Name Pin Number
DM1A F2
DP1A E3
DM2A C2
DP2A D3
4.2 OTG Interface
EZ-OTG has one USB port that is compatible with the USB On-The-Go supplement to the USB 2.0 specification. The USB OTG
port has a various hardware features to support Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). OTG is
only supported on USB PORT 1A.
4.2.1 OTG Features
• Internal Charge Pump to supply and control VBUS
• VBUS Valid Status (above 4.4V)
• VBUS Status for 2.4V< VBUS <0.8V
• ID Pin Status
• Switchable 2KΩ internal discharge resistor on VBUS
• Switchable 500Ω internal Pull-up resistor on VBUS
• Individually switchable internal Pull-up and Pull-down resistors on the USB Data Lines
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CY7C67200
4.2.2 OTG Pins.
Table 4-4. OTG Interface Pins
Pin Name Pin Number
DM1A F2
DP1A E3
OTGVBUS C1
OTGID F4
CSwitchA D1
CSwitchB D2
4.3 General Purpose I/O Interface
EZ-OTG has up to 25 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overall
number of available GPIOs.
4.3.1 GPIO Description
All Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48-MHZ clock cycles. GPIO pins are
latched directly into registers, a single flip-flop.
4.3.2 Unused Pin Descriptions
Unused USB pins should be tri-stated with the D+ line pulled high through the internal pull-up resistor and the D- line pulled low
through the internal pull-down resistor.
Unused GPIO pins should be configured as outputs and driven low.
4.4 UART Interface
EZ-OTG has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as a
development port or for other interface requirements. The UART interface is exposed through GPIO pins.
4.4.1 UART Features
• Supports baud rates of 900 to 115.2K
• 8-N-1
4.4.2 UART Pins.
Table 4-5. UART Interface Pins
Pin Name Pin Number
TX B5
RX B4
4.5 I2C EEPROM Interface
EZ-OTG provides a master only I2C interface for external serial EEPROMs. The serial EEPROM can be used to store application
specific code and data. This I
2
The I
C EEPROM interface is a BIOS implementation and is exposed through GPIO pins. Please refer to the BIOS documentation
for additional details on this interface.
4.5.1 I
• Supports EEPROMs up to 64 KB (512K bit)
• Auto-detection of EEPROM size
2
C EEPROM Features
2
C interface is only to be used for loading code out of EEPROM, it is not a general I2C interface.
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4.5.2 I2C EEPROM Pins.
2
Table 4-6. I
4.6 Serial Peripheral Interface
EZ-OTG provides a SPI interface for added connectivity. EZ-OTG may be configured as either an SPI master or SPI slave. The
SPI interface can be exposed through GPIO pins or the External Memory port.
4.6.1 SPI Features
• Master or slave mode operation
• DMA block transfer and PIO byte transfer modes
• Full duplex or half duplex data communication
• 8-byte receive FIFO and 8-byte transmit FIFO
• Selectable master SPI clock rates from 250 KHz to 12 MHz
• Selectable master SPI clock phase and polarity
• Slave SPI signaling synchronization and filtering
• Slave SPI clock rates up to 2 MHz
• Maskable interrupts for block and byte transfer modes
• Individual bit transfer for non-byte aligned serial communication in PIO mode
• Programmable delay timing for the active/in-active master SPI clock
• Auto or manual control for master mode slave select signal
• Complete access to internal memory
C EEPROM Interface Pins
Pin Name Pin Number
SMALL EEPROM
SCK H3
SDA F3
LARGE EEPROM
SCK F3
SDA H3
4.6.2 SPI Pins
The SPI port has a few different pin location options as shown in Table 4-7. The pin location is selectable via the GPIO Control
Register [0xC006].
Table 4-7. SPI Interface Pins
Pin Name Pin Number
nSSI F6 or C6
SCK D5
MOSI D4
MISO C5
4.7 High-Speed Serial Interface
EZ-OTG provides an HSS interface. The HSS interface is a programmable serial connection with baud rate from 9600 baud to
2 Mbaud. The HSS interface supports both byte and block mode operations as well as hardware and software handshaking.
Complete control of EZ-OTG can be accomplished through this interface via an extensible API and communication protocol. The
HSS interface can be exposed through GPIO pins or the External Memory port.
4.7.1 HSS Features
• 8-bit, no parity code
• Programmable baud rate from 9600 baud to 2 Mbaud
• Selectable 1- or 2-stop bit on transmit
• Programmable inter-character gap timing for Block Transmit
• 8-byte receive FIFO
• Glitch filter on receive
• Block mode transfer directly to/from EZ-OTG internal memory (DMA transfer)
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• Selectable CTS/RTS hardware signal handshake protocol
• Selectable XON/XOFF software handshake protocol
• Programmable Receive interrupt, Block Transfer Done interrupts
• Complete access to internal memory
4.7.2 HSS Pins
Table 4-8. HSS Interface Pins
Pin Name Pin Number
CTS F6
RTS E4
RX E5
TX E6
4.8 Host Port Interface (HPI)
EZ-OTG has an HPI interface. The HPI interface provides DMA access to the EZ-OTG internal memory by an external host, plus
a bidirectional mailbox register for supporting high-level communication protocols. This port is designed to be the primary highspeed connection to a host processor. Complete control of EZ-OTG can be accomplished through this interface via an extensible
API and communication protocol. Other than the HW communication protocols, a host processor has identical control over
EZ-Host whether connecting to the HPI or HSS port. The HPI interface is exposed through GPIO pins.
4.8.1 HPI Features
• 16-bit data bus Interface
• 16 MB/s throughput
• Auto-Increment of address pointer for fast block mode transfers
• Direct memory access (DMA) to internal memory
• Bidirectional Mailbox register
• Byte Swapping
• Complete access to internal memory
• Complete control of SIEs through HPI
• Dedicated HPI Status Register
4.8.2 HPI Pins
Table 4-9. HPI Interface Pins
[1, 2]
Pin Name Pin Number
INT H4
nRD G4
nWR H5
nCS G5
A1 H6
A0 F5
D15 F6
D14 E4
D13 E5
D12 E6
D11 D4
D10 D5
D9 C6
D8 C5
D7 B5
Notes:
1. HPI_INT is for the Outgoing Mailbox Interrupt.
2. HPI strobes are negative logic sampled on rising edge.
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Table 4-9. HPI Interface Pins (continued)
D6 B4
D5 C4
D4 B3
D3 A3
D2 C3
D1 A2
D0 B2
The two HPI address pins are used to address one of four possible HPI port registers as shown in Ta bl e 4 -1 0 below.
Table 4-10. HPI Addressing
HPI A[1:0] A1 A0
HPI Data 0 0
HPI Mailbox 0 1
HPI Address 1 0
HPI Status 1 1
[1, 2]
4.9 Charge Pump Interface
VBUS for the USB On-The-Go (OTG) port can be produced by EZ-OTG using its built-in charge pump and some external
components. The circuit connections should look similar to the diagram below.
D1
D2
CSWITCHA
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CSWITCHB
C1
VBUS
OTGVBUS
C2
Figure 4-1. Charge Pump
Component details:
• D1 and D2: Schottky diodes with a current rating greater than 60 mA
• C1: Ceramic capacitor with a capacitance of 0.1 uF
• C2: Capacitor value should be no more that 6.5 uF since that is the maximum capacitance allowed by the USB OTG spec for
a dual-role device. The minimum value of C2 is 1 uF. There are no restrictions on the type of capacitor for C2.
If the VBUS charge pump circuit is not to be used, CSWITCHA, CSWITCHB, and OTGVBUS can be left unconnected.
4.9.1 Charge Pump Features
• Meets OTG Supplement Requirements, see the DC Characteristics: Charge Pump Table 13-2.
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p
4.9.2 Charge Pump Pins
Table 4-11. Charge Pump Interface Pins
Pin Name Pin Number
OTGVBUS C1
CSwitchA D1
CSwitchB D2
4.10 Booster Interface
EZ-OTG has an on-chip power booster circuit for use with power supplies that range between 2.7V and 3.6V. The booster circuit
boosts the power to 3.3V nominal to supply power for the entire chip. The booster circuit requires an external inductor, diode, and
capacitor. During power down mode, the circuit is disabled to save power. Figure 4-2 shows how to connect the booster circuit.
BOOSTVcc
2.7V to 3.6V
L1
VSWITCH
D1
power supply
3.3V
AVCC
C1 VCC
Figure 4-2. Power Supply Connection With Booster
Component details:
• L1: Inductor with inductance of 10 uH and a current rating of at least 250 mA
• D1: Schottky diode with a current rating of at least 250 mA
• C1: Tantalum or ceramic capacitor with a capacitance of at least 2.2 uF.
Figure 4-3 shows how to connect the power supply when the booster circuit is not being used.
BOOSTVcc
3.0V to 3.6V
ower supply
VSWITCH
VCC
AVCC
Figure 4-3. Power Supply Connection Without Booster
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4.10.1 Booster Pins.
Table 4-12. Charge Pump Interface Pins
Pin Name Pin Number
BOOSTVcc F1
VSWITCH E2
4.11 Crystal Interface
The recommended crystal circuit to be used with EZ-OTG is shown in Figure 4-4. If an oscillator is used instead of a crystal circuit,
connect it to XTALIN and leave XTALOUT unconnected. For further information on the crystal requirements, see Crystal Requirements Table 12-1.
XTALIN
C1 = 22 pF
Y1
12MHz
Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
C2 = 22 pF
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XTALOUT
Figure 4-4. Crystal Interface
4.11.1 Crystal Pins.
Table 4-13. Crystal Pins
Pin Name Pin Number
XTALIN G3
XTALOUT G2
4.12 Boot Configuration Interface
EZ-OTG can boot into any one of four modes. The mode it boots into is determined by the TTL voltage level of GPIO[31:30] at
the time nRESET is deasserted. The table below shows the different boot pin combinations possible. After a reset pin event
occurs, the BIOS bootup procedure executes for up to 3 ms. GPIO[31:30] are sampled by the BIOS during bootup only. After
bootup these pins are available to the application as GPIOs.
Table 4-14. Boot Configuration Interface
GPIO31 (Pin 39) GPIO30 (Pin 40) Boot Mode
0 0 Host Port Interface (HPI)
0 1 High Speed Serial (HSS)
1 0 Serial Peripheral Interface (SPI, slave mode)
11I
2
C EEPROM (Standalone Mode)
GPIO[31:30] should be pulled high or low as needed using resistors tied to VCC or GND with resistor values between 5KΩ and
15KΩ. GPIO[31:30] should not be tied directly to VCC or GND. Note that in Standalone mode, the pull-ups on those two pins are
used for the serial I
2
C EEPROM (if implemented). The resistors used for these pull-ups should conform to the serial EEPROM
manufacturer's requirements.
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If any mode other then standalone is chosen, EZ-OTG will be in coprocessor mode. The device will power up with the appropriate
communication interface enabled according to its boot pins and wait idle until a coprocessor communicates with it. See the BIOS
documentation for greater detail on the boot process.
4.13 Operational Modes
4.13.1 Coprocessor Mode
EZ-OTG can act as a coprocessor to an external host processor. In this mode, an external host processor drives EZ-OTG and
is the main processor rather then EZ-OTG’s own 16-bit internal CPU. An external host processor may interface to EZ-OTG
through one of the following three interfaces in coprocessor mode:
• HPI mode, a 16-bit parallel interface with up to 16MBytes transfer rate
• HSS mode, a serial interface with up to 2 MBaud transfer rate
• SPI mode, a serial interface with up to 2 Mbits/s transfer rate.
At bootup GPIO[31:30] determine which of these three interfaces are used for coprocessor mode. Please refer to Table 4-14 for
details. Bootloading begins from the selected interface after POR + 3 ms of BIOS bootup.
4.13.2 Stand-alone Mode
In stand-alone mode, there is no external processor connected to EZ-OTG. Instead, EZ-OTG’s own internal 16-bit CPU is the
main processor and firmware is typically downloaded from an EEPROM. Optionally, firmware may also be downloaded via USB.
Please refer to Ta bl e 4-1 4 for booting into stand-alone mode.
After booting into stand-alone mode (GPIO[31:30] = ‘11’), the following pins are affected:
• GPIO[31:20] are configured as output pins to examine the EEPROM contents
• GPIO[28:27] are enabled for debug UART mode
• GPIO[29] is configured for as OTGID for OTG applications on PORT1A
— If OTGID is logic 1 then PORT1A (OTG) is configured as a USB peripheral
— If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host
• Ports 1B, 2A, and 2B default as USB peripheral ports
• All other pins remain INPUT pins.
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4.13.2.1 Minimum Hardware Requirements for Stand-alone Mode – Peripheral Only
Minimum Standalone Hardware Configuration - Peripheral Only
EZ-OTG
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VReg
VBus
Up to 64k x8
EEPROM
D+
DGND
SHIELD
VCC
VCC
WP
SCL
SDA
Bootstrap Options
Vcc
Vcc
10k
10k
Bootloading Firmware
GPIO[30]
GPIO[31]
Standard-B
or Mini-B
A0
A1
A2
GND
*Bootloading begins after POR + 3ms BIOS bootup
*GPIO[31:30] 31 30
Up to 2k x8 SCL SDA
>2k x8 to 64k x8 SDA SCL
VCC, AVCC,
BoostVCC
DPlus
DMinus
SCL*
SDA*
Reserved
GND, AGND,
BoostGND
Figure 4-5. Minimum Standalone Hardware Configuration – Peripheral Only
nRESET
Int. 16k x8
Code / Data
XOUT
XIN
*
Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
12MHz
Reset
Logic
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22pf
22pf
5.0 Power Savings and Reset Description
5.1 Power Savings Mode Description
EZ-OTG has one main power savings mode, Sleep. For detailed information on Sleep mode please see section 5.2.
Sleep mode is used for USB applications to support USB suspend and non USB applications as the main chip power down mode.
In addition, EZ-OTG is capable of slowing down the CPU clock speed through the CPU Speed Register [0xC008] without affecting
other peripheral timing. Reducing the CPU clock speed from 48 MHz to 24 MHz will reduce the overall current draw by around
8mA while reducing it from 48 MHz to 3 MHz will reduce the overall current draw by approximately 15 mA.
5.2 Sleep
Sleep mode is the main chip power down mode and is also used for USB suspend. Sleep mode is entered by setting the Sleep
Enable (bit 1) of the Power Control Register [0xC00A]. During Sleep mode (USB Suspend) the following events and states are
true:
• GPIO pins maintain their configuration during sleep (in suspend)
• External Memory Address pins are driven low
• XTALOUT will be turned off
• Internal PLL will be turned off
• Firmware should disable the charge pump (OTG Control Register [0xC098]) causing OTGVBUS to drop below 0.2V. Otherwise
OTGVBUS will only drop to V
• Booster circuit will be turned off
• USB transceivers will be turned off
• CPU will suspend until a programmable wakeup event.
5.3 External (Remote) wakeup Source
There are several possible events available to wake EZ-OTG from Sleep mode as shown in Tab le 5 -1 . These may also be used
as remote wakeup options for USB applications. Please see the Power Down Control Register [0xC00A] for details.
– (2 schottky diode drops)
CC
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Upon wakeup, code will begin executing within 200 ms, the time it takes the PLL to stabilize.
Table 5-1. wakeup Sources
wakeup Source
(if enabled) Event
USB Resume D+/D- Signaling
OTGVBUS Level
OTGID Any Edge
HPI Read
HSS Read
SPI Read
IRQ0 (GPIO 24) Any Edge
5.4 Power-On Reset (POR) Description
The length of the power-on-reset event can be defined by (VCC ramp to valid) + (Crystal start up). A typical application might
utilize a 12-ms power-on-reset event = ~7 ms + ~5 ms, respectively.
5.5 Reset Pin
The Reset pin is active low and requires a minimum pulse duration of 16 12-MHz clock cycles (1.3 ms). A reset event will restore
all registers to their default POR settings. Code execution will then begin 200 ms later at 0xFF00 with an immediate jump to
0xE000, the start of BIOS.
It should be noted that for up to 3 ms after BIOS starts executing, GPIO[24:19] and GPIO[15:8] will be driven as outputs for a test
mode. If these pins need to be used as inputs, a series resistor is required (10Ω-48Ω is recommended). Please refer to BIOS
documentation for addition details.
[3, 4]
5.6 USB Reset
A USB Reset will affect registers 0xC090 and 0xC0B0, all other registers remain unchanged.
6.0 Memory Map
6.1 Mapping
The EZ-OTG has just over 24 KB of addressable memory mapped from 0x0000 to 0xFFFF. This 24 KB contains both program
and data space and is byte addressable. Figure 6-1. shows the various memory region address locations.
6.2 Internal Memory
Of the internal memory, 15 KB is allocated for user’s program and data code. The lower memory space from 0x0000 to 0x04A2
is reserved for interrupt vectors, general purpose registers, USB control registers, the stack, and other BIOS variables. The upper
internal memory space contains EZ-OTG control registers from 0xC000 to 0xC0FF and the BIOS ROM itself from 0xE000 to
0xFFFF. For more information on the reserved lower memory or the BIOS ROM, please refer to the Programmers documentation
and the BIOS documentation.
During development with the EZ-OTG toolset, the lower area of User's space (0x04A4 to 0x1000) should be left available to load
the GDB stub. The GDB stub is required to allow the toolset debug access into EZ-OTG.
Notes:
3. Read data will be discarded (dummy data).
4. HPI_INT will assert on a USB Resume.
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Internal Memory
HW INT's
0x0000 - 0x00FF
SW INT's
0x0100 - 0x011F
0x0120 - 0x013F
0x0140 - 0x0148
0x014A - 0x01FF
Primary Registers
Swap Registers
HPI Int / Mailbox
LCP Variables
0x0200- 0x02FF
0x0300- 0x030F
0x0310- 0x03FF
0x0400- 0x04A2
0x04A4- 0x3FFF
0xC000- 0xC0FF
USB Registers
Slave Setup Packet
BIOS Stack
USB Slave & OTG
USER SPACE
~15K
Control Registers
0xE000- 0xFFFF
Figure 6-1. Memory Map
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7.0 Registers
Some registers have different functions for a read vs. a write access or USB host vs. USB device mode. Therefore, registers of
this type will have multiple definitions for the same address.
The default register values listed in this data sheet may get altered to some other value during BIOS initialization. Please refer
to the BIOS documentation for Register initialization information.
7.1 Processor Control Registers
There are eight registers dedicated to general processor control. Each of these registers is covered in this section and is summarized in Figure 7-1.
Register Name Address R/W
CPU Flags Register 0xC000 R
Register Bank Register 0xC002 R/W
Hardware Revision Register 0xC004 R
CPU Speed Register 0xC008 R/W
Power Control Register 0xC00A R/W
Interrupt Enable Register 0xC00E R/W
Breakpoint Register 0xC014 R/W
USB Diagnostic Register 0xC03C W
Figure 7-1. Processor Control Registers
7.1.1 CPU Flags Register [0xC000] [R]
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Global
Read/Write - - - R R R R R
Default 0 0 0 X X X X X
Interrupt
Enable
Negative
Flag
Overflow
Flag
Carry
Flag
Figure 7-2. CPU Flags Register
Register Description
The CPU Flags Register is a read-only register that gives processor flags status.
Global Interrupt Enable (Bit 4)
The Global Interrupt Enable bit indicates if the Global Interrupts are enabled.
1: Enabled
0: Disabled
Negative Flag (Bit 3)
The Negative Flag bit indicates if an arithmetic operation results in a negative answer.
1: MS result bit is ‘1’
0: MS result bit is not ‘1’
Zero
Flag
Overflow Flag (Bit 2)
The Overflow Flag bit indicates if an overflow condition has occurred. An overflow condition can occur if an arithmetic result was
either larger than the destination operand size (for addition) or smaller than the destination operand should allow for subtraction.
1: Overflow occurred
0: Overflow did not occur
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Carry Flag (Bit 1)
The Carry Flag bit indicates if an arithmetic operation resulted in a carry for addition, or borrow for subtraction.
1: Carry/Borrow occurred
0: Carry/Borrow did not occur
Zero Flag (Bit 0)
The Zero Flag bit indicates if an instruction execution resulted in a ‘0’.
1: Zero occurred
0: Zero did not occur
7.1.2 Bank Register [0xC002] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 1
Bit # 7 6 5 4 3 2 1 0
Field ...Address Reserved
Read/Write R/W R/W R/W - - - - -
Default 0 0 0 X X X X X
Figure 7-3. Bank Register
Register Description
The Bank Register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers
R0–R15. A register address is automatically generated by:
a. Shifting the four LSBs of the register address left by 1.
b. ORing the four shifted bits of the register address with the 12 MSBs of the Bank Register.
c. Force the LSB to zero.
For example, if the Bank Register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 will be
read. See Table 7-1 for details.
Table 7-1. Bank Register Example
Register Hex Value Binary Value
Bank 0x0100 0000 0001 0000 0000
R14 0x000E << 1 = 0x001C 0000 0000 0001 1100
RAM Location 0x011C 0000 0001 0001 1100
Address (Bits [15:4])
The Address field is used as a base address for all register addresses to start from.
Reserved
All reserved bits should be written as ‘0’.
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7.1.3 Hardware Revision Register [0xC004] [R]
Bit # 15 14 13 12 11 10 9 8
Field Revision...
Read/Write R R R R R R R R
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field ...Revision
Read/Write R R R R R R R R
Default X X X X X X X X
Figure 7-4. Revision Register
Register Description
The Hardware Revision Register is a read only register that indicates the silicon revision number. The first silicon revision is
represented by 0x0101. This number will be increased by one for each new silicon revision.
Revision (Bits [15:0])
The Revision field contains the silicon revision number.
7.1.4 CPU Speed Register [0xC008] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved CPU Speed
Read/Write - - - - R/W R/W R/W R/W
Default 0 0 0 0 1 1 1 1
Figure 7-5. CPU Speed Register
Register Description
The CPU Speed Register allows the processor to operate at a user selected speed. This register will only affect the CPU, all other
peripheral timing is still based on the 48-MHz system clock (unless otherwise noted).
CPU Speed (Bits[3:0])
The CPU Speed field is a divisor that selects the operating speed of the processor as defined in Ta bl e 7-2 .
Table 7-2. CPU Speed Definition
CPU Speed [3:0] Processor Speed
0000 48 MHz/1
0001 48 MHz/2
0010 48 MHz/3
0011 48 MHz/4
0100 48 MHz/5
0101 48 MHz/6
0110 48 MHz/7
0111 48 MH z/8
1000 48 MHz/9
1001 48 MHz/10
1010 48 MHz/11
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Table 7-2. CPU Speed Definition (continued)
CPU Speed [3:0] Processor Speed
1011 48 MHz/12
1100 48 MHz/13
1101 48 MHz/14
1110 48 MHz/15
1111 48 MHz /1 6
Reserved
All reserved bits should be written as ‘0’.
7.1.5 Power Control Register [0xC00A] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved Host/Device 2
Read/Write - R/W - R/W R/W - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field HPI
Wake Enable
Read/Write R/W - - R/W - R R/W R/W
Default 0 0 0 0 0 0 0 0
Wake Enable
Reserved Host/Device 1
Reserved GPI
Wake Enable
Wake Enable
OTG
Wake Enable
Reserved
Reserved HSS
Boost 3V
OK
Wake Enable
Sleep
Enable
Wake Enable
SPI
Halt
Enable
Figure 7-6. Power Control Register
Register Description
The Power Control Register controls the power-down and wakeup options. Either the sleep mode or the halt mode options can
be selected. All other writable bits in this register can be used as a wakeup source while in sleep mode.
Host/Device 2 Wake Enable (Bit 14)
The Host/Device 2 Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 2 transition. This wake
up from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wakeup on Host/Device 2 transition.
0: Disable wakeup on Host/Device 2 transition.
Host/Device 1 Wake Enable (Bit 12)
The Host/Device 1 Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 1 transition. This wakeup
from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wakeup on Host/Device 1 transition
0: Disable wakeup on Host/Device 1 transition
OTG Wake Enable (Bit 11)
The OTG Wake Enable bit enables or disables a wakeup condition to occur on either an OTG VBUS_Valid or OTG ID transition
(IRQ20).
1: Enable wakeup on OTG VBUS valid or OTG ID transition
0: Disable wakeup on OTG VBUS valid or OTG ID transition
HSS Wake Enable (Bit 9)
The HSS Wake Enable bit enables or disables a wakeup condition to occur on an HSS Rx serial input transition. The processor
may take several hundreds of microseconds before being operational after wakeup. Therefore, the incoming data byte that causes
the wakeup will be discarded.
1: Enable wakeup on HSS Rx serial input transition
0: Disable wakeup on HSS Rx serial input transition
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SPI Wake Enable (Bit 8)
The SPI Wake Enable bit enables or disables a wakeup condition to occur on a falling SPI_nSS input transition. The processor
may take several hundreds of microseconds before being operational after wakeup. Therefore, the incoming data byte that causes
the wakeup will be discarded.
1: Enable wakeup on falling SPI nSS input transition
0: Disable SPI_nSS interrupt
HPI Wake Enable (Bit 7)
The HPI Wake Enable bit enables or disables a wakeup condition to occur on an HPI interface read.
1: Enable wakeup on HPI interface read
0: Disable wakeup on HPI interface read
GPI Wake Enable (Bit 4)
The GPI Wake Enable bit enables or disables a wakeup condition to occur on a GPIO(25:24) transition.
1: Enable wakeup on GPIO(25:24) transition
0: Disable wakeup on GPIO(25:24) transition
Boost 3V OK (Bit 2)
The Boost 3V OK bit is a read only bit that returns the status of the OTG Boost circuit.
1: Boost circuit not ok and internal voltage rails are below 3.0V
0: Boost circuit ok and internal voltage rails are at or above 3.0V
Sleep Enable (Bit 1)
Setting this bit to ‘1’ will immediately initiate SLEEP mode. While in SLEEP mode, the entire chip is paused achieving the lowest
standby power state. All operations are paused, the internal clock is stopped, the booster circuit and OTG VBUS charge pump
are all powered down, and the USB transceivers are powered down. All counters and timers are paused but will retain their values.
SLEEP mode exits by any activity selected in this register. When SLEEP mode ends, instruction execution will resume within
0.5 ms.
1: Enable Sleep Mode
0: No Function
Halt Enable (Bit 0)
Setting this bit to ‘1’ will immediately initiate HALT mode. While in HALT mode, only the CPU is stopped. The internal clock still
runs and all peripherals still operate, including the USB engines. The power savings using HALT is most cases will be minimal,
but in applications that are very CPU intensive the incremental savings may provide some benefit.
The HALT state is exited when any enabled interrupt is triggered. Upon exiting the HALT state, one or two instructions immediately
following the HALT instruction may get executed before the waking interrupt is serviced (you may want to follow the HALT
instruction with two NOPs).
1: Enable Halt Mode
0: No Function
Reserved
All reserved bits should be written as ‘0’.
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7.1.6 Interrupt Enable Register [0xC00E] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved OTG
Read/Write - - - R/W R/W - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field HSS
Read/Write R/W R/W R/W - R/W R/W R/W R/W
Default 0 0 0 1 0 0 0 0
Interrupt
Enable
In Mailbox
Interrupt
Enable
Out Mailbox
Interrupt
Enable
Interrupt
Enable
Reserved UART
Figure 7-7. Interrupt Enable Register
Register Description
The Interrupt Enable Register allows control of the hardware interrupt vectors.
OTG Interrupt Enable (Bit 12)
The OTG Interrupt Enable bit enables or disables the OTG ID / OTG4.4V Valid hardware interrupt.
1: Enable OTG interrupt
0: Disable OTG interrupt
SPI
Interrupt
Enable
Interrupt
Enable
Reserved Host/Device 2
GPIO
Interrupt
Enable
Interrupt
Enable
Timer 1
Interrupt
Enable
Host/Device 1
Interrupt
Enable
Timer 0
Interrupt
Enable
SPI Interrupt Enable (Bit 11)
The SPI Interrupt Enable bit enables or disables the following three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA Block
Done.
1: Enable SPI interrupt
0: Disable SPI interrupt
Host/Device 2 Interrupt Enable (Bit 9)
The Host/Device 2 Interrupt Enable bit enables or disables all of the following Host/Device 2 hardware interrupts: Host 2 USB
Done, Host 2 USB SOF/EOP, Host 2 WakeUp/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB, Device
2 Endpoint n.
1: Enable Host 2 and Device 2 interrupt
0: Disable Host 2 and Device 2 interrupt
Host/Device 1 Interrupt Enable (Bit 8)
The Host/Device 1 Interrupt Enable bit enables or disables all of the following Host/Device 1 hardware interrupts: Host 1 USB
Done, Host 1 USB SOF/EOP, Host 1 WakeUp/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device
1Endpoint n.
1: Enable Host 2 and Device 2 interrupt
0: Disable Host 2 and Device 2 interrupt
HSS Interrupt Enable (Bit 7)
The HSS Interrupt Enable bit enables or disables the following High-speed Serial Interface hardware interrupts: HSS Block Done,
and HSS RX Full.
1: Enable HSS interrupt
0: Disable HSS interrupt
In Mailbox Interrupt Enable (Bit 6)
The In Mailbox Interrupt Enable bit enables or disables the HPI: Incoming Mailbox hardware interrupt.
1: Enable MBXI interrupt
0: Disable MBXI interrupt
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Out Mailbox Interrupt Enable (Bit 5)
The Out Mailbox Interrupt Enable bit enables or disables the HPI: Outgoing Mailbox hardware interrupt.
1: Enable MBXO interrupt
0: Disable MBXO interrupt
UART Interrupt Enable (Bit 3)
The UART Interrupt Enable bit enables or disables the following UART hardware interrupts: UART TX, and UART RX.
1: Enable UART interrupt
0: Disable UART interrupt
GPIO Interrupt Enable (Bit 2)
The GPIO Interrupt Enable bit enables or disables the General Purpose I/O Pins Interrupt (See the GPIO Control Register). When
GPIO bit is reset, all pending GPIO interrupts are also cleared.
1: Enable GPIO interrupt
0: Disable GPIO interrupt
Timer 1 Interrupt Enable (Bit 1)
The Timer 1 Interrupt Enable bit enables or disables the TImer1 Interrupt Enable. When this bit is reset, all pending Timer 1
interrupts are cleared.
1: Enable TM1interrupt
0: Disable TM1 interrupt
Timer 0 Interrupt Enable (Bit 0)
The Timer 0 Interrupt Enable bit enables or disables the TImer0 Interrupt Enable. When this bit is reset, all pending Timer 0
interrupts are cleared.
1: Enable TM0 interrupt
0: Disable TM0 interrupt
Reserved
All reserved bits should be written as ‘0’.
7.1.7 Breakpoint Register [0xC014] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-8. Breakpoint Register
Register Description
The Breakpoint Register holds the breakpoint address. When the program counter match this address, the INT127 interrupt
occurs. To clear this interrupt, a zero value should be written to this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
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7.1.8 USB Diagnostic Register [0xC03C] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved Port 2A
Read/Write - R/W - R/W - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Pull-down
Read/Write - R/W R/W R/W - R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Diagnostic
Enable
Enable
Register Description
The USB Diagnostic Register provides control of diagnostic modes. It is intended for use by device characterization tests, not for
normal operations. This register is Read/Write by the on-chip CPU but is write only via the HPI port.
Port 2A Diagnostic Enable (Bit 15)
The Port 2A Diagnostic Enable bit enables or disables Port 2A for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD
0: Do not apply test conditions
Reserved Port 1A
LS Pull-up
Enable
Diagnostic
Enable
FS Pull-up
Enable
Reserved Force Select
Figure 7-9. USB Diagnostic Register
Reserved...
Port 1A Diagnostic Enable (Bit 15)
The Port 1A Diagnostic Enable bit enables or disables Port 1A for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD
0: Do not apply test conditions
Pull-down Enable (Bit 6)
The Pull-down Enable bit enables or disables full-speed pull-down resistors (pull-down on both D+ and D–) for testing.
1: Enable pull-down resistors on both D+ and D–
0: Disable pull-down resistors on both D+ and D–
LS Pull-up Enable (Bit 5)
The LS Pull-up Enable bit enables or disables a low-speed pull-up resistor (pull-up on D–) for testing.
1: Enable low-speed pull-up resistor on D–
0: Pull-up resistor is not connected on D–
FS Pull-up Enable (Bit 4)
The FS Pull-up Enable bit enables or disables a full-speed pull-up resistor (pull-up on D+) for testing.
1: Enable full-speed pull-up resistor on D+
0: Pull-up resistor is not connected on D+
Force Select (Bits [2:0])
The Force Select field bit selects several different test condition states on the data lines (D+/D–). See Tab le 7 -3 for details.
Table 7-3. Force Select Definition
Force Select [2:0] Data Line State
1xx Assert SE0
01x Toggle JK
001 Assert J
000 Assert K
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Reserved
All reserved bits should be written as ‘0’.
7.2 Timer Registers
There are three registers dedicated to timer operations. Each of these registers are discussed in this section and are summarized
in Figure 7-10.
Register Name Address R/W
Watchdog Timer Register 0xC00C R/W
Timer 0 Register 0xC010 R/W
Timer 1 Register 0xC012 R/W
Figure 7-10. Timer Registers
7.2.1 Watchdog Timer Register [0xC00C] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Timeout
Read/Write R/W R/W R/W R/W R/W R/W R/W W
Default 0 0 0 0 0 0 0 0
Flag
Period
Select
Lock
Enable
WDT
Enable
Reset
Strobe
Figure 7-11. Watchdog Timer Register
Register Description
The Watchdog Timer Register provide status and control over the Watchdog timer. The Watchdog timer can also interrupt the
processor.
Timeout Flag (Bit 5)
The Timeout Flag bit indicates if the Watchdog timer has expired. The processor can read this bit after exiting a reset to determine
if a Watchdog time-out occurred. This bit will be cleared on the next external hardware reset.
1: Watchdog timer expired
0: Watchdog timer did not expire
Period Select (Bits [4:3])
The Period Select field is defined in Table 7-4. If this time expires before the Reset Strobe bit is set, the internal processor will
get reset.
Table 7-4. Period Select Definition
Period Select[4:3] WDT Period Value
00 1.4 ms
01 5.5 ms
10 22.0 ms
11 66 .0 m s
Lock Enable (Bit 2)
The Lock Enable bit will not allow any writes to this register until a reset. In doing so the Watchdog timer can be set up and enabled
permanently so that it can only be cleared on reset (the WDT Enable bit is ignored).
1: Watchdog timer permanently set
0: Watchdog timer not permanently set
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WDT Enable (Bit 1)
The WDT Enable bit enables or disables the Watchdog timer.
1: Enable Watchdog timer operation
0: Disable Watchdog timer operation
Reset Strobe (Bit 0)
The Reset Strobe is a write-only bit that resets the Watchdog timer count. It must be set to ‘1’ before the count expires to avoid
a Watchdog trigger
1: Reset Count
Reserved
All reserved bits should be written as ‘0’.
7.2.2 Timer n Register [R/W]
• Timer 0 Register 0xC010
• Timer 1 Register 0xC012
Bit # 15 14 13 12 11 10 9 8
Field Count...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1
Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1
Figure 7-12. Timer n Register
Register Description
The Timer n Register sets the Timer n count. Both Timer 0 and Timer 1 decrement by one every 1 µs clock tick. Each can provide
an interrupt to the CPU when the timer reaches zero.
Count (Bits [15:0])
The Count field sets the Timer count.
7.3 General USB Registers
There is one set of register dedicated to general USB control. This set consists of two identical registers, one for Host/Device
Port 1 and one for Host/Device Port 2. This register set has functions for both USB host and USB peripheral options and is covered
in this section and summarized in Figure 7-13. USB Host-only registers are covered in section 7.4 and USB Device-only registers
are covered in section 7.5.
Register Name Address (SIE1/SIE2) R/W
USB n Control Register 0xC08A / 0xC0AA R/W
Figure 7-13. USB Registers
7.3.1 USB n Control Register [R/W]
• USB 1 Control Register 0xC08A
• USB 2 Control Register 0xC0AA
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Bit # 15 14 13 12 11 10 9 8
Field Reserved Port A
Read/Write - - R R - R/W R/W -
Default X X X X 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field Port A
Read/Write R/W - - R/W R/W R/W - R/W
Default 0 0 0 0 0 0 0 0
Resistors Enable
D+ Status
Reserved Port A
Figure 7-14. USB n Control Register
Register Description
The USB n Control Register is used in both host and device mode. It monitors and controls the SIE and the data lines of the USB
ports. This register can be accessed by the HPI interface.
Port A D+ Status (Bit 13)
The Port A D+ Status bit is a read-only bit that indicates the value of DATA+ on Port A.
1: D+ is high
0: D+ is low
Port A D– Status (Bit 12)
The Port A D– Status bit is a read-only bit that indicates the value of DATA– on Port A.
1: D– is high
0: D– is low
Port A
D– Status
Force D± State
Reserved LOA Mode
Suspend
Enable
Select
Reserved Port A
Reserved
SOF/EOP Enable
LOA (Bit 10)
The LOA bit selects the speed of Port A.
1: Port A is set to Low speed mode
0: Port A is set to Full speed mode
Mode Select (Bit 9)
The Mode Select bit sets the SIE for host or device operation. When set for device operation only one USB port is supported.
The active port is selected by the Port Select bit in the Host n Count Register.
1: Host mode
0: Device mode
Port A Resistors Enable (Bit 7)
The Port A Resistors Enable bit enables or disables the pull-up/pull-down resistors on Port A. When enabled, the Mode Select
bit and LOA bit of this Register will set the pull-up/pull-down resistors appropriately. When the Mode Select is set for Host mode,
the pull-down resistors on the data lines (D+ and D–) are enabled. When the Mode Select is set for Device mode, a single pullup resistor on either D+ or D–, determined by the LOA bit, will be enabled. Please see Tab le 7-5 for details.
1: Enable pull-up/pull-down resistors
0: Disable pull-up/pull-down resistors
Table 7-5. USB Data Line Pull-Up and Pull-Down Resistors
L0A Mode Select Port n Resistors Enable Function
X X 0 Pull-up/Pull-down on D+ and D– Disabled
X 1 1 Pull-down on D+ and D– Enabled
1 0 1 Pull-up on USB D– Enabled
0 0 1 Pull-up on USB D+ Enabled
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Port A Force D± State (Bits [4:3])
The Port A Force D± State field controls the forcing state of the D+ D– data lines for Port A. This field will Force the state of the
Port A data lines independent of the Port Select bit setting. See Table 7-6 for details.
Table 7-6. Port A Force D± State
Port A Force D± State Function
0 0 Normal Operation
0 1 Force USB Reset, SE0 State
1 0 Force J-State.
1 1 Force K-State.
Suspend Enable (Bit 2)
The Suspend Enable bit enables or disables the suspend feature on both ports. When suspend is enabled the USB transceivers
are powered down and can not transmit or received USB packets but can still monitor for a wakeup condition.
1: Enable suspend
0: Disable suspend
Port A SOF/EOP Enable (Bit 0)
The Port A SOF/EOP Enable bit is only applicable in host mode. In device mode this bit should be written as ‘0’. In host mode
this bit enables or disables SOFs or EOPs for Port A. Either SOFs or EOPs will be generated depending on the LOA bit in the
USB n Control Register when Port A is active.
1: Enable SOFs or EOPs
0: Disable SOFs or EOPs
Reserved
All reserved bits should be written as ‘0’.
7.4 USB Host Only Registers
There are twelve sets of dedicated registers to USB host only operation. Each set consists of two identical registers (unless
otherwise noted), one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized
in Figure 7-15.
Register Name Address (Host 1 / Host 2) R/W
Host n Control Register 0xC080 / 0xC0A0 R/W
Host n Address Register 0xC082 / 0xC0A2 R/W
Host n Count Register 0xC084 / 0xC0A4 R/W
Host n Endpoint Status Register 0xC086 / 0xC0A6 R
Host n PID Register 0xC086 / 0xC0A6 W
Host n Count Result Register 0xC088 / 0xC0A8 R
Host n Device Address Register 0xC088 / 0xC0A8 W
Host n Interrupt Enable Register 0xC08C / 0xC0AC R/W
Host n Status Register 0xC090 / 0xC0B0 R/W
Host n SOF/EOP Count Register 0xC092 / 0xC0B2 R/W
Host n SOF/EOP Counter Register 0xC094 / 0xC0B4 R
Host n Frame Register 0xC096 / 0xC0B6 R
Figure 7-15. USB Host Only Register
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7.4.1 Host n Control Register [R/W]
• Host 1 Control Register 0xC080
• Host 2 Control Register 0xC0A0
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field Preamble
Read/Write R/W R/W R/W R/W - - - R/W
Default 0 0 0 0 0 0 0 0
Enable
Register Description
The Host n Control Register allows high-level USB transaction control.
Preamble Enable (Bit 7)
The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. This bit should
only be set when communicating with a low-speed device.
1: Enable Preamble packet
0: Disable Preamble packet
Sequence
Select
Sync
Enable
ISO
Enable
Figure 7-16. Host n Control Register
Reserved Arm
Enable
Sequence Select (Bit 6)
The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receiving data packets; sequence
checking must be handled in firmware.
1: Send DATA1
0: Send DATA0
Sync Enable (Bit 5)
The Sync Enable bit will synchronize the transfer with the SOF packet in full-speed mode and the EOP packet in low-speed mode.
1: The next enabled packet will be transferred after the SOF or EOP packet is transmitted
0: The next enabled packet will be transferred as soon as the SIE is free
ISO Enable (Bit 4)
The ISO Enable bit enables or disables an Isochronous transaction.
1: Enable Isochronous transaction
0: Disable Isochronous transaction
Arm Enable (Bit 0)
The Arm Enable bit arms an endpoint and starts a transaction. This bit is automatically cleared to ‘0’ when a transaction is
complete.
1: Arm endpoint and begin transaction
0: Endpoint disarmed
Reserved
All reserved bits should be written as ‘0’.
7.4.2 Host n Address Register [R/W]
• Host 1 Address Register 0xC082
• Host 2 Address Register 0xC0A2
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Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-17. Host n Address Register
Register Description
The Host n Address Register is used as the base pointer into memory space for the current host transactions.
Address (Bits [15:0])
The Address field sets the address pointer into internal RAM or ROM.
7.4.3 Host n Count Register [R/W]
• Host 1 Count Register 0xC084
• Host 2 Count Register 0xC0A4
Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - - - - - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-18. Host n Count Register
Register Description
The Host n Count Register is used to hold the number of bytes (packet length) for the current transaction. The maximum packet
length is 1023 bytes in ISO mode. The Host Count value is used to determine how many bytes to transmit, or the maximum
number of bytes to receive. If the number of received bytes is greater then the Host Count value then an overflow condition will
be flagged by the Overflow bit in the Host n Endpoint Status Register.
Count (Bits [9:0])
The Count field sets the value for the current transaction data packet length. This value is retained when switching between host
and device mode, and back again.
Reserved
All reserved bits should be written as ‘0’.
7.4.4 Host n Endpoint Status Register [R]
• Host 1 Endpoint Status Register 0xC086
• Host 2 Endpoint Status Register 0xC0A6
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Bit # 15 14 13 12 11 10 9 8
Field Reserved Overflow
Read/Write - - - - R R - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field Stall
Read/Write R R R - R R R R
Default 0 0 0 0 0 0 0 0
Flag
NAK
Flag
Length
Exception
Flag
Reserved Sequence
Flag
Status
Figure 7-19. Host n Endpoint Status Register
Register Description
The Host n Endpoint Status Register is a read only register that provides status for the last USB transaction.
Overflow Flag (Bit 11)
The Overflow Flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the
Host n Count Register. The Overflow Flag should be checked in response to a Length Exception signified by the Length Exception
Flag set to ‘1’.
1: Overflow condition occurred
0: Overflow condition did not occur
Underflow
Flag
Timeout
Flag
Error
Flag
Reserved
ACK
Flag
Underflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specified
in the Host n Count Register. The Underflow Flag should be checked in response to a Length Exception signified by the Length
Exception Flag set to ‘1’.
1: Underflow condition occurred
0: Underflow condition did not occur
Stall Flag (Bit 7)
The Stall Flag bit indicates that the peripheral device replied with a Stall in the last transaction.
1: Device returned Stall
0: Device did not return Stall
NAK Flag (Bit 6)
The NAK Flag bit indicates that the peripheral device replied with a NAK in the last transaction.
1: Device returned NAK
0: Device did not return NAK
Length Exception Flag (Bit 5)
The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximum
Host Count specified in the Host n Count Register. A Length Exception can either mean an overflow or underflow and the Overflow
and Underflow flags (bits 11 and 10, respectively) should be checked to determine which event occurred.
1: An overflow or underflow condition occurred
0: An overflow or underflow condition did not occur
Sequence Status (Bit 3)
The Sequence Status bit indicates the state of the last received data toggle from the device. Firmware is responsible for monitoring
and handling the sequence status. The Sequence bit is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to ‘0’ when
an error is detected in the transaction and the Error bit will be set.
1: DATA1
0: DATA0
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Timeout Flag (Bit 2)
The Timeout Flag bit indicates if a timeout condition occurred for the last transaction. A timeout condition can occur when a device
either takes too long to respond to a USB host request or takes too long to respond with a handshake.
1: Timeout occurred
0: Timeout did not occur
Error Flag (Bit 1)
The Error Flag bit indicates a transaction failed for any reason other than the following: Timeout, receiving a NAK, or receiving a
STALL. Overflow and Underflow are not considered errors and do not affect this bit. CRC5 and CRC16 errors will result in an
Error flag along with receiving incorrect packet types.
1: Error detected
0: No error detected
ACK Flag (Bit 0)
The ACK Flag bit indicates two different conditions depending on the transfer type. For non-Isochronous transfers, this bit
represents a transaction ending by receiving or sending an ACK packet. For Isochronous transfers, this bit represents a
successful transaction that will not be represented by an ACK packet.
1: For non-Isochronous transfers, the transaction was ACKed. For Isochronous transfers, the transaction was completed
successfully.
0: For non-Isochronous transfers, the transaction was not ACKed. For Isochronous transfers, the transaction did not completed
successfully.
7.4.5 Host n PID Register [W]
• Host 1 PID Register 0xC086
• Host 2 PID Register 0xC0A6
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field PID Select Endpoint Select
Read/Write W W W W W W W W
Default 0 0 0 0 0 0 0 0
Figure 7-20. Host n PID Register
Register Description
The Host n PID Register is a write-only register that provides the PID and Endpoint information to the USB SIE to be used in the
next transaction.
PID Select (Bits [7:4])
The PID Select field defined as in Ta bl e 7-7 . ACK and NAK tokens are automatically sent based on settings in the Host n Control
Register and do not need to be written in this register.
Table 7-7. PID Select Definition
PID TYPE PID Select [7:4]
set-up 1101 (D Hex)
IN 1001 (9 Hex)
OUT 0001 (1 Hex)
SOF 0101 (5 Hex)
PREAMBLE 1100 (C Hex)
NAK 1010 (A Hex)
STALL 1110 (E Hex)
DATA0 0011 (3 Hex)
DATA1 1011 (B Hex)
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Endpoint Select (Bits [3:0])
The Endpoint field which allows addressing up to 16 different endpoints.
Reserved
All reserved bits should be written as ‘0’.
7.4.6 Host n Count Result Register [R]
• Host 1 Count Result Register 0xC088
• Host 2 Count Result Register 0xC0A8
Bit # 15 14 13 12 11 10 9 8
Field Result...
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Result
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0
Figure 7-21. Host n Count Result Register
Register Description
The Host n Count Result Register is a read-only register that contains the size difference in bytes between the Host Count Value
specified in the Host n Count Register and the last packet received. If an overflow or underflow condition occurs, i.e., the received
packet length differs from the value specified in the Host n Count Register, the Length Exception Flag bit in the Host n Endpoint
Status Register will be set. The value in this register is only valid when the Length Exception Flag bit is set and the Error Flag bit
is not set; both bits are in the Host n Endpoint Status Register.
Result (Bits [15:0])
The Result field will contain the differences in bytes between the received packet and the value specified in the Host n Count
Register. If an overflow condition occurs, Result [15:10] will be set to ‘111111’, a 2’s complement value indicating the additional
byte count of the received packet. If an underflow condition occurs, Result [15:0] will indicate the excess bytes count (number of
bytes not used).
Reserved
All reserved bits should be written as ‘0’.
7.4.7 Host n Device Address Register [W]
• Host 1 Device Address Register 0xC088
• Host 2 Device Address Register 0xC0A8
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Address
Read/Write - W W W W W W W
Default 0 0 0 0 0 0 0 0
Figure 7-22. Host n Device Address Register
Register Description
The Host n Device Address Register is a write-only register that contains the USB Device Address that the host wishes to
communicate with.
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Address (Bits [6:0])
The Address field contains the value of the USB address for the next device that the host is going to communicate with. This
value needs to be written by firmware.
Reserved
All reserved bits should be written as ‘0’.
7.4.8 Host n Interrupt Enable Register [R/W]
• Host 1 Interrupt Enable Register 0xC08C
• Host 2 Interrupt Enable Register 0xC0AC
Bit # 15 14 13 12 11 10 9 8
Field VBUS
Read/Write R/W R/W - - - - R/W -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field Reserved Port A
Read/Write - R/W - R/W - - - R/W
Default 0 0 0 0 0 0 0 0
Interrupt Enable
ID Interrupt
Enable
Wake Interrupt Enable
Reserved SOF/EOP
Reserved Port A Connect
Change
Interrupt Enable
Interrupt Enable
Reserved Done
Reserved
Interrupt Enable
Figure 7-23. Host n Interrupt Enable Register
Register Description
The Host n Interrupt Enable Register will allow control over host-related interrupts.
In this register a bit set to ‘1’ enables the corresponding interrupt while ‘0’ disables the interrupt.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit will enable or disable the OTG VBUS interrupt. When enabled this interrupt will trigger on both
rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Host 1and is a reserved
bit in Host 2.
1: Enable VBUS interrupt
0: Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit will enable or disable the OTG ID interrupt. When enabled this interrupt will trigger on both rising and
falling edge of OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.
1: Enable ID interrupt
0: Disable ID interrupt
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit will enable or disable the SOF/EOP timer interrupt.
1: Enable SOF/EOP timer interrupt
0: Disable SOF/EOP timer interrupt
Port A Wake Interrupt Enable (Bit 6)
The Port A Wake Interrupt Enable bit will enable or disable the remote wakeup interrupt for Port A.
1: Enable remote wakeup interrupt for Port A
0: Disable remote wakeup interrupt for Port A
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Port A Connect Change Interrupt Enable (Bit 4)
The Port A Connect Change Interrupt Enable bit will enable or disable the Connect Change interrupt on Port A. This interrupt will
trigger when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).
1: Enable Connect Change interrupt
0: Disable Connect Change interrupt
Done Interrupt Enable (Bit 0)
The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt. The USB Transfer Done will trigger when
either the host responding with and ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout. This
interrupt is used for both Port A and Port B.
1: Enable USB Transfer Done interrupt
0: Disable USB Transfer Done interrupt
Reserved
All reserved bits should be written as ‘0’.
7.4.9 Host n Status Register [R/W]
• Host 1 Status Register 0xC090
• Host 2 Status Register 0xC0B0
Bit # 15 14 13 12 11 10 9 8
Field VBUS
Interrupt Flag
Read/Write R/W R/W - - - - R/W -
Default X X X X X X X X
ID Interrupt
Flag
Reserved SOF/EOP
Interrupt Flag
Reserved
Bit # 7 6 5 4 3 2 1 0
Field Reserved Port A
Read/Write - R/W - R/W - R/W - R/W
Default X X X X X X X X
Wake Interrupt
Flag
Reserved Port A Connect
Change
Interrupt Flag
Reserved Port A
SE0
Status
Reserved Done
Interrupt Flag
Figure 7-24. Host n Status Register
Register Description
The Host n Status Register will provide status information for host operation. Pending interrupts can be cleared by writing a ‘1’ to
the corresponding bit. This register can be accessed by the HPI interface.
VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt will
trigger on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Host 1 and is a reserved bit in Host 2.
1: Interrupt triggered
0: Interrupt did not trigger
ID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt will trigger on
both the rising and falling edge of the OTG ID pin. This bit is only available for Host 1 and is a reserved bit in Host 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates the status of the SOF/EOP Timer interrupt. This bit will trigger ‘1’ when the SOF/EOP
timer expires.
1: Interrupt triggered
0: Interrupt did not trigger
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Port A Wake Interrupt Flag (Bit 6)
The Port A Wake Interrupt Flag bit indicates remote wakeup on PortA
1: Interrupt triggered
0: Interrupt did not trigger
Port A Connect Change Interrupt Flag (Bit 4)
The Port A Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port A. This bit will trigger
‘1’ on either a rising edge or falling edge of a USB Reset condition (device inserted or removed). Together with the Port A SE0
Status bit, it can be determined whether a device was inserted or removed.
1: Interrupt triggered
0: Interrupt did not trigger
Port A SE0 Status (Bit 2)
The Port A SE0 Status bit indicates if Port A is in an SE0 state or not. Together with the Port A Connect change Interrupt Flag
bit, it can be determined whether a device was inserted (non-SE0 condition) or removed (SE0 condition).
1: SE0 condition
0: Non-SE0 condition
Done Interrupt Flag (Bit 0)
The Done Interrupt Flag bit indicates the status of the USB Transfer Done interrupt. The USB Transfer Done will trigger when
either the host responding with and ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout.This
interrupt is used for both Port A and Port B.
1: Interrupt triggered
0: Interrupt did not trigger
7.4.10 Host n SOF/EOP Count Register [R/W]
• Host 1 SOF/EOP Count Register 0xC092
• Host 2 SOF/EOP Count Register 0xC0B2
Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - R/W R/W R/W R/W R/W R/W
Default 0 0 1 0 1 1 1 0
Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 0 0 0 0 0
Figure 7-25. Host n SOF/EOP Count Register
Register Description
The Host n SOF/EOP Count Register contains the SOF/EOP Count Value that is loaded into the SOF/EOP counter. This value
is loaded each time the SOF/EOP counter counts down to zero. The default value set in this register at power-up is 0x2EE0,
which will generate a 1-ms time frame. The SOF/EOP counter is a down counter decremented at a 12-MHz rate. When this
register is read, the value returned is the programmed SOF/EOP count value.
Count (Bits [13:0])
The Count field sets the SOF/EOP counter duration.
Reserved
All reserved bits should be written as ‘0’.
7.4.11 Host n SOF/EOP Counter Register [R]
• Host 1 SOF/EOP Counter Register 0xC094
• Host 2 SOF/EOP Counter Register 0xC0B4
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Bit # 15 14 13 12 11 10 9 8
Field Reserved Counter...
Read/Write - - R R R R R R
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field ...Counter
Read/Write R R R R R R R R
Default X X X X X X X X
Figure 7-26. Host n SOF/EOP Counter Register
Register Description
The Host n SOF/EOP Counter Register contains the current value of the SOF/EOP down counter. This value can be used to
determine the time remaining in the current frame.
Counter (Bits [13:0])
The Counter field contains the current value of the SOF/EOP down counter.
7.4.12 Host n Frame Register [R]
• Host 1 Frame Register 0xC096
• Host 2 Frame Register 0xC0B6
Bit # 15 14 13 12 11 10 9 8
Field Reserved Frame...
Read/Write - - - - - R R R
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Frame
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0
Figure 7-27. Host n Frame Register
Register Description
The Host n Frame Register maintains the next frame number to be transmitted (current frame number + 1). This value is updated
after each SOF transmission. This register resets to 0x0000 after each CPU write to the Host n SOF/EOP Count Register (Host 1:
0xC092, Host 2: 0xC0B2).
Frame (Bits [10:0])
The Frame field contains the next frame number to be transmitted.
Reserved
All reserved bits should be written as ‘0’.
7.5 USB Device Only Registers
There are ten sets of USB Device only registers. All sets consist of at least two registers, one for Device Port 1 and one for Device
Port 2. In addition, each Device port has eight possible endpoints. This gives each endpoint register set eight registers for each
Device Port for a total of 16 registers per set. The USB Device only registers are covered in this section and summarized in
Figure 7-28.
Register Name Address (Device 1/Device 2) R/W
Device n Endpoint n Control Register 0x02n0 R/W
Device n Endpoint n Address Register 0x02n2 R/W
Device n Endpoint n Count Register 0x02n4 R/W
Figure 7-28. USB Device Only Registers
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Register Name Address (Device 1/Device 2) R/W
Device n Endpoint n Status Register 0x02n6 R/W
Device n Endpoint n Count Result Register 0x02n8 R/W
Device n Interrupt Enable Register 0xC08C / 0xC0AC R/W
Device n Address Register 0xC08E / 0xC0AE R/W
Device n Status Register 0xC090 / 0xCB0 R/W
Device n Frame Number Register 0xC092 / 0xC0B2 R
Device n SOF/EOP Count Register 0xC094 / 0xC0B4 W
Figure 7-28. USB Device Only Registers (continued)
7.5.1 Device n Endpoint n Control Register [R/W]
• Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280]
• Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290]
• Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0]
• Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0]
• Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0]
• Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0]
• Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0]
• Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0]
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field IN/OUT
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
Ignore
Enable
Sequence
Select
Stall
Enable
ISO
Enable
NAK
Interrupt
Enable
Direction
Select
Enable Arm
Enable
Figure 7-29. Device n Endpoint n Control Register
Register Description
The Device n Endpoint n Control Register provides control over a single EP in device mode. There are a total of eight endpoints
for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Control Register.
IN/OUT Ignore Enable (Bit 6)
The IN/OUT Ignore Enable bit will force endpoint 0 (EP0) to ignore all IN and OUT requests. This bit should be set so that EP0
only excepts Set-up packets at the start of each transfer. This bit must be cleared to except IN/OUT transactions. This bit only
applies to EP0.
1: Ignore IN/OUT requests
0: Do not ignore IN/OUT requests
Sequence Select (Bit 6)
The Sequence Select bit will determine whether a DATA0 or a DATA1 will be sent for the next data toggle. This bit has no effect
on receiving data packets, sequence checking must be handled in firmware.
1: Send a DATA1
0: Send a DATA0
Stall Enable (Bit 5)
The Stall Enable bit will send a Stall in response to the next request (unless it is a set-up request, which are always ACKed). This
is a sticky bit and will continue to respond with Stalls until cleared by firmware.
1: Send Stall
0: Do not send Stall
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ISO Enable (Bit 4)
The ISO Enable bit enables and disables an Isochronous transaction. This bit is only valid for EPs 1–7 and has no function for EP0.
1: Enable Isochronous transaction
0: Disable Isochronous transaction
NAK Interrupt Enable (Bit 3)
The NAK Interrupt Enable bit enables and disables the generation of an Endpoint n interrupt when the device responds to the
host with a NAK. The Endpoint n Interrupt Enable bit in the Device n Interrupt Enable Register must also be set. When a NAK is
sent to the host, the corresponding EP Interrupt Flag in the Device n Status Register will be set. In addition, the NAK Flag in the
Device n Endpoint n Status Register will be set.
1: Enable NAK interrupt
0: Disable NAK interrupt
Direction Select (Bit 2)
The Direction Select bit needs to be set according to the expected direction of the next data stage in the next transaction. If the
data stage direction is different from what is set in this bit, it will get NAKed and either the IN Exception Flag or the OUT Exception
Flag will be set in the Device n Endpoint n Status Register. If a set-up packet is received and the Direction Select bit is set
incorrectly, the set-up will get ACKed and the Set-up Status Flag will be set (please refer to the set-up bit of the Device n Endpoint
n Status Register for details).
1: OUT transfer (host to device)
0: IN transfer (device to host)
Enable (Bit 1)
The Enable bit must be set to allow transfers to the endpoint. If Enable is set to ‘0’ then all USB traffic to this endpoint will be
ignored. If Enable is set ‘1’ and Arm Enable (bit 0) is set ‘0’ then NAKs will automatically be returned from this endpoint (except
set-up packets which are always ACKed as long as the Enable bit is set.)
1: Enable transfers to an endpoint
0: Do not allow transfers to an endpoint
Arm Enable (Bit 0)
The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to ‘0’ when a transaction is complete.
1: Arm endpoint
0: Endpoint disarmed
Reserved
All reserved bits should be written as ‘0’.
7.5.2 Device n Endpoint n Address Register [R/W]
• Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282]
• Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292]
• Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2]
• Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2]
• Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2]
• Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2]
• Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2]
• Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2]
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
Figure 7-30. Device n Endpoint n Address Register
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Register Description
The Device n Endpoint n Address Register is used as the base pointer into memory space for the current Endpoint transaction.
There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint
n Address Register.
Address (Bits [15:0])
The Address field sets the base address for the current transaction on a signal endpoint.
7.5.3 Device n Endpoint n Count Register [R/W]
• Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284]
• Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294]
• Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4]
• Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4]
• Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4]
• Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4]
• Device n Endpoint 6 Count Register [Device 1: 0x0264 Device 2: 0x02E4]
• Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4]
Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - - - - - R/W R/W
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
Figure 7-31. Device n Endpoint n Count Register
Register Description
The Device n Endpoint n Count Register designates the maximum packet size that can be received from the host for OUT
transfers for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN token
for a single endpoint. The maximum packet length is 1023 bytes in ISO mode. There are a total of eight endpoints for each of the
two ports. All endpoints have the same definition for their Device n Endpoint n Count Register.
Count (Bits [9:0])
The Count field sets the current transaction packet length for a single endpoint.
Reserved
All reserved bits should be written as ‘0’.
7.5.4 Device n Endpoint n Status Register [R/W]
• Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286]
• Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296]
• Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6]
• Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6]
• Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6]
• Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6]
• Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6]
• Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6]
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Bit # 15 14 13 12 11 10 9 8
Field Reserved Overflow
Read/Write - - - - R/W R/W R/W R/W
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field Stall
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
Flag
NAK
Flag
Length
Exception Flag
Set-up
Flag
Flag
Sequence
Figure 7-32. Device n Endpoint n Status Register
Register Description
The Device n Endpoint n Status Register provides packet status information for the last transaction received or transmitted. This
register is updated in hardware and does not need to be cleared by firmware. There are a total of eight endpoints for each of the
two ports. All endpoints have the same definition for their Device n Endpoint n Status Register.
The Device n Endpoint n Status Register is a memory-based register that should be initialized to 0x0000 before USB Device
operations are initiated. After initialization, this register should not be written to again.
Overflow Flag (Bit 11)
The Overflow Flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the
Device n Endpoint n Count Register. The Overflow Flag should be checked in response to a Length Exception signified by the
Length Exception Flag set to ‘1’.
1: Overflow condition occurred
0: Overflow condition did not occur
Flag
Underflow
Flag
Time-out
OUT
Exception FlagINException Flag
Flag
Error
Flag
ACK
Flag
Underflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specified
in the Device n Endpoint n Count Register. The Underflow Flag should be checked in response to a Length Exception signified
by the Length Exception Flag set to ‘1’.
1: Underflow condition occurred
0: Underflow condition did not occur
OUT Exception Flag (Bit 9)
The OUT Exception Flag bit will indicates when the device received an OUT packet when armed for an IN.
1: Received OUT when armed for IN
0: Received IN when armed for IN
IN Exception Flag (Bit 8)
The IN Exception Flag bit will indicates when the device received an IN packet when armed for an OUT.
1: Received IN when armed for OUT
0: Received OUT when armed for OUT
Stall Flag (Bit 7)
The Stall Flag bit indicates that a Stall packet was sent to the host.
1: Stall packet was sent to the host
0: Stall packet was not sent
NAK Flag (Bit 6)
The NAK Flag bit indicates that a NAK packet was sent to the host.
1: NAK packet was sent to the host
0: NAK packet was not sent
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Length Exception Flag (Bit 5)
The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximum
Endpoint Count specified in the Device n Endpoint n Count Register. A Length Exception can either mean an overflow or
underflow and the Overflow and Underflow flags (bits 11 and 10, respectively) should be checked to determine which event
occurred.
1: An overflow or underflow condition occurred
0: An overflow or underflow condition did not occur
Set-up Flag (Bit 4)
The Set-up Flag bit indicates that a set-up packet was received. In device mode set-up packets get stored at memory location
0x0300 for Device 1 and 0x0308 for Device 2. Set-up packets are always accepted regardless of the Direction Select and Arm
Enable bit settings as long as the Device n EP n Control Register Enable bit is set.
1: Set-up packet was received
0: Set-up packet was not received
Sequence Flag (Bit 3)
The Sequence Flag bit indicates whether the last data toggle received was a DATA1 or a DATA0. This bit has no effect on receiving
data packets, sequence checking must be handled in firmware.
1: DATA1 was received
0: DATA0 was received
Time-out Flag (Bit 2)
The Time-out Flag bit indicates whether a time-out condition occurred on the last transaction. On the device side, a time-out can
occur if the device sends a data packet in response to an IN request but then does not receive a handshake packet in a
predetermined time. It can also occur if the device does not receive the data stage of an OUT transfer in time.
1: Time-out occurred
0: Time-out condition did not occur
Error Flag (Bit 2)
The Error Flag bit will be set if a CRC5 and CRC16 error occurs, or if an incorrect packet type is received. Overflow and Underflow
are not considered errors and do not affect this bit.
1: Error occurred
0: Error did not occur
ACK Flag (Bit 0)
The ACK Flag bit indicates whether the last transaction was ACKed.
1: ACK occurred
0: ACK did not occur
7.5.5 Device n Endpoint n Count Result Register [R/W]
• Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288]
• Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298]
• Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8]
• Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8]
• Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8]
• Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8]
• Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8]
• Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8]
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Bit # 15 14 13 12 11 10 9 8
Field Result...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field ...Result
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
Figure 7-33. Device n Endpoint n Count Result Register
Register Description
The Device n Endpoint n Count Result Register contains the size difference in bytes between the Endpoint Count specified in
the Device n Endpoint n Count Register and the last packet received. If an overflow or underflow condition occurs. i.e. the received
packet length differs from the value specified in the Device n Endpoint n Count Register, the Length Exception Flag bit in the
Device n Endpoint n Status Register will be set. The value in this register is only value when the Length Exception Flag bit is set
and the Error Flag bit is not set, both bits are in the Device n Endpoint n Status Register.
The Device n Endpoint n Count Result Register is a memory based register that should be initialized to 0x0000 before USB
Device operations are initiated. After initialization, this register should not be written to again.
Result (Bits [15:0])
The Result field will contain the differences in bytes between the received packet and the value specified in the Device n Endpoint
n C oun t R egist er. I f an ov erflo w cond it ion oc curs, Resul t [15: 10] wi ll be s et to ‘ 111111’, a 2 ’s compl ement value in dicat ing th e
additional byte count of the received packet. If an underflow condition occurs, Result [15:0] will indicate the excess bytes count
(number of bytes not used).
Reserved
All reserved bits should be written as ‘0’.
7.5.6 Device n Interrupt Enable Register [R/W]
• Device 1 Interrupt Enable Register 0xC08C
• Device 2 Interrupt Enable Register 0xC0AC
Bit # 15 14 13 12 11 10 9 8
Field VBUS
Read/Write R/W R/W - - R/W - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field EP7 Interrupt
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Interrupt
Enable
Enable
ID Interrupt
Enable
EP6 Interrupt
Enable
Reserved SOF/EOP
EP5 Interrupt
Enable
EP4 Interrupt
Enable
Time-out
Interrupt Enable
EP3 Interrupt
Enable
Reserved SOF/EOP
EP2 Interrupt
Enable
Interrupt
EP1 Interrupt
Enable
Enable
Reset
Interrupt
Enable
EP0 Interrupt
Enable
Figure 7-34. Device n Interrupt Enable Register
Register Description
The Device n Interrupt Enable Register provides control over device related interrupts including eight different endpoint interrupts.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit will enable or disable the OTG VBUS interrupt. When enabled this interrupt will trigger on both
rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Device 1 and is a
reserved bit in Device 2.
1: Enable VBUS interrupt
0: Disable VBUS interrupt
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ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit will enable or disable the OTG ID interrupt. When enabled this interrupt will trigger on both rising and
falling edge of OTG ID pin (only supported in Port 1A). This bit is only available for Device 1and is a reserved bit in Device 2.
1: Enable ID interrupt
0: Disable ID interrupt
SOF/EOP Time-out Interrupt Enable (Bit 11)
The SOF/EOP Time-out Interrupt Enable bit will enable or disable the SOF/EOP Time-out Interrupt. When enabled this interrupt
will trigger when the USB host fails to send a SOF or EOP packet within the time period specified in the Device n SOF/EOP Count
Register. In addition, the Device n Frame Register counts the number of times the SOF/EOP Timeout Interrupt triggers between
receiving SOF/EOPs.
1: SOF/EOP time-out occurred
0: SOF/EOP time-out did not occur
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit will enable or disable the SOF/EOP received interrupt.
1: Enable SOF/EOP Received interrupt
0: Disable SOF/EOP Received interrupt
Reset Interrupt Enable (Bit 8)
The Reset Interrupt Enable bit will enable or disable the USB Reset Detected interrupt
1: Enable USB Reset Detected interrupt
0: Disable USB Reset Detected interrupt
EP7 Interrupt Enable (Bit 7)
The EP7 Interrupt Enable bit will enable or disable endpoint seven (EP7) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP7 Transaction Done interrupt
0: Disable EP7 Transaction Done interrupt
EP6 Interrupt Enable (Bit 6)
The EP6 Interrupt Enable bit will enable or disable endpoint seven (EP6) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP6 Transaction Done interrupt
0: Disable EP6 Transaction Done interrupt
EP5 Interrupt Enable (Bit 5)
The EP5 Interrupt Enable bit will enable or disable endpoint seven (EP5) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP5 Transaction Done interrupt
0: Disable EP5 Transaction Done interrupt
EP4 Interrupt Enable (Bit 4)
The EP4 Interrupt Enable bit will enable or disable endpoint seven (EP4) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP4 Transaction Done interrupt
0: Disable EP4 Transaction Done interrupt
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EP3 Interrupt Enable (Bit 3)
The EP3 Interrupt Enable bit will enable or disable endpoint seven (EP3) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP3 Transaction Done interrupt
0: Disable EP3 Transaction Done interrupt
EP2 Interrupt Enable (Bit 2)
The EP2 Interrupt Enable bit will enable or disable endpoint seven (EP2) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP2 Transaction Done interrupt
0: Disable EP2 Transaction Done interrupt
EP1 Interrupt Enable (Bit 1)
The EP1 Interrupt Enable bit will enable or disable endpoint seven (EP1) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP1 Transaction Done interrupt
0: Disable EP1 Transaction Done interrupt
EP0 Interrupt Enable (Bit 0)
The EP0 Interrupt Enable bit will enable or disable endpoint seven (EP0) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP0 Transaction Done interrupt
0: Disable EP0 Transaction Done interrupt
Reserved
All reserved bits should be written as ‘0’.
7.5.7 Device n Address Register [W]
• Device 1 Address Register 0xC08E
• Device 2 Address Register 0xC0AE
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Address
Read/Write - W W W W W W W
Default 0 0 0 0 0 0 0 0
Figure 7-35. Device n Address Register
Register Description
The Device n Address Register holds the device address assigned by the host. This register initializes to the default address 0
at reset but must be updated by firmware when the host assigns a new address. Only USB data sent to the address contained
in this register will be responded to, all others are ignored.
Address (Bits [6:0])
The Address field contains the USB address of the device assigned by the host.
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Reserved
All reserved bits should be written as ‘0’.
7.5.8 Device n Status Register [R/W]
• Device 1 Status Register 0xC090
• Device 2 Status Register 0xC0B0
Bit # 15 14 13 12 11 10 9 8
Field VBUS
Read/Write R/W R/W - - - - R/W R/W
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field EP7 Interrupt
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
Interrupt Flag
Flag
Register Description
The Device n Status Register provides status information for device operation. Pending interrupts can be cleared by writing a ‘1’
to the corresponding bit. This register can be accessed by the HPI interface.
ID Interrupt
Flag
EP6 Interrupt
Flag
Reserved SOF/EOP
EP5 Interrupt
Flag
EP4 Interrupt
Flag
EP3 Interrupt
Flag
Figure 7-36. Device n Status Register
EP2 Interrupt
Flag
Interrupt Flag
EP1 Interrupt
Flag
Reset
Interrupt Flag
EP0 Interrupt
Flag
VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt will
trigger on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Device 1 and is a reserved bit in Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
ID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt will trigger on
both the rising and falling edge of the OTG ID pin. This bit is only available for Device 1 and is a reserved bit in Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP received interrupt has triggered.
1: Interrupt triggered
0: Interrupt did not trigger
Reset Interrupt Flag (Bit 8)
The Reset Interrupt Flag bit indicates if the USB Reset Detected interrupt has triggered.
1: Interrupt triggered
0: Interrupt did not trigger
EP7 Interrupt Flag (Bit 7)
The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7) Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
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EP6 Interrupt Flag (Bit 6)
The EP6 Interrupt Flag bit indicates if the endpoint six (EP6) Transaction Done interrupt has triggered. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receive
ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in
the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP5 Interrupt Flag (Bit 5)
The EP5 Interrupt Flag bit indicates if the endpoint five (EP5) Transaction Done interrupt has triggered. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receive
ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in
the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP4 Interrupt Flag (Bit 4)
The EP4 Interrupt Flag bit indicates if the endpoint four (EP4) Transaction Done interrupt has triggered. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receive
ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in
the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP3 Interrupt Flag (Bit 3)
The EP3 Interrupt Flag bit indicates if the endpoint three (EP3) Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP2 Interrupt Flag (Bit 2)
The EP2 Interrupt Flag bit indicates if the endpoint two (EP2) Transaction Done interrupt has triggered. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receive
ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in
the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP1 Interrupt Flag (Bit 1)
The EP1 Interrupt Flag bit indicates if the endpoint one (EP1) Transaction Done interrupt has triggered. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receive
ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in
the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP0 Interrupt Flag (Bit 0)
The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0) Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
Reserved
All reserved bits should be written as ‘0’.
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7.5.9 Device n Frame Number Register [R]
• Device 1 Frame Number Register 0xC092
• Device 2 Frame Number Register 0xC0B2
Bit # 15 14 13 12 11 10 9 8
Field SOF/EOP
Read/Write R R R R - R R R
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Frame
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0
Time-out Flag
Register Description
The Device n Frame Number Register is a read only register that contains the Frame number of the last SOF packet received.
This register also contains a count of SOF/EOP Timeout occurrences.
SOF/EOP Time-out Flag (Bit 15)
The SOF/EOP Time-out Flag bit indicates when an SOF/EOP Timeout Interrupt occurs.
1: An SOF/EOP Time-out interrupt occurred
0: An SOF/EOP Time-out interrupt did not occur
SOF/EOP
Time-out Interrupt Counter
Reserved Frame...
Figure 7-37. Device n Frame Number Register
SOF/EOP Time-out Interrupt Counter (Bits [14:12])
The SOF/EOP Time-out Interrupt Counter field will increment by 1 from 0 to 7 for each SOF/EOP Time-out Interrupt. This field
resets to 0 when a SOF/EOP is received. This field is only updated when the SOF/EOP Time-out Interrupt Enable bit in the Device
n Interrupt Enable Register is set.
Frame (Bits [10:0])
The Frame field contains the frame number from the last received SOF packet in full speed mode. This field has no function for
low speed mode. If a SOF Timeout occurs, this field will contain the last received Frame number.
7.5.10 Device n SOF/EOP Count Register [W]
• Device 1 SOF/EOP Count Register 0xC094
• Device 2 SOF/EOP Count Register 0xC0B4
Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - R R R R R R
Default 0 0 1 0 1 1 1 0
Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R R R R R R R R
Default 1 1 1 0 0 0 0 0
Figure 7-38. Device n SOF/EOP Count Register
Register Description
The Device n SOF/EOP Count Register should be written with the time expected between receiving a SOF/EOPs. If the SOF/EOP
counter expires before an SOF/EOP is received, an SOF/EOP Time-out Interrupt can be generated. The SOF/EOP Time-out
Interrupt Enable and SOF/EOP Time-out Interrupt Flag are located in the Device n Interrupt Enable and Status Registers,
respectively.
The SOF/EOP count should be set slightly greater than the expected SOF/EOP interval. The SOF/EOP counter decrements at
a 12-MHz rate. Therefore in the case of an expected 1-ms SOF/EOP interval, the SOF/EOP count should be set slightly greater
then 0x2EE0.
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Count (Bits [13:0])
The Count field contains the current value of the SOF/EOP down counter. At power-up and reset, this value is set to 0x2EE0 and
for expected 1-ms SOF/EOP intervals, this SOF/EOP count should be increased slightly.
Reserved
All reserved bits should be written as ‘0’.
7.6 OTG Control Registers
There is one register dedicated for OTG operation. This register is covered in this section and summarized in Figure 7-39.
Register Name Address R/W
OTG Control Register C098H R/W
Figure 7-39. OTG Registers
7.6.1 OTG Control Register [0xC098] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved VBUS
Read/Write - - R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field D+
Read/Write R/W R/W - - - R R R
Default 0 0 0 0 0 X X X
Pull-down
Enable
D–
Pull-down
Enable
Pull-up
Enable
Figure 7-40. OTG Control Register
Receive
Disable
Reserved OTG Data
Charge Pump
Enable
VBUS
Discharge
Enable
Status
D+
Pull-up
Enable
ID
Status
D–
Pull-up
Enable
VBUS Valid
Flag
Register Description
The OTG Control Register allows control and monitoring over the OTG port on Port1A.
VBUS Pull-up Enable (Bit 13)
The VBUS Pull-up Enable bit enables or disables a 500Ω pull-up resistor onto OTG VBus.
1: 500Ω pull-up resistor enabled
0: 500Ω pull-up resistor disabled
Receive Disable (Bit 12)
The Receive Disable bit enables or powers down (disables) the OTG receiver section.
1: OTG receiver powered down and disabled
0: OTG receiver enabled
Charge Pump Enable (Bit 11)
The Charge Pump Enable bit enables or disables the OTG VBus charge pump.
1: OTG VBus charge pump enabled
0: OTG VBus charge pump disabled
VBUS Discharge Enable (Bit 10)
The VBUS Discharge Enable bit enables or disables a 2KΩ discharge pull-down resistor onto OTG VBus.
1: 2KΩ pull-down resistor enabled
0: 2KΩ pull-down resistor disabled
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D+ Pull-up Enable (Bit 9)
The D+ Pull-up Enable bit enables or disables a pull-up resistor on the OTG D+ data line.
1: OTG D+ dataline pull-up resistor enabled
0: OTG D+ dataline pull-up resistor disabled
D– Pull-up Enable (Bit 8)
The D– Pull-up Enable bit enables or disables a pull-up resistor on the OTG D– data line.
1: OTG D– dataline pull-up resistor enabled
0: OTG D– dataline pull-up resistor disabled
D+ Pull-down Enable (Bit 7)
The D+ Pull-down Enable bit enables or disables a pull-down resistor on the OTG D+ data line.
1: OTG D+ dataline pull-down resistor enabled
0: OTG D+ dataline pull-down resistor disabled
D– Pull-down Enable (Bit 6)
The D– Pull-down Enable bit enables or disables a pull-down resistor on the OTG D- data line.
1: OTG D– dataline pull-down resistor enabled
0: OTG D– dataline pull-down resistor disabled
OTG Data Status (Bit 2)
The OTG Data Status bit is a read-only bit and indicates the TTL logic state of the OTG VBus pin.
1: OTG VBus is greater than 2.4V
0: OTG VBus is less than 0.8V
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ID Status (Bit 1)
The ID Status bit is a read-only bit that indicates the state of the OTG ID pin on Port A.
1: OTG ID Pin is not connected directly to ground (>10kΩ)
0: OTG ID Pin is connected directly ground (< 10Ω)
VBUS Valid Flag (Bit 0)
The VBUS Valid Flag bit indicates whether OTG VBus is greater than 4.4V. After turning on VBUS, firmware should wait at least
10 µs before this reading this bit.
1: OTG VBus is greater then 4.4V
0: OTG VBus is less then 4.4V
Reserved
All reserved bits should be written as ‘0’.
7.7 GPIO Registers
There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized in
Figure 7-41.
Register Name Address R/W
GPIO Control Register 0xC006 R/W
GPIO0 Output Data Register 0xC01E R/W
GPIO0 Input Data Register 0xC020 R
GPIO0 Direction Register 0xC022 R/W
GPIO1 Output Data Register 0xC024 R/W
GPIO1 Input Data Register 0xC026 R
GPIO1 Direction Register 0xC028 R/W
Figure 7-41. GPIO Registers
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7.7.1 GPIO Control Register [0xC006] [R/W]
Bit # 15 14 13 12 11 10 9 8
Enable
Reserved
SAS
Enable
Reserved Interrupt 0
Mode
Select
Polarity Select
Interrupt 0
Enable
Field Write Protect
Read/Write R/W R/W R - R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field HSS
Read/Write R/W - R/W - - - R/W R/W
Default 0 0 0 0 0 0 0 0
Enable
Enable
UD
Reserved SPI
Figure 7-42. GPIO Control Register
Register Description
The GPIO Control Register configures the GPIO pins for various interface options. It also controls the polarity of the GPIO interrupt
on IRQ0 (GPIO24).
Write Protect Enable (Bit 15)
The Write Protect Enable bit enables or disables the GPIO write protect. When Write Protect is enabled, the GPIO Mode Select
[10:8] field read-only until a chip reset.
1: Enable Write Protect
0: Disable Write Protect
UD (Bit 14)
The UD bit routes the Host/Device 1A Port’s transmitter enable status to GPIO[30]. This is for use with an external ESD protection
circuit when needed.
1: Route the signal to GPIO[30]
0: Do not route the signal to GPIO[30]
SAS Enable (Bit 11)
The SAS Enable bit, when in SPI mode, will reroute the SPI port SPI_nSSI pin to GPIO[15] rather then GPIO[9].
1: Reroute SPI_nss to GPIO[15]
0: Leave SPI_nss on GPIO[9]
Mode Select (Bits [10:8])
The Mode Select field selects how GPIO[15:0] and GPIO[24:19] are used as defined in Tab le 7 -8 .
Table 7-8. Mode Select Definition
Mode Select [10:8] GPIO Configuration
111 Reserved
110 SCAN — (HW) Scan diagnostic.
For production test only. Not for
normal operation
101 HPI — Host Port Interface
100 Reserved
011 Reserved
010 Reserved
001 Reserved
000 GPIO — General Purpose Input
Output
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HSS Enable (Bit 7)
The HSS Enable bit routes HSS to GPIO[15:12].
1: HSS is routed to GPIO
0: HSS is not routed to GPIOs. GPIO[15:12] are free for other purposes.
SPI Enable (Bit 5)
The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable bit is set, it will override and route the SPI_nSSI pin to GPIO15.
1: SPI is routed to GPIO[11:8]
0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other purposes.
Interrupt 0 Polarity Select (Bit 1)
The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.
1: Sets IRQ0 to rising edge
0: Sets IRQ0 to falling edge
Interrupt 0 Enable (Bit 0)
The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO bit on the interrupt Enable Register must also be set in order for
this for this interrupt to be enabled.
1: Enable IRQ0
0: Disable IRQ0
Reserved
All reserved bits should be written as ‘0’.
7.7.2 GPIO 0 Output Data Register [0xC01E] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-43. GPIO 0 Output Data Register
Register Description
The GPIO 0 Output Data Register controls the output data of the GPIO pins. The GPIO 0 Output Data Register controls GPIO15
to GPIO0 while the GPIO 1 Output Data Register controls GPIO31 to GPIO19. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data Register).
Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.
Reserved
All reserved bits should be written as ‘0’.
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7.7.3 GPIO 1 Output Data Register [0xC024] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field GPIO31 GPIO30 GPIO29 Reserved GPIO24
Read/Write R/W R/W R/W - - - - R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved
Read/Write R/W R/W R/W R/W R/W - - -
Default 0 0 0 0 0 0 0 0
Figure 7-44. GPIO n Output Data Register
Register Description
The GPIO 1 Output Data Register controls the output data of the GPIO pins. The GPIO 0 Output Data Register controls GPIO15
to GPIO0 while the GPIO 1 Output Data Register controls GPIO31 to GPIO19. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data Register).
Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.
Reserved
All reserved bits should be written as ‘0’.
7.7.4 GPIO 0 Input Data Register [0xC020] [R]
Bit # 15 14 13 12 11 10 9 8
Field GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0
Figure 7-45. GPIO 0 Input Data Register
Register Description
The GPIO 0 Input Data Register reads the input data of the GPIO pins. The GPIO 0 Input Data Register reads from GPIO15 to
GPIO0 while the GPIO 1 Input Data Register reads from GPIO31 to GPIO19.
Every bit represents the voltage of that GPIO pin.
7.7.5 GPIO 1 Input Data Register [0xC026] [R]
Bit # 15 14 13 12 11 10 9 8
Field GPIO31 GPIO30 GPIO29 Reserved GPIO24
Read/Write R R R - - - - R
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved
Read/Write R R R R R - - -
Default 0 0 0 0 0 0 0 0
Figure 7-46. GPIO 1 Input Data Register
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Register Description
The GPIO 1 Input Data Register reads the input data of the GPIO pins. The GPIO 0 Input Data Register reads from GPIO15 to
GPIO0 while the GPIO 1 Input Data Register reads from GPIO31 to GPIO19.
Every bit represents the voltage of that GPIO pin.
7.7.6 GPIO 0 Direction Register [0xC022] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-47. GPIO 0 Direction Register
Register Description
The GPIO 0 Direction Register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction Register controls
GPIO15 to GPIO0 while the GPIO 1 Direction Register controls GPIO31 to GPIO19.
When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register is
set to ‘0’, the corresponding GPIO data pin becomes an input.
Reserved
All reserved bits should be written as ‘0’.
7.7.7 GPIO 1 Direction Register [0xC028] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field GPIO31 GPIO30 GPIO29 Reserved GPIO24
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-48. GPIO 1 Direction Register
Register Description
The GPIO 1 Direction Register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction Register controls
GPIO15 to GPIO0 while the GPIO 1 Direction Register controls GPIO31 to GPIO19.
When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register is
set to ‘0’, the corresponding GPIO data pin becomes an input.
Reserved
All reserved bits should be written as ‘0’.
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7.8 HSS Registers
There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in
Figure 7-49.
Register Name Address R/W
HSS Control Register 0xC070 R/W
HSS Baud Rate Register 0xC072 R/W
HSS Transmit Gap Register 0xC074 R/W
HSS Data Register 0xC076 R/W
HSS Receive Address Register 0xC078 R/W
HSS Receive Length Register 0xC07A R/W
HSS Transmit Address Register 0xC07C R/W
HSS Transmit Length Register 0xC07E R/W
Figure 7-49. HSS Registers
7.8.1 HSS Control Register [0xC070] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field HSS
Enable
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
RTS
Polarity Select
CTS
Polarity Select
XOFF XOFF
Enable
CTS
Enable
Receive
Interrupt
Enable
Done
Interrupt
Enable
Bit # 7 6 5 4 3 2 1 0
Field Transmit
Read/Write R/W R/W R/W R R/W R/W R R
Default 0 0 0 0 0 0 0 0
Done Interrupt
Enable
Receive
Done Interrupt
Enable
One
Stop Bit
Transmit
Ready
Packet
Mode
Select
Receive
Overflow
Flag
Receive
Packet Ready
Flag
Figure 7-50. HSS Control Register
Register Description
The HSS Control Register provides high-level status and control over the HSS port.
HSS Enable (Bit 15)
The HSS Enable bit enables or disables HSS operation.
1: Enables HSS operation
0: Disables HSS operation
RTS Polarity Select (Bit 14)
The RTS Polarity Select bit selects the polarity of RTS.
1: RTS is true when LOW
0: RTS is true when HIGH
CTS Polarity Select (Bit 13)
The CTS Polarity Select bit selects the polarity of CTS.
1: CTS is true when LOW
0: CTS is true when HIGH
Receive
Ready
Flag
XOFF (Bit 12)
The XOFF bit is a read-only bit that indicates if an XOFF has been received. This bit will automatically clear when an XON has
been received.
1: XOFF received
0: XON received
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XOFF Enable (Bit 11)
The XOFF Enable bit enables or disables XON/XOFF software handshaking.
1: Enable XON/XOFF software handshaking
0: Disable XON/XOFF software handshaking
CTS Enable (Bit 10)
The CTS Enable bit enables or disables CTS/RTS hardware handshaking.
1: Enable CTS/RTS hardware handshaking
0: Disable CTS/RTS hardware handshaking
Receive Interrupt Enable (Bit 9)
The Receive Interrupt Enable bit enables or disables the Receive Ready and Receive Packet Ready interrupts.
1: Enable the Receive Ready and Receive Packet Ready interrupts
0: Disable the Receive Ready and Receive Packet Ready interrupts
Done Interrupt Enable (Bit 8)
The Done Interrupt Enable bit enables or disables the Transmit Done and Receive Done interrupts.
1: Enable the Transmit Done and Receive Done interrupts
0: Disable the Transmit Done and Receive Done interrupts
Transmit Done Interrupt Flag (Bit 7)
The Transmit Done Interrupt Flag bit indicates the status of the Transmit Done Interrupt. It will set when a block transmit is finished.
To clear the interrupt, a ‘1’ should be written to this bit.
1: Interrupt triggered
0: Interrupt did not trigger
Receive Done Interrupt Flag (Bit 6)
The Receive Done Interrupt Flag bit indicates the status of the Receive Done Interrupt. It will set when a block transmit is finished.
To clear the interrupt, a ‘1’ should be written to this bit.
1: Interrupt triggered
0: Interrupt did not trigger
One Stop Bit (Bit 5)
The One Stop Bit bit selects between one and two stop bits for transmit byte mode. In receive mode, the number of stop bits may
vary and does not need to be fixed.
1: One stop bit
0: Two stop bits
Transmit Ready (Bit 4)
The Transmit Ready bit is a read only bit that indicates if the HSS Transmit FIFO is ready for the CPU to load new data for
transmission.
1: HSS transmit FIFO ready for loading
0: HSS transmit FIFO not ready for loading
Packet Mode Select (Bit 3)
The Packet Mode Select bit selects between Receive Packet Ready and Receive Ready as the interrupt source for the RxIntr
interrupt.
1: Selects Receive Packet Ready as the source
0: Selects Receive Ready as the source
Receive Overflow Flag (Bit 2)
The Receive Overflow Flag bit indicates if the Receive FIFO overflowed when set. This flag can be cleared by writing a ‘1’ to this
bit.
1: Overflow occurred
0: Overflow did not occur
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Receive Packet Ready Flag (Bit 1)
The Receive Packet Ready Flag bit is a read only bit that indicates if the HSS receive FIFO is full with eight bytes or not.
1: HSS receive FIFO is full
0: HSS receive FIFO is not full
Receive Ready Flag (Bit 0)
The Receive Ready Flag is a read only bit that indicates if the HSS receive FIFO is empty or not.
1: HSS receive FIFO is not empty (one or more bytes is reading for reading)
0: HSS receive FIFO is empty
7.8.2 HSS Baud Rate Register [0xC072] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved Baud...
Read/Write - - - R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Baud
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 1 0 1 1 1
Figure 7-51. HSS Baud Rate Register
Register Description
The HSS Baud Rate Register will set the HSS Baud Rate. At reset, the default value is 0x0017 which will set the baud rate to
2.0 MHz.
Baud (Bits [12:0])
The Baud field is the baud rate divisor minus one, in units of 1/48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts
a constraint on the Baud Value as follows: (24 – 1) ≤ Baud ≥ (5000 – 1)
Reserved
All reserved bits should bit written as ‘0’.
7.8.3 HSS Transmit Gap Register [0xC074] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field Transmit Gap Select
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 1 0 0 1
Figure 7-52. HSS Transmit Gap Register
Register Description
The HSS Transmit Gap Register is only valid in block transmit mode. It allows for a programmable number of stop bits to be
inserted thus overwriting the One Stop Bit in the HSS Control Register. The default reset value of this register is 0x0009, equivalent
to two stop bits.
Transmit Gap Select (Bits [7:0])
The Transmit Gap Select field sets the inactive time between transmitted bytes. The inactive time = (Transmit Gap Select – 7) *
bit time. Therefore an Transmit Gap Select Value of 8 is equal to having one Stop bit.
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Reserved
All reserved bits should be written as ‘0’.
7.8.4 HSS Data Register [0xC076] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field Data
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
Figure 7-53. HSS Data Register
Register Description
The HSS Data Register contains data received on the HSS port (not for block receive mode) when read. This receive data is valid
when the Receive Ready bit of the HSS Control Register is set to ‘1’. Writing to this register will initiate a single byte transfer of
data. The Transmit Ready Flag in the HSS Control Register should read ‘1’ before writing to this register (this avoids disrupting
the previous/current transmission).
Data (Bits [7:0])
The Data field contains the data received or to be transmitted on the HSS port.
Reserved
All reserved bits should be written as ‘0’.
7.8.5 HSS Receive Address Register [0xC078] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-54. HSS Receive Address Register
Register Description
The HSS Receive Address Register is used as the base pointer address for the next HSS block receive transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block receive transfer.
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7.8.6 HSS Receive Counter Register [0xC07A] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved Counter...
Read/Write - - - - - - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Counter
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-55. HSS Receive Counter Register
Register Description
The HSS Receive Counter Register designates the block byte length for the next HSS receive transfer. This register should be
loaded with the word count minus one to start the block receive transfer. As each byte is received this register value is decremented. When read, this register indicates the remaining length of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When
the transfer is complete this register returns 0x03FF until reloaded.
Reserved
All reserved bits should be written as ‘0’.
7.8.7 HSS Transmit Address Register [0xC07C] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-56. HSS Transmit Address Register
Register Description
The HSS Transmit Address Register is used as the base pointer address for the next HSS block transmit transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block transmit transfer.
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7.8.8 HSS Transmit Counter Register [0xC07E] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved Counter...
Read/Write - - - - - - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Counter
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-57. HSS Transmit Counter Register
Register Description
The HSS Transmit Counter Register designates the block byte length for the next HSS transmit transfer. This register should be
loaded with the word count minus one to start the block transmit transfer. As each byte is transmitted this register value is
decremented. When read, this register indicates the remaining length of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When
the transfer is complete this register returns 0x03FF until reloaded.
Reserved
All reserved bits should be written as ‘0’.
7.9 HPI Registers
There are five registers dedicated to HPI operation. In addition, there is an HPI status port which can be address over HPI. Each
of these registers is covered in this section and are summarized in Figure 7-58.
Register Name Address R/W
HPI Breakpoint Register 0x0140 R
Interrupt Routing Register 0x0142 R
SIE1msg Register 0x0144 W
SIE2msg Register 0x0148 W
HPI Mailbox Register 0xC0C6 R/W
Figure 7-58. HPI Registers
7.9.1 HPI Breakpoint Register [0x0140] [R]
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0
Figure 7-59. HPI Breakpoint Register
Register Description
The HPI Breakpoint Register is a special onchip memory location which the external processor can access using normal HPI
memory read/write cycles. This register is read only by the CPU but is read/write by the HPI port. The contents of this register
have the same effect as the Breakpoint Register [0xC014]. This special Breakpoint Register is used by software debuggers which
interface through the HPI port instead of the serial port.
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When the program counter matches the Breakpoint Address, the INT127 interrupt will trigger. To clear this interrupt, a zero value
should be written to this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
7.9.2 Interrupt Routing Register [0x0142] [R]
Bit # 15 14 13 12 11 10 9 8
Field VBUS to HPI
Read/Write R R R R R R R R
Default 0 001010 0
Bit # 7 6 5 4 3 2 1 0
Field Resume2 to
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Enable
HPI Enable
Register Description
The Interrupt Routing Register allows the HPI port to take over some or all of the SIE interrupts that usually go to the on-chip
CPU. This register is read only by the CPU but is read/write by the HPI port. By setting the appropriate bit to ‘1’, the SIE interrupt
is routed to the HPI port to become the HPI_INTR signal and also readable in the HPI Status Register. The bits in this register
select where the interrupts are routed. The individual interrupt enable is handled in the SIE interrupt enable register.
ID to HPI
Enable
Resume1 to
HPI Enable
SOF/EOP2 to
HPI Enable
SOF/EOP2 to
CPU Enable
Reserved Done2 to HPI
SOF/EOP1 to
HPI Enable
Enable
Figure 7-60. Interrupt Routing Register
SOF/EOP1 to
CPU Enable
Done1 to HPI
Enable
Reset2 to HPI
Enable
Reset1 to HPI
Enable
HPI Swap 1
Enable
HPI Swap 0
Enable
VBUS to HPI Enable (Bit 15)
The VBUS to HPI Enable bit routes the OTG VBUS interrupt to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
ID to HPI Enable (Bit 14)
The ID to HPI Enable bit routes the OTG ID interrupt to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to HPI Enable (Bit 13)
The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt to the HPI port.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to CPU Enable (Bit 12)
The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2 interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can be
routed to both the on-chip CPU and the HPI port the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU
0: Do not route signal to CPU
SOF/EOP1 to HPI Enable (Bit 11)
The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt to the HPI port.
1: Route signal to HPI port
0: Do not route signal to HPI port
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SOF/EOP1 to CPU Enable (Bit 10)
The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1 interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can be
routed to both the on-chip CPU and the HPI port the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU
0: Do not route signal to CPU
Reset2 to HPI Enable (Bit 9)
The Reset2 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
HPI Swap 1 Enable (Bit 8)
Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes to
HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant
data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].
Resume2 to HPI Enable (Bit 7)
The Resume2 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Resume1 to HPI Enable (Bit 6)
The Resume1 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Done2 to HPI Enable (Bit 3)
The Done2 to HPI Enable bit routes the Done interrupt for Host/Device 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Done1 to HPI Enable (Bit 2)
The Done1 to HPI Enable bit routes the Done interrupt for Host/Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Reset1 to HPI Enable (Bit 1)
The Reset1 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
HPI Swap 0 Enable (Bit 0)
Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes to
HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant
data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].
7.9.3 SIEXmsg Register [W]
• SIE1msg Register 0x0144
• SIE2msg Register 0x0148
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Bit # 15 14 13 12 11 10 9 8
Field Data...
Read/Write W W W W W W W W
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field ...Data
Read/Write W W W W W W W W
Default X X X X X X X X
Figure 7-61. SIEXmsg Register
Register Description
The SIEXmsg Register allows an interrupt to be generated on the HPI port. Any write to this register will cause the SIEXmsg flag
in the HPI Status Port to go high. If the SIEXmsg interrupt enable bit is set, this will also cause an interrupt on the HPI_INTR pin.
The SIEXmsg flag is automatically cleared when the HPI port reads from this register.
Data (Bits [15:0])
The Data field[15:0] simply needs to have any value written to it to cause SIExmsg flag in the HPI Status Port to go high.
7.9.4 HPI Mailbox Register [0xC0C6] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Message...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Message
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-62. HPI Mailbox Register
Register Description
The HPI Mailbox Register provides a common mailbox between the CY7C67200 and the external host processor.
If enabled, the HPI Mailbox RX Full interrupt will trigger when the external host processor writes to this register. When the
CY7C67200 reads this register the HPI Mailbox RX Full interrupt will automatically get cleared.
If enabled, the HPI Mailbox TX Empty interrupt will trigger when the external host processor reads from this register. The HPI
Mailbox TX Empty interrupt will automatically clear when the CY7C67200 writes to this register.
In addition, when the CY7C67200 writes to this register, the HPI_INTR signal on the HPI port will assert signaling the external
processor that there is data in the mailbox to read. The HPI_INTR signal will de-assert when the external host processor reads
from this register.
Message (Bits [15:0])
The Message field contains the message that the host processor wrote to the HPI Mailbox Register.
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7.9.5 HPI Status Port [] [HPI: R]
Bit # 15 14 13 12 11 10 9 8
Field VBUS
Read/Write R R - R - R R R
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field Resume2
Read/Write R R R R R R R R
Default X X X X X X X X
Flag
Flag
Register Description
The HPI Status Port provides the external host processor with the MailBox status bits plus several SIE status bits. This register
is not accessible from the on-chip CPU. The additional SIE status bits are provided to aid external device driver firmware
development, and are not recommended for applications that do not have an intimate relationship with the on-chip BIOS.
Reading from the HPI Status Port does not result in a CPU HPI interface memory access cycle. The external host may continuously poll this register without degrading the CPU or DMA performance.
VBUS Flag (Bit 15)
The VBUS Flag bit is a read-only bit that indicates whether OTG VBus is greater than 4.4V. After turning on VBUS, firmware
should wait at least 10 µs before this reading this bit.
1: OTG VBus is greater then 4.4V
0: OTG VBus is less then 4.4V
ID
Flag
Resume1
Flag
Reserved SOF/EOP2
SIE2msg
Flag
SIE1msg
Figure 7-63. HPI Status Port
Reserved SOF/EOP1
Done2
Flag
Flag
Done1
Flag
Reset2
Flag
Reset1
Flag
Mailbox In
Flag
Mailbox Out
Flag
ID Flag (Bit 14)
The ID Flag bit is a read-only bit that indicates the state of the OTG ID pin.
SOF/EOP2 Flag (Bit 12)
The SOF/EOP2 Flag bit is a read-only bit that indicates if a SOF/EOP interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP1 Flag (Bit 10)
The SOF/EOP1 Flag bit is a read-only bit that indicates if a SOF/EOP interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Reset2 Flag (Bit 9)
The Reset2 Flag bit is a read-only bit that indicates if a USB Reset interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Mailbox In Flag (Bit 8)
The Mailbox In Flag bit is a read-only bit that indicates if a message is ready in the incoming mailbox. This interrupt clears when
onchip CPU reads from the HPI Mailbox Register.
1: Interrupt triggered
0: Interrupt did not trigger
Resume2 Flag (Bit 7)
The Resume2 Flag bit is a read-only bit that indicates if a USB resume interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
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Resume1 Flag (Bit 6)
The Resume1 Flag bit is a read-only bit that indicates if a USB resume interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
SIE2msg (Bit 5)
The SIE2msg Flag bit is a read only bit that indicates if the CY7C67200 CPU has written to the SIE2msg register. This bit will
clear on an HPI read.
1: The SIE2msg register has been written by the CY7C67200 CPU
0: The SIE2msg register has not been written by the CY7C67200 CPU
SIE1msg (Bit 4)
The SIE1msg Flag bit is a read only bit that indicates if the CY7C67200 CPU has written to the SIE1msg register. This bit will
clear on an HPI read.
1: The SIE1msg register has been written by the CY7C67200 CPU
0: The SIE1msg register has not been written by the CY7C67200 CPU
Done2 Flag (Bit 3)
In host mode the Done2 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 2. In device mode
this read-only bit indicates if an any of the endpoint interrupts occurs on Device 2. Firmware will need to determine which endpoint
interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Done1 Flag (Bit 2)
In host mode the Done 1 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 1. In device mode
this read-only bit indicates if an any of the endpoint interrupts occurs on Device 1. Firmware will need to determine which endpoint
interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Reset1 Flag (Bit 1)
The Reset1 Flag bit is a read-only bit that indicates if a USB Reset interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Mailbox Out Flag (Bit 0)
The Mailbox Out Flag bit is a read only bit that indicates if a message is ready in the outgoing mailbox. This interrupt clears when
the external host reads from the HPI Mailbox Register.
1: Interrupt triggered
0: Interrupt did not trigger
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7.10 SPI Registers
There are 12 registers dedicated to SPI operation. Each register is covered in this section and summarized in Figure 7-64.
Register Name Address R/W
SPI Configuration Register 0xC0C8 R/W
SPI Control Register 0xC0CA R/W
SPI Interrupt Enable Register 0xC0CC R/W
SPI Status Register 0xC0CE R
SPI Interrupt Clear Register 0xC0D0 W
SPI CRC Control Register 0xC0D2 R/W
SPI CRC Value 0xC0D4 R/W
SPI Data Register 0xC0D6 R/W
SPI Transmit Address Register 0xC0D8 R/W
SPI Transmit Count Register 0xC0DA R/W
SPI Receive Address Register 0xC0DC R/W
SPI Receive Count Register 0xC0DE R/W
Figure 7-64. SPI Registers
7.10.1 SPI Configuration Register [0xC0C8] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field 3Wire
Read/Write R/W R/W R/W R/W R/W R/W R/W -
Default 1 0 0 0 0 0 0 0
Enable
Phase
Select
SCK Polarity
Select
Scale Select Reserved
Bit # 7 6 5 4 3 2 1 0
Field Master
Active Enable
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 1 1 1 1 1
Master
Enable
SS
Enable
SS Delay Select
Figure 7-65. SPI Configuration Register
Register Description
The SPI Configuration Register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
3Wire Enable (Bit 15)
The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowing only half duplex operation.
1: MISO and MOSI data lines are tied together
0: Normal MISO and MOSI Full Duplex operation (not tied together)
Phase Select (Bit 14)
The Phase Select bit selects advanced or delayed SCK phase. This field only applies to master mode.
1: Advanced SCK phase
0: Delayed SCK phase
SCK Polarity Select (Bit 13)
This SCK Polarity Select bit selects the polarity of SCK.
1: Positive SCK polarity
0: Negative SCK polarity
Scale Select (Bits [12:9])
The Scale Select field provides control over the SCK frequency, based on 48 MHz. See Table 7-9 for a definition of this field. This
field only applies to master mode.
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Table 7-9. Scale Select Field Definition for SCK Frequency
Scale Select [12:9] SCK Frequency
0000 12 MHz
0001 8 MHz
0010 6 MHz
0011 4 MHz
0100 3 MHz
0101 2 MHz
0110 1.5 MHz
0111 1 MHz
1000 750 KHz
1001 500 KHz
1010 375 KHz
1011 250 KHz
1100 375 KHz
1101 250 KHz
1110 375 KHz
1111 2 50 KHz
Master Active Enable (Bit 7)
The Master Active Enable bit is a read only bit that indicates if the master state machine is active or idle. This field only applies
to master mode.
1: Master state machine is active
0: Master state machine is idle
Master Enable (Bit 6)
The Master Enable bit sets the SPI interface to master or slave. This bit is only writable when the Master Active Enable bit reads
‘0’, otherwise value will not change.
1: Master SPI interface
0: Slave SPI interface
SS Enable (Bit 5)
The SS Enable bit enables or disables the master SS output.
1: Enable master SS output
0: Disable master SS output (three-state master SS output, for single SS line in slave mode)
SS Delay Select (Bits [4:0])
When the SS Delay Select field is set to ‘00000’ this indicates manual mode. In manual mode SS is controlled by the SS Manual
bit of the SPI Control Register. When the SS Delay Select field is set between ‘00001’ to ‘11111’, this value indicates the count in
half bit times of auto transfer delay for: SS LOW to SCK active, SCK inactive to SS HIGH, SS HIGH time. This field only applies
to master mode.
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7.10.2 SPI Control Register [0xC0CA] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field SCK
Read/Write W W R/W R/W R/w R/W R R
Default 0 0 0 0 0 0 0 1
Bit # 7 6 5 4 3 2 1 0
Field Transmit
Read/Write R R R/W R/W R/W R/W R/w R/W
Default 1 0 0 0 0 0 0 0
Strobe
Empty
Register Description
The SPI Control Register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
SCK Strobe (Bit 15)
The SCK Strobe bit starts the SCK strobe at the selected frequency and polarity (set in the SPI Configuration Register), but not
phase. This bit feature can only be enabled when in master mode and must be during a period of inactivity. This bit is self clearing.
1: SCK Strobe Enable
0: No Function
FIFO
Init
Receive
Full
Byte
Mode
Full Duplex SS
Transmit Bit Length Receive Bit Length
Manual
Figure 7-66. SPI Control Register
Read
Enable
Transmit
Ready
Receive
Data Ready
FIFO Init (Bit 14)
The FIFO Init bit will initialize the FIFO and clear the FIFO Error Status bit. This bit is self clearing.
1: FIFO Init Enable
0: No Function
Byte Mode (Bit 13)
The Byte Mode bit selects between PIO (byte mode) and DMA (block mode) operation.
1: Set PIO (byte mode) operation
0: Set DMA (block mode) operation
Full Duplex (Bit 12)
The Full Duplex bit selects between full duplex and half duplex operation.
1: Enable full duplex. Full duplex is not allowed and will not set if the 3Wire Enable bit of the SPI Configuration Register is set to ‘1’
0: Enable half duplex operation
SS Manual (Bit 11)
The SS Manual bit activates or deactivates SS if the SS Delay Select field of the SPI Control Register is all zeros and is configured
as master interface. This field only applies to master mode.
1: Activate SS, master drives SS line asserted LOW
0: Deactivate SS, master drives SS line deasserted HIGH
Read Enable (Bit 10)
The Read Enable bit will initiate a read phase for a master mode transfer or set the slave to receive (in slave mode).
1: Initiates a read phase for a master transfer or sets a slave to receive. In master mode this bit is sticky and remains set until
the read transfer begins.
0: Initiates the write phase for slave operation
Transmit Ready (Bit 9)
The Transmit Ready bit is a read-only bit that indicates if the transmit port is ready to empty and ready to be written.
1: Ready for data to be written to the port. The transmit FIFO is not full.
0: Not ready for data to be written to the port
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CY7C67200
Receive Data Ready (Bit 8)
The Receive Data Ready bit is a read-only bit that indicates if the receive port has data ready.
1: Receive port has data ready to read
0: Receive port does not have data ready
Transmit Empty (Bit 7)
The Transmit Empty bit is a read-only bit that indicates if the transmit FIFO is empty.
1: Transmit FIFO is empty
0: Transmit FIFO is not empty
Receive Full (Bit 6)
The Receive Full bit is a read-only bit that indicates if the receive FIFO is full.
1: Receive FIFO is full
0: Receive FIFO is not full
Transmit Bi t Length (Bits [5:3])
The Transmit Bit Length field controls whether a full byte or partial byte is to be transmitted. If Transmit Bit Length is ‘000’, a full
byte will be transmitted. If Transmit Bit Length is ‘001’ to ‘111’, the value indicates the number of bits that will be transmitted.
Receive Bit Length (Bits [2:0])
The Receive Bit Length field controls whether a full byte or partial byte will be received. If Receive Bit Length is ‘000’ then a full
byte will be received. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that will be received.
7.10.3 SPI Interrupt Enable Register [0xC0CC] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Receive
Read/Write - - - - - R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Interrupt Enable
Transmit
Interrupt Enable
Transfer
Interrupt Enable
Figure 7-67. SPI Interrupt Enable Register
Register Description
The SPI Interrupt Enable Register controls the SPI port.
Receive Interrupt Enable (Bit 2)
The Receive Interrupt Enable bit will enable or disable the byte mode receive interrupt (RxIntVal).
1: Enable byte mode receive interrupt
0: Disable byte mode receive interrupt
Transmit Interrupt Enable (Bit 1)
The Transmit Interrupt Enable bit will enable or disable the byte mode transmit interrupt (TxIntVal).
1: Enables byte mode transmit interrupt
0: Disables byte mode transmit interrupt
Transfer Interrupt Enable (Bit 0)
The Transfer Interrupt Enable bit will enable or disable the block mode interrupt (XfrBlkIntVal).
1: Enables block mode interrupt
0: Disables block mode interrupt
Document #: 38-08014 Rev. *E Page 75 of 98
CY7C67200
Reserved
All reserved bits should be written as ‘0’.
7.10.4 SPI Status Register [0xC0CE] [R]
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field FIFO Error
Read/Write R - - - - R R R
Default 0 0 0 0 0 0 0 0
Flag
Reserved
Figure 7-68. SPI Status Register
Register Description
The SPI Status Register is a read only register that provides status for the SPI port.
FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read only bit that indicates if a FIFO error occurred. When this bit is set to ‘1’ and the Transmit Empty
bit of the SPI Control Register is set to ‘1’, then a Tx FIFO underflow has occurred. Similarly, when set with the Receive Full bit
of the SPI Control Register, a Rx FIFO overflow has occured.This bit automatically clear when the SPI FIFO Init Enable bit of the
SPI Control register is set.
1: Indicates FIFO error
0: Indicates no FIFO error
Receive
Interrupt Flag
Transmit
Interrupt Flag
Transfer
Interrupt Flag
Receive Interrupt Flag (Bit 2)
The Receive Interrupt Flag is a read only bit that indicates if a byte mode receive interrupt has triggered.
1: Indicates a byte mode receive interrupt has triggered
0: Indicates a byte mode receive interrupt has not triggered
Transmit Interrupt Flag (Bit 1)
The Transmit Interrupt Flag is a read only bit that indicates a byte mode transmit interrupt has triggered.
1: Indicates a byte mode transmit interrupt has triggered
0: Indicates a byte mode transmit interrupt has not triggered
Transfer Interrupt Flag (Bit 0)
The Transfer Interrupt Flag is a read only bit that indicates a block mode interrupt has triggered.
1: Indicates a block mode interrupt has triggered
0: Indicates a block mode interrupt has not triggered
Document #: 38-08014 Rev. *E Page 76 of 98
CY7C67200
7.10.5 SPI Interrupt Clear Register [0xC0D0] [W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field Reserved Transmit
Read/Write - - - - - - W W
Default 0 0 0 0 0 0 0 0
Interrupt Clear
Figure 7-69. SPI Interrupt Clear Register
Register Description
The SPI Interrupt Clear Register is a write-only register that allows the SPI Transmit and SPI Transfer Interrupts to be cleared.
Transmit Interrupt Clear (Bit 1)
The Transmit Interrupt Clear bit is a write-only bit that will clear the byte mode transmit interrupt. This bit is self clearing.
1: Clear the byte mode transmit interrupt
0: No function
Transfer Interrupt Clear (Bit 0)
The Transfer Interrupt Clear bit is a write-only bit that will clear the block mode interrupt. This bit is self clearing.
1: Clear the block mode interrupt
0: No function
Reserved
All reserved bits should be written as ‘0’.
Transfer
Interrupt Clear
7.10.6 SPI CRC Control Register [0xC0D2] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field CRC Mode CRC
Enable
Read/Write R/W R/W R/W R/W R/W R R -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
CRC
Clear
Receive
CRC
One in
CRC
Zero in
CRC
Figure 7-70. SPI CRC Control Register
Register Description
The SPI CRC Control Register provides control over the CRC source and polynomial value.
CRC Mode (Bits [15:14)
The CRCMode field selects the CRC polynomial as defined in Table 7-10.
Table 7-10. CRC Mode Definition
CRCMode [9:8] CRC Polynomial
00 MMC 16-bit: X^16 + X^12 + X^5 + 1(CCITT Standard)
01 CRC7 7-bit: X^7+ X^3 + 1
10 MST 16-bit: X^16+ X^15 + X^2 + 1
11 Reserved, 16-bit polynomial 1.
Reserved...
Document #: 38-08014 Rev. *E Page 77 of 98
CY7C67200
CRC Enable (Bit 13)
The CRC Enable bit will enable or disable the CRC operation.
1: Enables CRC operation
0: Disables CRC operation
CRC Clear (Bit 12)
The CRC Clear bit will clear the CRC with a load of all ones. This bit is self clearing and always reads ‘0’.
1: Clear CRC with all ones
0: No Function
Receive CRC (Bit 11)
The Receive CRC bit determines whether the receive bit stream or the transmit bit stream is used for the CRC data input in full
duplex mode. This bit is a don’t care in half duplex mode.
1: Assigns the receive bit stream
0: Assigns the transmit bit stream
One in CRC (Bit 10)
The One in CRC bit is a read-only bit that indicates if the CRC value is all zeros or not.
1: CRC value is not all zeros
0: CRC value is all zeros
Zero in CRC (Bit 9)
The Zero in CRC bit is a read-only bit that indicates if the CRC value is all ones or not.
1: CRC value is not all ones
0: CRC value is all ones
Reserved
All reserved bits should be written as ‘0’.
7.10.7 SPI CRC Value Register [0xC0D4] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field CRC...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1
Bit # 7 6 5 4 3 2 1 0
Field ...CRC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1
Figure 7-71. SPI CRC Value Register
Register Description
The SPI CRC Value Register contains the CRC value.
CRC (Bits [15:0])
The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value will be a seven bit value [6:0]. Therefore bits [15:7]
are invalid in CRC7 mode.
Document #: 38-08014 Rev. *E Page 78 of 98
CY7C67200
7.10.8 SPI Data Register [0xC0D6] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field Data
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
Figure 7-72. SPI Data Register
Register Description
The SPI Data Register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO
byte mode. This receive data is valid when the receive bit of the SPI Interrupt Value is set to ‘1’ (RxIntVal triggers) or the Receive
Data Ready bit of the SPI Control Register is set to ‘1’. Writing to this register in PIO byte mode will initiate a transfer of data, the
number of bits defined by Transmit Bit Length field in the SPI Control Register.
Data (Bits [7:0])
The Data field contains data received or to be transmitted on the SPI port.
Reserved
All reserved bits should be written as ‘0’.
7.10.9 SPI Transmit Address Register [0xC0D8] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-73. SPI Transmit Address Register
Register Description
The SPI Transmit Address Register is used as the base address for the SPI transmit DMA.
Address (Bits [15:0])
The Address field sets the base address for the SPI transmit DMA.
7.10.10 SPI Transmit Count Register [0xC0DA] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - - - - R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-74. SPI Transmit Count Register
Document #: 38-08014 Rev. *E Page 79 of 98
CY7C67200
Register Description
The SPI Transmit Count Register designates the block byte length for the SPI transmit DMA transfer.
Count (Bits [10:0])
The Count field sets the count for the SPI transmit DMA transfer.
Reserved
All reserved bits should be written as ‘0’.
7.10.11 SPI Receive Address Register [0xC0DC [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-75. SPI Receive Address Register
Register Description
The SPI Receive Address Register is issued as the base address for the SPI Receive DMA.
Address (Bits [15:0])
The Address field sets the base address for the SPI receive DMA.
7.10.12 SPI Receive Count Register [0xC0DE] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - - - - R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-76. SPI Receive Count Register
Register Description
The SPI Receive Count Register designates the block byte length for the SPI receive DMA transfer.
Count (Bits [10:0])
The Count field sets the count for the SPI receive DMA transfer.
Reserved
All reserved bits should be written as ‘0’.
Document #: 38-08014 Rev. *E Page 80 of 98
CY7C67200
7.11 UART Registers
There are three registers dedicated to UART operation. Each of these registers is covered in this section and summarized in
Figure 7-77.
Register Name Address R/W
UART Control Register 0xC0E0 R/W
UART Status Register 0xC0E2 R
UART Data Register 0xC0E4 R/W
Figure 7-77. UART Registers
7.11.1 UART Control Register [0xC0E0] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Scale
Select
Read/Write - - - R/W R/W R/W R/W R/W
Default 0 0 0 0 0 1 1 1
Baud
Select
UART
Enable
Figure 7-78. UART Control Register
Register Description
The UART Control Register enables or disables the UART allowing GPIO7 (UART_TXD) and GPIO6 (UART_RXD) to be freed
up for general use. This register must also be written to set the baud rate, which is based on a 48-MHz clock.
Scale Select (Bit 4)
The Scale Select bit acts as a prescaler that will divide the baud rate by eight.
1: Enable prescaler
0: Disable prescaler
Baud Select (Bits [3:1])
Please refer to Ta bl e 7-11 for a definition of this field.
Table 7-11. UART Baud Select Definition
Baud Select [3:1]
Baud Rate w/
DIV8 = 0
Baud Rate w/
DIV8 = 1
000 115.2 KBaud 14.4 KBaud
001 57.6 KBaud 7.2 KBaud
010 38.4 KBaud 4.8 KBaud
011 28.8 KBaud 3.6 KBaud
100 19.2 KBaud 2.4 KBaud
101 14.4 KBaud 1.8 KBaud
110 9.6 KBaud 1.2 KBaud
111 7.2 KBaud 0.9 KBaud
UART Enable (Bit 0)
The UART Enable bit enables or disables the UART.
1: Enable UART
0: Disable UART. This allows GPIO6 and GPIO7 to be used for general use
Document #: 38-08014 Rev. *E Page 81 of 98
CY7C67200
Reserved
All reserved bits should be written as ‘0’.
7.11.2 UART Status Register [0xC0E2] [R]
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Receive Full Transmit Full
Read/Write - - - - - - R R
Default 0 0 0 0 0 0 0 0
Figure 7-79. UART Status Register
Register Description
The UART Status Register is a read-only register that indicates the status of the UART buffer.
Receive Full (Bit 1)
The Receive Full bit indicates whether the receive buffer is full. It can be programmed to interrupt the CPU as interrupt #5 when
the buffer is full. This can be done though the UART bit of the Interrupt Enable Register (0xC00E). This bit will automatically be
cleared when data is read from the UART Data Register.
1: Receive buffer full
0: Receive buffer empty
Transmit Full (Bit 0)
The Transmit Full bit indicates whether the transmit buffer is full or not. It can be programmed to interrupt the CPU as interrupt
#4 when the buffer is empty. This can be done though the UART bit of the Interrupt Enable Register (0xC00E). This bit will
automatically be set to ‘1’ after data is written by EZ-Host to the UART Data Register (to be transmitted). This bit will automatically
be cleared to ‘0’ after the data is transmitted.
1: Transmit buffer full (transmit busy)
0: Transmit buffer is empty and ready for a new byte of data
7.11.3 UART Data Register [0xC0E4] [R/W]
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field Data
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Figure 7-80. UART Data Register
Register Description
The UART Data Register contains data to be transmitted or received from the UART port. Data written to this register will start a
data transmission and also causes the UART Transmit Empty Flag of the UART Status Register to set. When data received on
the UART port is read from this register, the UART Receive Full Flag of the UART Status Register will get cleared.
Data (Bits [7:0])
The Data field is where the UART data to be transmitted or received is located
Reserved
All reserved bits should be written as ‘0’.
Document #: 38-08014 Rev. *E Page 82 of 98
8.0 Pin Diagram
CY7C67200 48-pin FBGA
CY7C67200
A1
B1
AGND
C1
OTGVBUS
D1
E1
F1
BOOSTVCC
G1
AVC C
H1
GND
A2
GPIO1/D1
B2
GPIO0/D0
C2
DM2A
D2
E2
VSWITCHBOOSTGND
F2
DM1A
G2
XTALOUT
H2
VCC
A3
GPIO3/D3
B3
GPIO4/D4
C3
GPIO2/D2
D3
DP2ACSWITCHA CSWITCHB
E3
DP1A
F3
GPIO30/SDA
G3
XTALIN
H3
GPIO31/SCL
A4
VCC
B4
GPIO6/D6/RX
C4
GPIO5/D5
D4
GPIO11/D1/
MOSI
E4
GPIO14/D14/
RTS
F4
GPIO29/
OTGID
G4
GPIO23/nRD/
nWAIT
H4
GPIO24/INT/
IRQ0
A5
nRESET
B5
GPIO7/D7/TX
C5
GPIO8/D8/
MISO
D5
GPIO10/D10/
SCK
E5
GPIO13/D13/
RXD
F5
GPIO19/A0
G5
GPIO21/nCS/
nRESET
H5
GPIO22/nWR
A6
ReservedGND
B6
GND
C6
GPIO9/D9/
nSSI
D6
VCC
E6
GPIO12/D12/
TXD
F6
GPIO15/D15/
CTS/nSSI
G6
GND
H6
GPIO20/A1
Figure 8-1. EZ-OTG Pin Diagram
Document #: 38-08014 Rev. *E Page 83 of 98
9.0 Pin Descriptions
Table 9-1. Pin Descriptions
Pin Name Type Description
H3 GPIO31/SCK I/O GPIO31: General Purpose I/O
F3 GPIO30/SDA I/O GPIO30: General Purpose I/O
F4 GPIO29/OTGID I/O GPIO29: General Purpose I/O
H4 GPIO24/INT/IRQ0 I/O GPIO24: General Purpose I/O
G4 GPIO23/nRD I/O GPIO23: General Purpose I/O
H5 GPIO22/nWR I/O GPIO22: General Purpose I/O
G5 GPIO21/nCS I/O GPIO21: General Purpose I/O
H6 GPIO20/A1 I/O GPIO20: General Purpose I/O
F5 GPIO19/A0 I/O GPIO19: General Purpose I/O
F6 GPIO15/D15/CTS/
nSSI
E4 GPIO14/D14/RTS I/O GPIO14: General Purpose I/O
E5 GPIO13/D13/RXD I/O GPIO13: General Purpose I/O
E6 GPIO12/D12/TXD I/O GPIO12: General Purpose I/O
D4 GPIO11/D11/MOSI I/O GPIO11: General Purpose I/O
D5 GPIO10/D10/SCK I/O GPIO10: General Purpose I/O
C6 GPIO9/D9/nSSI I/O GPIO9: General Purpose I/O
C5 GPIO8/D8/MISO I/O GPIO8: General Purpose I/O
B5 GPIO7/D7/TX I/O GPIO7: General Purpose I/O
B4 GPIO6/D6/RX I/O GPIO6: General Purpose I/O
SCK: I2C EEPROM SCK
SDA: I2C EEPROM SDA
OTGID: Input for OTG ID pin. When used as OTGID, this pin should
be tied high through an external pull-up resistor. Assuming V
a 10K to 40K resistor should be used.
INT: HPI INT
IRQ0: Interrupt Request 0. See Register 0xC006. This pin is also one
of two possible GPIO wakeup sources.
nRD: HPI nRD
nWR: HPI nWR
nCS: HPI nCS
A1: HPI A1
A0: HPI A0
I/O GPIO15: General Purpose I/O
D15: D15 for HPI
CTS: HSS CTS
nSSI: SPI nSSI
D14: D14 for HPI
RTS: HSS RTS
D13: D13 for HPI
RXD: HSS RXD (Data is received on this pin)
D12: D12 for HPI
TXD: HSS TXD (Data is transmitted from this pin)
D11: D11 for HPI
MOSI: SPI MOSI
D10: D10 for HPI
SCK: SPI SCK
D9: D9 for HPI
nSSI: SPI nSSI
D8: D8 for HPI
MISO: SPI MISO
D7: D7 for HPI
TX: UART TX (Data is transmitted from this pin)
D6: D6 for HPI
RX: UART RX (Data is received on this pin)
CY7C67200
= 3.0V,
CC
Document #: 38-08014 Rev. *E Page 84 of 98
Table 9-1. Pin Descriptions (continued)
Pin Name Type Description
C4 GPIO5/D5 I/O GPIO5: General Purpose I/O
D5: D5 for HPI
B3 GPIO4/D4 I/O GPIO4: General Purpose I/O
D4: D4 for HPI
A3 GPIO3/D3 I/O GPIO3: General Purpose I/O
D3: D3 for HPI
C3 GPIO2/D2 I/O GPIO2: General Purpose I/O
D2: D2 for HPI
A2 GPIO1/D1 I/O GPIO1: General Purpose I/O
D1: D1 for HPI
B2 GPIO0/D0 I/O GPIO0: General Purpose I/O
D0: D0 for HPI
F2 DM1A I/O USB Port 1A D–
E3 DP1A I/O USB Port 1A D+
C2 DM2A I/O USB Port 2A D–
D3 DP2A I/O USB Port 2A D+
G3 XTALIN Input Crystal Input or Direct Clock Input
G2 XTALOUT Output Crystal output. Leave floating if direct clock source is used.
A5 nRESET Input Reset
A6 Reserved – Tie to Gnd for normal operation.
F1 BOOSTV
CC
Power Booster Power Input: 2.7V to 3.6V
E2 VSWITCH Analog Output Booster Switching Output
E1 BOOSTGND Ground Booster Ground
C1 OTGVBUS Analog I/O USB OTG Vbus
D1 CSWITCHA Analog Charge Pump Capacitor
D2 CSWITCHB Analog Charge Pump Capacitor
G1 AV
CC
Power USB Power
B1 AGND Ground USB Ground
H2, D6, A4 V
CC
Power Main Vcc
G6, B6, A1, H1 GND Ground Main Ground
CY7C67200
10.0 Absolute Maximum Ratings
This section lists the absolute maximum ratings. Stresses above those listed can cause permanent damage to the device.
Exposure to maximum rated conditions for extended periods can affect device operation and reliability.
Storage Temperature .................................. –40°C to +125°C
Ambient Temperature with Power Supplied .. –40°C to +85°C
Supply Voltage to Ground Potential................. 0.0V to +3.6V
DC Input Voltage to Any General Purpose Input Pin ..... 5.5V
DC Voltage Applied to XTALIN ............. –0.5V to V
CC
+ 0.5V
Static Discharge Voltage.......................................... > 2000V
Max Output Current, per I/O.. ....................................... 4 mA
11.0 Operating Conditions
TA (Ambient Temperature Under Bias) ......... –40°C to +85°C
Supply Voltage (V
Supply Voltage (BoostV
Ground Voltage ..................................................................0V
(Oscillator or Crystal Frequency) ....12 MHz ± 500 ppm
F
OSC
...................................................................Parallel Resonant
Note:
5. The on-chip voltage booster circuit boosts BoostV
Document #: 38-08014 Rev. *E Page 85 of 98
, AVCC) .......................... +3.0V to +3.6V
CC
[5]
)
......................... +2.7V to +3.6V
CC
to provide a nominal 3.3V VCC supply.
CC
CY7C67200
12.0 Crystal Requirements (XTALIN, XTALOUT)
Table 12-1. Crystal Requirements
Crystal Requirements, (XTALIN, XTALOUT) Min. Typical Max. Unit
Parallel Resonant Frequency 12 MHz
Frequency Stability –500 +500 PPM
Load Capacitance 20 33 pF
Driver Level 500 µW
Start-up Time 5ms
Mode of Vibration: Fundamental
13.0 DC Characteristics
Table 13-1. DC Characteristics
Parameter Description Conditions Min. Typ. Max. Unit
V
, AV
CC
BoosV
V
IH
V
IL
I
I
V
OH
V
OL
I
OH
I
OL
C
IN
V
HYS
[7, 8]
I
CC
[7, 8]
I
CCB
I
SLEEP
I
SLEEPB
Supply Voltage 3.0 3.3 3.6 V
CC
Supply Voltage 2.7 3.6 V
CC
Input HIGH Voltage 2.0 5.5 V
Input LOW Voltage 0.8 V
Input Leakage Current 0< VIN < V
Output Voltage HIGH I
Output LOW Voltage I
Output Current HIGH 4mA
Output Current LOW 4mA
Input Pin Capacitance Except D+/D– 10 pF
Hysteresis on nReset Pin 250 mV
Supply Current 2 transceivers powered 80 100 mA
Supply Current with Booster Enabled 2 transceivers powered 135 180 mA
Sleep Current USB Peripheral: includes 1.5K
Sleep Current with Booster Enabled USB Peripheral: includes 1.5K
[6]
CC
= 4 mA 2.4 V
OUT
= –4 mA 0.4 V
OUT
–10.0 +10.0 µA
D+/D– 15 pF
210 500 µA
internal pull-up
Without 1.5K internal pull-up 5 30 µA
210 500 µA
internal pull-up
Without 1.5K internal pull-up 5 30 µA
Table 13-2. DC Characteristics: Charge Pump
Parameter Description Conditions Min. Typ. Max. Unit
V
A_VBUS_OUT
T
A_VBUS_RISE
I
A_VBUS_OUT
C
DRD_VBUS
V
A_VBUS_LKG
V
DRD_DATA_LKG
Notes:
6. All tests were conducted with Charge pump off.
7. I
and I
CC
8. There is no appreciable difference in I
Regulated OTGVBUS Voltage 8 mA< I
V
Rise Time I
BUS
LOAD
< 10 mA 4.4 5.25 V
LOAD
= 10 mA 100 ms
Maximum Load Current 8 10 mA
OUTVBUS Bypass Capacitance 4.4V< V
< 5.25V 1.0 6.5 pF
BUS
OTGVBUS Leakage Voltage OTGVBUS not driven 200 mV
Dataline Leakage Voltage 342 mV
values are the same regardless of USB host or peripheral configuration.
CCB
CC
and I
values when only one transceiver is powered.
CCB
Document #: 38-08014 Rev. *E Page 86 of 98
CY7C67200
Table 13-2. DC Characteristics: Charge Pump (continued)
Parameter Description Conditions Min. Typ. Max. Unit
I
CHARGE
I
CHARGEB
I
B_DSCHG_IN
V
A_VBUS_VALID
V
A_SESS_VALID
V
B_SESS_VALID
V
A_SESS_END
E Efficiency When Loaded I
R
PD
R
A_BUS_IN
R
B_SRP_UP
R
B_SRP_DWN
Charge Pump Current Draw I
Charge Pump Current Draw with
Booster Active
B-Device (SRP Capable)
Discharge Current
= 8 mA 20 20 mA
LOAD
I
= 0 mA 0 1 mA
LOAD
I
= 8 mA 30 45 mA
LOAD
I
= 0 mA 0 5 mA
LOAD
0V< V
< 5.25V 8 mA
BUS
A-Device VBUS Valid 4.4 V
A-Device Session Valid 0.8 2.0 V
B-Device Session Valid 0.8 4.0 V
B-Device Session End 0.2 0.8 V
= 8 mA, VCC = 3.3V 75 %
LOAD
Data Line Pull-down 14.25 24.8 Ω
A-device V
to GND
B-device V
B-device V
Input Impedance
BUS
SRP Pull-up Pull-up voltage = 3.0V 281 Ω
BUS
SRP Pull-down 656 Ω
BUS
V
is not being driven 40 100 kΩ
BUS
13.1 USB Transceiver
USB 2.0-compatible in full- and low-speed modes.
14.0 AC Timing Characteristics
14.1 Reset Timing
t
RESET
nRESET
t
IOACT
nRD or nWRL or nW RH
Reset Timing
Parameter Description Min. Typ. Max. Unit
t
RESET
t
IOACT
Note:
9. Clock is 12 MHz nominal.
nRESET pulse width 16 clocks
nRESET HIGH to nRD or
200 µs
nWRx active
[9]
Document #: 38-08014 Rev. *E Page 87 of 98
14.2 Clock Timing
XTALIN
t
CLK
t
LOW
CY7C67200
HIGH
t
FALLt
t
RISE
Clock Timing
Parameter Description Min. Typ. Max. Unit
f
CLK
v
XINH
t
CLK
t
HIGH
t
LOW
t
RISE
t
FALL
[10]
Clock frequency 12.0 MHz
Clock input high
1.5 3.0 3.6 V
(XTALOUT left floating)
Clock period 83.17 83.33 83.5 ns
Clock high time 36 44 ns
Clock low time 36 44 ns
Clock rise time 5.0 ns
Clock fall time 5.0 ns
Duty Cycle 45 55 %
14.3 I2C EEPROM Timing
1. I2C EEPROM Bus Timing - Serial I/O
t
HIGH
t
R
t
SU.DAT t
t
F
t
SU.STO
SCL
t
SU.STA
t
HD.STA
t
LOW
t
HD.DAT
BUF
SDA IN
t
AA
t
DH
SDA OUT
Parameter Description Min. Typical Max. Unit
f
SCL
t
LOW
t
HIGH
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
Note:
10.
v
XINH
Clock Frequency 400 kHz
Clock Pulse Width Low 1300 ns
Clock Pulse Width High 600 ns
Clock Low to Data Out Valid 900 ns
Bus Idle Before New Transmission 1300 ns
Start Hold Time 600 ns
Start Set-up Time 600 ns
Data In Hold Time 0 ns
Data In Set-up Time 100 ns
Input Rise Time 300 ns
Input Fall Time 300 ns
Stop Set-up Time 600 ns
Data Out Hold Time 0 ns
is required to be 3.0 V to obtain an internal 50/50 duty cycle clock.
Document #: 38-08014 Rev. *E Page 88 of 98
14.4 HPI (Host Port Interface) Write Cycle Timing
t
CY7C67200
CYC
t
ASU
t
WP
t
AH
ADDR [1:0]
t
CSSU
t
CSH
nCS
nWR
nRD
Dout [15:0]
t
DSU
Parameter Description Min. Typical Max. Unit
t
ASU
t
AH
t
CSSU
t
CSH
t
DSU
t
WDH
t
WP
t
CYC
Note:
11. T = system clock period = 1/48 MHz.
Address set-up –1 ns
Address hold –1 ns
Chip select set-up –1 ns
Chip select hold –1 ns
Data set-up 6 ns
Write data hold 2 ns
Write pulse width 2 T
Write cycle time 6 T
t
WDH
[11]
[11]
Document #: 38-08014 Rev. *E Page 89 of 98
14.5 HPI (Host Port Interface) Read Cycle Timing
t
CY7C67200
CYC
t
ASU
t
RP
t
AH
ADDR [1:0]
t
CSSU
t
CSH
nCS
nWR
t
RDH
nRD
Din [15:0]
t
ACC
Parameter Description Min. Typ. Max. Unit
t
ASU
t
AH
t
CSSU
t
CSH
t
ACC
t
RDH
t
RP
t
CYC
Address set-up –1 ns
Address hold –1 ns
Chip select set-up –1 ns
Chip select hold –1 ns
Data access time, from HPI_nRD falling 1 T
Read data hold, relative to the earlier of HPI_nRD
rising or HPI_nCS rising
Read pulse width 2 T
Read cycle time 6 T
t
RDH
[11]
07ns
[11]
[11]
Document #: 38-08014 Rev. *E Page 90 of 98
14.6 HSS BYTE Mode Transmit
qt_clk
CPU_A[2:0]
CPUHSS_cs
CPU_wr
TxRdy flag
CY7C67200
CPU may start another BYTE
transmit right after TxRdy
goes high
BT
BT
HSS_TxD
Byte transmit
triggered by a
CPU write to the
HSS_TxData register
start bit bit 0
TxRdy low to start bit delay:
0 min, BT max when starting from IDEL.
For back to back transmit, new START Bit
begins immediately following previous STOP bit.
(BT = bit period)
bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
start of last data bit to TxRdy high:
0 min, 4 T max.
(T is qt_clk period)
stop bit start bit
programmable
1 or 2 stop bits.
1 stop bit shown.
qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU operations and HSS port operations.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.
14.7 HSS Block Mode Transmit
BT
HSS_TxD
t
GAP
BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.
The BLOCK mode STOP bit time, t
Transmit Gap Register 90xC074].
The default t
GAP
is 2 BT.
BT = bit time = 1/baud rate.
= (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS
GAP
14.8 HSS BYTE and BLOCK Mode Receive
BT +/- 5%
BT +/- 5%
HSS_RxD
start bit bit 0
bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit
10 BT +/- 5%
Receive data arrives asynchronously relative to the internal clock.
Incoming data bit rate may deviate from the programmed baud rate clock by as much as ±5% (with HSS_RATE value of 23 or
higher).
BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag.
BLOCK mode received bytes are written directly to the memory system.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.
Document #: 38-08014 Rev. *E Page 91 of 98
received byte added to
receive FIFO during the final data bit time
14.9 Hardware CTS/RTS Handshake
tCTSsetup
HSS_RTS
HSS_CTS
HSS_TxD
tCTShold
CY7C67200
tCTShold
tCTSsetup
Start of transmission not delayed by HSS_CTS
t
CTSset-up
t
CTShold
Start of transmission delayed until HSS_CTS goes high
: HSS_CTS set-up time before HSS_RTS = 1.5T min.
: HSS_CTS hold time after START bit = 0 ns min.
T = 1/48 MHz.
When RTS/CTS hardware handshake is enabled, transmission can be held off by deasserting HSS_CTS at least 1.5T before
HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit.
HSS_RTS is deasserted in the third data bit time.
An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit.
Document #: 38-08014 Rev. *E Page 92 of 98
CY7C67200
15.0 Register Summary
Table 15-1. Register Summary
R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High
R 0x0140 HPI Breakpoint Address... 0000 0000
R 0x0142 Interrupt Routing VBUS to HPI
W 1: 0x0144
R/W 0x02n0 Device n Endpoint n Control Reserved xxxx xxxx
R/W 0x02n2 Device n Endpoint n Address Address... xxxx xxxx
R.W 0x02n4 Device n Endpoint n Count Reserved Count... xxxx xxxx
R/W 0x02n6 Device n Endpoint n Status Reserved Overflow
R/W 0x02n8 Device n Endpoint n Count Re-
R 0xC000 CPU Flags Reserved... 0000 0000
R/W 0xC002 Bank Address... 0000 0001
R 0xC004 Hardware Revision Revision... xxxx xxxx
R/W 0xC006 GPIO Control Write Protect
R/W 0xC008 CPU Speed Reserved... 0000 0000
R/W 0xC00A Power Control Reserved Host/Device 2
R/W 0xC00C Watchdog Timer Reserved... 0000 0000
R/W 0xC00E Interrupt Enable Reserved OTG
R/W 0xC098 OTG Control Reserved VBUS
R/W 0: 0xC010
R/W 0xC014 Breakpoint Address... 0000 0000
R/W 1: 0xC018
R/W 0xC01E GPIO 0 Output Data GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 0000 0000
R 0xC020 GPIO 0 Input Data GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 0000 0000
R/W 0xC022 GPIO 0 Direction GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 0000 0000
R/W 0xC024 GPIO 1 Output Data GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000
SIEXmsg Data... xxxx xxxx
2: 0x0148
sult
Timer n Count... 1111 1111
1: 0xC012
Extended Page n Map Address...
2: 0xC01A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low
...Address 0000 0000
Enable
Resume2 to
HPI Enable
...Data xxxx xxxx
IN/OUT
Ignore Enable
...Address xxxx xxxx
...Count xxxx xxxx
Stal l
Flag
Result... xxxx xxxx
...Result xxxx xxxx
...Reserved Global Inter-
...Address Reserved 000x xxxx
...Revision xxxx xxxx
Enable
HSS
Enable
.Reserved CPU Speed 0000 000F
HPI
Wake E nable
...Reserved Timeout
HSS Interrupt
Enable
D+
Pull-down
Enable
...Count 1111 1111
...Address 0000 0000
...Address
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 0000 0000
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 0000 0000
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 0000 0000
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved 0000 0000
ID to HPI
Enable
Resume1 to
HPI Enable
Sequence
Select
NAK
Flag
UD Reserved SAS
Reserved SPI
Wake Enable
Reserved GPI
In Mailbox
Interrupt
Enable
DPull-down
Enable
SOF/EOP2 to
HPI Enable
Reserved Done2 to HPI
Stal l
Enable
Length
Exception Flag
Enable
Reserved Host/Device 1
Flag
Out Mailbox
Interrupt
Enable
Pull-up Enable
Reserved OTG Data Sta-
SOF/EOP2 to
CPU Enable
ISO
Enable
Set-up
Flag
rupt Enable
Reserved Interrupt 0
Wake Enab le
Wake Enab le
Period
Select
Interrupt
Enable
Reserved UART
Receive
Disable
SOF/EOP1 to
HPI Enable
Enable
NAK Interrupt
Enable
Flag
Sequence
Stat us
Negative
Flag
Enable
OTG
Wake E nable
Reserved Boost 3VOKSleep
SPI
Interrupt
Enable
Interrupt
Enable
Charge Pump
Enable
SOF/EOP1 to
CPU Enable
Done1 to HPI
Enable
Direction
Select
Underflow
Flag
Time out
Flag
Overflow
Flag
Mode
Select
Reserved HSS
Lock
Enable
Reserved Host/Device 2
GPIO
Interrupt
Enable
VBUS Discharge EnableD+Pull-up EnableD-Pull-up Enable
tus
Reset2 to HPI
Enable
Reset1 to HPI
Enable
Enable ARM
OUT
Exception FlagINException Flag
Error
Flag
Carry
Flag
Polarity Select
Wake Enabl e
Enable
WDT
Enable
Interrupt
Enable
Timer 1
Interrupt
Enable
ID
Stat us
HPI Swap 1
Enable
HPI Swap 0
Enable
Enable
ACK
Flag
Zero
Flag
Interrupt 0
Enable
SPI
Wake Enab le
Halt
Enable
Reset
Stro be
Host/Device 1
Interrupt
Enable
Time r 0
Interrupt
Enable
VBUS Valid
Flag
0001 0100
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
000x xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0001 0000
0000 0000
0000 0XXX
Document #: 38-08014 Rev. *E Page 93 of 98
CY7C67200
Table 15-1. Register Summary (continued)
R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High
R 0xC026 GPIO 1 Input Data GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000
R/W 0xC028 GPIO 1 Direction GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000
R/W 0xC03C USB Diagnostic Reserved Port 2A Diag-
R/W 0xC070 HSS Control HSS
R/W 0xC072 HSS Baud Rate Reserved HSS Baud... 0000 0000
R/W 0xC074 HSS Transmit Gap Reserved 0000 0000
R/W 0xC076 HSS Data Reserved xxxx xxxx
R/W 0xC078 HSS Receive Address Address... 0000 0000
R/W 0xC07A HSS Receive Counter Reserved Counter... 0000 0000
R/W 0xC07C HSS Transmit Address Address.. 0000 0000
R/W 0xC07E HSS Transmit Counter Reserved Counter... 0000 0000
R/W 0xC080
R/W 0xC082
R/W 0xC084
R 0xC086
W 0xC086
R 0xC088
W 0xC088
R/W 0xC08A
R/W 0xC08C Host 1 Interrupt Enable VBUS
R/W 0xC08C Device 1 Interrupt Enable VBUS
R/W 0xC08E
R/W 0xC090 Host 1 Status VBUS
Host n Control Reserved 0000 0000
0xC0A0
Host n Address Address... 0000 0000
0xC0A2
Host n Count Reserved Port Select Reserved Count... 0000 0000
0xC0A4
Host n PID Reserved Overflow
0xC0A6
Host n EP Status Reserved 0000 0000
0xC0A4
Host n Count Result Result... 0000 0000
0xC0A8
Host n Device Address Reserved... 0000 0000
0xC0A8
USB n Control Reserved Port A
0xC0AA
Device n Address Reserved... 0000 0000
0xC0AE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved 0000 0000
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved 0000 0000
nostic Enable
...Reserved Pull-down
Enable
Transmit Done
Interrupt Flag
...Baud 0001 0111
Transmit Gap Select 0000 1001
Data xxxx xxxx
...Address 0000 0000
...Counter 0000 0000
...Address 0000 0000
...Counter 0000 0000
Preamble
Enable
...Address 0000 0000
...Count 0000 0000
Stal l
Flag
PID Select Endpoint Select 0000 0000
...Result 0000 0000
...Reserved Address 0000 0000
Port A
Resistors
Enable
Interrupt
Enable
Reserved Port A
Interrupt
Enable
EP7
Interrupt
Enable
...Reserved Address 0000 0000
Interrupt
Flag
Reserved Port A
Enable
RTS
Polarity Select
Receive Done
Interrupt Flag
Sequence
Select
NAK
Flag
Reserved Port A
ID
Interrupt
Enable
Wake Interrupt
Enable
ID
Interrupt
Enable
EP6
Interrupt
Enable
ID
Interrupt
Flag
Wake Interrupt
Flag
Reserved Port 1A Diag-
LS Pull-up
Enable
CTS
Polarity Select
One
Stop Bit
Sync
Enable
Length
Exception Flag
D+ Status
Reserved SOF/EOP
Reserved Port A Con-
Reserved SOF/EOP
EP5
Interrupt
Enable
Reserved SOF/EOP
Reserved Port A Con-
nostic Enable
FS Pull-up
Enable
XOFF XOFF
Tran smit
Ready
ISO
Enable
Reserved Sequence
Port A
D- Status
Force D+/Stat e
nect Change
Interrupt
Enable
EP4
Interrupt
Enable
nect
Change
Interrupt Flag
Reserved... 0000 0000
Reserved Force Select 0000 0000
Enable
Packet
Mode Select
Reserved Arm
Flag
Stat us
Reserved LOA Mode
Reserved Done
Timeout Interrupt Enable
EP3
Interrupt
Enable
Reserved Port A
CTS
Enable
Receive
Overflow Flag
Underflow
Flag
Time out
Flag
Suspend
Enable
Reserved SOF/EOP
EP2
Interrupt
Enable
SE0
Status
Receive Interrupt Enable
Receive Packet Ready Flag
Reserved 0000 0000
Error
Flag
Select
Reserved Port A
Interrupt
Enable
Interrupt
Enable
EP1
Interrupt
Enable
Interrupt
Flag
Reserved Done
Done Interrupt
Enable
Receive
Ready Flag
Enable
ACK
Flag
Reserved xxxx 0000
SOF/EOP
Enable
Reserved 0000 0000
Interrupt
Enable
Reset
Interrupt
Enable
EP0
Interrupt
Enable
Reserved xxxx xxxx
Interrupt
Flag
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
Document #: 38-08014 Rev. *E Page 94 of 98
CY7C67200
Table 15-1. Register Summary (continued)
R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High
R/W 0xC090 Device 1 Status VBUS
R/W 0xC092
R 0xC092
R 0xC094
W 0xC094
R 0xC096
R/W 0xC0AC Host 2 Interrupt Enable Reserved SOF/EOP
R/W 0xC0AC Device 2 Interrupt Enable Reserved SOF/EOP
R/W 0xC0B0 Host 2 Status Reserved SOF/EOP
R/W 0xC0B0 Device 2 Status Reserved SOF/EOP
R/W 0xC0C6 HPI Mailbox Message... 0000 0000
R/W 0xC0C8 SPI Configuration 3Wire
R/W 0xC0CA SPI Control SCK
R/W 0xC0CC SPI Interrupt Enable Reserved... 0000 0000
R 0xC0CE SPI Status Reserved... 0000 0000
W 0xC0D0 SPI Interrupt Clear Reserved... 0000 0000
R/W 0xC0D2 SPI CRC Control CRC Mode CRC Enable CRC Clear Receive CRC One in CRC Zero in CRC Reserved... 0000 0000
R/W 0xC0D4 SPI CRC Value CRC.. 1111 1111
R/W 0xC0D6 SPI Data Port t Reserved xxxx xxxx
R/W 0xC0D8 SPI Transmit Address Address... 0000 0000
R/W 0xC0DA SPI Transmit Count Reserved Count... 0000 0000
Host n SOF/EOP Count Reserved Count... 0010 1110
0xC0B2
Device n Frame Number SOF/EOP
0xC0B2
Host n SOF/EOP Counter Reserved Counter...
0xC0B4
Device n SOF/EOP Count Reserved Count...
0xC0B4
Host n Frame Reserved Frame... 0000 0000
0xC0B6
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low
Interrupt
Flag
EP7
Interrupt
Flag
...Count 1110 0000
Timeout
Flag
...Frame 0000 0000
...Counter
...Count
...Frame 0000 0000
Reserved Port A
EP7
Interrupt
Enable
Reserved Port A
EP7
Interrupt Flag
...Message 0000 0000
Enable
Master
Active Enable
Stro be
Trans mit
Empty
...Reserved Receive Inter-
FIFO Error
Flag
...Reserved Transmit
...Reserved 0000 0000
...CRC 1111 1111
Data xxxx xxxx
...Address 0000 0000
...Count 0000 0000
ID
Interrupt
Flag
EP6
Interrupt
Flag
SOF/EOP
Timeout
Interrupt Count
Wake Interrupt
Enable
EP6
Interrupt
Enable
Wake Interrupt
Flag
EP6
Interrupt Flag
Phase
Select
Master
Enable
FIFO
Init
Receive
Full
Reserved Receive
Reserved SOF/EOP
EP5
Interrupt
Flag
Reserved Port A Con-
EP5
Interrupt
Enable
Reserved Port A Con-
EP5
Interrupt Flag
SCK
Polarity Select
SS
Enable
Byte
Mode
Transmit Bit Length Receive Bit Length 1000 0000
EP4
Interrupt
Flag
nect Change
Interrupt
Enable
EP4
Interrupt
Enable
nect Change
Interrupt Flag
EP4
Interrupt Flag
Scale Select Reserved 1000 0000
SS Delay Select 0001 1111
FullDuplex SS
EP3
Interrupt
Flag
Reserved Frame... 0000 0000
Reserved Done
Timeout Interrupt Enable
EP3
Interrupt
Enable
Reserved Port A
Timeout
Interrupt
Enable
EP3
Interrupt Flag
Manual
EP2
Interrupt
Flag
Wake
Interrupt
Enable
EP2
Interrupt
Enable
SE0
Status
Wake
Interrupt
Flag
EP2
Interrupt Flag
Read
Enable
rupt
Enable
Interrupt Flag
Interrupt
Flag
EP1
Interrupt
Flag
Interrupt
Enable
SOF/EOP
Interrupt
Enable
EP1
Interrupt
Enable
Interrupt Flag
Reserved Done
SOF/EOP
Interrupt
Flag
EP1
Interrupt Flag
Transmit
Ready
Transmit
Interrupt
Enable
Transmit
Interrupt Flag
Interrupt Clear
Reset
Interrupt
Flag
EP0
Interrupt
Flag
Reserved 0000 0000
Interrupt
Enable
Reset
Interrupt
Enable
EP0
Interrupt
Enable
Reserved xxxx xxxx
Interrupt
Flag
Reset
Interrupt
Flag
EP0
Interrupt Flag
Receive
Data Ready
Transfer
Interrupt
Enable
Transfer
Interrupt Flag
Transmit
Interrupt Clear
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0001
0000 0000
0000 0000
0000 0000
Document #: 38-08014 Rev. *E Page 95 of 98
CY7C67200
Table 15-1. Register Summary (continued)
R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High
R/W 0xC0DC SPI Receive Address Address... 0000 0000
R/W 0xC0DE SPI Receive Count Reserved Count... 0000 0000
R/W 0xC0E0 UART Control Reserved... 0000 0000
R 0xC0E2 UART Status Reserved... 0000 0000
R/W 0xC0E4 UART Data Reserved 0000 0000
R HPI Status Port VBUS
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low
...Address 0000 0000
...Count 0000 0000
...Reserved Scale
...Reserved Receive
Data 0000 0000
Flag
Resume2
Flag
ID
Flag
Resume1
Flag
Reserved SOF/EOP2
SIE2msg SIE1msg Done2
Select
Flag
Baud
Select
Reserved SOF/EOP1
Flag
Flag
Done1
Flag
Full
Reset2
Flag
Reset1
Flag
UART
Enable
Transmit
Full
Mailbox In
Flag
Mailbox Out
Flag
0000 0111
0000 0000
Document #: 38-08014 Rev. *E Page 96 of 98
CY7C67200
16.0 Ordering Information
Table 16-1. Ordering Information
Ordering Code Package Type Temperature Range
CY7C67200-48BAI 48 FBGA –40 to 85°C
CY3663 Development Kit
17.0 Package Diagrams
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips
2
I
C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips. EZ-OTG is a trademark of Cypress Semiconductor. All product and company names mentioned in this
document are trademarks of their respective holders.
Document #: 38-08014 Rev. *E Page 97 of 98
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other righ ts. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C67200
Document History Page
Document Title: CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller
Document Number: 38-08014
REV. ECN NO.
** 111872 03/22/02 MUL New Data Sheet
*A 116988 08/23/02 MUL Preliminary Data Sheet
*B 124954 04/10/03 MUL Added Memory Map Section and Ordering Information Section
*C 126211 05/23/03 MUL Added Interface Description Section and Power Savings and Reset Section
*D 127334 05/29/03 KKV Corrected font to enable correct symbol display
*E 129394 10/07/03 MUL Final Data Sheet
Issue
Date
Orig. of
Change Description of Change
Moved Functional Register Map Tables into Register section
General Clean-up
Changed from “Preliminary“ to “Preliminary Confidential“
Added Char Data
General Clean-up
Removed DRAM, MDMA, and EPP
Added “Programmable” to the title page
Changed Memory Map Section
Added USB OTG Logo
General Clean-up
Document #: 38-08014 Rev. *E Page 98 of 98
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