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CY7C66013C
User Manual
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CYPRESS CY7C66013C, CY7C66113C User Manual

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CY7C66013
Full-Speed USB (12 Mbps) Peripher
Controller with Integrated Hu

Full-Spee d U SB (12 Mbps) Peripheral Controller with Integrated Hub

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08024 Rev. *B Revised January 2, 2006
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CY7C66013

TABLE OF CONTENTS

1.0 FEATURES .............. ........................................................................................................................6
2.0 FUNCTIONAL OVERVIEW .............................................................................................................7
2.1 GPIO .............. ............................................................................................................................7
2.2 DAC ......... ...................................................................................................................................7
2.3 Clock ..........................................................................................................................................7
2.4 Memory .............. ........................................................................................................................7
2.5 Power-on Reset, Watchdog, and Free-running Timer ..... ..........................................................7
2.6 I2C and HAPI Interface ..............................................................................................................7
2.7 Timer ... .......................................................................................................................................7
2.8 Interrupts ....................................................................................................................................8
2.9 USB ............................................................................................................................................8
3.0 PIN CONFIGURATIONS ....... ........................................................................................................10
4.0 PRODUCT SUMMARY TABLES ..................................................................................................14
4.1 Pin Assignments ......................................................................................................................14
4.2 I/O Register Summary ..............................................................................................................14
4.3 Instruction Set Summary ..........................................................................................................16
5.0 PROGRAMMING MODEL .............................................................................................................17
5.1 14-bit Program Counter (PC) .............. .....................................................................................17
5.1.1 Program Memory Or gan i za tion .......................................................................................... ..........18
5.2 8-bit Accumulator (A) ...............................................................................................................19
5.3 8-bit Temporary Register (X) ....................................................................................................19
5.4 8-bit Program Stack Pointer (PSP) ..... .....................................................................................19
5.4.1 Data Memory Organization ............................................................................................. .. .............19
5.5 8-bit Data Stack Pointer (DSP) ................................................................................................19
5.6 Address Modes ........................................................................................................................20
5.6.1 Data (Immediate ) ............................................................................................................................20
5.6.2 Direct ...... ........................................................................................................................................20
5.6.3 Indexed ..........................................................................................................................................20
6.0 CLOCKING ....................................................................................................................................20
7.0 RESET .......... .................................................................................................................................21
7.1 Power-on Reset .......................................................................................................................21
7.2 Watchdog Reset .......................................................................................................................21
8.0 SUSPEND MODE ..........................................................................................................................22
9.0 GENERAL-PURPOSE I/O (GPIO) PORTS ...................................................................................22
9.1 GPIO Configuration Port ..........................................................................................................23
9.2 GPIO Interrupt Enable Ports ....................................................................................................24
10.0 DAC PORT ..................................................................................................................................25
10.1 DAC Isink Registers ...............................................................................................................26
10.2 DAC Port Interrupts ................................................................................................................26
11.0 12-BIT FREE-RUNNING TIMER .................................................................................................27
2
12.0 I
13.0 I
C AND HAPI CONFIGURATION REGISTER ...........................................................................27
2
C-COMPATIBLE CONTROLLER .............................................................................................28
14.0 HARDWARE ASSISTED PARALLEL INTERFACE (HAPI) ....................................................... 30
15.0 PROCESSOR STATUS AND CONTROL REGISTER ................................................................31
Document #: 38-08024 Rev. *B Page 2 of 61
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16.0 INTERRUPTS ..............................................................................................................................31
16.1 Interrupt Vectors .....................................................................................................................33
16.2 Interrupt Latency ....................................................................................................................34
16.3 USB Bus Reset Interrupt ........................................................................................................34
16.4 Timer Interrupt ........................................................................................................................ 34
16.5 USB Endpoint Interrupts ........................................................................................................34
16.6 USB Hub Interrupt ..................................................................................................................35
16.7 DAC Interrupt .........................................................................................................................35
16.8 GPIO/HAPI Interrupt ..............................................................................................................35
16.9 I
17.0 USB OVERVIEW .........................................................................................................................36
17.1 USB Serial Interface Engine ..................................................................................................36
17.2 USB Enumeration ..................................................................................................................36
18.0 USB HUB .....................................................................................................................................37
18.1 Connecting/Disconnecting a USB Device ..............................................................................37
18.2 Enabling/Disabling a USB Device ..........................................................................................38
18.3 Hub Downstream Ports Status and Control ...........................................................................39
18.4 Downstream Port Suspend and Resume ...............................................................................40
18.5 USB Upstream Port Status and Control .................................................................................41
19.0 USB SIE OPERATION ................................................................................................................42
2
C Interrupt ............................................................................................................................36
19.1 USB Device Addresses ..........................................................................................................42
19.2 USB Device Endpoints ...........................................................................................................42
19.3 USB Control Endpoint Mode Registers ..................................................................................43
19.4 USB Non-Control Endpoint Mode Registers ..........................................................................44
19.5 USB Endpoint Counter Registers ...........................................................................................44
19.6 Endpoint Mode/Count Registers Update and Locking Mechanism ........................................44
20.0 USB MODE TABLES ..................................................................................................................47
21.0 REGISTER SUMMARY ...............................................................................................................51
22.0 SAMPLE SCHEMATIC ................................................................................................................53
23.0 ABSOLUTE MAXIMUM RATINGS ..............................................................................................54
24.0 ELECTRICAL CHARACTERISTICS ...........................................................................................54
25.0 SWITCHING CHARACTERISTICS
26.0 ORDERING INFORMATION .......................................................................................................57
27.0 PACKAGE DIAGRAMS ...............................................................................................................58
28.0 QUAD FLAT PACKAGE NO LEADS (QFN) PACKAGE DESIGN NOTES ................................59
.............................................................................................55
Document #: 38-08024 Rev. *B Page 3 of 61
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CY7C66013

LIST OF FIGURES

Figure 3-1. CY7C66113C 56-pin QFN Pin Assignment .......................................................................11
Figure 3-2. CY7C66113C DIE .............................................................................................................. 12
Figure 5-1. Program Memory Space with Interrupt Vector Table .........................................................18
Figure 6-1. Clock Oscillator On-Chip Circuit ........................................................................................20
Figure 7-1. Watchdog Reset ................................................................................................................ 21
Figure 9-1. Block Diagram of a GPIO Pin ............................................................................................22
Figure 9-2. Port 0 Data ........................................................................................................................23
Figure 9-3. Port1 Data .........................................................................................................................23
Figure 9-4. Port 2 Data ........................................................................................................................23
Figure 9-5. Port 3 Data ........................................................................................................................23
Figure 9-6. GPIO Configuration Register .............................................................................................23
Figure 9-7. Port 0 Interrupt Enable .......................................................................................................24
Figure 9-8. Port 1 Interrupt Enable .......................................................................................................25
Figure 9-9. Port 2 Interrupt Enable .......................................................................................................25
Figure 9-10. Port 3 Interrupt Enable .....................................................................................................25
Figure 10-1. Block Diagram of a DAC Pin ............................................................................................25
Figure 10-2. DAC Port Data .................................................................................................................26
Figure 10-3. DAC Sink Register ...........................................................................................................26
Figure 10-4. DAC Port Interrupt Enable ...............................................................................................26
Figure 10-5. DAC Port Interrupt Polarity ..............................................................................................26
Figure 11-3. Timer Block Diagram .......................................................................................................27
Figure 11-1. Timer LSB Register .........................................................................................................27
Figure 11-2. Timer MSB Register ........................................................................................................27
Figure 12-1. HAPI/I Figure 13-1. I Figure 13-2. I
Figure 15-1. Processor Status and Control Register ...........................................................................31
Figure 16-1. Global Interrupt Enable Register .....................................................................................32
Figure 16-2. USB Endpoint Interrupt Enable Register .........................................................................32
Figure 16-3. Interrupt Controller Function Diagram .............................................................................33
Figure 16-4. GPIO Interrupt Structure ..................................................................................................35
Figure 18-1. Hub Ports Connect Status ...............................................................................................38
Figure 18-2. Hub Ports Speed .............................................................................................................38
Figure 18-3. Hub Ports Enable Register ..............................................................................................38
Figure 18-4. Hub Downstream Ports Control Register .........................................................................39
Figure 18-5. Hub Ports Force Low Register .........................................................................................39
Figure 18-6. Hub Ports SE0 Status Register .......................................................................................39
Figure 18-7. Hub Ports Data Register ..................................................................................................40
Figure 18-8. Hub Ports Suspend Register ........................................................................................... 40
Figure 18-9. Hub Ports Resume Status Register .................................................................................40
Figure 18-10. USB Status and Control Register ..................................................................................41
Figure 19-1. USB Device Address Registers .......................................................................................42
Figure 19-2. USB Endpoint 0 Mode Registers .....................................................................................43
Figure 19-3. USB Non-Control Endpoint Mode Registers ....................................................................44
Figure 19-4. USB Endpoint Counter Registers ....................................................................................44
Figure 19-5. Token/Data Packet Flow Diagram ...................................................................................46
Figure 22-1. Sample Schematic ...........................................................................................................53
Figure 25-1. Clock Timing ....................................................................................................................56
Figure 25-2. USB Data Signal Timing ..................................................................................................56
Figure 25-3. HAPI Read by External Interface from USB Microcontroller ............................................56
Figure 25-4. HAPI Write by External Device to USB Microcontroller ...................................................57
Figure 28-1. Cross-section of the Area Underneath the QFN Package ...............................................60
Figure 28-2. Plot of the Solder Mask (White Area) ..............................................................................60
2 2 2
C Configuration Register ......................................................................................27
C Data Register .............................................................................................................28
C Status and Control Register .......................................................................................28
Document #: 38-08024 Rev. *B Page 4 of 61
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CY7C66013

LIST OF TABLES

Table 3-1. Pad Coordinates in microns (0,0) to bond pad centers .......................................................13
Table 4-1. Pin Assignments .................................................................................................................14
Table 4-2. I/O Register Summary ........................................................................................................14
Table 4-3. Instruction Set Summary .....................................................................................................16
Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity .............................................24
Table 12-1. HAPI Port Configuration .......................................................................................... ..........28
Table 12-2. I Table 13-1. I
Table 14-1. Port 2 Pin and HAPI Configuration Bit Definitions ............................................................30
Table 16-1. Interrupt Vector Assignments .......... ..................................................................................34
Table 18-1. Control Bit Definition for Downstream Ports ................. ............................. .... ...................39
Table 18-2. Control Bit Definition for Upstream Port ............................................................................41
Table 19-1. Memory Allocation for Endpoints ......................................................................................42
Table 20-1. USB Register Mode Encoding ..........................................................................................47
Table 20-2. Decode T able for Table 20-3: “Details of Modes for Differing Traffic Conditio ns” ........... .48
Table 20-3. Details of Modes for Differing Traffic Conditions
2
C Port Configuration .................. .....................................................................................28
2
C Status and Control Register Bit Definitions .................................................................29
...............................................................49
Document #: 38-08024 Rev. *B Page 5 of 61
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CY7C66013

1.0 Features

• Full-speed USB peripheral microcontroller with an integrated USB hub
—Well-suited for USB compound devices such as a keyboard hub functi on
• 8-bit USB optimized microcontroller
—Harvard architecture —6-MHz external clock source —12-MHz internal CPU clock —48-MHz internal Hub clock
• Internal memory
—256 bytes of RAM —8 KB of PROM
2
• Integrated Master/Slave I
• Hardware-assisted Parallel Interface (HAPI) for data transfer to external devices
•I/O ports —Three GPIO ports (Port 0 to 2) capable of sinking 8 mA per pin (typical) —An additional GPIO port (Port 3) capable of sinking 12 mA per pin (typical) for high current requirements: LEDs —Higher current drive achievable by connectin g multiple GPIO pins together to drive a common output —Each GPIO port can be configured as inputs with inter nal pull-ups or open drain output s or traditional CMOS output s —A Digital-to-Analog Conversion (DAC) port with programmable current sink output s is available on the CY7C661 13C
device
—Maskable interrupts on all I/O pins
• 12-bit free-runni ng ti me r wit h one microsecond clock ticks
• Watchdog T imer (WDT)
• Internal Power-on Reset (POR)
• USB Specification compliance
—Conforms to USB Specification, Version 1.1 —Conforms to USB HID Specification, Version 1.1 —Supports one or two device addresses with up to five user-configured endpoints
• Up to two 8-byte control endpoi nts
• Up to four 8-byte data endpoints
• Up to two 32-byte data end points
—Integrated USB transceivers —Supports four downstream USB ports —GPIO pins can provide individual power control outputs for each downstream USB port —GPIO pins can provide indivi dual port over current inputs for each downstream USB port
• Improved output drive rs to reduce electromagnetic inte rference (EMI)
• Operating voltage from 4.0V–5.5V DC
• Operating temperature from 0°–70°C
• CY7C66013C available in 48-pin SSOP (-PVC) packages
• CY7C66113C available in 56-pin QFN or 56-pin SSOP (-PVC) packages
• Industry-standard programmer support
C-compatible controller (100 kHz) enabled through General-purpose I/O (GPIO) pins
Document #: 38-08024 Rev. *B Page 6 of 61
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CY7C66013

2.0 Functional Overview

The CY7C66013C and CY7C66113C are compound devices with a full-speed USB microcontroller in combination with a USB hub. Each device is well-suited for combination peripheral functions with hubs, such as a keyboard hub function. The eight-bit one-time-programm able microcontroller with a 12-Mbps USB Hub supports as many as four downstream ports.
2.1 GPIO
The CY7C66013C feat ures 29 G PIO pins t o support USB and other applic ations. The I /O pins are grouped into fo ur port s (P0[7:0 ], P1[7:0], P2[7:0], P3[4:0]) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. Ports 0 to 2 are rated at 8 mA per pin (typical) sink current. Port 3 pins are rated at 12 mA per pin (typical) sink current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive curre nt capacity. Additional ly, each I/O pin can be used to generate a GPIO interrupt to the m icrocontroller. All of the GPIO interrupts all share the same “GPIO” interrupt vector.
The CY7C66113C has 31 GPIO pins (P0[7:0], P1[7:0], P2[7:0], P3[6:0]).
2.2 DAC
The CY7C66113C has an additional port P4[7:0] that features an additional eight programmable sink current I/O pins (DAC). Every DAC pin includes an integrated 14-kΩ pull-up resistor. When a ‘1’ is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven HIGH by the internal pull-up resistor. When a ‘0’ is written to a DAC I/O pin, the internal pull-up is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin can be used as an input with an internal pull- up by wri ting a ‘1’ to the pin.
The sink current for each DAC I/O pin can be individually programmed to one of sixteen values using dedicated Isink registers. DAC bits DAC[1:0] can be used as high current outputs with a programmable sink current range of 3.2 to 16 mA (typical). DAC bits DAC[7:2] have a programmable current sink range of 0.2 to 1.0 mA (typical). Multiple DAC pins can be connected together to drive a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the microcontroller. Also, the int errupt polarity for each DAC I/O pin is indi vidually programmable.
2.3 Clock
The microcontroller uses an external 6-MHz crystal and an internal oscillator to provide a reference to an internal PLL-based clock generator. This technology all ows the customer application to use an inexpensive 6-MH z fundamental crystal that r educes the clock-related noise emissions (EMI). A PLL clock generator provides the 6-, 12-, and 48-MHz clock signals for distribution within the microcont roller.
2.4 Memory
The CY7C66013C and CY7C66113C have 8 KB of PROM.
2.5 Power-on Reset, Watchdog, and Free-running Timer
These parts include POR logic, a WDT, and a 12-bit free-running timer. The POR logic detects when power is applied to the device, rese ts the l ogic to a known sta te, and begins exec uting in structions at PROM addre ss 0x0000 . The WDT is us ed to en sure that the microco ntrolle r recover s aft er a period of inact ivit y. The firmware may become inactive for a vari ety of reas ons, inc luding errors in the code or a hardwar e fai lure such as waiting for an interrupt that never occurs.
2.6 I2C and HAPI Interface
The microcontroller can communicate with external electronics through the GPIO pins. An I2C-compatible interface accommo­dates a 100-kHz serial link with an external device. There is also a Hardware-assisted Parallel Interface (HAPI) which can be used to transfer data to an external device.
2.7 Timer
The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-µs and 1.024-ms. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of the timer are lat ched i nto an i nternal r egist er when th e fir mware reads the l ower ei ght bi t s. A read f rom the upper four bit s actually reads data fr om the i nternal regi ster, instead of the timer. This feature eliminates t he need f or fir mware to try to compens ate if the upper four bits increment immediately after the lower eight bits are read.
Document #: 38-08024 Rev. *B Page 7 of 61
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2.8 Interrupts
The microcontrol ler support s eleven mask abl e inter rupt s in the vec tored i nterr upt contr oll er . Inter rupt sour ces incl ude the 128 -µs (bit 6) and 1.024-ms (bit 9) outputs from the fr ee-running timer, five USB end points, the USB hub, the DAC port, the GPIO ports, and the I to HIGH ‘1.’ The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller sends a packet to the USB host. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC inte rr upt. The GPIO ports also have a level of mask ing to select which GPIO inputs can cause a GPI O interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be rising edge (‘0’ to ‘1’ ) or falling edge (‘1’ to ‘0’).
2.9 USB
The CY7C66013C and CY7C66113C include an integrated USB Serial Interface Engine (SIE) that supports the integrated peripherals and the hub cont roller func tion. The har dwar e support s up to t wo USB devi ce address es with one device addr ess for the hub (two endpo int s) and a devi ce address f or a compound devi ce (thr ee endpo int s). The SI E allows the USB host t o commu­nicate with the hub and func tions int egrate d into t he microco ntr olle r . The p art incl udes a 1:4 hub r epeater with one up st ream port and four downstream ports. The USB Hub allows power-management control of the downstream ports by using GPIO pins assigned by the user firmware. The user has the option of ganging the downstream ports together with a single pair of power-management pins, or providing power management for each port with four pairs of power- m anagement pins.
2
C-compatible master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles from LOW ‘0’
Document #: 38-08024 Rev. *B Page 8 of 61
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Logic Block Diagram
CY7C66013
External 6-MHz crystal
PLL
48 MHz
Clock
Divider
6 MHz
12 MHz
12-MHz
8-bit
CPU
PROM
8 KB
RAM
256 byte
12-bit Timer
8-bit Bus
USB
SIE
Interrupt
Controller
GPIO
PORT 0
P0[0]
P0[7]
USB
Transceiver
Repeater
Power management under firmware
D+[0]
Upstream USB Port
D–[0]
USB
Transceiver
USB
Transceiver
USB
Transceiver
USB
Transceiver
Downstream USB Ports
control using GPIO pins
D+[1] D–[1]
D+[2] D–[2]
D+[3] D–[3]
D+[4] D–[4]
Watchdog
Timer
Power-On
Reset
GPIO
PORT 1
GPIO/ HAPI
PORT 2
GPIO
PORT 3
GPIO
PORT 3
DAC
PORT
I2C Interface
*I2C-compatible interface enabled by firmware through P2[1:0] or P1[1:0]
P1[0]
P1[7]
P2[0:1,7] P2[2]; Latch_Empty
P2[3]; Data_Ready P2[4]; STB P2[5]; OE P2[6]; CS
P3[0]
P3[4]
P3[5] P3[6]
DAC[0]
DAC[7]
CY7C66113C only
SCLK SDATA
High Current Outputs
Additional High Current Outputs
Document #: 38-08024 Rev. *B Page 9 of 61
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3.0 Pin Configurations

CY7C66013
XTALOUT
XTALIN
V
REF
P1[3] P1[5] P1[7]
P3[1] D+[0] D–[0] P3[3]
GND D+[1] D–[1] P2[1] D+[2] D–[2] P2[3] P2[5] P2[7]
GND P0[7] P0[5] P0[3] P0[1]
CY7C66013C
48-pin SSOP
1
48
2
47
3
46
4
45
5
44 43
6 7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30 29
20 21
28
22
27
23
26
24 25
TOP VIEW
V
CC
P1[1] P1[0] P1[2] P1[4] P1[6] P3[0] D–[3]
D+[3] P3[2] GND P3[4] D–[4] D+[4] P2[0] P2[2] GND P2[4] P2[6] V
PP
P0[0] P0[2] P0[4] P0[6]
XTALOUT
XTALIN
V
REF
P1[3] P1[5] P1[7]
P3[1] D+[0] D–[0] P3[3]
GND P3[5] D+[1] D–[1] P2[1] D+[2] D–[2] P2[3] P2[5] P2[7]
DAC[7]
P0[7] P0[5] P0[3] P0[1]
DAC[5] DAC[3] DAC[1]
CY7C66113C 56-pin SSOP
1
56
2
55 54
3 4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44 43
14 15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
V
CC
P1[1] P1[0] P1[2] P1[4] P1[6] P3[0] D–[3]
D+[3] P3[2] P3[4] D–[4] D+[4] P3[6] P2[0] P2[2] GND P2[4] P2[6] DAC[0] V
PP
P0[0] P0[2] P0[4]
P0[6] DAC[2] DAC[4] DAC[6]
Document #: 38-08024 Rev. *B Page 10 of 61
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D+[0]
56
P3[1]
55
P1[7]
54
P1[5]
53
P1[3]
52
Vref
51
CY7C66013
XTALOUT
XTALIN
P1[6]
P1[4]
P1[2]
P1[0]
P1[1]
Vcc
43
44
45
46
47
48
49
50
D-[0]
P3[3]
GND
P3[5] D+[1] D–[1]
P2[1] D+[2] D–[2]
P2[3]
P2[5]
P2[7]
DAC[7]
P0[7]
10 11 12 13 14
1 2 3 4 5 6 7 8 9
18
17
16
15
DAC[5]
P0[1]
P0[3]
P0[5]
CY7C66113C
56-pin QFN
21
20
19
DAC[6]
DAC[1]
DAC[3]
22
DAC[4]
23
DAC[2]
24
P0[6]
25
P0[4]
26
P0[2]
27
P0[0]
28
Vpp
42 41 40 39 38 37 36 35 34 33 32 31 30 29
P3[0] D–[3] D+[3] P3[2] P3[4] D–[4] D+[4] P3[6] P2[0] P2[2] GND P2[4] P2[6] DAC[0]
Figure 3-1. CY7C66113C 56-pin QFN Pin Assignment
Document #: 38-08024 Rev. *B Page 1 1 of 61
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(
4)
CY7C66013
(3398, 419
Cypress Logo
Pin 15
Pin 1
Pin 60
Pin 30 Pin 45
0,0)
Document #: 38-08024 Rev. *B Page 12 of 61
DIE ST EP : 3398 x 4194 m icrons Die Size: 3322 x 4129 m icrons Die Thickness: 14 mils = 355.6 microns Pad Size: 80 x 80 microns
Figure 3-2. CY7C66113C DIE
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CY7C66013

Table 3-1. Pad Coordinates in microns (0,0) to bond pad centers

Pad # Pin Name X Y Pad # Pin Name X Y
1 XtalOut 1274.2 3588.8 37 DAC6 2000.6 210.6 2 XtalIn 1132.8 3588.8 38 DAC4 2103.6 210.6 3 Vref 889.85 3588.8 39 DAC2 2206.6 210.6 4 Port11b 684.65 3588.8 40 Port06 2308.4 210.6 5 Port13 581.65 3588.8 41 Port04 2411.4 210.6 6 Port15 478.65 3588.8 42 Port02 2514.4 210.6 7 Vss 375.65 3588.8 43 Port00 2617.4 210.6 8 Port17 0 3408.35 44 Vpp 2992.4 25.4
9 Port31 0 3162.05 45 DAC0 2992.4 151.75 10 Du+ 0 3060.55 46 Port26 2992.4 306.15 11 Du– 0 2752.4 47 DD+6 2992.4 407.65 12 Port33 0 2650.95 48 DD–6 2992.4 715.75 13 Vss 0 2474.6 49 Port24 2992.4 817.25 14 Port35 0 2368.45 50 Vss 2992.4 923.4 15 DD+1 0 2266.95 51 Port22 2992.4 1086.75 16 DD–1 0 1958.85 52 DD+5 2992.4 1188.25 17 Port37 0 1857.35 53 DD–5 2992.4 1496.35 18 Vref 0 1680.4 54 Port20 2992.4 1597.85 19 Port21 0 1567.4 55 Vref 2992.4 1710.8 20 DD+2 0 1465.95 56 Port36 2992.4 1874.75 21 DD–2 0 1157.85 57 DD+4 2992.4 1976.25 22 Port23 0 1056.35 58 DD–4 2992.4 2284.35 23 Vss 0 880 59 Port34 2992.4 2385.85 24 Port25 0 773.85 60 Vss 2992.4 2492 25 DD+7 0 672.35 61 Port32 2992.4 2655.35 26 DD–7 0 364.25 62 DD+3 2992.4 2756.85 27 Port27 0 262.75 63 DD–3 2992.4 3064.95 28 DAC7 0 100.75 64 Port30 2992.4 3166.45 29 Vss 0 0 65 Port16 2992.4 3412.25 30 Port07 375.2 210.6 66 Port14 2634.2 3588.8 31 Port05 478.2 210.6 67 Port12 2531.2 3588.8 32 Port03 581.2 210.6 68 Port10 2428.2 3588.8 33 Port01 684.2 210.6 69 Port11 2325.2 3588.8 34 DAC5 788.4 210.6 70 VCC 2221.75 3588.8 35 DAC3 891.4 210.6 71 PadOpt 2121.75 3588.8 36 DAC1 994.4 210.6 72
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4.0 Product Summary Tables

4.1 Pin Assignments
Table 4-1. Pin Assignments
Name I/O 48-Pin 56-Pin QFN 5 6-Pi n SSO P Description
D+[0], D–[0] I/O 8, 9 56, 1 8, 9 Upstream port, USB differential data. D+[1], D–[1] I/O 12, 13 5, 6 13, 14 Downstream port 1, USB differential data. D+[2], D–[2] I/O 15, 16 8, 9 16, 17 Downstream port 2, USB differential data. D+[3], D–[3] I/O 40, 41 40, 41 48, 49 Downstream port 3, USB differential data. D+[4], D–[4] I/O 35, 36 36, 37 44, 45 Downstream port 4, USB differential data. P0[7:0] I/O 21, 25, 22, 26,
23, 27, 24, 28
P1[7:0] I/O 6, 43, 5, 44, 4,
P2[7:0] I/O 19, 30, 18, 31,
P3[6:0] I/O 37, 10, 39, 7, 4255, 2, 4, 35,
DAC[7:0] I/O n/a 1 3, 18, 19, 20,
XTAL
IN
XTAL
OUT
V
PP
V
CC
GND 1 1, 20, 32, 38 3, 32 11, 40 Ground. V
REF
45, 47, 46
17, 33, 14, 34
IN 2 50 2 6-MHz crystal or external clock input.
OUT 1 49 1 6-MHz crystal out.
29 28 36 Programming voltage supply, tie to ground during
48 48 56 Voltage supply.
IN 3 51 3 External 3.3V supply voltage for the differential data
14, 15, 16, 17, 24, 25, 26, 27
52, 53, 54, 43, 44, 45, 46, 47
7, 10, 11, 12, 30, 31, 33, 34
38, 39, 42,
21, 22, 23, 29
22, 32, 23, 33, 24, 34, 25, 35
6, 51, 5, 52, 4, 53, 55, 54
20, 38, 19, 39, 18, 41, 15, 42
43, 12, 46, 10, 47, 7, 50
21, 29, 26, 30, 27, 31, 28, 37
GPIO Port 0.
GPIO Port 1.
GPIO Port 2.
GPIO Port 3, capab le of sinking 12 mA (typical).
Digital to Analog Converter (DAC) Port with program-
mable current sink outputs. DAC[1 :0] offer a pro grammable range of 3.2 to 16 mA typical. DAC[7:2] have a program­mable sink current range of 0.2 to 1.0 mA typical.
norma l op e r at io n .
output buffers and the D+ pull-up.
4.2 I/O Register Summary
I/O registers ar e access ed via the I/O Rea d ( IORD) and I/O W rite ( I OWR, IOWX) inst ructi ons. I ORD reads dat a fr om t he sele cted port into the accumul ator. IOWR performs the reverse; it writes dat a from the accumul ator to the sel ected port . Index ed I/O W rite (IOWX) adds the contents of X to the address in the instruction to form the port address and writes dat a from the accumula tor to the specified po rt . Specifying address 0 (e.g., IOWX 0h) means the I/ O regi ster is selected solely by the contents of X.
All undefined registers are reserved. It is important not to write to reserved registers as this may cause an undefined operation or increased curre nt consumpti on dur in g operat ion. When writing to regi sters with res erved bi ts, the res erved b its must be wr it ten with ‘0 .’
Table 4-2. I/O Register Summary
Register Name I/O Address Read/Write Function

Port 0 Data 0x00 R/W GPIO Port 0 Data 23 Port 1 Data 0x01 R/W GPIO Port 1 Data 23 Port 2 Data 0x02 R/W GPIO Port 2 Data 23 Port 3 Data 0x03 R/W GPIO Port 3 Data 23 Port 0 Interrupt Enable 0x04 W Interrupt Enable for Pins in Port 0 24 Port 1 Interrupt Enable 0x05 W Interrupt Enable for Pins in Port 1 25 Port 2 Interrupt Enable 0x06 W Interrupt Enable for Pins in Port 2 25 Port 3 Interrupt Enable 0x07 W Interrupt Enable for Pins in Port 3 25

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Table 4-2. I/O Register Summary ( continued)
Register Name I/O Address Read/Write Function

GPIO Configuration 0x08 R/W G PIO Port Configurations 23

2

HAPI and I USB Device Address A 0x10 R/W USB Device Address A 42 EP A0 Counter Register 0x11 R/W USB Address A, Endpoint 0 Counter 44 EP A0 Mode Register 0x12 R/W USB Address A, Endpoint 0 Configuration 43 EP A1 Counter Register 0x13 R/W USB Address A, Endpoint 1 Counter 44 EP A1 Mode Register 0x14 R/W USB Address A, Endpoint 1 Configuration 44 EP A2 Counter Register 0x15 R/W USB Address A, Endpoint 2 Counter 44 EP A2 Mode Register 0x16 R/W USB Address A, Endpoint 2 Configuration 44 USB Status & Control 0x1F R/W USB Upstream Port Traffic Status and Control 41 Global Interrupt Enab le 0x20 R/W Global Interrupt Enab le 32 Endpoint Interru pt Enable 0x21 R/W USB Endpoint Interrupt Enables 32 Interrupt Vector 0x23 R Pending Interrupt Vector Read/Clear 34 Timer (LSB) 0x24 R Lower 8 Bits of Free-running Timer (1 MHz) 27 Timer (MSB) 0x25 R Upper 4 Bits of Free-running T imer 27 WDT Clear 0x26 W Watchdog Timer Clear 21

2

C Control & Status 0x28 R/W I2C Status and Control 28

I
2

C Data 0x29 R/W I2C Data 28

I DAC Data 0x30 R/W DAC Data 26 DAC Interrupt Enable 0x31 W Interrupt Enable for each DAC Pin 26 DAC Int er ru p t P o la rity 0x32 W Interr u pt Po la r ity fo r ea c h DAC P in 26 DAC Isink 0x38-0x3F W Input Sink Current Control for each DAC Pin 26 USB Device Address B 0x40 R/W USB Device Address B (not used in 5-endpoint mode) 42 EP B0 Counter Register 0x41 R/W USB Address B, Endpoint 0 Counter 44 EP B0 Mode Register 0x42 R/W USB Address B, Endpoint 0 Configuration, or

EP B1 Counter Register 0x43 R/W USB Address B, Endpoint 1 Counter 44 EP B1 Mode Register 0x44 R/W USB Address B, Endpoint 1 Configuration, or

Hub Port Connect Status 0x48 R/ W Hub Downstream Port Connect Status 38 Hub Port Enable 0x49 R/W Hub Downstream Ports Enable 38 Hub Port Speed 0x4A R/W Hub Downstream Ports Speed 38 Hub Port Control (Ports [4:1]) 0x4B R/W Hub Downstream Ports Control 39 Hub Port Suspend 0x4D R/W Hub Downstream Port Suspend Control 40 Hub Port Resume Status 0x4E R Hub Downstream Ports Resume Status 40 Hub Ports SE0 Status 0x4F R Hub Downstream Ports SE0 Status 39 Hub Ports Data 0x50 R Hub Downstream Ports Differential data 40 Hub Downstream Force Low 0x51 R/W Hub Downstream Ports Force LOW 39 Processor Status & Control 0xFF R/W Microprocessor Status and Control Register 31

C Configuration 0x09 R/W HAPI Width and I2C Position Configur ati on 27

USB Address A, Endpoint 3 in 5-endpoint mode
USB Address A, Endpoint 4 in 5-endpoint mode
Page
43
44
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4.3 Instruction Set Summary
Refer to the CYASM Assembler User’s Guide for more details.

Table 4-3. Instruction Set Summary

MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles
HALT 00 7 NOP 20 4 ADD A,expr data 01 4 INC A acc 21 4 ADD A,[expr] direct 02 6 INC X x 22 4 ADD A,[X+expr] index 03 7 INC [expr] direct 23 7 ADC A,expr data 04 4 INC [X+expr] index 24 8 ADC A,[expr] direct 05 6 DEC A acc 25 4 ADC A,[X+expr] index 06 7 DEC X x 26 4 SUB A,expr data 07 4 DEC [expr] direct 27 7 SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8 SUB A,[X+expr] index 09 7 IORD expr address 29 5 SBB A,expr data 0A 4 IOWR expr address 2A 5 SBB A,[expr] direct 0B 6 POP A 2B 4 SBB A,[X+expr] index 0C 7 POP X 2C 4 OR A,expr data 0D 4 PUSH A 2D 5 OR A,[expr] direct 0E 6 PUSH X 2E 5 OR A,[X+expr] index 0F 7 SWAP A,X 2F 5 AND A,expr data 10 4 SWAP A,DSP 30 5 AND A,[ex p r] direct 1 1 6 MOV [expr],A direct 31 5 AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6 XOR A,expr data 13 4 O R [expr],A direct 33 7 XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8 XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7 CMP A,expr data 16 5 AND [X+expr],A i ndex 36 8 CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7 CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8 MOV A,expr data 19 4 IOWX [X+expr] index 39 6 MOV A,[expr] direct 1A 5 CPL 3A 4 MOV A,[X+expr] index 1B 6 ASL 3B 4 MOV X,expr data 1C 4 ASR 3C 4 MOV X,[expr] direct 1D 5 RLC 3D 4 reserved 1E RRC 3E 4 XPAGE 1F 4 RET 3F 8 MOV A,X 40 4 DI 70 4 MOV X,A 41 4 EI 72 4 MOV PSP,A 60 4 RETI 73 8 CALL addr 50 - 5F 10 JC addr C0-CF 5 JMP addr 80-8F 5 JNC addr D0-DF 5 CALL addr 90-9F 10 JACC addr E0-EF 7 JZ addr A0-AF 5 INDEX addr F0-FF 14 JNZ addr B0-BF 5
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5.0 Programming Model

5.1 14-bit Program Counter (PC)
The 14-bit Program Counter (PC) allows access to up to 8 KB of PROM available with the CY7C66x13C architecture. The top 32 bytes of the ROM in the 8K part are reserved for testi ng purposes. The program count er is cleared duri ng reset, such that th e first instr uction executed after a reset is at a ddress 0x0000h. Typically, this is a jump instruction t o a reset handler that initializes the application (see Section 16.1, Interru pt Vectors, on page 33).
The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the program counter ar e incr emented by exe cut ing an XPAGE instruction. As a result , the la st inst ruct ion execu ted within a 256- byt e “page” of sequen tial code should be an XPAGE instructi on. T he assembler direct ive “XPAGEON” causes the assembler to insert XPAGE instructions automatically. Because instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE to execute corr ectly.
The address of the next instr ucti on to be execute d, the carr y flag, and the zer o flag ar e saved as two bytes on the program st ack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack during a RETI instruction. Onl y the pr ogram counter is restored during a RET instruction.
The program counter cannot be accessed directly by the firmware. The program stack can be ex am ined by reading SRAM from location 0x00 and up.
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5.1.1 Program Memory Organization

after reset Address 14-bit PC 0x0000

Program execution begins here after a reset
CY7C66013

0x0002

0x0004

0x0006

0x0008

0x000A

0x000C

0x000E

0x0010

0x0012

0x0014

0x0016

0x0018

USB Bus Reset interrupt vector
128-µs timer interrupt vector
1.024-ms timer i nterrupt vector
USB address A endpoint 0 interrupt vector
USB address A endpoint 1 interrupt vector
USB address A endpoint 2 interrupt vector
USB address B endpoint 0 interrupt vector
USB address B endpoint 1 interrupt vector
Hub interrupt vector
DAC interrupt vector
GPIO/HAPI interrupt vector
I2C interrupt vector

0x001A

0x1FDF

Figure 5-1. Progra m Memory Space with Interr upt Vector Table
Program Memory begins here
8 KB (-32) PROM ends here.
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5.2 8-bit Accumulator (A)
The accumulator is the general-purpose register for the microcontroller.
5.3 8-bit Temporary Register (X)
The “X” regi ster i s avail able to the firmwar e for t emporary storage of int ermediate results. The mi crocontro ller ca n perform indexed operations based on the value in X. Refer to Section 5.6.3 for addi ti onal information.
5.4 8-bit Progr a m Stack Pointer (PSP)
During a reset, the Program Stack Pointer (PSP) is set to 0x00 and “grows” upward from this address. The PSP may be set by firmware, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control. The PSP is not readable by the firmware.
During an interrupt acknowledge, interrupts are disabled and the 14-bit progr am counter, carry flag, and zero flag are written as two bytes of dat a memory . The f irst byte i s stored in the m emory address ed by the PSP, then the PSP is incre mented. The secon d byte is stored in memory addressed by the PSP, and the PSP is incremented again. The overall effect is to store the program counter and flags on the pro gram “stack” and increment th e PSP by two.
The Return From I nterr upt (RETI ) ins truct ion dec remen ts t he PSP, then rest ores t he second b yte from mem ory addr essed by th e PSP. The PSP is decremente d ag ain and the f irst byte is r estor ed f rom m emory add ressed by t he PSP. After the pro gram count er and flags hav e be en rest ored f r om sta ck, the i nter rupt s ar e enabl ed. Th e ov erall ef fec t is to r estor e t he prog ram c ounter and flags from the program stack, decrement the PSP by two, and re-enable interrupts.
The Call Subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.
The Return From Subroutine (RET) instruction restores the program counter but not the flags from the program stack and decrements the PSP by two.
5.4.1 Data Memory Organization
The CY7C66x13C microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program stack, us er varia bles, data st ack, an d USB endpoi nt FI FOs. The f ol lowing is o ne e xample o f where t he program st ack, dat a st a ck, and user variable s areas could be located.

After reset Address 8-bit DSP 8-bit PSP 0x00

(Move DSP

8-bit DSP

[1]
)

user selected

0xFF

User variables
USB FIFO sp ace for up to two Addresses and five endpoints
Program Stack Growth
Data Stack Growth
[2]
5.5 8-bit Data Stack Pointer (DSP)
The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads data from the memory lo cation addressed by the DSP, then post-increment s the DSP.
During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM (address 0xFF). This writes data to the memory area reserved for USB endpoint FIFOs. Therefore, the DSP should be indexed at an appropriate memory location that does not compromise the Program Stack, user-defined memory (variables), or the USB endpoint FIFOs.

Notes:

1. Refer to Section 5.5 for a description of DSP.
2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see
Table 19-1.
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