Page 1
CY7C65213
USB-UART LP Bridge Controller
USB-UART LP Bridge Controller
The USB-UART LP Bridge controller (CY7C65213) is fully compliant with the USB 2.0 specification, USB-IF
Test-ID (TID) 40860041.
Features
■ USB 2.0 certified, Full-Speed (12 Mbps)
❐ Supports communication driver class (CDC), personal health
care device class (PHDC), and vendor-specific drivers
❐ Battery charger detection (BCD) compliant with USB Battery
Charging Specification Rev. 1.2 (peripheral detect only)
❐ Integrated USB termination resistors
■ Single-channel configurable UART interfaces
❐ Data rates up to 3 Mbps
❐ 256 bytes for each transmit and receive buffer
❐ Data format:
• 7 to8 data bits
• 1 to 2 stop bits
• No parity, even, odd, mark, or space parity
❐ Supports parity, overrun, and framing errors
❐ Supports flow control using CTS, RTS, DTR, DSR
■ General-purpose input/output (GPIO): 8 pins
■ Configuration utility (Windows) to configure the following:
❐ Vendor ID (VID), Product ID (PID), and Product and
Manufacturer descriptors
❐ UART
❐ Charger detection
❐ GPIO
■ Driver support for VCOM and DLL
❐ Windows 8: 32- and 64-bit versions
❐ Windows 7: 32- and 64-bit versions
❐ Windows Vista: 32- and 64-bit versions
❐ Windows XP: 32- and 64-bit versions
❐ Windows CE
❐ Mac OS-X: 10.6, 10.7
❐ Linux: Kernel version 2.6.35 and later versions
❐ Android: Gingerbread and later versions
■ 512-byte flash for storing configuration parameters
■ Clocking: Integrated 48-MHz clock oscillator
■ USB suspend mode for low power
■ Supports bus-/self-powered configurations
■ Compatible with USB 2.0 and USB 3.0 host controllers
■ Operating voltage: 1.71 to 5.50 V
■ Operating temperature: –40 C to 85 C
■ ESD protection: 2.2-kV HBM
■ RoHS-compliant package
❐ 28-pin SSOP (10 × 7.5 × 1.65 mm, 0.65-mm pitch)
❐ 32-pin QFN (5 × 5 × 1 mm, 0.5-mm pitch)
■ Ordering part number
❐ CY7C65213-28PVXI
❐ CY7C65213-32LTXI
Applications
■ Blood glucose meter
■ Battery-operated devices
■ USB-to-UART cables
■ Enables USB connectivity in legacy peripherals with UART
■ Point-of-Sale (POS) terminals
■ Industrial and T&M devices
USB Compliant
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-81011 Rev. *G Revised January 22, 2014
Page 2
CY7C65213
Contents
Block Diagram ..................................................................3
Functional Overview ........................................................3
USB and Charger Detect .............................................3
UART Interface ............................................................3
GPIO Interface ............................................................3
Memory ....................................................................... 4
System Resources ......................................................4
Suspend and Resume .................................................4
WAKEUP .....................................................................4
Software ...................................................................... 4
Internal Flash Configuration ........................................6
Electrical Specifications ..................................................8
Absolute Maximum Ratings .........................................8
Operating Conditions ................................................... 8
Device-Level Specifications ........................................8
GPIO ...........................................................................9
Reset .........................................................................10
UART .........................................................................10
Flash Memory ............................................................10
Pin Description ...............................................................11
USB Power Configuration ..............................................14
USB Bus-Powered Configuration ..............................14
Self-Powered Configuration ......................................15
USB Bus Powered with Variable I/O Voltage ............ 16
Application Examples .................................................... 17
USB to RS232 Converter ..........................................17
Battery Operated Bus-Powered USB to MCU
with Battery Charge Detection ..........................................18
LED Interface ............................................................ 20
Ordering Information ......................................................21
Ordering Code Definitions .........................................21
Package Information ...................................................... 22
Acronyms ........................................................................ 24
Document Conventions ................................................. 24
Units of Measure .......................................................24
Document History Page .................................................25
Sales, Solutions, and Legal Information ......................27
Worldwide Sales and Design Support ....................... 27
Products .................................................................... 27
PSoC® Solutions ......................................................27
Cypress Developer Community .................................27
Technical Support ..................................................... 27
Document Number: 001-81011 Rev. *G Page 2 of 27
Page 3
CY7C65213
Block Diagram
USB
Transceiver
with
Integrated
Resistor
Voltage
Regulator
Internal
48 MHz OSC
GPIO
USBDP
USBDM
USB
Internal
32 KHz OSC
Reset
UART
256 Bytes
RX Buffer
RESET#
VCCIO
VCCD
256 Bytes
TX Buffer
512 Bytes
Flash
Memory
SIE
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
TXD
DTR#
RTS#
RXD
RI#
DSR#
DCD#
CTS#
VCC
Battery
Charger
Detection
BCD
GPIO0
GPIO1
GPIO2
Functional Overview
CY7C65213 is a fully integrated USB-to-UART bridge that
provides a simple method to upgrade UART-based devices to
USB with a minimal number of components. CY7C65213
includes a USB 2.0 Full-Speed controller, a UART transceiver,
an internal regulator, an internal oscillator, and a 512-byte flash
in a 32-pin QFN and 28-pin SSOP package.
The internal flash is used to store custom-specific USB
descriptors and GPIO configuration. This is done in-system
using a configuration utility that communicates over the USB
interface.
Cypress provides royalty-free Virtual COM Port (VCP) device
drivers. The drivers allow the device to appear as a COM port in
PC applications. All UART signals, including handshaking and
control signals, are implemented.
USB and Charger Detect
USB
CY7C65213 has a built-in USB 2.0 Full-Speed transceiver. The
transceiver incorporates an internal USB series termination
resistor on the USB data lines and a 1.5-k pull-up resistor on
the USBDP.
Charger Detection
CY7C65213 supports BCD for Peripheral Detect only and
complies with the USB Battery Charging Specification, Rev. 1.2.
It supports the following charging ports:
■ Standard Downstream Port (SDP): Allows the system to draw
up to 500-mA current from the host
■ Charging Downstream Port (CDP): Allows the system to draw
up to 1.5-A current from the host
■ Dedicated Charging Port (DCP): Allows the system to draw up
to 1.5-A of current from the wall charger
UART Interface
The UART interface provides asynchronous serial
communication with other UART devices operating at speeds of
Document Number: 001-81011 Rev. *G Page 3 of 27
up to 3 Mbits/second. It supports 7 to 8 data bits, 1 to 2 stop bits,
odd, even, mark, space, and no parity. The UART interface
supports full-duplex communication with a signaling format
compatible with the standard UART protocol. The UART pins
may be interfaced to industry-standard RS-232 transceivers to
manage different voltage levels.
Common UART functions, such as parity error and frame error,
are supported. A 256-byte buffer is available in both TX and RX
directions. CY7C65213 supports baud rates ranging from 300
baud to 3 Mbaud. UART baud rates can be set using the
configuration utility.
UART Flow Control
The CY7C65213 device supports UART hardware flow control
using control signal pairs, such as RTS# (Request to Send) /CTS# (Clear to Send) and DTR# (Data Terminal Ready) / DSR#
(Data Set Ready).
The following sections describe the flow control signals:
■ CTS# (Input) / RTS# (Output)
CTS# can pause or resume data transmission over the UART
interface. Data transmission can be paused by de-asserting the
CTS signal and resumed by using CTS# assertion. The pause
and resume operation does not affect data integrity. The receive
buffer has a watermark level of 80%. After the data in the receive
buffer reaches that level, the RTS# signal is de-asserted,
instructing the transmitting device to stop data transmission. The
start of data consumption by the application reduces device data
backlog. After it reaches the 50% watermark level, the RTS#
signal is asserted to resume data reception.
■ DSR# (Input) / DTR# (Output)
The DSR#/DTR# signals are used to establish a communication
link with the UART. These signals complement each other in their
functionality, similar to CTS# and RTS#.
GPIO Interface
CY7C65213 has eight GPIOs. The configuration utility lets you
configure the GPIO pins. The configurable options are as
follows:
Page 4
CY7C65213
■ TRISTATE: GPIO tristated
■ DRIVE 1: Output static 1
■ DRIVE 0: Output static 0
■ POWER#: Power control for bus power designs
■ TXLED#: Drives LED during USB transmit
■ RXLED#: Drives LED during USB receive
■ TX or RX LED#: Drives LED during USB transmit or receive.
GPIO can be configured to drive LED at 8-mA drive strength.
■ SLEEP#: Indicates USB suspend
■ BCD0/1: Two-pin output to indicate the type of USB charger
■ BUSDETECT: Connects VBUS pin for USB host detection
Memory
CY7C65213 has a 512-byte flash. Flash is used to store USB
parameters, such as VID/PID, serial number, and Product and
Manufacturer Descriptors, which can be programmed by the
configuration utility.
System Resources
Power System
CY7C65213 supports the USB Suspend mode to control power
usage. CY7C65213 operates in bus-powered or self-powered
modes over a range of 3.15 V to 5.25 V.
Clock System
CY7C65213 has a fully integrated clock and does not require any
external crystal. The clock system is responsible for providing
clocks to all subsystems.
Internal 48-MHz Oscillator
The internal 48-MHz oscillator is the primary source of internal
clocking in the CY7C65213 device.
Internal 32-kHz Oscillator
The internal 32-kHz oscillator, which is low-power and relatively
inaccurate, is primarily used to generate clocks for peripheral
operation in the USB Suspend mode.
Reset
The reset block ensures reliable power-on reset or
reconfiguration to a known state. The RESET# (active low) pin
can be used by external devices to reset the CY7C65213.
Suspend and Resume
The CY7C65213 device asserts the SLEEP# pin when the USB
bus goes into the suspend state. This helps to meet the stringent
suspend current requirements of the USB 2.0 specification, while
using the device in bus-powered mode. The device resumes
from the suspend state under either of the following two
conditions:
1. Any activity is detected on the USB bus
2. The RI# (configured as wakeup) pin is asserted to generate
remote wakeup to the host.
WAKEUP
The RI# (configured as wakeup) pin is used to generate the
remote wakeup signal on the USB bus. The remote wakeup
signal is sent only if the host enables this feature through the
SET_FEATURE request. The device communicates support for
the remote wakeup to the host through the configuration
descriptor during the USB enumeration process. The
CY7C65213 device allows enabling/disabling of the remote
wakeup feature through the configuration utility.
Software
Cypress delivers a complete set of software drivers and a
configuration utility to enable product configuration during
system development.
Drivers for Linux Operating Systems
Cypress provides a User Mode USB driver library
(libcyusbserial.so) that abstracts vendor commands for the
UART interface and provides a simplified API interface for user
applications. This library uses the standard open-source libUSB
library to enable USB communication. The Cypress serial library
supports the USB plug-and-play feature using the Linux ‘udev’
mechanism.
CY7C65213 supports the standard USB CDC UART-class
driver, which is bundled with the Linux kernel.
Android Support
The CY7C65213 solution also includes an Android Java
class–CyUsbSerial.java–which exposes a set of interface
functions to communicate with the device.
Drivers for Mac OSx
Cypress delivers a dynamically linked shared library
(CyUSBSerial.dylib) based on libUSB, which enables
communication to the CY7C65213 device.
In addition, the device also supports the native Mac OSx CDC
UART-class driver.
Document Number: 001-81011 Rev. *G Page 4 of 27
Page 5
CY7C65213
Drivers for Windows Operating Systems
For Windows operating systems (XP, Vista, Win7, and Win8),
Cypress delivers a User Mode dynamically linked
library–CyUSBSerial DLL.This library abstracts the
vendor-specific interface of the CY7C65213 devices and
provides convenient APIs to the user. It provides interface APIs
for vendor-specific UART and class-specific APIs for PHDC.
A virtual COM port driver–CyUSBSerial.sys–is also delivered,
which implements the USB CDC class driver. The Cypress
Windows drivers are:
■ Windows Driver Foundation (WDF) compliant
■ Compatible with any USB 2.0-compliant device
■ Compatible with Cypress USB 3.0-compliant devices
They also support Windows plug-and-play and power
management and USB Remote Wake-up
CY7C65213 also works with the Windows-standard USB CDC
UART class driver.
Windows-CE support
The CY7C65213 solution also includes a dynamically linked
library (DLL) and a CDC UART driver library for Windows-CE
platforms.
Device Configuration Utility (Windows only)
A Windows-based configuration utility is available to configure
device initialization parameters. This graphical user application
provides an interactive interface to define boot parameters
stored in the device flash.
This utility allows the user to save a user-selected configuration
to text or xml formats. It also allows users to load a selected
configurations from text or xml formats. The configuration utility
allows the following operations:
■ View current device configuration
■ Select and configure UART, battery charging, and GPIOs
■ Configure USB VID, PID, and string descriptors
■ Save or Load configuration
You can download the free configuration utility and drivers at
www.cypress.com/go/usbserial.
Document Number: 001-81011 Rev. *G Page 5 of 27
Page 6
CY7C65213
Internal Flash Configuration
The internal flash memory can be used to store configuration parameters as shown in the following table. A free configuration utility
is provided to configure the parameters listed in the table to meet application-specific requirements over a USB interface. The
configuration utility can be downloaded at www.cypress.com/go/usbserial.
Table 1. Internal Flash Configuration
Parameter Default Value Description
USB Configuration
USB Vendor ID (VID) 0x04B4 Default Cypress VID. Can be configured to customer VID
USB Product ID (PID) 0x0003 Default Cypress PID. Can be configured to customer PID
Manufacturer string Cypress Can be configured with any string up to 64 characters
Product string USB-UART LP Can be configured with any string up to 64 characters
Serial string Can be configured with any string up to 64 characters
Power mode Bus powered Can be configured to bus-powered or self-powered mode
Max current draw 100 mA Can be configured to any value from 0 to 500 mA. The configuration
descriptor will be updated based on this.
Remote wakeup Enabled Can be disabled. Remote wakeup is initiated by driving #RI low
USB interface protocol CDC Can be configured to function in CDC, PHDC, or Cypress vendor class
VCC voltage is 3.3 V Disabled This option should be checked if we need to bypass USB regulator in
VCCIO voltage is less
than 2 V
Enable manufacturing
interface
I/O Level CMOS Can be configured to either CMOS or LVTTL.
I/O Mode Fast Can be configured to either fast or slow for EMI considerations.
Baud Rate 115200 Can be configured in an editable drop-down combo box that lists the
Type 8 pin Can be configured to 2 pin, 4 pin, 6 pin or 8 pin.
Data Width 8 bits Can be configured to either 7 bits or 8 bits.
Stop Bits 1 bit Can be configured to either 1 bit or 2 bits.
Parity None Can be configured to either None, Odd, Even, Mark, or Space.
Invert RTS Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Invert CTS Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Invert DTR Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Invert DSR Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Invert DCD Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Invert RI Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Drop packets on RX
error
Disabled This option should be checked if we need to bypass VCCIO regulator in
Enabled This option enables an additional vendor class manufacturing mode interface
Disabled This parameter defines the behavior of the UART when an error is detected
CY7C65213.
CY7C65213.
to reconfigure the CY7C65213.
predefined, standard baud rates. You can also enter a specific baud rate in
the combo box.
RTS line can be inverted.
CTS line can be inverted.
DTR line can be inverted.
DSR line can be inverted.
DCD line can be inverted.
RI line can be inverted.
in the packet received (RX packet/byte). When this option is selected in USB
Serial Configuration Utility, the data packet/byte in the RX buffer is discarded.
Document Number: 001-81011 Rev. *G Page 6 of 27
Page 7
CY7C65213
Table 1. Internal Flash Configuration (continued)
Parameter Default Value Description
Disable CTS and DSR
pull-up during suspend
BCD Disabled Charger detect is disabled by default. When BCD is enabled, three of the
GPIO0 TXLED#
GPIO1 RXLED#
GPIO2 TRISTATE
GPIO3 POWER#
GPIO4 SLEEP#
GPIO5 BUSDETECT
GPIO6 BCD0
GPIO7 BCD1
Enabled In an embedded system, this parameter can be selected in USB Serial
Configuration Utility to reduce system current consumption during Suspend
state. This parameter disables the CTS and DSR pull-up resistors in the
Suspend state to meet USB 2.0 Specification current requirements.
GPIOs must be configured for BCD.
GPIO Configuration
GPIO can be configured as shown in Table 12 on page 13.
Document Number: 001-81011 Rev. *G Page 7 of 27
Page 8
CY7C65213
Electrical Specifications
Note
1. Usage above the absolute maximum conditions may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of
time may affect device reliability. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Absolute Maximum Ratings
Exceeding maximum ratings
device.
Storage temperature .................................... –55 °C to +100 °C
[1]
may shorten the useful life of the
Static discharge voltage ESD protection levels:
■ 2.2-kV HBM per JESD22-A114
Latch-up current ........................................................... 140 mA
Maximum current per GPIO ............................................ 25 mA
Ambient temperature with
power supplied (Industrial) ............................ –40 °C to +85 °C
Supply voltage to ground potential
V
................................................................................ 6.0 V
CCIO
V
................................................................................... 6.0 V
CC
V
............................................................................... 1.95 V
CCD
V
...................................................................... V
GPIO
CCIO
+ 0.5
Operating Conditions
TA (ambient temperature under bias)
Industrial ........................................................ –40 °C to +85 °C
V
supply voltage .......................................... 3.15 V to 5.25 V
CC
V
supply voltage ....................................... 1.71 V to 5.50 V
CCIO
V
supply voltage ........................................ 1.71 V to 1.89 V
CCD
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C, TJ 100 °C, and 1.71 V to 5.50 V, except where noted.
Table 2. DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
V
CC
V
CCIO
V
CCD
Cefc External Regulator voltage bypass 1.00 1.30 1.60 µF X5R ceramic or better
I
CC1
I
CC2
VCC supply voltage 3.15 3.30 3.45 V Set and configure correct voltage
4.35 5.00 5.25 V
V
supply voltage 1.71 1.80 1.89 V Used to set I/O voltage. Set and
CCIO
2.0 3.3 5.5 V
range using the configuration utility
for VCC. Default 5 V.
configure the correct voltage range
using the configuration utility for
V
. Default 3.3 V.
CCIO
Output voltage (for core logic) – 1.80 – V Do not use this supply to drive the
external device.
•1.71V VCCIO 1.89 V: Short
V
pin with the V
CCD
•V
capacitor (Cefc) between the
V
> 2 V – connect a 1-µF
CCIO
pin and ground
CCD
Operating supply current – 20 – mA USB 2.0 FS, UART at 1-Mbps single
channel, no GPIO switching
USB Suspend supply current – 5 – µA Does not include current through the
pull-up resistor on USBDP
CCIO
pin
Table 3. AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
Z
OUT
USB driver output impedance 28 – 44 As CY7C65213 has internal
termination resistors, external
resistors are not required.
Twakeup Wakeup from USB Suspend mode – 25 – µs
Document Number: 001-81011 Rev. *G Page 8 of 27
Page 9
CY7C65213
GPIO
Note
2. V
IH
must not exceed V
CCIO
+ 0.2 V.
Table 4. GPIO DC Specification
Parameter Description Min Typ Max Units Details/Conditions
[2]
V
IH
V
IL
[2]
V
IH
V
IL
[2]
V
IH
V
IL
V
OH
V
OH
V
OH
V
OL
V
OL
V
OL
Rpullup Pull-up resistor 3.5 5.6 8.5 kΩ
Rpulldown Pull-down resistor 3.5 5.6 8.5 kΩ
I
IL
C
IN
Vhysttl Input hysteresis LVTTL; V
Vhyscmos Input hysteresis CMOS 0.05 × V
Input voltage high threshold 0.7 × V
CCIO
Input voltage low threshold – – 0.3 × V
LVTTL input, V
LVTTL input, V
LVTTL input, V
LVTTL input, V
Output voltage high level,
CMOS Output
Output voltage high level,
CMOS Output
Output voltage high level,
CMOS Output
Output voltage low level,
< 2.7 V 0.7 × V
CCIO
< 2.7 V – – 0.3 × V
CCIO
> 2.7 V 2 – – V
CCIO
> 2.7 V – – 0.8 V
CCIO
CCIO
V
– 0.4 – – V IOH = 4 mA,
CCIO
V
– 0.6 – – V IOH = 4 mA,
CCIO
V
– 0.5 – – V IOH = 1 mA,
CCIO
––0.4VI
CMOS Output
Output voltage low level,
––0.6VI
CMOS Output
Output voltage low level,
––0.6VI
CMOS Output
– – V CMOS Input
CCIO
V CMOS Input
– – V
CCIO
V
= 5 V +/- 10%
V
CCIO
V
CCIO =
= 1.8 V +/- 5%
V
CCIO
= 8 mA,
OL
= 5 V +/- 10%
V
CCIO
= 8 mA,
OL
= 3.3 V +/- 10%
V
CCIO
= 4 mA,
OL
= 1.8 V +/- 5%
V
CCIO
Input leakage current (absolute value) – – 2 nA 25 °C, V
Input Capacitance – – 7 pF
> 2.7 V 25 40 – mV
CCIO
CCIO
–– mV
3.3 V +/- 10%
= 3.0 V
CCIO
Table 5. GPIO AC Specification
Parameter Description Min Ty p Max Units Details/Conditions
T
RiseFast1
T
FallFast1
T
RiseSlow1
T
FallSlow1
T
RiseFast2
T
FallFast2
T
RiseSlow2
T
FallSlow2
Rise Time in Fast mode 2 – 12 ns V
Fall Time in Fast mode 2 – 12 ns V
Rise Time in Slow mode 10 – 60 ns V
Fall Time in Slow mode 10 – 60 ns V
Rise Time in Fast mode 2 – 20 ns V
Fall Time in Fast mode 20 – 100 ns V
Rise Time in Slow mode 2 – 20 ns V
Fall Time in Slow mode 20 – 100 ns V
= 3.3 V/ 5.5 V,
CCIO
Cload = 25 pF
= 3.3 V/ 5.5 V,
CCIO
Cload = 25 pF
= 3.3 V/ 5.5 V,
CCIO
Cload = 25 pF
= 3.3 V/ 5.5 V,
CCIO
Cload = 25 pF
= 1.8 V,
CCIO
Cload = 25 pF
= 1.8 V,
CCIO
Cload = 25 pF
= 1.8 V,
CCIO
Cload = 25 pF
= 1.8 V,
CCIO
Cload = 25 pF
Document Number: 001-81011 Rev. *G Page 9 of 27
Page 10
CY7C65213
Reset
Table 6. Reset DC Specifications
Parameter Description Min Ty p Max Units Details/Conditions
V
IH
V
IL
Input voltage high threshold 0.7 × V
CCIO
–– V
Input voltage low threshold – – 0.3 × V
CCIO
V
Rpullup Pull-up resistor 3.5 5.6 8.5 kΩ
C
IN
Input capacitance – 5 – pF
Vhysxres Input voltage hysteresis – 100 – mV
Table 7. Reset AC Specifications
Parameter Description Min Ty p Max Units Details/Conditions
Tresetwidth Reset pulse width 1 – – µs
UART
Table 8. UART AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
F
UART
UART bit rate 0.3 – 3,000 kbps
Flash Memory
Table 9. Flash Memory Specifications
Parameter Description Min Typ Max Units Details/Conditions
Fend Flash endurance 100K – – cycles
Fret Flash retention. TA 85 °C, 10 K
program/erase cycles
10 – – years
Document Number: 001-81011 Rev. *G Page 10 of 27
Page 11
CY7C65213
Pin Description
TXD
DTR#
RTS#
VCCIO
RXD
RI#
GND
GPIO5
DSR#
DCD#
CTS#
GPIO4
GPIO2
GPIO3 USBDP
USBDM
VCCD
GND
RESET#
VCC
GND
GPIO1
GPIO0
NC
NC
DNU
GPIO6
GPIO7
CY7C65213
-28 PVXI
TOP VIEW
Table 10. CY7C65213-28PVXI (28-pin SSOP) Pin Description
Pin Name Typ e Default Description
1 TXD Output – Transmit asynchronous data output
2 DTR# Output – Data terminal ready control output
3 RTS# Output –
4VCCIOPower –
5 RXD Input –
6 RI# Input –
7 GND Power –
8 GPIO5 I/O Tristate
9DSR#Input –
10 DCD# Input – Data carrier detect control input
11 CTS# Input –
12 GPIO4 I/O Sleep# Configurable GPIO
13 GPIO2 I/O Tristate
14 GPIO3 I/O Power#
15 USBDP USBIO –
16 USBDM USBIO – USB Data Signal Minus, integrating
17 VCCD Power –
18 GND Power –
19 RESET# XRES – Chip reset, active low. Can be left
20 VCC Power – VBUS Supply voltage (USB) 3.15 to 5.25 V
21 GND Power – Digital Ground
22 GPIO1 I/O RXLED# Configurable GPIO
23 GPIO0 I/O TXLED# Configurable GPIO
24 NC – – No Connect
25 NC – – No Connect
26 DNU – – Do Not Use
27 GPIO6 I/O Tristate Configurable GPIO
28 GPIO7 I/O Tristate Configurable GPIO
Document Number: 001-81011 Rev. *G Page 11 of 27
Request to send control output
Supply to the device core and Interface,
1.71 to 5.5 V
Receiving asynchronous data input
Ring indicator control input. Can be
configured as wake-up; low signal on this
pin is used to wake up the USB Host
controller out of the suspend State
Digital Ground
Configurable GPIO
Data set ready control input
Clear to send control input
Configurable GPIO
Configurable GPIO
USB Data Signal Plus, integrating
termination resistor and a 1.5-kΩ pull-up
resistor
termination resistor
This pin is an output of an internal regulator
and cannot drive external devices.
Decouple this pin to ground using 1uF
capacitor when the VCCIO voltage is
greater then 2 V. Connect this pin to VCCIO
supply when the VCCIO voltage is less then
2 V.
Digital Ground
unconnected or have a pull-up resistor
connected to VCCIO supply.
Page 12
CY7C65213
Table 11. CY7C65213-32LTXI (32-pin QFN) Pin Description
CY7C65213
-32QFN
Top View
1
2
3
4
5
6
7
8
9
1011121314
15
16
313029
28
27
26
25
32
23
22
21
20
19
18
17
24
VCCIO
RXD
RI#
GND
GPIO5
DSR#
DCD#
CTS#
AGND
DNU
GPIO0
GPIO1
GND
VCC
RESET#
GND
GPIO4
GPIO2
GPIO3
GPIO6
GPIO7
USBDP
USBDM
VCCD
RTS#
DTR#
TXD
DNU
DNU
DNU
DNU
DNU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
31
30
29
28
27
26
25
32
23
22
21
20
19
18
17
24
VCCIO
RXD
RI#
GND
GPIO5
DSR#
DCD#
CTS#
AGND
DNU
GPIO0
GPIO1
GND
VCC
RESET#
GND
GPIO4
GPIO2
GPIO3
GPIO6
GPIO7
USBDP
USBDM
VCCD
RTS#
DTR#
TXD
DNU
DNU
DNU
DNU
DNU
CY7C65213
-32QFN
Bottom
View
Notes
3. All active low signals for the signal name are indicated by a # in this document.
4. Any pin acting as an Input pin should not be left unconnected.
Pin Name Type Default Description
1 VCCIO Power – Supply to the device core and
Interface, 1.71 to 5.5 V
2 RXD Input – Receiving asynchronous data input
3 RI# Input –
Ring indicator control input. Can be
configured as wake-up; low signal on
this pin is used to wake up the USB
Host controller out of the suspend
state
4 GND Power – Digital Ground
5 GPIO5 I/O TRISTATE
6 DSR# Input –
7 DCD# Input –
8 CTS# Input –
9 GPIO4 I/O SLEEP#
Configurable GPIO. See Ta ble 1 2.
Data set ready control input
Data carrier detect control input
Clear to send control input
Configurable GPIO. See Ta ble 1 2.
10 GPIO2 I/O TRISTATE Configurable GPIO. See Ta ble 1 2.
11 GPIO3 I/O POWER#
12 GPIO6 I/O TRISTATE
13 GPIO7 I/O TRISTATE
14 USBDP USBIO –
Configurable GPIO. See Ta ble 1 2.
Configurable GPIO. See Ta ble 1 2.
Configurable GPIO. See Ta ble 1 2.
USB Data Signal Plus, integrating
termination resistor and a 1.5-k
pull-up resistor
15 USBDM USBIO –
USB Data Signal Minus, integrating
termination resistor
16 VCCD Power –
This pin is an output of an internal
regulator and cannot drive external
devices.
Decouple this pin to ground using
1 µF capacitor when the VCCIO
voltage is greater then 2 V. Connect
this pin to VCCIO supply when the
VCCIO voltage is less then 2 V.
17 GND Power –
Digital Ground
18 RESET# XRES – Chip reset, active low. Can be left
unconnected or have a pull-up
resistor connected to VCCIO supply.
19 VCC Power – Supply voltage (USB) 3.15 to 5.25 V
20 GND Power – Digital Ground
21 GPIO1 I/O RXLED# Configurable GPIO. See Ta b le 1 2.
22 GPIO0 I/O TXLED# Configurable GPIO. See Tab l e 1 2 .
23 DNU – – Do Not Use
24 AGND Power – Analog Ground
Document Number: 001-81011 Rev. *G Page 12 of 27
[3, 4]
Page 13
CY7C65213
Table 11. CY7C65213-32LTXI (32-pin QFN) Pin Description (continued)
Note
5. When VBUS = VCCIO, connect VBUS to BUSDETECTION with a 10-K series resistor
When VBUS > VCCIO, connect VBUS to BUSDETECTION via the resistor divider network. Select R1 and R2 values as follows:
R1 ≥ 10 k
R2 / (R1 + R2) = VCCIO/VBUS
[3, 4]
Pin Name Type Default Description
25 DNU – –
Do Not Use
26 DNU – – Do Not Use
27 DNU – – Do Not Use
28 DNU – – Do Not Use
29 DNU – – Do Not Use
30 TXD Output – Transmit asynchronous data output
31 DTR# Output – Data terminal ready control output
32 RTS# Output – Request to send control output
Table 12. GPIO Configuration
The following signal options can be configured on the GPIO pins using a Cypress-provided configuration utility, which you can
download at www.cypress.com
GPIO Configuration Option Description
TRISTATE I/O tristated
DRIVE 1 Output static 1
DRIVE 0 Output static 0
POWER# This output is used to control power to an external logic through a switch to cut off power prior to
USB configuration and during USB suspend.
0 - USB device in Configured state
1 - USB device in Unconfigured state or during USB suspend mode
TXLED# Drives LED during USB transmit
RXLED# Drives LED during USB receive
TX and RX LED# Drives LED during USB transmit and receive
SLEEP# When low indicates USB suspend
BCD0 Configurable battery charger detect pins to indicate the type of USB charger (SDP, CDP, or DCP)
BCD1
Configuration example:
00 - Draw up to 100 mA (Unconfigured state)
01 - SDP (up to 500 mA)
10 - CDP/DCP (up to 1.5 A)
11 - Suspend (up to 2.5 mA)
This truth table can be configured using a configuration utility
BUSDETECT VBUS detection. Connect VBUS to this pin for VBUS detection when using the BCD feature
Document Number: 001-81011 Rev. *G Page 13 of 27
[5]
.
Page 14
CY7C65213
USB Power Configuration
USB
CONNECTOR
VBUS
D+
D-
GND
VCCIO
VCCD
1 uF
0.1 uF
USB-UART LP
CY7C65213
USBDP
USBDM
GND
RESET#
VCC
TXD
RXD
CTS#
RTS#
DTR#
DSR#
DCD#
RI#
GPIO4
AGND
GPIO5
GPIO6
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
GND
GND
DNU
DNU
DNU
DNU
DNU
DNU
0.1 uF 0.1 uF
VCC
VCC
The following section describes possible USB power configurations for the CY7C65213. Refer to the Pin Description on page
11 for signal details.
USB Bus-Powered Configuration
Figure 1 shows an example of the CY7C65213 in a bus-powered
design. VBUS is connected directly to the CY7C65213 because
it has an internal regulator.
The USB bus-powered system must comply with the following
requirements:
1. The system should not draw more than 100 mA prior to USB
enumeration (unconfigured state).
2. The system should not draw more than 2.5 mA during USB
Suspend mode.
Figure 1. Bus-Powered Configuration
3. A high-power bus-powered system (can draw more than
100 mA when operational) must use POWER# (configured
over GPIO) to keep the current consumption below 100 mA
prior to USB enumeration and 2.5 mA during USB Suspend
state.
4. The system should not draw more than 500 mA from the USB
host.
The configuration descriptor in the CY7C65213 flash should be
updated to indicate bus power and the maximum current
required by the system using a configuration utility.
Document Number: 001-81011 Rev. *G Page 14 of 27
Page 15
CY7C65213
Self-Powered Configuration
USB
CONNECTOR
VBUS
D+
D-
GND
0.1 uF
10K
4.7K
1.71 to 1.89 V
or
2.00 to 5.50 V
VCCIO
VCCD
1 uF
USB-UART LP
CY7C65213
USBDP
USBDM
GND
RESET#
VCC
TXD
RXD
CTS#
RTS#
DTR#
DSR#
DCD#
RI#
GPIO4
AGND
GPIO5
GPIO6
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
GND
GND
DNU
DNU
DNU
DNU
DNU
DNU
0.1 uF 0.1 uF
VCC
Figure 2 shows an example of CY7C65213 in a self-powered
design. A self-powered system does not use VBUS from the host
to power the system but has its own power supply. A
self-powered system has no restriction on current consumption
because it does not draw any current from the VBUS.
The VBUS of the USB host is used to control the RESET# pin of
CY7C65213. When the VBUS is present, reset to CY7C65213 is
de-asserted and the device enables an internal, 1.5-k pull-up
resistor on USBDP. When the VBUS is absent (the USB host is
powered down), reset to CY7C65213 is asserted, which causes
Figure 2. Self-Powered Configuration
the device to remove the 1.5-k pull-up resistor on USBDP. This
ensures that no current flows from the USBDP to the USB host
through a 1.5-k pull-up resistor, to comply with USB 2.0 specification.
When reset is asserted to CY7C65213, all the I/O pins are
tristated.
Using the configuration utility, the configuration descriptor in the
CY7C65213 flash should be updated to indicate that it is
self-powered.
Document Number: 001-81011 Rev. *G Page 15 of 27
Page 16
CY7C65213
USB Bus Powered with Variable I/O Voltage
USB
CONNECTOR
VBUS
D+
D-
GND
VCC
VCCD
1 uF
0.1uF
USB-UART LP
CY7C65213
USBDP
USBDM
GND
RESET#
VCCIO
TXD
RXD
CTS#
RTS#
DTR#
DSR#
DCD#
RI#
GPIO4
AGND
GPIO5
GPIO6
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
GND
GND
DNU
DNU
DNU
DNU
DNU
DNU
Vin
GND
SHDn
Vout
Vadj
Jumper to select
1.8 V or 3.3 V
VBUS
0.1 uF
TC 1070
1uF
1M
1 2 3
562K2M
3.3 V
1.8 V
1
2
3
VCCIO_1.8/3.3 V
VCCIO_1.8/3.3 V
1.8 V or 3.3 V or 5 V
Supply to External Logic
Jumper to select
1.8 V/3.3 V or 5 V
Power
Switch
0.1 uF 0.1 uF
VCC
Refer to
Note 6
Note
6. 1.71 V V
CCIO
1.89 V - Short V
CCD
pin with V
CCIO
pin; V
CCIO
> 2 V - connect a 1-uF decoupling capacitor to the V
CCD
pin.
Figure 3 shows the CY7C65213 in a bus-powered system with
variable I/O voltage. A low dropout (LDO) regulator is used to
supply 1.8 V or 3.3 V (using a jumper switch) the input of which
is 5 V from the VBUS. Another jumper switch is used to select
VCCIO_1.8/3.3 V or 5 V from the VBUS for the VCCIO pin of
CY7C65213. This allows I/O voltage and supply to external logic
to be selected among 1.8 V, 3.3 V, or 5 V.
The USB bus-powered system must comply with the following:
1. The system should not draw more than 100 mA prior to USB
enumeration (Unconfigured state).
2. The system should not draw more than 2.5 mA during USB
Suspend mode.
3. A hjgh-power bus-powered system (can draw more than
100 mA when operational) must use POWER# (configured
over GPIO) to keep the current consumption below 100 mA
prior to USB enumeration and 2.5 mA during USB Suspend
state.
Figure 3. USB Bus-Powered with 1.8-V, 3.3-V, or 5-V Variable I/O Voltage
[6]
Document Number: 001-81011 Rev. *G Page 16 of 27
Page 17
CY7C65213
Application Examples
USB
CONNECTOR
VBUS
D+
D-
GND
VCCIO
VCCD
1 uF
0.1 uF
USB-UART LP
CY7C65213
USBDP
USBDM
GND
RESET#
VCC
TXD
RXD
CTS#
RTS#
DTR#
DSR#
DCD#
RI#
GPIO4
AGND
GPIO5
GPIO6
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
GND
GND
DNU
DNU
DNU
DNU
DNU
DNU
TXD
RXD
CTS#
RTS#
DTR#
DSR#
DCD#
RI#
TXDout
RXDout
CTSout
RTSout
DTRout
DSRout
DCDout
RIout
1
2
3
4
6
7
8
9
5
DCDout
DSRout
RXDout
GND
RIout
DTRout
CTSout
TXDout
RTSout
1K
TXLED#
RXLED#
1K
VCC
VCC
PWRE#
SLEEP#
VCC
RS232 LEVEL
CONVERTER
0.1 uF 0.1 uF
VCC
The following section provides CY7C65213 application examples.
USB to RS232 Converter
CY7C65213 can connect any embedded system, with a serial
port, to a host PC through USB. CY7C65213 enumerates as a
COM port on the host PC.
The RS232 protocol follows bipolar signaling, that is, the output
signal toggles between negative and positive polarity. The valid
RS232 signal is either in the –3-V to –15-V range or in the +3-V
to +15-V range, and the range between –3 V to +3 V is invalid.
In RS232, Logic 1 is called “Mark” and corresponds to a negative
voltage range. Logic 0 is called “Space” and corresponds to a
positive voltage range. The RS232 level converter facilitates this
polarity inversion and the voltage-level translation between the
CY7C65213's UART interface and RS232 signaling.
In this application, as shown in Figure 4, GPIO4 can be
configured as SLEEP# or POWER# and connected to the
SHDN# pin of the RS232-level converter. Default configuration
of the GPIO4 in the device is SLEEP#. If GPIO4 is configured as
Figure 4. USB to RS232 Converter
SLEEP#, a low on this pin indicates USB suspend; if GPIO4 is
configured as POWER#, a high on this pin indicates a state prior
to USB configuration or USB suspend. GPIO0 and GPIO1 are
configured as TXLED# and RXLED# to drive two LEDs,
indicating data transmit and receive, respectively.
CY7C65213 has been tested with Maxim’s MAX3245
transceiver.
A simple loop-back test can be performed on the USB-to-RS232
converter as follows: Connect the TX and RX lines of the RS232
interface with a jumper, transmit data to the converter through a
COM Port communication terminal (such as Hyper Terminal or
Tera Term), and verify if the same data is received.
For detailed steps to test a USB-to-RS232 solution, refer to the
section ‘Testing a USB to RS232 solution’ in the application note
AN85514.
Document Number: 001-81011 Rev. *G Page 17 of 27
Page 18
CY7C65213
Battery Operated Bus-Powered USB to MCU with Battery Charge Detection
BAT
SYS
USB
CONNECTOR
VBUS
D+
DGND
VCCIO
VCCD
1 uF
0.1 uF
USB-UART LP
CY7C65213
USBDP
USBDM
GND
RESET#
TXD
RXD
CTS#
RTS#
DTR#
DSR#
DCD#
RI#
GPIO4
AGND
GPIO6
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
GND
GND
DNU
DNU
DNU
DNU
DNU
DNU
4.7K
BCD0
BCD1
MCU
VCC
RXD
TXD
RTS#
CTS#
I/O
GND
I/O
SLEEP#
WAKEUP#
GPIO5
EN2
IN
Battery
Charger
(MAX8856)
EN1
4.7K
BUSDETECT
BA
OVP
VCC
Notes
7. Add a 100 K pull-down resistor on the VBUS pin for quick discharge.
Figure 5 illustrates CY7C65213 as a USB-to-microcontroller
interface. The TXD and RXD lines are used for data transfer, and
the RTS# and CTS# lines are used for handshaking. GPIO4 is
configured as SLEEP# to indicate to the MCU if the device is in
the USB Suspend mode, and the RI# pin is configured to wake
up the USB host controller from the Suspend mode.
This application illustrates a battery-operated system, which is
bus-powered. CY7C65213 implements the battery charger
detection functionality based on the USB Battery Charging
Specification Rev. 1.2.
Battery-operated bus power systems must comply with the
following conditions:
1. The system can be powered from the battery (if not
discharged) and can be operational if the VBUS is not
connected or powered down.
2. The system should not draw more than 100 mA from the
VBUS prior to USB enumeration and USB Suspend.
3. The system should not draw more than 500 mA for SDP and
1.5 A for CDP/DCP.
Figure 5. Battery-Operated Bus-Powered USB to MCU with Battery Charge Detection
To comply with the first requirement, the VBUS from the USB
host is connected to the battery charger and to CY7C65213, as
shown in Figure 5. When the VBUS is connected, CY7C65213
initiates battery charger detection and indicates the type of USB
charger over BCD0 and BCD1. If the USB charger is SDP or
CDP, CY7C65213 enables a 1.5-K pull-up resistor on the
USBDP for Full-Speed enumeration. When the VBUS is
disconnected, CY7C65213 indicates an absence of the USB
charger over BCD0 and BCD1, and removes the 1.5-K pull-up
resistor on the USBDP. Removing this resistor ensures that no
current flows from the supply to the USB host through the
USBDP pin, to comply with the USB 2.0 specification.
To comply with the second and third requirements, the BCD0 and
BCD1 signals are configured over GPIO to communicate the
type of USB charger and the amount of current the battery
charger can draw from the VBUS. The BCD0 and BCD1 signals
can be configured using the configuration utility.
[7]
Document Number: 001-81011 Rev. *G Page 18 of 27
Page 19
CY7C65213
In a battery charger system, a 9-V spike on the VBUS is possible. The CY7C65213 VCC pin is intolerant to voltage above 6 V. In the
B
Battery Charger
BAT
SYS
USB-UART LP
CY7C65213
VCC
GPIO
BUSDETECT
Rs
A
B
A
R1
B
A
R2
VBUS = VCCIO
VBUS > VCCIO
R1 = 10 K
R2/(R1+R2) = VCCIO/VBUS
Rs = 10 K
VBUS
Rs
VBUS
VCCIO
BUSDETECT
CY7C65213
R1
VBUS
R2
VCCIO
CY7C65213
BUSDETECT
absence of over-voltage protection (OVP) on the VBUS line, the VBUS should be connected to BUSDETECT (GPIO configured) using
the resistive network and the output of the battery charger to the VCC pin of CY7C65213, as shown in the following figure.
Figure 6. GPIO VBUS Detect (BUSDETECT)
When VBUS and VCCIO are at the same voltage potential, the
VBUS can be connected to GPIO using a series resistor (Rs).
This is shown in the following figure. If there is a charger failure
and the VBUS becomes 9 V, then the 10-k resistor plays two
roles. It reduces the amount of current flowing into the now
forward-biased diodes in the GPIO, and it reduces the voltage
seen on the pad.
Figure 7. GPIO VBUS Detection, VBUS = VCCIO
When VBUS > VCCIO, a resistor voltage divider is required to
reduce the voltage from the VBUS down to VCCIO for the GPIO
sensing the VBUS voltage. This is shown in Figure 8.
The resistors should be sized as follows:
■ R1 ≥ 10 k
■ R2 / (R1 + R2) = VCCIO / VBUS
The first condition limits the voltage and current for the charger
failure situation, as described in the previous paragraph, while
the second condition allows for normal-operation VBUS
detection.
Figure 8. GPIO VBUS Detection, VBUS > VCCIO
Document Number: 001-81011 Rev. *G Page 19 of 27
Page 20
CY7C65213
LED Interface
CY7C65213
270R
VCCIO
GPIO[0..7]
TX or RX
LED#
CY7C65213
1K
VCCIO
GPIO[0..7]
GPIO[0..7]
1K
TXLED#
RXLED#
Any GPIO can be configured to drive an LED. Three
configuration options (TXLED#, RXLED#, and TX or RX LED#)
are available for driving LEDs. Refer to Table 12 on page 13.
The following figure shows an example of the CY7C65213 drive
single-LED configuration and dual-LED configurations,
respectively. In the single-LED configuration, the GPIO pin is
used to indicate when data is transmitted or received over USB
by the device (TX or RX LED#). In the dual-LED configuration,
when data is transmitted or received over USB, the respective
GPIO pins will drive the LED to indicate the transfer.
Figure 9. Single-LED Configuration
Figure 10. Double-LED Configuration
Document Number: 001-81011 Rev. *G Page 20 of 27
Page 21
CY7C65213
Ordering Information
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = PV or LT
PV = SSOP; LT = QFN
Number of pins: XX = 28 or 32
Part Number
Family Code:
65 = USB Hubs
Technology Code: C = CMOS
Marketing Code: 7 = Cypress products
Company ID: CY = Cypress
CCY 65 I-XX X2137 XX
Ta bl e 13 lists the CY7C65213 key package features and ordering codes. The table contains only the parts that are currently available.
If you do not see what you are seeking, contact your local sales representative. For more information, visit the Cypress website at
www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Table 13. Key Features and Ordering Information
Package Ordering Code Operating Range
28-pin SSOP (10 × 7.5 × 1.65 mm, 0.65 mm pitch) CY7C65213-28PVXI Industrial
32-pin QFN (5 × 5 × 1 mm, 0.5 mm pitch) (Pb-free) CY7C65213-32LTXI Industrial
Ordering Code Definitions
Document Number: 001-81011 Rev. *G Page 21 of 27
Page 22
CY7C65213
Package Information
001-30999 *D
51-85079 *E
Figure 11. 32-pin QFN (5 × 5 × 1.0 mm) LT32B 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-30999
Figure 12. 28-pin SSOP (10 × 7 × 1.65 mm, 210 Mils) Package Outline, 51-85079
Document Number: 001-81011 Rev. *G Page 22 of 27
Page 23
CY7C65213
Table 14. Package Characteristics
Parameter Description Min Typ Max Units
T
A
THJ Package JA (32-pin QFN) – 19 – °C/W
Table 15. Solder Reflow Peak Temperature
Table 16. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Operating ambient temperature –40 25 85 °C
Package JA (28-pin SSOP) – 62 – °C/W
Package Maximum Peak Temperature Maximum Time at Peak Temperature
32-pin QFN 260 °C 30 seconds
28-pin SSOP 260 °C 30 seconds
Package MSL
32-pin QFN MSL3
28-pin SSOP MSL3
Document Number: 001-81011 Rev. *G Page 23 of 27
Page 24
CY7C65213
Acronyms Document Conventions
Table 17. Acronyms Used in this Document
Acronym Description
BCD battery charger detection
CDC communication driver class
CDP charging downstream port
DCP dedicated charging port
DLL dynamic link library
ESD electrostatic discharge
GPIO general-purpose input/output
HBM human-body model
MCU microcontroller unit
OSC oscillator
PHDC personal health care device class
PID product identification
SDP standard downstream port
SIE serial interface engine
VCOM virtual communication port
USB Universal Serial Bus
UART universal asynchronous receiver transmitter
VID vendor identification
Units of Measure
Table 18. Units of Measure
Symbol Unit of Measure
C degree Celsius
DMIPS Dhrystone million instructions per second
k kilo-ohm
KB kilobyte
kHz kilohertz
kV kilovolt
Mbps megabits per second
MHz megahertz
mm millimeter
Vvolt
Document Number: 001-81011 Rev. *G Page 24 of 27
Page 25
CY7C65213
Document History Page
Document Title: CY7C65213, USB-UART LP Bridge Controller
Document Number: 001-81011
Revision ECN
** 3657798 ZKR 06/28/2012 New data sheet.
*A 3714911 ZKR 08/24/2012 Moved datasheet status to Preliminary.
*B 3814090 ZKR 12/19/2012 Removed reference to HID.
*C 3947144 ZKR 03/28/2013 Removed “4-KB SRAM” from Features and Contents.
*D 4002280 ZKR 05/16/2013 Updated flash size to 512 bytes.
*E 4019327 ZKR 06/13/2013 Changed status from Preliminary to Final.
*F 4105000 SAMT 08/26/2013 Final production release of datasheet.
Orig. of
Change
Submission
Date
Description of Change
Added electrical specs and pin information.
Updated description for Vhysttl parameter.
Updated Pin Description.
Added USB Power Configuration and Application Examples sections.
Updated Functional Overview and System Resources.
Removed CPU, Flash, and SRAM sections.
Updated USB PID in Internal Flash ConfigurationTable 1.
Removed VCC2 and VCCIO2 parameter descriptions in DC Specifications.
Changed CPU Frequency parameter to Frequency parameter in AC
Specifications.
Updated GPIO AC Specification
Updated Pin Description and Battery Operated Bus-Powered USB to MCU with
Battery Charge Detection sections.
Added Figure 6.
Removed Flash/SRAM feature from Ordering Information.
Added a note about compliance with the USB 2.0 specification.
Added a note for Absolute Maximum Ratings.
Updated maximum current per GPIO from 100 mA to 25 mA.
Added note for V
Updated content in USB to RS232 Convertor section.
Updated USB to MCU with BCD schematic.
Updated Features.
Updated Block Diagram.
Updated Functional Overview.
Updated Electrical Specifications.
Updated Pin Description.
Updated USB Power Configuration.
Updated Application Examples.
Updated in new template.
parameter in GPIO DC specifications.
IH
Document Number: 001-81011 Rev. *G Page 25 of 27
Page 26
CY7C65213
Document History Page (continued)
Document Title: CY7C65213, USB-UART LP Bridge Controller
Document Number: 001-81011
Revision ECN
*G 4250679 MVTA 01/17/2014 Updated Features.
Orig. of
Change
Submission
Date
Updated Functional Overview:
Updated description.
Updated UART Interface:
Updated UART Flow Control:
Updated description.
Updated System Resources:
Updated Power System:
Updated description.
Updated Software:
Updated Windows-CE support:
Updated description.
Updated Internal Flash Configuration:
Updated description.
Updated Table 1.
Updated Electrical Specifications:
Updated Device-Level Specifications:
Updated Table 3.
Updated GPIO:
Updated Table 4.
Updated Pin Description:
Added Ta bl e 10.
Updated Table 11.
Description of Change
Updated USB Power Configuration:
Updated USB Bus-Powered Configuration:
Updated Figure 1.
Updated Self-Powered Configuration:
Updated Figure 2.
Updated USB Bus Powered with Variable I/O Voltage:
Updated Figure 3.
Updated Application Examples:
Updated USB to RS232 Converter:
Updated description.
Added Figure 4.
Removed the figure “USB to RS232 Converter (32-pin QFN package)”.
Updated Battery Operated Bus-Powered USB to MCU with Battery Charge
Detection:
Updated description.
Added Figure 5.
Removed the figure “Battery-Operated Bus-Powered USB to MCU with Battery
Charge Detection (32-pin QFN package)”.
Updated Ordering Information (Updated part numbers).
Updated
Added Figure 12.
Updated Table 14, Ta bl e 15 , Table 16.
Package Information:
Document Number: 001-81011 Rev. *G Page 26 of 27
Page 27
CY7C65213
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© Cypress Semiconductor Corporation, 2012-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-81011 Rev. *G Revised January 22, 2014 Page 27 of 27
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