CYPRESS CY7C6521328PVXIT Datasheet
CY7C65213
USB-UART LP Bridge Controller
USB-UART LP Bridge Controller
The USB-UART LP Bridge controller (CY7C65213) is fully compliant with the USB 2.0 specification, USB-IF
Test-ID (TID) 40860041.
Features
■ USB 2.0 certified, Full-Speed (12 Mbps)
❐ Supports communication driver class (CDC), personal health
care device class (PHDC), and vendor-specific drivers
❐ Battery charger detection (BCD) compliant with USB Battery
Charging Specification Rev. 1.2 (peripheral detect only)
❐ Integrated USB termination resistors
■ Single-channel configurable UART interfaces
❐ Data rates up to 3 Mbps
❐ 256 bytes for each transmit and receive buffer
❐ Data format:
• 7 to8 data bits
• 1 to 2 stop bits
• No parity, even, odd, mark, or space parity
❐ Supports parity, overrun, and framing errors
❐ Supports flow control using CTS, RTS, DTR, DSR
■ General-purpose input/output (GPIO): 8 pins
■ Configuration utility (Windows) to configure the following:
❐ Vendor ID (VID), Product ID (PID), and Product and
Manufacturer descriptors
❐ UART
❐ Charger detection
❐ GPIO
■ Driver support for VCOM and DLL
❐ Windows 8: 32- and 64-bit versions
❐ Windows 7: 32- and 64-bit versions
❐ Windows Vista: 32- and 64-bit versions
❐ Windows XP: 32- and 64-bit versions
❐ Windows CE
❐ Mac OS-X: 10.6, 10.7
❐ Linux: Kernel version 2.6.35 and later versions
❐ Android: Gingerbread and later versions
■ 512-byte flash for storing configuration parameters
■ Clocking: Integrated 48-MHz clock oscillator
■ USB suspend mode for low power
■ Supports bus-/self-powered configurations
■ Compatible with USB 2.0 and USB 3.0 host controllers
■ Operating voltage: 1.71 to 5.50 V
■ Operating temperature: –40 C to 85 C
■ ESD protection: 2.2-kV HBM
■ RoHS-compliant package
❐ 28-pin SSOP (10 × 7.5 × 1.65 mm, 0.65-mm pitch)
❐ 32-pin QFN (5 × 5 × 1 mm, 0.5-mm pitch)
■ Ordering part number
❐ CY7C65213-28PVXI
❐ CY7C65213-32LTXI
Applications
■ Blood glucose meter
■ Battery-operated devices
■ USB-to-UART cables
■ Enables USB connectivity in legacy peripherals with UART
■ Point-of-Sale (POS) terminals
■ Industrial and T&M devices
USB Compliant
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-81011 Rev. *G Revised January 22, 2014
CY7C65213
Contents
Block Diagram ..................................................................3
Functional Overview ........................................................3
USB and Charger Detect .............................................3
UART Interface ............................................................3
GPIO Interface ............................................................3
Memory ....................................................................... 4
System Resources ......................................................4
Suspend and Resume .................................................4
WAKEUP .....................................................................4
Software ...................................................................... 4
Internal Flash Configuration ........................................6
Electrical Specifications ..................................................8
Absolute Maximum Ratings .........................................8
Operating Conditions ................................................... 8
Device-Level Specifications ........................................8
GPIO ...........................................................................9
Reset .........................................................................10
UART .........................................................................10
Flash Memory ............................................................10
Pin Description ...............................................................11
USB Power Configuration ..............................................14
USB Bus-Powered Configuration ..............................14
Self-Powered Configuration ......................................15
USB Bus Powered with Variable I/O Voltage ............ 16
Application Examples .................................................... 17
USB to RS232 Converter ..........................................17
Battery Operated Bus-Powered USB to MCU
with Battery Charge Detection ..........................................18
LED Interface ............................................................ 20
Ordering Information ......................................................21
Ordering Code Definitions .........................................21
Package Information ...................................................... 22
Acronyms ........................................................................ 24
Document Conventions ................................................. 24
Units of Measure .......................................................24
Document History Page .................................................25
Sales, Solutions, and Legal Information ......................27
Worldwide Sales and Design Support ....................... 27
Products .................................................................... 27
PSoC® Solutions ......................................................27
Cypress Developer Community .................................27
Technical Support ..................................................... 27
Document Number: 001-81011 Rev. *G Page 2 of 27
CY7C65213
Block Diagram
USB
Transceiver
with
Integrated
Resistor
Voltage
Regulator
Internal
48 MHz OSC
GPIO
USBDP
USBDM
USB
Internal
32 KHz OSC
Reset
UART
256 Bytes
RX Buffer
RESET#
VCCIO
VCCD
256 Bytes
TX Buffer
512 Bytes
Flash
Memory
SIE
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
TXD
DTR#
RTS#
RXD
RI#
DSR#
DCD#
CTS#
VCC
Battery
Charger
Detection
BCD
GPIO0
GPIO1
GPIO2
Functional Overview
CY7C65213 is a fully integrated USB-to-UART bridge that
provides a simple method to upgrade UART-based devices to
USB with a minimal number of components. CY7C65213
includes a USB 2.0 Full-Speed controller, a UART transceiver,
an internal regulator, an internal oscillator, and a 512-byte flash
in a 32-pin QFN and 28-pin SSOP package.
The internal flash is used to store custom-specific USB
descriptors and GPIO configuration. This is done in-system
using a configuration utility that communicates over the USB
interface.
Cypress provides royalty-free Virtual COM Port (VCP) device
drivers. The drivers allow the device to appear as a COM port in
PC applications. All UART signals, including handshaking and
control signals, are implemented.
USB and Charger Detect
USB
CY7C65213 has a built-in USB 2.0 Full-Speed transceiver. The
transceiver incorporates an internal USB series termination
resistor on the USB data lines and a 1.5-k pull-up resistor on
the USBDP.
Charger Detection
CY7C65213 supports BCD for Peripheral Detect only and
complies with the USB Battery Charging Specification, Rev. 1.2.
It supports the following charging ports:
■ Standard Downstream Port (SDP): Allows the system to draw
up to 500-mA current from the host
■ Charging Downstream Port (CDP): Allows the system to draw
up to 1.5-A current from the host
■ Dedicated Charging Port (DCP): Allows the system to draw up
to 1.5-A of current from the wall charger
UART Interface
The UART interface provides asynchronous serial
communication with other UART devices operating at speeds of
Document Number: 001-81011 Rev. *G Page 3 of 27
up to 3 Mbits/second. It supports 7 to 8 data bits, 1 to 2 stop bits,
odd, even, mark, space, and no parity. The UART interface
supports full-duplex communication with a signaling format
compatible with the standard UART protocol. The UART pins
may be interfaced to industry-standard RS-232 transceivers to
manage different voltage levels.
Common UART functions, such as parity error and frame error,
are supported. A 256-byte buffer is available in both TX and RX
directions. CY7C65213 supports baud rates ranging from 300
baud to 3 Mbaud. UART baud rates can be set using the
configuration utility.
UART Flow Control
The CY7C65213 device supports UART hardware flow control
using control signal pairs, such as RTS# (Request to Send) /CTS# (Clear to Send) and DTR# (Data Terminal Ready) / DSR#
(Data Set Ready).
The following sections describe the flow control signals:
■ CTS# (Input) / RTS# (Output)
CTS# can pause or resume data transmission over the UART
interface. Data transmission can be paused by de-asserting the
CTS signal and resumed by using CTS# assertion. The pause
and resume operation does not affect data integrity. The receive
buffer has a watermark level of 80%. After the data in the receive
buffer reaches that level, the RTS# signal is de-asserted,
instructing the transmitting device to stop data transmission. The
start of data consumption by the application reduces device data
backlog. After it reaches the 50% watermark level, the RTS#
signal is asserted to resume data reception.
■ DSR# (Input) / DTR# (Output)
The DSR#/DTR# signals are used to establish a communication
link with the UART. These signals complement each other in their
functionality, similar to CTS# and RTS#.
GPIO Interface
CY7C65213 has eight GPIOs. The configuration utility lets you
configure the GPIO pins. The configurable options are as
follows:
CY7C65213
■ TRISTATE: GPIO tristated
■ DRIVE 1: Output static 1
■ DRIVE 0: Output static 0
■ POWER#: Power control for bus power designs
■ TXLED#: Drives LED during USB transmit
■ RXLED#: Drives LED during USB receive
■ TX or RX LED#: Drives LED during USB transmit or receive.
GPIO can be configured to drive LED at 8-mA drive strength.
■ SLEEP#: Indicates USB suspend
■ BCD0/1: Two-pin output to indicate the type of USB charger
■ BUSDETECT: Connects VBUS pin for USB host detection
Memory
CY7C65213 has a 512-byte flash. Flash is used to store USB
parameters, such as VID/PID, serial number, and Product and
Manufacturer Descriptors, which can be programmed by the
configuration utility.
System Resources
Power System
CY7C65213 supports the USB Suspend mode to control power
usage. CY7C65213 operates in bus-powered or self-powered
modes over a range of 3.15 V to 5.25 V.
Clock System
CY7C65213 has a fully integrated clock and does not require any
external crystal. The clock system is responsible for providing
clocks to all subsystems.
Internal 48-MHz Oscillator
The internal 48-MHz oscillator is the primary source of internal
clocking in the CY7C65213 device.
Internal 32-kHz Oscillator
The internal 32-kHz oscillator, which is low-power and relatively
inaccurate, is primarily used to generate clocks for peripheral
operation in the USB Suspend mode.
Reset
The reset block ensures reliable power-on reset or
reconfiguration to a known state. The RESET# (active low) pin
can be used by external devices to reset the CY7C65213.
Suspend and Resume
The CY7C65213 device asserts the SLEEP# pin when the USB
bus goes into the suspend state. This helps to meet the stringent
suspend current requirements of the USB 2.0 specification, while
using the device in bus-powered mode. The device resumes
from the suspend state under either of the following two
conditions:
1. Any activity is detected on the USB bus
2. The RI# (configured as wakeup) pin is asserted to generate
remote wakeup to the host.
WAKEUP
The RI# (configured as wakeup) pin is used to generate the
remote wakeup signal on the USB bus. The remote wakeup
signal is sent only if the host enables this feature through the
SET_FEATURE request. The device communicates support for
the remote wakeup to the host through the configuration
descriptor during the USB enumeration process. The
CY7C65213 device allows enabling/disabling of the remote
wakeup feature through the configuration utility.
Software
Cypress delivers a complete set of software drivers and a
configuration utility to enable product configuration during
system development.
Drivers for Linux Operating Systems
Cypress provides a User Mode USB driver library
(libcyusbserial.so) that abstracts vendor commands for the
UART interface and provides a simplified API interface for user
applications. This library uses the standard open-source libUSB
library to enable USB communication. The Cypress serial library
supports the USB plug-and-play feature using the Linux ‘udev’
mechanism.
CY7C65213 supports the standard USB CDC UART-class
driver, which is bundled with the Linux kernel.
Android Support
The CY7C65213 solution also includes an Android Java
class–CyUsbSerial.java–which exposes a set of interface
functions to communicate with the device.
Drivers for Mac OSx
Cypress delivers a dynamically linked shared library
(CyUSBSerial.dylib) based on libUSB, which enables
communication to the CY7C65213 device.
In addition, the device also supports the native Mac OSx CDC
UART-class driver.
Document Number: 001-81011 Rev. *G Page 4 of 27
CY7C65213
Drivers for Windows Operating Systems
For Windows operating systems (XP, Vista, Win7, and Win8),
Cypress delivers a User Mode dynamically linked
library–CyUSBSerial DLL.This library abstracts the
vendor-specific interface of the CY7C65213 devices and
provides convenient APIs to the user. It provides interface APIs
for vendor-specific UART and class-specific APIs for PHDC.
A virtual COM port driver–CyUSBSerial.sys–is also delivered,
which implements the USB CDC class driver. The Cypress
Windows drivers are:
■ Windows Driver Foundation (WDF) compliant
■ Compatible with any USB 2.0-compliant device
■ Compatible with Cypress USB 3.0-compliant devices
They also support Windows plug-and-play and power
management and USB Remote Wake-up
CY7C65213 also works with the Windows-standard USB CDC
UART class driver.
Windows-CE support
The CY7C65213 solution also includes a dynamically linked
library (DLL) and a CDC UART driver library for Windows-CE
platforms.
Device Configuration Utility (Windows only)
A Windows-based configuration utility is available to configure
device initialization parameters. This graphical user application
provides an interactive interface to define boot parameters
stored in the device flash.
This utility allows the user to save a user-selected configuration
to text or xml formats. It also allows users to load a selected
configurations from text or xml formats. The configuration utility
allows the following operations:
■ View current device configuration
■ Select and configure UART, battery charging, and GPIOs
■ Configure USB VID, PID, and string descriptors
■ Save or Load configuration
You can download the free configuration utility and drivers at
www.cypress.com/go/usbserial.
Document Number: 001-81011 Rev. *G Page 5 of 27
CY7C65213
Internal Flash Configuration
The internal flash memory can be used to store configuration parameters as shown in the following table. A free configuration utility
is provided to configure the parameters listed in the table to meet application-specific requirements over a USB interface. The
configuration utility can be downloaded at www.cypress.com/go/usbserial.
Table 1. Internal Flash Configuration
Parameter Default Value Description
USB Configuration
USB Vendor ID (VID) 0x04B4 Default Cypress VID. Can be configured to customer VID
USB Product ID (PID) 0x0003 Default Cypress PID. Can be configured to customer PID
Manufacturer string Cypress Can be configured with any string up to 64 characters
Product string USB-UART LP Can be configured with any string up to 64 characters
Serial string Can be configured with any string up to 64 characters
Power mode Bus powered Can be configured to bus-powered or self-powered mode
Max current draw 100 mA Can be configured to any value from 0 to 500 mA. The configuration
descriptor will be updated based on this.
Remote wakeup Enabled Can be disabled. Remote wakeup is initiated by driving #RI low
USB interface protocol CDC Can be configured to function in CDC, PHDC, or Cypress vendor class
VCC voltage is 3.3 V Disabled This option should be checked if we need to bypass USB regulator in
VCCIO voltage is less
than 2 V
Enable manufacturing
interface
I/O Level CMOS Can be configured to either CMOS or LVTTL.
I/O Mode Fast Can be configured to either fast or slow for EMI considerations.
Baud Rate 115200 Can be configured in an editable drop-down combo box that lists the
Type 8 pin Can be configured to 2 pin, 4 pin, 6 pin or 8 pin.
Data Width 8 bits Can be configured to either 7 bits or 8 bits.
Stop Bits 1 bit Can be configured to either 1 bit or 2 bits.
Parity None Can be configured to either None, Odd, Even, Mark, or Space.
Invert RTS Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Invert CTS Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Invert DTR Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Invert DSR Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Invert DCD Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Invert RI Disabled By selecting this option in USB Serial Configuration Utility, the polarity of the
Drop packets on RX
error
Disabled This option should be checked if we need to bypass VCCIO regulator in
Enabled This option enables an additional vendor class manufacturing mode interface
Disabled This parameter defines the behavior of the UART when an error is detected
CY7C65213.
CY7C65213.
to reconfigure the CY7C65213.
predefined, standard baud rates. You can also enter a specific baud rate in
the combo box.
RTS line can be inverted.
CTS line can be inverted.
DTR line can be inverted.
DSR line can be inverted.
DCD line can be inverted.
RI line can be inverted.
in the packet received (RX packet/byte). When this option is selected in USB
Serial Configuration Utility, the data packet/byte in the RX buffer is discarded.
Document Number: 001-81011 Rev. *G Page 6 of 27
CY7C65213
Table 1. Internal Flash Configuration (continued)
Parameter Default Value Description
Disable CTS and DSR
pull-up during suspend
BCD Disabled Charger detect is disabled by default. When BCD is enabled, three of the
GPIO0 TXLED#
GPIO1 RXLED#
GPIO2 TRISTATE
GPIO3 POWER#
GPIO4 SLEEP#
GPIO5 BUSDETECT
GPIO6 BCD0
GPIO7 BCD1
Enabled In an embedded system, this parameter can be selected in USB Serial
Configuration Utility to reduce system current consumption during Suspend
state. This parameter disables the CTS and DSR pull-up resistors in the
Suspend state to meet USB 2.0 Specification current requirements.
GPIOs must be configured for BCD.
GPIO Configuration
GPIO can be configured as shown in Table 12 on page 13.
Document Number: 001-81011 Rev. *G Page 7 of 27
CY7C65213
Electrical Specifications
Note
1. Usage above the absolute maximum conditions may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of
time may affect device reliability. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Absolute Maximum Ratings
Exceeding maximum ratings
device.
Storage temperature .................................... –55 °C to +100 °C
[1]
may shorten the useful life of the
Static discharge voltage ESD protection levels:
■ 2.2-kV HBM per JESD22-A114
Latch-up current ........................................................... 140 mA
Maximum current per GPIO ............................................ 25 mA
Ambient temperature with
power supplied (Industrial) ............................ –40 °C to +85 °C
Supply voltage to ground potential
V
................................................................................ 6.0 V
CCIO
V
................................................................................... 6.0 V
CC
V
............................................................................... 1.95 V
CCD
V
...................................................................... V
GPIO
CCIO
+ 0.5
Operating Conditions
TA (ambient temperature under bias)
Industrial ........................................................ –40 °C to +85 °C
V
supply voltage .......................................... 3.15 V to 5.25 V
CC
V
supply voltage ....................................... 1.71 V to 5.50 V
CCIO
V
supply voltage ........................................ 1.71 V to 1.89 V
CCD
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C, TJ 100 °C, and 1.71 V to 5.50 V, except where noted.
Table 2. DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
V
CC
V
CCIO
V
CCD
Cefc External Regulator voltage bypass 1.00 1.30 1.60 µF X5R ceramic or better
I
CC1
I
CC2
VCC supply voltage 3.15 3.30 3.45 V Set and configure correct voltage
4.35 5.00 5.25 V
V
supply voltage 1.71 1.80 1.89 V Used to set I/O voltage. Set and
CCIO
2.0 3.3 5.5 V
range using the configuration utility
for VCC. Default 5 V.
configure the correct voltage range
using the configuration utility for
V
. Default 3.3 V.
CCIO
Output voltage (for core logic) – 1.80 – V Do not use this supply to drive the
external device.
•1.71V VCCIO 1.89 V: Short
V
pin with the V
CCD
•V
capacitor (Cefc) between the
V
> 2 V – connect a 1-µF
CCIO
pin and ground
CCD
Operating supply current – 20 – mA USB 2.0 FS, UART at 1-Mbps single
channel, no GPIO switching
USB Suspend supply current – 5 – µA Does not include current through the
pull-up resistor on USBDP
CCIO
pin
Table 3. AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
Z
OUT
USB driver output impedance 28 – 44 As CY7C65213 has internal
termination resistors, external
resistors are not required.
Twakeup Wakeup from USB Suspend mode – 25 – µs
Document Number: 001-81011 Rev. *G Page 8 of 27
CY7C65213
GPIO
Note
2. V
IH
must not exceed V
CCIO
+ 0.2 V.
Table 4. GPIO DC Specification
Parameter Description Min Typ Max Units Details/Conditions
[2]
V
IH
V
IL
[2]
V
IH
V
IL
[2]
V
IH
V
IL
V
OH
V
OH
V
OH
V
OL
V
OL
V
OL
Rpullup Pull-up resistor 3.5 5.6 8.5 kΩ
Rpulldown Pull-down resistor 3.5 5.6 8.5 kΩ
I
IL
C
IN
Vhysttl Input hysteresis LVTTL; V
Vhyscmos Input hysteresis CMOS 0.05 × V
Input voltage high threshold 0.7 × V
CCIO
Input voltage low threshold – – 0.3 × V
LVTTL input, V
LVTTL input, V
LVTTL input, V
LVTTL input, V
Output voltage high level,
CMOS Output
Output voltage high level,
CMOS Output
Output voltage high level,
CMOS Output
Output voltage low level,
< 2.7 V 0.7 × V
CCIO
< 2.7 V – – 0.3 × V
CCIO
> 2.7 V 2 – – V
CCIO
> 2.7 V – – 0.8 V
CCIO
CCIO
V
– 0.4 – – V IOH = 4 mA,
CCIO
V
– 0.6 – – V IOH = 4 mA,
CCIO
V
– 0.5 – – V IOH = 1 mA,
CCIO
––0.4VI
CMOS Output
Output voltage low level,
––0.6VI
CMOS Output
Output voltage low level,
––0.6VI
CMOS Output
– – V CMOS Input
CCIO
V CMOS Input
– – V
CCIO
V
= 5 V +/- 10%
V
CCIO
V
CCIO =
= 1.8 V +/- 5%
V
CCIO
= 8 mA,
OL
= 5 V +/- 10%
V
CCIO
= 8 mA,
OL
= 3.3 V +/- 10%
V
CCIO
= 4 mA,
OL
= 1.8 V +/- 5%
V
CCIO
Input leakage current (absolute value) – – 2 nA 25 °C, V
Input Capacitance – – 7 pF
> 2.7 V 25 40 – mV
CCIO
CCIO
–– mV
3.3 V +/- 10%
= 3.0 V
CCIO
Table 5. GPIO AC Specification
Parameter Description Min Ty p Max Units Details/Conditions
T
RiseFast1
T
FallFast1
T
RiseSlow1
T
FallSlow1
T
RiseFast2
T
FallFast2
T
RiseSlow2
T
FallSlow2
Rise Time in Fast mode 2 – 12 ns V
Fall Time in Fast mode 2 – 12 ns V
Rise Time in Slow mode 10 – 60 ns V
Fall Time in Slow mode 10 – 60 ns V
Rise Time in Fast mode 2 – 20 ns V
Fall Time in Fast mode 20 – 100 ns V
Rise Time in Slow mode 2 – 20 ns V
Fall Time in Slow mode 20 – 100 ns V
= 3.3 V/ 5.5 V,
CCIO
Cload = 25 pF
= 3.3 V/ 5.5 V,
CCIO
Cload = 25 pF
= 3.3 V/ 5.5 V,
CCIO
Cload = 25 pF
= 3.3 V/ 5.5 V,
CCIO
Cload = 25 pF
= 1.8 V,
CCIO
Cload = 25 pF
= 1.8 V,
CCIO
Cload = 25 pF
= 1.8 V,
CCIO
Cload = 25 pF
= 1.8 V,
CCIO
Cload = 25 pF
Document Number: 001-81011 Rev. *G Page 9 of 27
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