How it Works
CYPRESS
Loading...
CY7C65113C
User Manual
49 pgs2.53 Mb0
User Manual
49 pgs2.6 Mb0
Table of contents
Loading...

CYPRESS CY7C65113C User Manual

r
CY7C65113C
USB Hub with Microcontrolle
USB Hub with Microcontroller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08002 Rev. *D Revised March 6, 2006
CY7C65113C
TABLE OF CONTENTS
1.0 FEATURES ......................................................................................................................................5
2.0 FUNCTIONAL OVERVIEW .............................................................................................................6
3.0 PIN CONFIGURATIONS .................................................................................................................8
4.0 PRODUCT SUMMARY TABLES ....................................................................................................8
4.1 Pin Assignments .......................................................................................................................8
4.2 I/O Register Summary ................................................................................................................9
4.3 Instruction Set Summary ..........................................................................................................10
5.0 PROGRAMMING MODEL .............................................................................................................11
5.1 14-bit Program Counter ............................................................................................................11
5.1.1 Program Memory Organization ......................................................................................................12
5.2 8-bit Accumulator (A) ...............................................................................................................13
5.3 8-bit Temporary Register (X) ....................................................................................................13
5.4 8-bit Program Stack Pointer (PSP) ..........................................................................................13
5.4.1 Data Memory Organization ............................................................................................................13
5.5 8-bit Data Stack Pointer (DSP) ................................................................................................14
5.6 Address Modes ........................................................................................................................14
5.6.1 Data (Immediate) ............................................................................................................................14
5.6.2 Direct ..............................................................................................................................................14
5.6.3 Indexed ..........................................................................................................................................14
6.0 CLOCKING ....................................................................................................................................15
7.0 RESET ...........................................................................................................................................15
7.1 Power-on Reset .......................................................................................................................15
7.2 Watchdog Reset .......................................................................................................................16
8.0 SUSPEND MODE ..........................................................................................................................16
9.0 GENERAL-PURPOSE I/O PORTS ................................................................................................17
9.1 GPIO Configuration Port ..........................................................................................................18
9.2 GPIO Interrupt Enable Ports ....................................................................................................19
10.0 12-BIT FREE-RUNNING TIMER .................................................................................................19
11.0 I
2
C CONFIGURATION REGISTER ............................................................................................20
12.0 I2C-COMPATIBLE CONTROLLER .............................................................................................21
13.0 PROCESSOR STATUS AND CONTROL REGISTER ................................................................23
14.0 INTERRUPTS ..............................................................................................................................24
14.1 Interrupt Vectors .....................................................................................................................25
14.2 Interrupt Latency ....................................................................................................................26
14.3 USB Bus Reset Interrupt ........................................................................................................26
14.4 Timer Interrupt ........................................................................................................................26
14.5 USB Endpoint Interrupts ........................................................................................................27
14.6 USB Hub Interrupt ..................................................................................................................27
14.7 GPIO Interrupt ........................................................................................................................27
14.8 I
2
C Interrupt ............................................................................................................................27
15.0 USB OVERVIEW .........................................................................................................................28
15.1 USB Serial Interface Engine (SIE) .........................................................................................28
15.2 USB Enumeration ..................................................................................................................28
CY7C65113C
16.0 USB HUB .....................................................................................................................................29
16.1 Connecting/Disconnecting a USB Device ..............................................................................29
16.2 Enabling/Disabling a USB Device ..........................................................................................30
16.3 Hub Downstream Ports Status and Control ...........................................................................30
16.4 Downstream Port Suspend and Resume ...............................................................................32
16.5 USB Upstream Port Status and Control .................................................................................33
17.0 USB SERIAL INTERFACE ENGINE OPERATION .....................................................................34
17.1 USB Device Addresses ..........................................................................................................34
17.2 USB Device Endpoints ...........................................................................................................34
17.3 USB Control Endpoint Mode Registers ..................................................................................35
17.4 USB Non-control Endpoint Mode Registers ...........................................................................36
17.5 USB Endpoint Counter Registers ...........................................................................................36
17.6 Endpoint Mode/Count Registers Update and Locking Mechanism ........................................37
18.0 USB MODE TABLES ..................................................................................................................39
19.0 REGISTER SUMMARY ...............................................................................................................43
20.0 SAMPLE SCHEMATIC ................................................................................................................45
21.0 ABSOLUTE MAXIMUM RATINGS ..............................................................................................45
22.0 ELECTRICAL CHARACTERISTICS ...........................................................................................46
23.0 SWITCHING CHARACTERISTICS ..............................................................................................47
24.0 ORDERING INFORMATION .......................................................................................................48
25.0 PACKAGE DIAGRAM .................................................................................................................48
LIST OF FIGURES
Figure 5-1. Program Memory Space with Interrupt Vector Table .........................................................12
Figure 6-1. Clock Oscillator On-Chip Circuit ........................................................................................15
Figure 7-1. Watchdog Reset (Address 0x26) .......................................................................................16
Figure 9-1. Block Diagram of a GPIO Pin ............................................................................................17
Figure 9-2. Port 0 Data ........................................................................................................................17
Figure 9-3. Port1 Data .........................................................................................................................17
Figure 9-4. GPIO Configuration Register .............................................................................................18
Figure 9-5. Port 0 Interrupt Enable .......................................................................................................19
Figure 9-6. Port 1 Interrupt Enable .......................................................................................................19
Figure 10-1. Timer LSB Register .........................................................................................................20
Figure 10-2. Timer MSB Register ........................................................................................................20
Figure 10-3. Timer Block Diagram .......................................................................................................20
Figure 11-1. I Figure 12-1. I Figure 12-2. I
2
C Configuration Register ...............................................................................................20
2
C Data Register .............................................................................................................21
2
C Status and Control Register .......................................................................................21
Figure 13-1. Processor Status and Control Register ...........................................................................23
Figure 14-1. Global Interrupt Enable Register .....................................................................................24
Figure 14-2. USB Endpoint Interrupt Enable Register .........................................................................24
Figure 14-3. Interrupt Controller Function Diagram .............................................................................25
Figure 14-4. GPIO Interrupt Structure ..................................................................................................27
Figure 16-1. Hub Ports Connect Status ...............................................................................................29
Figure 16-2. Hub Ports Speed .............................................................................................................30
Figure 16-3. Hub Ports Enable Register ..............................................................................................30
Figure 16-4. Hub Downstream Ports Control Register .........................................................................31
CY7C65113C
Figure 16-5. Hub Ports Force Low Register .........................................................................................31
Figure 16-6. Hub Ports SE0 Status Register .......................................................................................31
Figure 16-7. Hub Ports Data Register ..................................................................................................32
Figure 16-8. Hub Ports Suspend Register ...........................................................................................32
Figure 16-9. Hub Ports Resume Status Register .................................................................................33
Figure 16-10. USB Status and Control Register ..................................................................................33
Figure 17-1. USB Device Address Registers .......................................................................................34
Figure 17-2. USB Device Endpoint Zero Mode Registers ....................................................................35
Figure 17-3. USB Non-control Device Endpoint Mode Registers ........................................................36
Figure 17-4. USB Endpoint Counter Registers ....................................................................................36
Figure 17-5. Token/Data Packet Flow Diagram ...................................................................................38
LIST OF TABLES
Table 4-1. Pin Assignments ...................................................................................................................8
Table 4-2. I/O Register Summary ..........................................................................................................9
Table 4-3. Instruction Set Summary .....................................................................................................10
Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity .............................................19
Table 11-1. I Table 12-1. I
Table 14-1. Interrupt Vector Assignments ............................................................................................26
Table 16-1. Control Bit Definition for Downstream Ports .....................................................................31
Table 16-2. Control Bit Definition for Upstream Port ............................................................................34
Table 17-1. Memory Allocation for Endpoints .....................................................................................35
Table 18-1. USB Register Mode Encoding ..........................................................................................39
Table 18-2. Decode table for Table 18-3: “Details of Modes for Differing Traffic Condition .................40
Table 18-3. Details of Modes for Differing Traffic Conditions
2
C Port Configuration .......................................................................................................20
2
C Status and Control Register Bit Definitions .................................................................21
...............................................................41
CY7C65113C

1.0 Features

• Full Speed USB hub with an integrated microcontroller
• 8-bit USB optimized microcontroller
— Harvard architecture
— 6-MHz external clock source
— 12-MHz internal CPU clock
— 48-MHz internal hub clock
• Internal memory
— 256 bytes of RAM
— 8 KB of PROM
• Integrated Master/Slave I
• I/O ports
— Two GPIO ports (Port 0 to 2) capable of sinking 7 mA per pin (typical)
— Higher current drive achievable by connecting multiple GPIO pins together to drive a common output
— Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs
— Maskable interrupts on all I/O pins
• 12-bit free-running timer with one microsecond clock ticks
• Watchdog timer (WDT)
• Internal Power-on Reset (POR)
• USB Specification compliance
— Conforms to USB Specification, Version 1.1
— Conforms to USB HID Specification, Version 1.1
— Supports one or two device addresses with up to 5 user-configured endpoints
Up to two 8-byte control endpoints
Up to four 8-byte data endpoints
Up to two 32-byte data endpoints
— Integrated USB transceivers
— Supports four downstream USB ports
— GPIO pins can provide individual power control outputs for each downstream USB port
— GPIO pins can provide individual port over current inputs for each downstream USB port
• Improved output drivers to reduce electromagnetic interference (EMI)
• Operating voltage from 4.0V to 5.5V DC
• Operating temperature from 0° to 70° C
• Available in 28-pin SOIC (-SXC) package
• Industry-standard programmer support.
2
C-compatible Controller (100 kHz) enabled through General-purpose I/O (GPIO) pins
CY7C65113C

2.0 Functional Overview

The CY7C65113C device is a one-time programmable 8-bit microcontroller with a built-in 12-Mbps USB hub that supports up to four downstream ports. The microcontroller instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications.
GPIO
The CY7C65113C has 11 GPIO pins (P0[7:0], P1[2:0]), both rated at 7 mA per pin (typical) sink current. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity.
Clock
The microcontroller uses an external 6-MHz crystal and an internal oscillator to provide a reference to an internal phase-locked loop (PLL)-based clock generator. This technology allows the customer application to use an inexpensive 6-MHz fundamental crystal that reduces the clock-related noise emissions (EMI). A PLL clock generator provides the 6-, 12-, and 48-MHz clock signals for distribution within the microcontroller.
Memory
The CY7C65113C is offered with 8 KB of PROM.
Power-on Reset, Watchdog, and Free-running Timer
These parts include power-on reset logic, a Watchdog timer, and a 12-bit free-running timer. The POR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address 0x0000. The Watchdog timer is used to ensure the microcontroller recovers after a period of inactivity. The firmware may become inactive for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs.
2
I
C
The microcontroller can communicate with external electronics through the GPIO pins. An I dates a 100-kHz serial link with an external device.
Timer
The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-µs and 1.024-ms. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read.
Interrupts
The microcontroller supports ten maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus Reset interrupt, the 128-µs (bit 6) and 1.024-ms (bit 9) outputs from the free-running timer, five USB endpoints, the USB hub, the GPIO ports, and the I from LOW ‘0’ to HIGH ‘1’. The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller sends a packet to the USB host. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be rising edge (‘0’ to ‘1’) or falling edge (‘1’ to ‘0’).
USB
The CY7C65113C includes an integrated USB Serial Interface Engine (SIE) that supports the integrated peripherals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the hub (two endpoints) and a device address for a compound device (three endpoints). The SIE allows the USB host to communicate with the hub and functions integrated into the microcontroller. The CY7C65113C part includes a 1:4 hub repeater with one upstream port and four downstream ports. The USB Hub allows power management control of the downstream ports by using GPIO pins assigned by the user firmware. The user has the option of ganging the downstream ports together with a single pair of power management pins, or providing power management for each port with four pairs of power management pins.
2
C-compatible master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles
2
C-compatible interface accommo-
Logic Block Diagram
CY7C65113C
6-MHz crystal
PLL
48 MHz
Clock
Divider
12 MHz
6 MHz
12-MHz
8-bit
CPU
PROM
8 KB
RAM
256 byte
12-bit Timer
8-bit Bus
USB
SIE
Interrupt
Controller
GPIO
PORT 0
P0[0]
P0[7]
USB
Transceiver
Repeater
D+[0]
Upstream USB Port
D–[0]
Downstream USB Ports
USB
Transceiver
USB
Transceiver
USB
Transceiver
USB
Transceiver
Power management under firmware
control using GPIO pins
D+[1] D–[1]
D+[2] D–[2]
D+[3] D–[3]
D+[4] D–[4]
Watchdog
Timer
Power-on
Reset
GPIO
PORT 1
I2C comp. Interface
2
C-compatible interface enabled by firmware through
*I
P1[1:0]
P1[0]
P1[2]
SCLK SDATA

3.0 Pin Configurations

XTALOUT
XTALIN
V
REF
GND
D+[0]
D–[0]
D+[1]
D–[1]
D+[2]
D–[2]
P0[7]
P0[5]
P0[3]
P0[1]
Top View
CY7C65113C
28-pin SOIC
1
28
2
27
26
3
4
25
5
24
23
6
7
22
8
21
9
20
19
10
11
18
12
17
13
16
15
14
V
CC
P1[1]
P1[0]
P1[2]
D–[3]
D+[3]
D–[4]
D+[4]
GND
V
PP
P0[0]
P0[2]
P0[4]
P0[6]
CY7C65113C

4.0 Product Summary Tables

4.1 Pin Assignments

Table 4-1. Pin Assignments
Name I/O 28-pin Description
D+[0], D–[0] I/O 5, 6 Upstream port, USB differential data.
D+[1], D–[1] I/O 7, 8 Downstream Port 1, USB differential data.
D+[2], D–[2] I/O 9, 10 Downstream Port 2, USB differential data.
D+[3], D–[3] I/O 23, 24 Downstream Port 3, USB differential data.
D+[4], D–[4] I/O 21, 22 Downstream Port 4, USB differential data.
P0 I/O P1[7:0]
11, 15, 12, 16, 13, 17, 14, 18
P1 I/O P1[2:0]
25, 27, 26
XTAL
XTAL
V
PP
V
CC
IN
OUT
IN 2 6-MHz crystal or external clock input.
OUT 1 6-MHz crystal out.
19 Programming voltage supply, tie to ground during normal operation.
28 Voltage supply.
GND 4, 20 Ground.
V
REF
IN 3 External 3.3V supply voltage for the downstream differential data output
GPIO Port 0 capable of sinking 7 mA (typical).
GPIO Port 1 capable of sinking 7 mA (typical).
buffers and the D+ pull-up.
CY7C65113C

4.2 I/O Register Summary

I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X.
All undefined registers are reserved. Do not write to reserved registers as this may cause an undefined operation or increased current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with ‘0.’
Table 4-2. I/O Register Summary
Register Name I/O Address Read/Write Function Page
Port 0 Data 0x00 R/W GPIO Port 0 Data 17
Port 1 Data 0x01 R/W GPIO Port 1 Data 17
Port 0 Interrupt Enable 0x04 W Interrupt Enable for Pins in Port 0 19
Port 1 Interrupt Enable 0x05 W Interrupt Enable for Pins in Port 1 19
GPIO Configuration 0x08 R/W GPIO Port Configurations 18
2
C Configuration 0x09 R/W I2C Position Configuration 20
I
USB Device Address A 0x10 R/W USB Device Address A 34
EP A0 Counter Register 0x11 R/W USB Address A, Endpoint 0 Counter 36
EP A0 Mode Register 0x12 R/W USB Address A, Endpoint 0 Configuration 35
EP A1 Counter Register 0x13 R/W USB Address A, Endpoint 1 Counter 36
EP A1 Mode Register 0x14 R/W USB Address A, Endpoint 1 Configuration 36
EP A2 Counter Register 0x15 R/W USB Address A, Endpoint 2 Counter 36
EP A2 Mode Register 0x16 R/W USB Address A, Endpoint 2 Configuration 36
USB Status & Control 0x1F R/W USB Upstream Port Traffic Status and Control 33
Global Interrupt Enable 0x20 R/W Global Interrupt Enable 24
Endpoint Interrupt Enable 0x21 R/W USB Endpoint Interrupt Enables 24
Interrupt Vector 0x23 R Pending Interrupt Vector Read/Clear 26
Timer (LSB) 0x24 R Lower Eight Bits of Free-running Timer (1 MHz) 20
Timer (MSB) 0x25 R Upper Four Bits of Free-running Timer 20
WDR Clear 0x26 W Watchdog Reset Clear 16
2
C Control & Status 0x28 R/W I2C Status and Control 21
I
2
C Data 0x29 R/W I2C Data 21
I
Reserved 0x30 Reserved
Reserved 0x31 Reserved
Reserved 0x32 Reserved
Reserved 0x38-0x3F Reserved
USB Device Address B 0x40 R/W USB Device Address B (not used in 5-endpoint mode) 34
EP B0 Counter Register 0x41 R/W USB Address B, Endpoint 0 Counter 36
EP B0 Mode Register 0x42 R/W USB Address B, Endpoint 0 Configuration, or
USB Address A, Endpoint 3 in 5-endpoint mode
EP B1 Counter Register 0x43 R/W USB Address B, Endpoint 1 Counter 36
EP B1 Mode Register 0x44 R/W USB Address B, Endpoint 1 Configuration, or
USB Address A, Endpoint 4 in 5-endpoint mode
Hub Port Connect Status 0x48 R/W Hub Downstream Port Connect Status 29
Hub Port Enable 0x49 R/W Hub Downstream Ports Enable 30
Hub Port Speed 0x4A R/W Hub Downstream Ports Speed 30
35
36
CY7C65113C
Table 4-2. I/O Register Summary (continued)
Register Name I/O Address Read/Write Function Page
Hub Port Control (Ports [4:1]) 0x4B R/W Hub Downstream Ports Control (Ports [4:1]) 31
Hub Port Suspend 0x4D R/W Hub Downstream Port Suspend Control 32
Hub Port Resume Status 0x4E R Hub Downstream Ports Resume Status 33
Hub Ports SE0 Status 0x4F R Hub Downstream Ports SE0 Status 31
Hub Ports Data 0x50 R Hub Downstream Ports Differential Data 32
Hub Downstream Force Low 0x51 R/W Hub Downstream Ports Force LOW (Ports [1:4]) 31
Processor Status & Control 0xFF R/W Microprocessor Status and Control Register 23

4.3 Instruction Set Summary

Refer to the CYASM Assembler User’s Guide for more details. Note that conditional jump instructions (i.e., JC, JNC, JZ, JNZ) take five cycles if jump is taken, four cycles if no jump.
Table 4-3. Instruction Set Summary
MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles
HALT 00 7 NOP 20 4
ADD A,expr data 01 4 INC A acc 21 4
ADD A,[expr] direct 02 6 INC X x 22 4
ADD A,[X+expr] index 03 7 INC [expr] direct 23 7
ADC A,expr data 04 4 INC [X+expr] index 24 8
ADC A,[expr] direct 05 6 DEC A acc 25 4
ADC A,[X+expr] index 06 7 DEC X x 26 4
SUB A,expr data 07 4 DEC [expr] direct 27 7
SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8
SUB A,[X+expr] index 09 7 IORD expr address 29 5
SBB A,expr data 0A 4 IOWR expr address 2A 5
SBB A,[expr] direct 0B 6 POP A 2B 4
SBB A,[X+expr] index 0C 7 POP X 2C 4
OR A,expr data 0D 4 PUSH A 2D 5
OR A,[expr] direct 0E 6 PUSH X 2E 5
OR A,[X+expr] index 0F 7 SWAP A,X 2F 5
AND A,expr data 10 4 SWAP A,DSP 30 5
AND A,[expr] direct 11 6 MOV [expr],A direct 31 5
AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6
XOR A,expr data 13 4 OR [expr],A direct 33 7
XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8
XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7
CMP A,expr data 16 5 AND [X+expr],A index 36 8
CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7
CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8
MOV A,expr data 19 4 IOWX [X+expr] index 39 6
MOV A,[expr] direct 1A 5 CPL 3A 4
MOV A,[X+expr] index 1B 6 ASL 3B 4
MOV X,expr data 1C 4 ASR 3C 4
MOV X,[expr] direct 1D 5 RLC 3D 4
reserved 1E RRC 3E 4
Document #: 38-08002 Rev. *D Page 10 of 49
CY7C65113C
Table 4-3. Instruction Set Summary (continued)
MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles
XPAGE 1F 4 RET 3F 8
MOV A,X 40 4 DI 70 4
MOV X,A 41 4 EI 72 4
MOV PSP,A 60 4 RETI 73 8
CALL addr 50-5F 10 JC addr C0-CF 5 (or 4)
JMP addr 80-8F 5 JNC addr D0-DF 5 (or 4)
CALL addr 90-9F 10 JACC addr E0-EF 7
JZ addr A0-AF 5 (or 4) INDEX addr F0-FF 14
JNZ addr B0-BF 5 (or 4)

5.0 Programming Model

5.1 14-bit Program Counter

The 14-bit Program Counter (PC) allows access to up to 8 KB of PROM available with the CY7C65113C architecture. The top 32 bytes of the ROM in the 8K part are reserved for testing purposes. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. Typically, this is a jump instruction to a reset handler that initializes the application (see Interrupt Vectors on page 25).
The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page” of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” causes the assembler to insert XPAGE instructions automatically. Because instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE to execute correctly.
The address of the next instruction to be executed, the carry flag, and the zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack during a RETI instruction. Only the program counter is restored during a RET instruction.
The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.
Document #: 38-08002 Rev. *D Page 11 of 49

5.1.1 Program Memory Organization

after reset Address
14-bit PC 0x0000 Program execution begins here after a reset
CY7C65113C
0x0002 USB Bus Reset interrupt vector
0x0004 128-µs timer interrupt vector
0x0006 1.024-ms timer interrupt vector
0x0008 USB address A endpoint 0 interrupt vector
0x000A USB address A endpoint 1 interrupt vector
0x000C USB address A endpoint 2 interrupt vector
0x000E USB address B endpoint 0 interrupt vector
0x0010 USB address B endpoint 1 interrupt vector
0x0012 Hub interrupt vector
0x0014 Reserved
0x0016 GPIO interrupt vector
0x0018
0x001A Program Memory begins here
I2C interrupt vector
0x1FDF (8 KB -32) PROM ends here (CY7C65113C)
Figure 5-1. Program Memory Space with Interrupt Vector Table
Note that
Document #: 38-08002 Rev. *D Page 12 of 49
the upper 32 bytes of the 8K PROM are reserved. Therefore, user’s program must not overwrite this space.
CY7C65113C

5.2 8-bit Accumulator (A)

The accumulator is the general-purpose register for the microcontroller.

5.3 8-bit Temporary Register (X)

The “X” register is available to the firmware for temporary storage of intermediate results. The microcontroller can perform indexed operations based on the value in X. Refer to Section 5.6.3 for additional information.

5.4 8-bit Program Stack Pointer (PSP)

During a reset, the Program Stack Pointer (PSP) is set to 0x00 and “grows” upward from this address. The PSP may be set by firmware, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control. The PSP is not readable by the firmware.
During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the PSP, then the PSP is incremented. The second byte is stored in memory addressed by the PSP, and the PSP is incremented again. The overall effect is to store the program counter and flags on the program “stack” and increment the PSP by two.
The Return From Interrupt (RETI) instruction decrements the PSP, then restores the second byte from memory addressed by the PSP. The PSP is decremented again and the first byte is restored from memory addressed by the PSP. After the program counter and flags have been restored from stack, the interrupts are enabled. The overall effect is to restore the program counter and flags from the program stack, decrement the PSP by two, and re-enable interrupts.
The Call Subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.
The Return From Subroutine (RET) instruction restores the program counter but not the flags from the program stack and decrements the PSP by two.

5.4.1 Data Memory Organization

The CY7C65113C microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program stack, user variables, data stack, and USB endpoint FIFOs. The following is one example of where the program stack, data stack, and user variables areas could be located.
After reset Address
8-bit DSP 8-bit PSP 0x00 Program Stack Growth
(Move DSP
8-bit DSP
Notes:
1. Refer to Section 5.5 for a description of DSP.
2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7). See Table 17-1.
[1]
)
user selected Data Stack Growth
User variables
USB FIFO space for up to two Addresses and five endpoints
0xFF
[2]
Document #: 38-08002 Rev. *D Page 13 of 49
CY7C65113C

5.5 8-bit Data Stack Pointer (DSP)

The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads data from the memory location addressed by the DSP, then post-increments the DSP.
During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM (address 0xFF). This writes data to the memory area reserved for USB endpoint FIFOs. Therefore, the DSP should be indexed at an appropriate memory location that does not compromise the Program Stack, user-defined memory (variables), or the USB endpoint FIFOs.
For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are described in Section 17.2. Example assembly instructions to do this with two device addresses (FIFOs begin at 0xD8) are shown below:
MOV A,20h ; Move 20 hex into Accumulator (must be D8h or less)
SWAP A,DSP ; swap accumulator value into DSP register.

5.6 Address Modes

The CY7C65113 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed.

5.6.1 Data (Immediate)

“Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0xD8:
• MOV A, 0D8h.
This instruction requires two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the second byte. The second byte of the instruction is the constant “0xD8.” A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:
• DSPINIT: EQU 0D8h
• MOV A, DSPINIT.

5.6.2 Direct

“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10:
• MOV A, [10h].
Normally, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above:
• buttons: EQU 10h
• MOV A, [buttons].

5.6.3 Indexed

“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the “X” register. Normally, the constant is the “base” address of an array of data and the X register contains an index that indicates which element of the array is actually addressed:
•array: EQU 10h
•MOV X, 3
• MOV A, [X+array].
This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10. The fourth element would be at address 0x13.
Document #: 38-08002 Rev. *D Page 14 of 49

6.0 Clocking

XTALOUT
(pin 1)
CY7C65113C
XTALIN
(pin 2)
30 pF
Figure 6-1. Clock Oscillator On-Chip Circuit
The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to these pins. When using an external crystal, keep PCB traces between the chip leads and crystal as short as possible (less than 2 cm). A 6-MHz fundamental frequency parallel resonant crystal can be connected to these pins to provide a reference frequency for the internal PLL. The two internal 30-pF load caps appear in series to the external crystal and would be equivalent to a 15-pF load. Therefore, the crystal must have a required load capacitance of about 15–18 pF. A ceramic resonator does not allow the microcontroller to meet the timing specifications of full speed USB and therefore a ceramic resonator is not recommended with these parts.
An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Grounding the XTALOUT pin when driving XTALIN with an oscillator does not work because the internal clock is effectively shorted to ground.
To Internal PLL
30 pF

7.0 Reset

The CY7C65113C supports two resets: POR and WDR. Each of these resets causes:
• all registers to be restored to their default states
• the USB device addresses to be set to 0
• all interrupts to be disabled
• the PSP and DSP to be set to memory address 0x00.
The occurrence of a reset is recorded in the Processor Status and Control Register, as described in Section. Bits 4 and 6 are used to record the occurrence of POR and WDR respectively. Firmware can interrogate these bits to determine the cause of a reset.
Program execution starts at ROM address 0x0000 after a reset. Although this looks like interrupt vector 0, there is an important difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. The firmware reset handler should configure the hardware before the “main” loop of code. Attempting to execute a RET or RETI in the firmware reset handler causes unpredictable execution results.

7.1 Power-on Reset

When VCC is first applied to the chip, the POR signal is asserted and the CY7C65113C enters a “semi-suspend” state. During the semi-suspend state, which is different from the suspend state defined in the USB specification, the oscillator and all other blocks of the part are functional, except for the CPU. This semi-suspend time ensures that both a valid VCC level is reached and that the internal PLL has time to stabilize before full operation begins. When the V the oscillator is stable, the POR is deasserted and the on-chip timer starts counting. The first 1 ms of suspend time is not interruptible, and the semi-suspend state continues for an additional 95 ms unless the count is bypassed by a USB Bus Reset on the upstream port. The 95 ms provides time for V
If a USB Bus Reset occurs on the upstream port during the 95 ms semi-suspend time, the semi-suspend state is aborted and program execution begins immediately from address 0x0000. In this case, the Bus Reset interrupt is pending but not serviced until firmware sets the USB Bus Reset Interrupt Enable bit (Bit 0, Figure 14-1) and enables interrupts with the EI command.
The POR signal is asserted whenever V again. Behavior is the same as described above.
Document #: 38-08002 Rev. *D Page 15 of 49
drops below approximately 2.5V, and remains asserted until VCC rises above this level
CC
to stabilize at a valid operating voltage before the chip executes code.
CC
has risen above approximately 2.5V, and
CC
Loading...
+ 34 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use