CYPRESS CY7C65013, CY7C65113 User Manual

CY7C6501

3
3

CY7C6511

USB Hub with Microcontroller

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-08002 Rev. *B Revised March 12, 2003

CY7C6501

3
3

TABLE OF CONTENTS

1.0 FEATURES ............................................ .. .. .. .. .................................................................................6

2.0 FUNCTIONAL OVERVIEW .................... ........................ .................................................................7

3.0 PIN CONFIGURATIONS .............................. .. .. ................................. ..............................................9

4.0 PRODUCT SUMMARY TABLES .................................................. .. .. ...................................... .. .. ....9

4.1 Pin Assignm e n ts ...................... .. ............. .. ........................... .. ............. ... ............. .. .. ..................9

4.2 I/O Registe r S u m ma ry ......... .............. .. ............. .. ............. ... ............. .. ............. ... .. ....................10

4.3 Instruction S e t S u mm a r y ........... .. .. ............. ... ............. .. .. ............. ... ............. .. ............. ... .. . ........11

5.0 PROGRAMM I N G M OD E L .................. .. .............. .. .. ............. .. .............. .. ............. .. ... ............. .. .......12

5.1 14-bit Program Counter ............................... ..................... ...................................... .................12

5.1.1 Program Memory Organization ......................................................................................................13

5.2 8-bit Accumulator (A) ...............................................................................................................14

5.3 8-bit Tempo r a ry R e gister (X) ............... .. ............. .. .............. .. .. ............. ... ............. .. ..................14

5.4 8-bit Program Stack Pointer (PSP) ..........................................................................................14

5.4.1 Data Memory Organization ............................................................................................................14

5.5 8-bit Data Stack Pointer (DSP) ................................. .................... .................... .......................15

5.6 Address Modes .......... .. ......................... .. ..................................................... ............................15

5.6.1 Data (Immediate) ...........................................................................................................................15

5.6.2 Direct ..............................................................................................................................................15

5.6.3 Indexed ..........................................................................................................................................15

6.0 CLOCKING ....................................................................................................................................16

CY7C6511

7.0 RESET ...................................... .. .. ............................. .. ............................. .. ...................................16

7.1 Power-on Reset .......................................................................................................................16

7.2 Watchdog Reset ......................................................................................................................17

8.0 SUSPEND MODE .................................. ........................................ .. .. ............................................17

9.0 GENERAL-PURPOSE I/O PORTS .................................... .. .. .................................... .. .. .. .............18

9.1 GPIO Configuration Port ..........................................................................................................19

9.2 GPIO Interrupt Enable Ports ............................ ........................ ................................................20

10.0 12-BIT FREE-RUNNING TIMER ....................... .. .. ......................................................... .............21

11.0 I

12.0 I2C-COMP ATIBLE CONT R OL L E R ... ... ............. .. ............. .. ........................... .. ............. ... ...........22

13.0 PROCESSOR STATUS AND CONTROL REGISTER ...............................................................24

14.0 INTERRUPTS ....................................................................... ............................... ........................25

2

C CONFIGURATION REGISTER ............................................................................................22

14.1 Interrupt Vectors ....................................................................................................................27

14.2 Interrupt Latency ....................................................................................................................28

14.3 USB Bus Reset Interrupt ........................................................................................................28

14.4 Timer Interrupt .......................................................................................................................28

14.5 USB Endpoint Interrupts ........................................................................................................28

14.6 USB Hub Interrupt ..................................................................................................................28

14.7 GPIO Interrupt ........................................................................................................................29

14.8 I

2

C Interrupt ............................................................................................................................29

15.0 USB OVERVIEW .........................................................................................................................30

15.1 USB Serial Interface Engine (SIE) .........................................................................................30

15.2 USB Enumeration ..................................................................................................................30

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TABLE OF CONTENTS (continued)

16.0 USB HUB ....................................................................................................................................31

16.1 Connecting/Disconnecting a USB Device .............................................................................. 31

16.2 Enabling/Disabling a USB Device ..........................................................................................32

16.3 Hub Downs tr e a m P or ts S ta t us a nd C o n tr o l ................... ... ............. .. ............. ... .. ............. .. .....32

16.4 Downstream Port Suspend and Resume .................. .. ............................................... ............34

16.5 USB Upstream Port Status and Control ............................................ .....................................35

17.0 USB SERIAL INTERFACE ENGINE OPERATION ....................................................................36

17.1 USB Device Addresses ..........................................................................................................36

17.2 USB Device Endpoints ...........................................................................................................37

17.3 USB Control Endpoint Mode Registers ..................................................................................37

17.4 USB Non-control Endpoint Mode Registers ........................................ ....................... .. ..........38

17.5 USB Endpoint Counter Registers .......................................................... ................................39

17.6 Endpoint Mode/Count Registers Update and Locking Mechanism ........................................39

18.0 USB MODE TABLES ..................................................................................................................41

19.0 REGISTER SUMMARY .............. .................................. .. .. .... .................................. .. .. .. .. .............45

20.0 SAMPLE SCHEMATIC ...............................................................................................................47

CY7C6511

21.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................47

22.0 ELECTRICAL CHARACTERISTICS ....................... .. ................................................................ ..48

23.0 SWITCHING CHARACTERISTICS

24.0 ORDERING INFORMATION .......................................................................................................49

25.0 PACKAGE DIAGRAMS ........................... .. ................................................................ .................49

(f

= 6.0 MHz) ..................................................................................... 48

OSC

Document #: 38-08002 Rev. *B Page 3 of 51

CY7C6501

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LIST OF FIGURES

Figure 5-1. Pro g ra m M e mory Space wit h In te rrupt Vector T ab le .............. ............. .. ............. .............. 13

Figure 6-1. Clo ck Os cillator On-Ch i p Cir cuit .. .. .. ............. .. .............. .. .......................... ... ............. .. .......16

Figure 7-1. Watchdog Reset (Address 0x26) ......................................................................................17

Figure 9-1. Blo ck Di a g ra m of a GPIO Pin ................. ............. .. .. ............. ... ............. .. .. .............. .. .........18

Figure 9-2. Por t 0 Dat a ..... .. ............. .. .............. .. .. ............. ... ............. .. .. .............. .. ............. ..................18

Figure 9-3. Por t1 Da ta ...... ............. .. .............. .. .. ............. .. .............. .. .. ............. ... ............. .. ..................18

Figure 9-4. Por t 2 Dat a ..... .. ............. .. .............. .. .. ............. ... ............. .. .. .............. .. ............. ..................18

Figure 9-6. GPIO C o n fig u r a tio n R e g is te r .... ... ............. .. .......................... ... ............. .. ............. ... .. .........19

Figure 9-5. Por t 3 Dat a ..... .. ............. .. .............. .. .. ............. ... ............. .. .. .............. .. ............. ..................19

Figure 9-7. Por t 0 Int e rr u p t E na b l e .... .............. .. ............. .. .............. .. .. ............. ... ............. .. ..................20

Figure 9-8. Por t 1 Int e rr u p t E na b l e .... .............. .. ............. .. .............. .. .. ............. ... ............. .. ..................20

Figure 10-1. Ti m e r L SB Re g is t e r .............. .. .............. .. .. ............. .. .............. .. .. ............. ... ......................21

Figure 10-2. Ti m e r MS B R egister .................... .. .. ............. ... ............. .. .. .............. .. ............. .. ................21

Figure 9-9. Por t 2 Int e rr u p t E na b l e .... .............. .. ............. .. .............. .. .. ............. ... ............. .. ..................21

Figure 9-10. Port 3 Interrupt Enable ....................................................................................................21

Figure 10-3. Ti m e r Bl o c k D ia g r a m .............. .............. .. .. ............. .. .............. .. .......................... ... ...........22

Figure 11-1. I
Figure 12-1. I
Figure 12-2. I

Figure 13-1. Processor Status and Control Register ...........................................................................24

Figure 14-1. Global Interrupt Enable Register .....................................................................................25

Figure 14-2. USB Endpoint Interrupt Enable Register .........................................................................26

Figure 14-3. Interrupt Controller Function Diagram .............................................................................27

Figure 14-4. GP IO In t er ru p t Structure ................. ............. ... ............. .. .. .............. .. ............. .. .. .............. 29

Figure 16-1. Hub Ports Connect Status ...............................................................................................31

Figure 16-2. Hub Ports Speed .............................................................................................................31

Figure 16-3. Hub Ports Enable Register ..............................................................................................32

Figure 16-4. Hub Downstrea m P o rts Control Re gi s te r .... . ... ............. .. ............. ... ............. .. ............. .. ... 33

Figure 16-5. Hub P o rt s F o rce Low Registe r .... .. ............. .. .............. .. .. ............. ... ............. .. .. ................33

Figure 16-6. Hub P o rt s F o rce Low Registe r .... .. ............. .. .............. .. .. ............. ... ............. .. .. ................33

Figure 16-7. Hub P o rts SE0 Status Re g i ster .................... ... ............. .. ............. ... ............. .. .. ................33

Figure 16-8. Hub P o rt s D a ta R e g is te r .......................... .. .. .............. .. ............. .. .............. .. .. ..................34

Figure 16-9. Hub Ports Suspend Register ...........................................................................................34

Figure 16-10 . Hub P o rts R e su me Status Reg ister ...................... .............. .. ............. .. .............. .. .........35

Figure 16-11. USB Status and Control Register ..................................................................................35

Figure 17-1. USB Device Address Registers .......................................................................................36

Figure 17-2. USB Device Endpoint Zero Mode Registers ...................................................................37

Figure 17-3. USB Non-control Device Endpoint Mode Registers ........................................................38

Figure 17-4. USB Endpoint Counter Registers ....................................................................................39

Figure 17-5. Token/Data Packet Flow Diagram ...................................................................................40

2

C Configuration Registe r ................. ... .. ............. .. ............. ... ............. .. ............. ... ...........22

2

C Data Regist e r .............. .. ............. .. .............. .. .. ............. .. .............. .. ............. .. .............. 23

2

C Status and Co n trol Register ................................. .. ............. .. ... ............. .. ............. .. ... 23

CY7C6511

Document #: 38-08002 Rev. *B Page 4 of 51

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LIST OF TABLES

Table 4-1. Pin Assignments ..................................................................... ..............................................9

Table 4-2. I/O Register Summary .............. ................................................. .......................... ...............10

Table 4-3. Instruction Set Summary ....................................................................................................11

Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarit y .............................................20

Table 11-1. I
Table 12-1. I

Table 14-1. Interrupt Vector Assignments ................. ...................... ...................... ..............................27

Table 16-1. Control Bit Definition for Downstream Ports ....................... ..............................................33

Table 16-2. Control Bit Definition for Upstream Port .................................. ...................... ...................36

Table 17-1. Memory Allocation for Endpoints ..................................... ...................... ..........................37

Table 18-1. USB Register Mode Encoding ......................... .................................................................41

Table 18-2. Decode table for Table 18-3: “Details of Modes for Differing Traffic Conditions” .............42

Table 18-3. Details of Modes for Differing Traffic Co nditions (see Table 18-2 for the decode legend) 43

2

C Port Configuration .......................................................................................................22

2

C Status and Control Register Bit Definitions ......................................... .................... ....23

CY7C6511

Document #: 38-08002 Rev. *B Page 5 of 51

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1.0 Features

• USB hub with an integrated microcontroller

• 8-bit USB optimized microcontroller
—Harvard arc hitecture

—6-MHz external clock source
—12-MHz internal CPU clock
—48-MHz internal hub clock

• Internal memory
—256 bytes of RAM

—8 KB of PROM

• Integrated Master/Slave I

•I/O ports
—Three GPIO ports (Port 0 to 2) capable of sinking 7 mA per pin (typical)

—An additional GPIO port (Port 3) capable of sinking 12 mA per pin (typical) for high current requirements: LEDs
—Higher current drive achievable by connecting multiple GPIO pins together to drive a common output
—Each GPIO port can be configured as input s with internal pull-ups or open drain output s or traditional CMOS outputs
—Maskable interrupts on all I/O pins

• 12-bit free-running timer with one microsecond clock ticks

• Watchdog timer (WDT)

• Internal Power-on Reset (POR)

• USB Specification compliance
—Conforms to USB Specification, Version 1.1

—Conforms to USB HID Specification, Version 1.1
—Supports one or two device addresses with up to 5 user-configured endpoints

Up to two 8-byte control endpoints
Up to four 8-byte data endpoints

Up to two 32-byte data endpoints
—Integrated USB transceivers
—Supports seven (CY7C65013) or four (CY7C65113) downstream USB ports
—GPIO pins can provide individual power control outputs for each downstream USB port
—GPIO pins can provide individual port over current inputs for each downstream USB port

• Improved output drivers to reduce electromagnetic interference (EMI)

• Operating voltage from 4.0V to 5.5V DC

• Operating temperature from 0° to 70° C

• CY7C65013 available in 48-pin PDIP (-PC) or 48-pin SSOP (-PVC) packages

• CY7C65113 available in 28-pin SOIC (-SC) or 28-pin PDIP (-PC) packages

• Industry-standard programmer support.

2

C-compatible Controller (100 kHz) enabled through General-purpose I/O (GPIO) pins

CY7C6511

Document #: 38-08002 Rev. *B Page 6 of 51

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2.0 Functional Overview

The CY7C65x13 device s are one-time pro grammable 8- bit microc ontrollers with a built- in 12-M bp s USB hu b t hat su pport s up to
seven downstream ports. The microcontroller instruction set has been optimized specifically for USB operations, although the
microcontrollers can be used for a variety of non-USB embedded applications.

GPIO

CY7C65013

The CY7C65013 featur es 22 GPIO pin s to support USB and other applicatio ns. The I/O p ins are grouped int o four port s (P0[7:0],
P1[7:4,2:0], P2[7:3], P3[1:0 ]) where eac h port can be co nfigured as inputs with internal pul l-ups, op en drain outpu ts, or tradi tional
CMOS outputs. Ports 0 to 2 are rated at 7 mA per pin (typical) sink current. Port 3 pins are rated at 12 mA per pin (typical) sink
current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more
drive current capa city. Additionally, ea ch I/O pin c an be u sed to genera te a GPI O inte rrupt to t he micr ocon troller. All of the GPIO
interrupts all share the same “GPIO” interrupt vector.

CY7C65113
The CY7C65113 has 11 GPIO pins (P0[7:0], P1[2:0]), both rated at 7 mA per pin (typical) sink current. Multiple GPIO pins can

be connected together to drive a single output for more drive current capacity.

Clock

The microcontroller us es an ex tern al 6 -MH z cry st a l an d an i nter nal oscillator to provide a referenc e to an inte rnal phase-locked
loop (PLL)-based clock generator. This technology allows the customer application to use an inexpensive 6-MHz fundamental
crystal that red uces the clock-related no ise emissions (EMI). A PLL cl ock generator provides the 6 -, 12-, and 48-MHz clock s ignals
for distribution within the microcontroller.

Memory

The CY7C65013 and the CY7C65113 are offered with 8 KB of PROM.

Power-on Reset, Watchdog, and Free-running Timer

These parts in clude power-o n reset logic , a Wa tchdog timer, and a 12-bit free-running timer. The PO R logic detect s when power
is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address 0x0000. The
Watchdog timer is u sed to ensure the mi crocontrol ler rec overs afte r a perio d of ina ctivi ty. The firmware may become inactive for
a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs.

2

C

I

2

The microcontroller can communicate with external electronics through the GPIO pins. An I
dates a 100-kHz serial link with an external device.

Timer

The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-µs and 1.024-ms. The timer can be used to
measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is
complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of
the timer are lat ched into an internal regi ster when the firmware reads the lower e ight bits. A read from th e upper four bits actually
reads data from the inte rnal register , in stead of the ti mer . This featur e eliminates the ne ed for firmware to t ry to compensate if the
upper four bits increment immediately after the lower eight bits are read.

Interrupts

The microcontroller su ppo rts ten maskable interrupt s in the vectored interrupt contro lle r. Interrupt sources include the USB Bus
Reset interrupt, the 128-µs (bit 6 ) and 1.024-ms (bi t 9) outpu ts from the free -running ti mer, five USB end points, the USB h ub, the
GPIO ports, and the I
from LOW ‘0’ to HIGH ‘1’. Th e USB endpoi nts i nterrupt afte r the USB h ost has w ritten dat a to the endpoint FIFO or after the USB
controller sends a p ac ke t to th e U SB hos t. T he GPIO ports also hav e a le vel of masking to select w hic h GPI O inp uts can cause
a GPIO interrupt. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt
polarity can be rising edge (‘0’ to ‘1’) or falling edge (‘1’ to ‘0’).

USB

The CY7C65013 and CY7C65113 include an integrated USB Serial Interface Engine (SIE) that supports the integrated periph­erals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the
hub (two endpoint s) and a device address for a compoun d device (three end points). The SIE a llows the USB host to c ommunicate
with the hub and fu nctions integrated into the microcon troller . The CY7C651 13 p art includes a 1:4 hub repeater with one upstream
port and four downstream ports, while the CY 7C65013 part inclu des a 1:7 hub repeater . The USB Hub allows power management
control of the downstream ports by using GPIO pins assigned by the user firmware. The user has the option of ganging the
downstream ports together with a single pair of power management pins, or providing power management for each port with four
(CY7C65113) or seven (CY7C65013) pairs of power management pins.

2

C-compatible master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles

C-compatible interface ac commo-

CY7C6511

Document #: 38-08002 Rev. *B Page 7 of 51

CY7C6501

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Logic Block Diagram

CY7C6511

6-MHz crystal

PLL

48 MHz

Clock

Divider

6 MHz

12 MHz

12-MHz

8-bit

CPU

PROM

8 KB

RAM

256 byte

12-bit
Timer

8-bit Bus

USB

SIE

Interrupt

Controller

GPIO

PORT 0

P0[0]

P0[7]

USB

Transceiver

Repeater

D+[0]

Upstream
USB Port

D–[0]

Downstream USB Ports

USB

Transceiver

USB

Transceiver

USB

Transceiver

USB

Transceiver

CY7C65013 only

Power management under firmware

control using GPIO pins

D+[1]
D–[1]

D+[4]
D–[4]

D+[5]
D–[5]

D+[7]
D–[7]

Watchdog

Timer

Power-on

Reset

GPIO

PORT 1

GPIO

PORT 2

GPIO

PORT 3

I2C comp.
Interface

2

*I

C-compatible interface enabled by firmware through

P2[1:0] or P1[1:0]

P1[0]

P1[2]

P2[7]

P2[3]

High Current

P3[1]

Outputs

P3[0]

CY7C65013 only

SCLK
SDATA

Document #: 38-08002 Rev. *B Page 8 of 51

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3.0 Pin Configurations

XTALOUT

XTALIN

48-pin SSOP

P1[1]
P1[5]
P1[7]
P3[1]
D+[0]

D–[0]

GND

D+[1]

D–[1]

V

REF

D+[2]

D–[2]

P2[3]

GND
P2[5]
D+[7]

D–[7]

P2[7]
P0[7]
P0[5]
P0[3]
P0[1]

CY7C65013

48

1
2

47
46

3
4

45

5

44
43

6

42

7

41

8
9

40
39

10
11

38
37

12
13

36
35

14

34

15
16

33

17

32
31

18
19

30
29

20
21

28

22

27

23

26
25

24

CY7C6501

Top View

CY7C65113

28-pin SOIC

V

CC

P1[0]
P1[2]
P1[4]
P1[6]
P3[0]
D–[3]
D+[3]

GND
D–[4]
D+[4]
V

REF

D–[5]
D+[5]
GND
P2[4]
D–[6]
D+[6]
P2[6]
V

PP

P0[0]
P0[2]
P0[4]
P0[6]

XTALOUT

XTALIN

V
GND

D+[0]

D–[0]

D+[1]

D–[1]

D+[2]

D–[2]

P0[7]
P0[5]
P0[3]
P0[1]

REF

1

28

V
2
3
4

5
6
7
8
9
10
11
12
13
14

CC

27

P1[1]

26

P1[0]

P1[2]

25

D–[3]

24

D+[3]

23

D–[4]

22

D+[4]

21

GND

20
19

V

PP

18

P0[0]

17

P0[2]

P0[4]

16
15

P0[6]

CY7C6511

4.0 Product Summary Tables

4.1 Pin Assignments

Table 4-1. Pin Assignments

Name I/O 48-pin 28-pin Description

D+[0], D–[0] I/O 7, 8 5, 6 Upstream port, USB differential data.
D+[1], D–[1] I/O 10, 11 7, 8 Downstream Port 1, USB differential data.
D+[2], D–[2] I/O 13, 14 9, 10 Downstream Port 2, USB differential data.
D+[3], D– [3] I/ O 41, 42 23, 24 Downstream Port 3, US B differential data.
D+[4], D– [4] I/ O 38, 39 21, 22 Downstream Port 4, US B differential data.
D+[5], D–[5] I/O 35, 36 Downstream Port 5, USB differential data.
D+[6], D–[6] I/O 31, 32 Downstream Port 6, USB differential data.
D+[7], D–[7] I/O 18, 19 Downstream Port 7, USB differential data.
P0 I/O P1[7:0]

21, 25, 22, 26, 23, 27,
24, 28

P1 I/O P1[7:4,2:0]

5, 44, 4, 45; 46, 3, 47

P2 I/O P2[7:3]

20, 30, 17,33, 15

P3 I/O P3[1:0]

6, 43

XTAL

IN

IN 2 2 6-MHz crystal or external clock input.

P1[7:0]
11, 15, 12, 16, 13,
17, 14, 18

P1[2:0]
25, 27, 26

GPIO Port 0 capable of sinking 7 mA (typical).

GPIO Port 1 capable of sinking 7 mA (typical).

GPIO Port 2 capable of sinking 12 mA (typical).

GPIO Port 3, capable of sinking 12 mA (typical).

Document #: 38-08002 Rev. *B Page 9 of 51

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Table 4-1. Pin Assignments (continued)

Name I/O 48-pin 28-pin Description

XTAL

OUT

V

PP

V

CC

GND 9, 16, 34, 40 4, 20 Ground.
V

REF

4.2 I/O Register Summary

I/O registers are accessed v ia the I/O Read (IORD) a nd I/O W rite (IOWR , IOWX) instructi ons. IORD reads data from the sel ected
port into the accumu lator . IOWR perform s the revers e; it wri tes dat a from the a ccumulator to the sel ected por t. Indexed I/O W rite
(IOWX) adds the co ntent s of X to t he add ress in th e ins tructio n to form the p ort add ress a nd wri tes da ta from th e acc umula tor t o
the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X.

All undefined registers are reserved. Do not write to reserved registers as this may cause an undefined operation or increased
current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with ‘0.’

Table 4-2. I/O Register Summary

Port 0 Data 0x00 R/W GPIO Port 0 Data 18
Port 1 Data 0x01 R/W GPIO Port 1 Data 17
Port 2 Data 0x02 R/W GPIO Port 2 Data 17
Port 3 Data 0x03 R/W GPIO Port 3 Data 19
Port 0 Interrupt Enable 0x04 W Interrupt Enable for Pins in Port 0 19
Port 1 Interrupt Enable 0x05 W Interrupt Enable for Pins in Port 1 19
Port 2 Interrupt Enable 0x06 W Interrupt Enable for Pins in Port 2 19
Port 3 Interrupt Enable 0x07 W Interrupt Enable for Pins in Port 3 19
GPIO Configuration 0x08 R/W GPIO Port Configurations 18

2

C Configuration 0x09 R/W I2C Position Configuration 20

I
USB Device Address A 0x10 R/W USB Device Address A 36
EP A0 Counter Register 0x11 R/W USB Address A, Endpoint 0 Counter 38
EP A0 Mode Register 0x12 R/W USB Address A, Endpoint 0 Configuration 37
EP A1 Counter Register 0x13 R/W USB Address A, Endpoint 1 Counter 38
EP A1 Mode Register 0x14 R/W USB Address A, Endpoint 1 Configuration 38
EP A2 Counter Register 0x15 R/W USB Address A, Endpoint 2 Counter 38
EP A2 Mode Register 0x16 R/W USB Address A, Endpoint 2 Configuration 38
USB Status & Control 0x1F R/W USB Upstream Port Traffic Status and Control 35
Global Interrupt Enable 0x20 R/W Global Interrupt Enable 25
Endpoint Interrupt Enable 0x21 R/W USB Endpoint Interrupt Enables 26
Interrupt Vector 0x23 R Pending Interrupt Vector Read/Clear 27
Timer (LSB) 0x24 R Lower Eight Bits of Free-running Timer (1 MHz) 20
Timer (MSB) 0x25 R Upper Four Bits of Free-running Timer 20
WDR Clear 0x26 W Watchdog Reset Clear 17

2

C Control & Sta tus 0x28 R/W I2C Status and Control 21

I

2

C Data 0x29 R/W I2C Data 23

I

OUT 1 1 6-MHz crystal out.

29 19 Programming voltage supply, tie to ground during normal

operation.

48 28 Voltage supply.

IN 12, 37 3 External 3.3V supply voltage for the down stream dif ferential

data output buffers and the D+ pull up.

Register Name I/O Address Read/Write Function Page

CY7C6511

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CY7C6501

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Table 4-2. I/O Register Summary (continued)

Register Name I/O Address Read/Write Function Page

Reserved 0x30 Reserved
Reserved 0x31 Reserved
Reserved 0x32 Reserved
Reserved 0x38-0x3F Reserved
USB Device Address B 0x40 R/W USB Device Address B (not used in 5-endpoint mod e) 36
EP B0 Counter Register 0x41 R/W USB Address B, Endpoint 0 Counter 38
EP B0 Mode Register 0x42 R/W USB Address B, Endpoint 0 Configuration, or

USB Address A, Endpoint 3 in 5-endpoint mode
EP B1 Counter Register 0x43 R/W USB Address B, Endpoint 1 Counter 38
EP B1 Mode Register 0x44 R/W USB Address B, Endpoint 1 Configuration, or

USB Address A, Endpoint 4 in 5-endpoint mode
Hub Port Connect Status 0x48 R/W Hub Downstream Port Connect Status 31
Hub Port Enable 0x49 R/W Hub Downstream Ports Enable 32
Hub Port Speed 0x4A R/W Hub Downstream Ports Speed 31
Hub Port Control (Ports [4:1]) 0x4B R/W Hub Downstream Ports Control (Ports [4:1]) 33
Hub Port Control (Ports [7:5]) 0x4C R/W Hub Downstream Ports Control (Ports [7:5]) 33
Hub Port Suspend 0x4D R/W Hub Downstream Port Suspend Control 34
Hub Port Resume Status 0x4E R Hub Downstream Ports Resume Status 35
Hub Ports SE0 Status 0x4F R Hub Downstream Ports SE0 Status 33
Hub Ports Data 0x50 R Hub Downstream Ports Differential Data 34
Hub Downstream Force Low 0x51 R/W Hub Downstream Ports Force LOW (Ports [1:4]) 33
Hub Downstream Force High 0x52 R/W Hub Downstream Ports Force HIGH (Ports [5:7]) 33
Processor Status & Control 0xFF R/W Microprocessor Status and Control Register 24

CY7C6511

37

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4.3 Instruction Set Summary

Refer to the CYASM Assembler User’s Guide for more details. Note that conditional jump instructions (i.e. JC, JNC, JZ, JNZ)
take five cycles if jump is taken, four cycles if no jump.

Table 4-3. Instruction Set Summary

MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles

HALT 00 7 NOP 20 4
ADD A,expr data 01 4 INC A acc 21 4
ADD A,[expr] direct 02 6 INC X x 22 4
ADD A,[X+expr] index 03 7 INC [expr] direct 23 7
ADC A,expr data 04 4 INC [X+expr] index 24 8
ADC A,[expr] direct 05 6 DEC A acc 2 5 4
ADC A,[X+expr] index 06 7 DEC X x 26 4
SUB A,expr data 07 4 DEC [expr] direct 27 7
SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8
SUB A,[X+expr] index 09 7 IORD expr address 29 5
SBB A,expr data 0A 4 IOWR expr address 2A 5
SBB A,[expr] direct 0B 6 POP A 2B 4
SBB A,[X+expr] index 0C 7 POP X 2C 4
OR A,expr data 0D 4 PUSH A 2D 5

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CY7C6501

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Table 4-3. Instruction Set Summary (continued)

MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles

OR A,[expr] direct 0E 6 PUSH X 2E 5
OR A,[X+expr] index 0F 7 SWAP A,X 2F 5
AND A,expr data 10 4 SWAP A,DSP 30 5
AND A,[expr] direct 11 6 MOV [expr],A direct 31 5
AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6
XOR A,expr data 13 4 OR [ex pr],A direct 33 7
XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8
XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7
CMP A,expr data 16 5 AND [X+expr],A index 36 8
CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7
CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8
MOV A,expr data 19 4 IOWX [X+expr] index 39 6
MOV A,[expr] direct 1A 5 CPL 3A 4
MOV A,[X+expr] index 1B 6 ASL 3B 4
MOV X,expr data 1C 4 ASR 3C 4
MOV X,[expr] direct 1D 5 RLC 3D 4
reserved 1E RRC 3E 4
XPAGE 1F 4 RET 3F 8
MOV A,X 40 4 DI 70 4
MOV X,A 41 4 EI 72 4
MOV PSP,A 60 4 RETI 73 8
CALL addr 50-5F 10 JC addr C0-CF 5 (or 4)
JMP addr 80-8F 5 JNC addr D0-DF 5 (or 4)
CALL addr 90-9F 10 JACC addr E0-EF 7
JZ addr A0-AF 5 (or 4) INDEX addr F0-FF 14
JNZ addr B0-BF 5 (or 4)

CY7C6511

5.0 Programming Model

5.1 14-bit Program Counter

The 14-bit Program Counter (PC) allows access to up to 8 KB of PROM available with the CY7C65x13 architecture. The top
32 bytes of the ROM in the 8K part are re serve d for testing purposes. The program c ounter is clea red during re set, su ch that the
first instruction e xecuted a fter a res et is a t addres s 0x0 000h. Typically, this is a jum p ins tructio n to a res et han dler tha t initializes
the application (see Interrupt Vectors on page 27).

The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the
program counter are increm ented by executing an XP AGE instructi on. As a result, the las t instruction exec uted within a 256-by te
“page” of sequen tial cod e should be an XPAGE instruction. The assemble r directive “XPAGEON” causes the as sembler to insert
XPAGE instructions au tomatical l y. Because instructions can be either one or two bytes lon g, the assembler may occasionally
need to insert a NOP followed by an XPAGE to execute correctly.

The address of the next ins truction to be execute d, the carry fl ag, and the zero fl ag are save d as two bytes on the progra m stack
during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the
program stack during a RETI instruction. Only the program counter is restored during a RET instruction.

The program counter ca nnot be accesse d direct ly by the firm ware . The progr am st ack can be exam ined by read in g SRAM from
location 0x00 and up.

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5.1.1 Program Memory Organization

after reset Address

14-bit PC 0x0000 Program execution begins here after a reset

0x0002 USB Bus Reset interrupt vector

0x0004 128-µs timer interrupt vector

0x0006 1.024-ms timer interrupt vector

0x0008 USB address A endpoint 0 interrupt vector

0x000A USB address A endpoint 1 interrupt vector

0x000C USB address A endpoint 2 interrupt vector

0x000E USB address B endpoint 0 interrupt vector

CY7C6501

CY7C6511

0x0010 USB address B endpoint 1 interrupt vector

0x0012 Hub interrupt vector

0x0014 Reserved

0x0016 GPIO interrupt vector

0x0018

0x001A Program Memory begi ns here

I2C interrupt vector

0x1FDF (8 KB -32) PROM ends here (CY7C65013, CY7C65113)

Figure 5-1. Program Memory Space with Interrupt Vector Table

Note that

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the upper 32 bytes of the 8K PROM are reserved. Therefore, user’s program must not overwrite this space.

CY7C6501

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5.2 8-bit Accumulator (A)

The accumulator is the general-purpose register for the microcontroller.

5.3 8-bit Temporary Register (X)

The “X” register is available to the firmware for temporary st orage of intermediate resul ts. The microcontroller can perform indexed
operations based on the value in X. Refer to Section 5.6.3 for additional information.

5.4 8-bit Program Stack Pointer (PSP)

During a reset, the Program Stack Pointer (PSP) is set to 0x00 and “grows” upward from this address. The PSP may be set by
firmware, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and
RETI instructions under firmware control. The PSP is not readable by the firmware.

During an interrupt a ck nowl edge, interrupts are dis abl ed and the 14-bit program coun ter, carry flag, and zero flag are written as
two bytes of dat a memory . The first byte is stored in the me mory addresse d by the PSP, then the PSP is increm ented. The second
byte is stored in memory addressed by the PSP, and the PSP is incremented again. The overall effect is to store the program
counter and flags on the program “stack” and increment the PSP by two.

The Return From Interr upt (RETI) instruc tion decrem ents the PSP, then restores the second byt e from memor y addressed by the
PSP . The PSP is decremented again and the first byte is restored from memory ad dressed by the PSP. After the program counter
and flags have b een rest ored from s tack, th e interrupt s are enab led. The o verall ef fect is t o restore the program counter and flags
from the program stack, decrement the PSP by two, and re-enable interrupts.

The Call Subroutine (CALL) instruction stor es the prog ram coun ter and fla gs on the prog ram st ac k and inc rem en t s the PSP by
two.

The Return From Subroutine (RET) instruction restores the program counter but not the flags from the program stack and
decrements the PSP by two.

CY7C6511

5.4.1 Data Memory Organization

The CY7C65x13 microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program
stack, user va riables, data s tack, and USB e ndpoint FIFOs. The following is one ex ample of where the program stack, dat a stack ,
and user variables areas could be located.

After reset Address

8-bit DSP 8-bit PSP 0x00 Program Stack Growth

(Move DSP

8-bit DSP

Notes:

1. Refer to Section 5.5 for a description of DSP.

2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7). See Table17-1.

[1]

)

user selected Data Stack Growth

User variables

USB FIFO space for up to tw o Address es and f ive endp oint s

0xFF

[2]

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CY7C6501

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5.5 8-bit Data Stack Pointer (DSP)

The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH
instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads
data from the memory location addressed by the DSP, then post-increments the DSP.

During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM
(address 0xFF). This writes dat a to the memory area res erved fo r USB en dp oin t FIFO s. There fore , the DSP shou ld b e ind ex ed
at an appropriate memory location that does not compromise the Program Stack, user-de fin ed me mory (variables), or the USB
endpoint FIFOs.

For USB applications , the firmware s hould set the DSP to an appropri ate location to avoid a mem ory conflict w ith RAM dedic ated
to USB FIFOs. The me mo ry requirements for the U SB en dpo ints are described in Sec t io n 1 7.2. Exa mp le as se mbl y ins truc ti ons
to do this with two device addresses (FIFOs begin at 0xD8) are shown below:

MOV A,20h ; Move 20 hex into Accumulator (must be D8h or less)
SWAP A,DSP ; swap accumulator value into DSP register.

5.6 Address Modes

The CY7C65013 and CY 7C65113 microcontrollers support three addressin g modes for ins tructions that require da ta opera nds::
data, direct, and indexed.

5.6.1 Data (Immediate)

“Data” address m ode refers t o a data operand th at is actuall y a cons tant en coded in t he instruc tion. As an example, c onsider th e
instruction that loads A with the constant 0xD8:

• MOV A, 0D8h.

This instruction requires two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction is the constant “0xD8.” A constant may be referred to by name if a prior “EQU”
statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:

• DSPINIT: EQU 0D8h

• MOV A, DSPINIT.

CY7C6511

5.6.2 Direct

“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the
variable is encode d in the instruction. As an example, consider an ins truction that loads A with the c onte nt s of memory address
location 0x10:

• MOV A, [10h].

Normally , varia ble names ar e assigned to va riable address es using “EQU” st atements to improve the re adability of th e assembler
source code. As an example, the following code is equivalent to the example shown above:

• buttons: EQU 10h

• MOV A, [buttons].

5.6.3 Indexed

“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is
the sum of a constan t encoded in the instru ction and the con tents of the “X” register . Norma lly , the co nstant is th e “base” address
of an array of data and the X register contains an index that indicates which element of the array is actually addressed:

• array: EQU 10h

•MOV X, 3

• MOV A, [X+array].

This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10. The fourth
element would be at address 0x13.

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6.0 Clocking

XTALOUT

(pin 1)

CY7C6501

CY7C6511

XTALIN

(pin 2)

30 pF

Figure 6-1. Clock Oscillator On-Chip Circuit

The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to
these pins. When u si ng an ex ternal crystal, kee p PC B trac es b etw ee n t he ch ip leads and cryst al as s hort as p os si ble (l ess t han
2 cm). A 6-MHz fundament al frequency p arallel resonan t crystal can be c onnected to these p ins to provide a refe rence frequency
for the internal PLL. The two int ernal 30-pF lo ad caps app ear in series to the externa l cryst al and would be equivalen t to a 15-pF
load. Therefore, the crystal must have a required load capacitance of about 15–18 pF. A ceramic resonator does not allow the
microcontroller to meet the timing specifications of full speed USB and therefore a ceramic resonator is not recommended with
these parts.

An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Grounding the XTALOUT pin when
driving XTALIN with an oscillator does not work because the internal clock is effectively shorted to ground.

To Internal PLL

30 pF

7.0 Reset

The CY7C65x13 supports two resets: POR and WDR. Each of these resets causes:

• all registers to be restored to their default states

• the USB device addresses to be set to 0

• all interrupts to be disabl ed

• the PSP and DSP to be set to memory address 0x00.

The occurrence of a reset is recorded in the Processor Status and Control Register, as described in Section. Bits 4 and 6 are
used to record the occurrence of POR and WDR respectively. Firmware can interrogate these bits to determine the cause of a
reset.

Program execution st arts at ROM address 0x000 0 af ter a re set . Although this looks like int errup t ve cto r 0, the re is an imp ort a n t
difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. The firmware
reset handler shou ld configure the hardw are before t he “main” loop of code. Attempting to execute a R ET or RETI in the firmw are
reset handler causes unpredictable execution results.

7.1 Power-on Reset

When VCC is first applied to the c hip, th e POR si gnal is asse rted and the C Y7C65x13 enters a “sem i-susp end” st ate . Durin g the
semi-suspend st ate, which i s diff erent from the suspend sta te defined i n the USB spec ification , the osci llator and al l other bl ocks
of the part are functional, except for the CPU. This semi-suspend time ensures that both a valid V
the internal PLL has time to stabilize before full operation begins. When the V
oscillator is st able, the POR is d easserted and th e on-chip timer st arts countin g. The first 1 ms of s uspend time is no t interruptible,
and the semi-suspe nd state conti nues for an addition al 95 ms unless the count is bypasse d by a USB Bus Reset on the up stream
port. The 95 ms provides time for V

If a USB Bus Reset occurs on the upstream port during the 95 ms semi-suspend time, the semi-suspend state is aborted and
program execution begins immediately from address 0x0000. In this case, the Bus Reset interrupt is pending but not serviced
until firmware sets the USB Bus Reset Interrupt Enable bit (Bit 0, Figure 14-1) and enables interrupts with the EI command.

The POR signal is asserte d whenever V
again. Behavior is the same as described above.

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to stabilize at a valid operating voltage before the chip executes code.

CC

drops below approxim ately 2.5V , and remains ass erted until VCC rises above this level

CC

has risen above approximately 2.5V, and the

CC

level is reached and that

CC