1July 6,
200100CY7C65013
CY7C65013
CY7C65113
CY7C65013
CY7C65113
USB Hub with Microcontroller
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 6, 2001
CY7C65013
CY7C65113
TABLE OF CONTENTS
1.0 FEATURES .............................................. .............................. ........................... ..............................5
2.0 FUNCTIONAL OVERVIEW ....................................... .. ...................................... ..............................6
3.0 PIN CONFIGURATIONS ... ........................... .. .. ........................... .. .. .. ........................... ...................8
4.0 PRODUCT SUMMARY TABLES ............... .. .... ................................. ................................ .. .. .. .. .. ....9
4.1 Pin Assignme n ts ...... .. ............... ... ............... .. ................ ............... .. ................ .. .............................9
4.2 I/O Registe r Summary ........... ................ .. ............... ................ .. ............... ................ .. ....................9
4.3 Instruction Set Summary ............................................................................................................ 11
5.0 PROGRAMM I N G M OD E L ....... .. ................ .. ............... ... ............... ................ .. ............... .. ..............12
5.1 14-Bit Program Counter (PC) ......................................................................................................12
5.1.1 Program Memory Organization .........................................................................................................13
5.2 8-Bit Accumulator (A) ..................................................................................................................14
5.3 8-Bit Temporary Register (X) ......................................................................................................14
5.4 8-Bit Program Stack Pointer (PSP) ............................................................................................14
5.4.1 Data Memory Organization ................................................................................................................14
5.5 8-Bit Data Stack Pointer (DSP) ...................................................................................................15
5.6 Address Modes ............................................................................................................................15
5.6.1 Data (Immediate) .................................................................................................................................15
5.6.2 Direct ...................................................................................................................................................15
5.6.3 Indexed ................................................................................................................................................15
6.0 CLOCKING ....................................................................................................................................16
7.0 RESET .................................. .. .......................... ......................... .. .. ................................................16
7.1 Power-On Reset (POR) ................................................................................................................16
7.2 Watch Dog Reset (WDR) .............................................................................................................17
8.0 SUSPEND MODE ............................ .. .. .. .................................. .. .. .. .. ..............................................17
9.0 GENERAL-PURPOSE I/O (GPIO) PORTS ............................................................ .. .....................18
9.1 GPIO Configuration Port .............................................................................................................19
9.2 GPIO Interrupt Enable Ports ............................. ................... .......................................................20
10.0 12-BIT FREE-RUNNING TIMER ......................... .. ............................................... .. .....................20
10.1 Timer (LSB ) ............. ............... .. ................ .. ................ ............... .. ................ .. .............................20
10.2 Timer (MSB) ...... ................ .. ............... ................ .. ............... ... ............... .. ................ ....................20
2
11.0 I
12.0 I
C CONFIGURATION REGISTER ..............................................................................................21
2
C COMPATIB L E CO N T R O L L ER ........... .. .. ................ ............... .. ................ .. ................ .. .........21
13.0 PROCESSOR STATUS AND CONTROL REGISTER ............................ ...................................23
14.0 INTERRUPTS .................................... .. ..................................................... ...................................24
14.1 Interrup t V e c to r s ............................. .. ................ .. ............... ................ .. ................ .. ....................24
14.2 Interrupt Latency .......................................................................................................................26
14.3 USB Bus Reset Interrupt ...........................................................................................................26
14.4 Timer Inter rupt .............. ... ............... ................ .. ............... .. ................ ............... ... ......................26
14.5 USB Endpoint Interrupts ...........................................................................................................26
14.6 USB Hub Interrupt .....................................................................................................................26
14.7 GPIO Interrupt ............................................................................................................................27
2
14.8 I
C Interrupt ............... ............... ................ .. ................ ............... .. ................ ............... .. . .............27
15.0 USB OVERVIEW .........................................................................................................................28
2
CY7C65013
CY7C65113
15.1 USB Serial Interface Engine (SIE) ........................ .................. .. .................. .. ............................28
15.2 USB Enumeration ......................................................................................................................28
16.0 USB HUB ....................................................................................................................................29
16.1 Connecting/Disconnecting a USB Device .......................................................... .....................29
16.2 Enabling/Disabling a USB Device ............................................................................................29
16.3 Hub Downstream Ports Status and Control .................................................... ........................30
16.4 Downstream Port Suspend and Resume .......... .. .. ....................... .. .........................................31
16.5 USB Upstream Port Status and Control .............................................................................. ....32
17.0 USB SERIAL INTERFACE ENGINE OPERATION ....................................................................33
17.1 USB Device Addresses .............................................................................................................33
17.2 USB Device Endpoints ..............................................................................................................33
17.3 USB Control Endpoint Mode Registers ...................................................................................34
17.4 USB Non-Control Endpoint Mode Registers ............................. ..............................................34
17.5 USB Endpoint Counter Registers ............................................................................................35
17.6 Endpoint Mode/Count Registers update and Locking Mechanism ......................................35
18.0 USB MODE TABLES ..................................................................................................................37
19.0 SAMPLE SCHEMATIC ................................................................................................................41
20.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................42
21.0 ELECTRICAL CHARACTERISTICS ................... .. .. .. ........................... ........................... ............42
22.0 SWITCHING CHARACTERISTICS ............................................. .. .. ............................. .. .............43
23.0 ORDERING INFORMATION .......................................................................................................43
24.0 PACKAGE DIAGRAMS ........................... .. .. .. ........................... .. .. ........................... ...................44
LIST OF FIGURES
Figure 5-1. Program Memory Space with Interrupt Vector Table .................. .................... ............13
Figure 6-1. Clock Oscillator On-Chip Circuit ................. .................... ...................................... ........16
Figure 7-1. Watch Dog Reset (WDR) ................................... .................. ...........................................17
Figure 9-1. Block Diagram of a GPIO Pin ...................................................... ...................... .. ..........18
Figure 9-2. Port 0 Data 0x00 (read/write) ................................ .. .......................................................18
Figure 9-3. Port 1 Data 0x01 (read/write) ................................ .. .......................................................18
Figure 9-4. Port 2 Data 0x02 (read/write) ................................ .. .......................................................18
Figure 9-5. Port 3 Data 0x03 (read/write) ................................ .. .......................................................18
Figure 9-6. GPIO Configuration Register 0x08 (read/write) .................... .................... ...................19
Figure 9-7. Port 0 Interrupt Enable 0x04 (read/write) .............. .................... .................. .. ...............20
Figure 9-8. Port 1 Interrupt Enable 0x05 (read/write) .............. .................... .................. .. ...............20
Figure 9-9. Port 2 Interrupt Enable 0x06 (read/write) .............. .................... .................. .. ...............20
Figure 9-10. Port 3 Interrupt Enable 0x07 (read/write) ............. ......................................................20
Figure 10-1. Timer Register 0x24 (read only) .................................. .................... .................... .. ......20
Figure 10-2. Timer Register 0x25 (read only) .................................. .................... .................... .. ......20
Figure 10-3. Timer Block Diagram .............................. ...................... .. ...................... ........................21
Figure 11-1. I
Figure 12-1. I
Figure 12-2. I
2
C Configuration Register 0x09 (read/write) .............................................................21
2
C Data Register 0x29 (separate read/write registers) ................................ .............22
2
C Status and Control Register 0x28 (read/write) ....................................................22
Figure 13-1. Processor Status and Control Register 0xFF ............................................................23
Figure 14-1. Global Interrupt Enable Register 0x20 (read/write) ...................................................24
Figure 14-2. USB Endpoint Interrupt Enable Register 0x21 (read/write) ......................................24
3
CY7C65013
CY7C65113
Figure 14-3. Interrupt Controller Functional Diagram ....................................................................25
Figure 14-4. Interrupt Vector Register 0x23 (read only) .................................................................26
Figure 14-5. GPIO Interrupt Structure ..............................................................................................27
Figure 16-1. Hub Ports Connect Status 0x48 (read/write), 1 = connect, 0 = disconnect .............29
Figure 16-2. Hub Ports Speed 0x4A (read/write), 1 = Low-Speed, 0 = Full-Speed ........... ............29
Figure 16-3. Hub Ports Enable Register 0x49 (read/write), 1 = Enabled, 0 = Disabled ................30
Figure 16-4. Hub Downstream Ports Control Register 0x4B (read/write) ................ .....................30
Figure 16-5. Hub Ports Force Low Register (read/write) 0x51, 1 = Force Low, 0 = no force ......31
Figure 16-6. Hub Ports Force High Register (read/write) 0x52, 1=For ce High, 0=no force .........31
Figure 16-7. Hub Ports SE0 Status Register 0x4F (read only), 1 = SE0, 0 = non-SE0 .................31
Figure 16-8. Hub Ports Data Register 0x50 (read only), 1 = (D+ > D–), 0 = (D+ < D–) ..................31
Figure 16-9. Hub Ports Suspend Register 0x4D (read/write),
1 = Port is Selectively Suspended ............................. ..................................................... ...................31
Figure 16-10. Hub Ports Resume Status Register 0x4E (read only),
1 = Port is in Resume State ............... ................................................................................................. 32
Figure 16-11. USB Status and Control Register 0x1F (read/write) ................ .. ...................... .. ......32
Figure 17-1. USB Device Address Registers 0x10, 0x40 (read/write) ...................... .................... .33
Figure 17-2. USB Device Endpoint Zero Mode Registers 0x12 and 0x42, (read/write) ...............34
Figure 17-3. USB Non-Control Device Endpoint Mode Registers
0x14, 0x16, 0x44, (read/write) ............................... ................................................... ..........................35
Figure 17-4. USB Endpoint Counter Registers 0x11, 0x13, 0x15, 0x41, 0x43 (read/wri te) ..........35
Figure 17-5. Token/Data Packet Flow Diagram ................................... .................... .................... .. ..36
Figure 22-1. Clock Timing .................................... ...................... .......................................................43
Figure 22-2. USB Data Signal Timing ............................................. .................... .. .................... ........43
LIST OF TABLES
Table 4-1. Pin Assignments ............. .................... ........................................ .................... .. .................9
Table 4-2. I/O Register Summary ............................................................................ ............................9
Table 4-3. Instruction Set Summary .............................................................. ...................................11
Table 9-1. Port Configurations .................................................. ................ .......................................19
Table 11-1. I
Table 12-1. I
2
C Port Config u r a tio n .... .. ............... ................ .. ............... ... ............... .. ................ .........21
2
C Status and Control Register Bit Definitions ..........................................................22
Table 14-1. Interrupt Vector Assignments ................................. ................................... ...................25
Table 16-1. Control Bit Definition for Downstream Ports ....................... .......................................30
Table 16-2. Control Bit Definition for Upstream Port ................. ....................................... .............33
Table 17-1. Memory Allocation for Endpoints ........................................... .. .................... ...............34
Table 18-1. USB Register Mode Encoding ............................................................ .. ........................37
Table 18-2. Decode table for
Table 18-3
: “Details of Modes for Differing Traffic Conditions” ...38
Table 18-3. Details of Modes for Differing Traffic Conditions ..................................................... ..39
4
CY7C65013
CY7C65113
1.0 Features
• USB Hub with an integrated microcontroller
• 8-bit USB Optimized Microcontroller
—Harvard architecture
—6-MHz external clock source
—12-MHz internal CPU clock
—48-MHz internal Hub clock
• Internal memory
—256 bytes of RAM
—8 KB of PROM
• Integrated Master/Slave I
•I/O ports
—Three GPIO ports (Port 0 to 2) capable of sinking 7 mA per pin (typical)
—An additional GPIO port (Port 3) capable of sinking 12 mA per pin (typical) for high current requirements: LEDs
—Higher current drive achievable by connecting multiple GPIO pins together to drive a common output
—Each GPIO port can be configure d as inputs with internal pull-ups or open drain outputs o r traditional CMOS outputs
—Maskable interrupts on all I/O pins
• 12-bit free-running timer with one microsecond clock ticks
• Watch Dog Timer (WDT)
• Internal Power-On Reset (POR)
• USB Specification Compliance
—Conforms to USB Specification, Version 1.1
—Conforms to USB HID Specification, Version 1.1
—Supports one or two device addresses with up to 5 user-configured endpoints
Up to two 8-byte control endpoints
Up to four 8-byte data endpoints
Up to two 32-byte data endpoints
—Integrated USB transceivers
—Supports 7 (CY7C65013) or 4 (CY7C65113) Downstream USB ports
—GPIO pins can provide individual power control outputs for each Downstream USB port
—GPIO pins can provide individual port over current inputs for each Downstream USB port
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.5V DC
• Operating temperature from 0 to 70 degrees Celsius
• CY7C65013 available in 48-pin PDIP (-PC) or 48-pin SSOP (-PVC) packages
• CY7C65113 available in 28-pin SOIC (-SC) or 28-pin PDIP (-PC) packages
• Industry standard programmer support
2
C compatible Controller (100 kHz) enabled through General-Purpose I/O (GPIO) pins
5
CY7C65013
CY7C65113
2.0 Functional Overview
The CY7C65x13 devices are One Time Programmable 8-bit microcontrollers with a built-in 12-Mbps USB hub that supports up
to seven downstre am ports. The mi cro con trol ler instruction set has be en optimized speci fic al ly for USB opera tio ns, although the
microcontrollers can be used for a variety of non-USB embedded applications.
The CY7C65013 f eature s 22 GPIO pi ns to sup port USB and other applica tions . The I/O pins are gro uped into f o ur ports (P0[7:0],
P1[7:4,2:0], P2[7:3], P3[1:0]) where eac h port can be configured as inputs with internal pull-ups, ope n drain outputs , or trad itional
CMOS outputs. Ports 0 to 2 are rated at 7 mA per pin (typical) sink current. Port 3 pins are rated at 12 mA per pin (typical) sink
current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more
drive current cap ac ity. Additionally, each I/O pin can be used to gener a te a G PIO in terrupt to th e m ic roc ontro ll er. All of the GPIO
interrupts all share the same “GPIO” interrupt vector.
The CY7C65113 has 11 GPIO pins (P0[7:0], P1[2:0]), both rated at 7 mA per pin (typical) sink current. Multiple GPIO pins can
be connected together to drive a single output for more drive current capacity.
The microcontroller uses an external 6-MHz crystal and an internal oscillator to provide a reference to an internal PLL-based
clock generator . This technolog y allows the custom er application to use an inexpensive 6-MHz fu nda me ntal c rystal that r edu ces
the clock-related noise emissions (EMI). A PLL clock generator provides the 6-, 12-, and 48-MHz clock signals for distribution
within the microcontroller.
The CY7C65013 and the CY7C65113 are offered with 8 KB of PROM.
These parts include power-on reset logic, a watch dog timer, and a 12-bit free-running timer. The Power-On Reset (POR) logic
detects when po wer is app lied to the de vice , resets the logic to a k nown state , and beg ins ex ecutin g instructions at PROM add ress
0x0000. The watch dog timer is used to ensure the microcon troller reco vers aft er a period of inactivity. The firmware may becom e
inactive f or a va riety of reasons, inclu ding errors in the co de or a hardware f ailure such as waiting f or an interrupt that n ev er occurs.
2
The microcontroller can communicate with external electronics through the GPIO pins. An I
dates a 100-kHz serial link with an external device.
The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-µs and 1.024-ms. The timer can be used to
measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is
complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of
the timer are latched into an in ternal register when the firmware rea ds the low er eight bits . A read from the upper f our bits actually
reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if
the upper four bits increment immediately after the lower eight bits are read.
The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus
Reset interrupt, the 12 8-µs (bi t 6) an d 1.0 24-ms (bit 9 ) outpu ts from the free-runn ing ti mer, five USB endpoints, the USB hu b, the
GPIO ports, and the I
from LOW ‘0’ to HIGH ‘1’. The USB endpo ints interrupt after the USB host has written data to th e endpoint FIFO or after the USB
controller sends a packet to the USB host. The GPIO ports also have a level of masking to select which GPIO inputs can cause
a GPIO interrupt. Input tra nsi tio n po larity c an be programmed f o r eac h GP IO port as part of the port configuration. The in terrupt
polarity can be rising edge (‘0’ to ‘1’) or falling edge (‘1’ to ‘0’).
The CY7C65013 and CY7C65113 include an integrated USB Serial Interface Engine (SIE) that supports the integrated peripherals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the
hub (two endpoint s) and a de vice address f or a compound device (three endpoints ). The SIE allow s the USB host to com municate
with the hub and funct ions integrate d into the microcontro ller. T he CY7C65113 part includes a 1 :4 hub repeater with one u pstream
port and four dow nstream ports, while the CY7C65013 pa rt includes a 1:7 hub repeater . The USB Hub allows po wer manage ment
control of the downstream ports by using GPIO pins assigned by the user firmware. The user has the option of ganging the
downstream ports together with a singl e pair of po wer manag ement pins , or prov iding po wer mana gement f or eac h port with four
(CY7C65113) or seven (CY7C65013) pairs of power management pins.
2
C compatible master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles
C compatible in terface acc ommo-
6
.
Logic Block Diagram
CY7C65013
CY7C65113
6-MHz crys tal
PLL
48 MHz
Clock
Divider
12 MHz
6 MHz
12-MHz
8-bit
CPU
PROM
8 KB
RAM
256 byte
12-bit
Timer
8-bit Bus
USB
SIE
Interrupt
Controller
GPIO
PORT 0
USB
Transceiver
Repeater
P0[0]
P0[7]
D+[0]
Upstream
USB Port
D–[0]
Downstream USB Ports
USB
Transceiver
USB
Transceiver
USB
Transceiver
USB
Transceiver
CY7C65013 only
Power management under firmware
control using GPIO pins
D+[1]
D–[1]
D+[4]
D–[4]
D+[5]
D–[5]
D+[7]
D–[7]
Watch Dog
Timer
Power-On
Reset
GPIO
PORT 1
GPIO
PORT 1
GPIO
PORT 2
GPIO
PORT 3
I2C comp.
Interface
2
C Compatible interface enabled by firmware through
*I
P2[1:0] or P1[1:0]
P1[0]
P1[2]
P1[7:4]
P2[7]
P2[3]
High Current
P3[1]
Outputs
P3[0]
CY7C65013 only
SCLK
SDATA
7
3.0 Pin Configurations
XTALOUT
XTALIN
CY7C65013
48-pin SSOP/48 PDIP
1
48
2
47
46
GND
REF
GND
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1[1]
P1[5]
P1[7]
P3[1]
D+[0]
D–[0]
D+[1]
D–[1]
V
D+[2]
D–[2]
P2[3]
P2[5]
D+[7]
D–[7]
P2[7]
P0[7]
P0[5]
P0[3]
P0[1]
TOP VIEW
V
CC
P1[0]
P1[2]
P1[4]
P1[6]
P3[0]
D–[3]
D+[3]
GND
D–[4]
D+[4]
V
REF
D–[5]
D+[5]
GND
P2[4]
D–[6]
D+[6]
P2[6]
V
PP
P0[0]
P0[2]
P0[4]
P0[6]
CY7C65113
28-pin SOIC/PDIP
XTALOUT
XTALIN
V
REF
GND
D+[0]
D–[0]
D+[1]
D–[1]
D+[2]
D–[2]
P0[7]
P0[5]
P0[3]
P0[1]
CY7C65013
CY7C65113
1
28
V
2
3
4
5
6
7
8
9
10
11
12
13
14
CC
27
P1[1]
26
P1[0]
P1[2]
25
D–[3]
24
D+[3]
23
D–[4]
22
D+[4]
21
GND
20
19
V
PP
18
P0[0]
17
P0[2]
P0[4]
16
15
P0[6]
8
4.0 Product Summary Tables
4.1 Pin Assignments
Table 4-1. Pin Assignments
Name I/O 48-Pin 28-Pin Description
D+[0], D–[0] I/O 7, 8 5, 6 Upstream port, USB differential data.
D+[1], D–[1] I/O 10, 11 7, 8 Downstream Port 1, USB differential data.
D+[2], D–[2] I/O 13, 14 9, 10 Downstream Port 2, USB differential data.
D+[3], D–[3] I/O 41, 42 23, 24 Downstream Port 3, USB differential data.
D+[4], D–[4] I/O 38, 39 21, 22 Downstream Port 4, USB differential data.
D+[5], D–[5] I/O 35, 36 Downstream Port 5, USB differential data.
D+[6], D–[6] I/O 31, 32 Downstream Port 6, USB differential data.
D+[7], D–[7] I/O 18, 19 Downstream Port 7, USB differential data.
P0 I/O P1[7:0]
P1 I/O P1[7:4,2:0]
P2 I/O P2[7:3]
P3 I/O P3[1:0]
XTAL
IN
XTAL
OUT
V
PP
V
CC
GND 9, 16, 34, 40 4, 20 Ground.
V
REF
OUT 1 1 6-MHz crystal out.
21, 25, 22, 26,
23, 27, 24, 28
5, 44, 4, 45;
46, 3, 47
20, 30, 17,
33, 15
6, 43
IN 2 2 6-MHz crystal or external clock input.
29 19 Programming v oltage sup ply, tie to ground during no rmal operatio n.
48 28 V olta ge su ppl y.
IN 12, 37 3 External 3.3V supply voltage for the downstream differential data
P1[7:0]
11, 15, 12, 16,
13, 17, 14, 18
P1[2:0]
25, 27, 26
GPIO Port 0 capable of sinking 7 mA (typical).
GPIO Port 1 capable of sinking 7 mA (typical).
GPIO Port 2 capable of sinking 12 mA (typical).
GPIO Port 3, capable of sinking 12 mA (typical).
output buffers and the D+ pull up.
CY7C65013
CY7C65113
4.2 I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IO WX) instructio ns. IORD reads data from the selected
port into the accumulator. IOWR performs the reverse; it writes da ta from the ac cum ulato r to the selec ted po rt. Indexed I/O Write
(IOWX) adds the contents of X t o the address in the instructi on to form the port address and writes data from the accumulat or to
the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X.
All undefined registers are reserved. Do not write to reserved registers as this may cause an undefined operation or increased
current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with ‘0.’
Table 4-2. I/O Register Summary
Register Name I/O Address Read/Write Function Page
Port 0 Data 0x00 R/W GPIO Port 0 Data 18
Port 1 Data 0x01 R/W GPIO Port 1 Data 18
Port 2 Data 0x02 R/W GPIO Port 2 Data 18
Port 3 Data 0x03 R/W GPIO Port 3 Data 18
Port 0 Interrupt Enable 0x04 W Interrupt Enable for Pins in Port 0 20
Port 1 Interrupt Enable 0x05 W Interrupt Enable for Pins in Port 1 20
Port 2 Interrupt Enable 0x06 W Interrupt Enable for Pins in Port 2 20
9
CY7C65013
CY7C65113
Table 4-2. I/O Register Summary (continued)
Register Name I/O Address Read/Write Function Page
Port 3 Interrupt Enable 0x07 W Interrupt Enable for Pins in Port 3 20
GPIO Configuration 0x08 R/W GPIO Port Configurations 19
2
C Configuration 0x09 R/W I2C Positi on Configuration 21
I
USB Device Address A 0x10 R/W USB Device Address A 33
EP A0 Counter Register 0x11 R/W USB Address A, Endpoint 0 Counter 35
EP A0 Mode Register 0x12 R/W USB Address A, Endpoint 0 Configuration 34
EP A1 Counter Register 0x13 R/W USB Address A, Endpoint 1 Counter 35
EP A1 Mode Register 0x14 R/W USB Address A, Endpoint 1 Configuration 35
EP A2 Counter Register 0x15 R/W USB Address A, Endpoint 2 Counter 35
EP A2 Mode Register 0x16 R/W USB Address A, Endpoint 2 Configuration 35
USB Status & Control 0x1F R/W USB Upstream Port Traffic Status and Control 32
Global Interrupt Enable 0x20 R/W Global Interrupt Enable 24
Endpoint Interrupt Enable 0x21 R/W USB Endpoint Interrupt Enables 24
Interrupt Vector 0x23 R Pending Interrupt Vector Read/Clear 25
Timer (LSB) 0x24 R Lower 8 Bits of Free-running Timer (1 MHz) 20
Timer (MSB) 0x25 R Upper 4 Bits of Free-running Timer 20
WDT Clear 0x26 W Watch Dog Timer Clear 17
2
C Control & Status 0x28 R/W I2C Status and C ontrol 22
I
2
C Data 0x29 R/W I2C Data 22
I
Reserved 0x30 Reserved
Reserved 0x31 Reserved
Reserved 0x32 Reserved
Reserved 0x38-0x3F Reserved
USB Device Address B 0x40 R/W USB Device Add r es s B (no t us ed in 5-endpoint mode) 33
EP B0 Counter Register 0x41 R/W USB Address B, Endpoint 0 Counter 35
EP B0 Mode Register 0x42 R/W USB Address B, Endpoint 0 Configuration, or
EP B1 Counter Register 0x43 R/W USB Address B, Endpoint 1 Counter 35
EP B1 Mode Register 0x44 R/W USB Address B, Endpoint 1 Configuration, or
Hub Port Connect Status 0x48 R/W Hub Downstream Port Connect Status 29
Hub Port Enable 0x49 R/W Hub Downstream Ports Enable 30
Hub Port Speed 0x4A R/W Hub Downstream Ports Speed 29
Hub Port Control (Ports [4:1]) 0x4B R/W Hub Downstream Ports Control (Ports [4:1]) 30
Hub Port Control (Ports [7:5]) 0x4C R/W Hub Downstream Ports Control (Ports [7:5]) 30
Hub Port Suspend 0x4D R/W Hub Downstream Port Suspend Control 31
Hub Port Resume Status 0x4E R Hub Downstream Ports Resume Status 32
Hub Ports SE0 Status 0x4F R Hub Downstream Ports SE0 Status 31
Hub Ports Data 0x50 R Hub Downstream Ports Differential Data 31
Hub Downstream Force Low 0x51 R/W Hub Downstream Ports Force LOW (Ports [1:4]) 31
Hub Downstream Force High 0x52 R/W Hub Downstream Ports Force HIGH (Ports [5:7]) 31
Processor Status & Control 0xFF R/W Microprocessor Status and Control Register 23
USB Address A, Endpoint 3 in 5-endpoint mode
USB Address A, Endpoint 4 in 5-endpoint mode
34
35
10
CY7C65013
CY7C65113
4.3 Instruction Set Summary
Refer to the CYASM Assembler User’s Guide for more details.
Table 4-3. Instruction Set Summary
MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles
HALT 00 7 NOP 20 4
ADD A,expr data 01 4 INC A acc 21 4
ADD A,[expr] direct 02 6 INC X x 22 4
ADD A,[X+expr] index 03 7 INC [expr] direct 23 7
ADC A,expr data 04 4 INC [X+expr] index 24 8
ADC A,[expr] direct 05 6 DEC A acc 25 4
ADC A,[X+expr] index 06 7 DEC X x 26 4
SUB A,expr data 07 4 DEC [expr] direct 27 7
SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8
SUB A,[X+expr] index 09 7 IORD expr address 29 5
SBB A,expr data 0A 4 IOWR expr address 2A 5
SBB A,[expr] direct 0B 6 POP A 2B 4
SBB A,[X+expr] index 0C 7 POP X 2C 4
OR A,expr data 0D 4 PUSH A 2D 5
OR A,[expr] direct 0E 6 PUSH X 2E 5
OR A,[X+expr] index 0F 7 SWAP A,X 2F 5
AND A,expr data 10 4 SWAP A,DSP 30 5
AND A,[expr] direct 11 6 MOV [expr],A direct 31 5
AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6
XOR A,expr data 13 4 OR [expr],A direct 33 7
XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8
XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7
CMP A,expr data 16 5 AND [X+expr],A index 36 8
CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7
CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8
MOV A,expr data 19 4 IOWX [X+expr] index 39 6
MOV A,[expr] direct 1A 5 CPL 3A 4
MOV A,[X+expr] index 1B 6 ASL 3B 4
MOV X,expr data 1C 4 ASR 3C 4
MOV X,[expr] direct 1D 5 RLC 3D 4
reserved 1E RRC 3E 4
XPAGE 1F 4 RET 3F 8
MOV A,X 40 4 DI 70 4
MOV X,A 41 4 EI 72 4
MOV PSP,A 60 4 RETI 73 8
CALL addr 50-5F 10 JC addr C0-CF 5
JMP addr 80-8F 5 JNC addr D0-DF 5
CALL addr 90-9F 10 JACC addr E0-EF 7
JZ addr A0-AF 5 INDEX addr F0-FF 14
JNZ addr B0-BF 5
11
CY7C65013
CY7C65113
5.0 Programming Model
5.1 14-Bit Program Counter (PC)
The 14-bit Program Counter (PC) allows access to up to 8 KB of PROM available with the CY7C65x13 architecture. The top
32 bytes of the R O M in th e 8K part are reserved for testing purposes. T he pr ogr am c ounter is cle ared du ring reset, s uch that th e
first instruction executed after a reset is at address 0x0000h. Typically, this is a jump instruction to a reset handler that initializes
the application (see Interrupt Vectors on page 24).
The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the
program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte
“page” of sequential code sh ould be an XPAGE instruction. The assemb ler di rective “XPAGEON” causes the asse mb l er to insert
XPAGE instructions automatically. Because instructions can be either one or two bytes long, the assembler may occasionally
need to inse rt a NOP followed by an XPAGE to execute cor rectly.
The address of the next instructio n t o b e exec ute d, the c arry flag, a nd the zero flag are s aved as two bytes o n t he program stack
during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the
program stack during a RETI in struction. Only the program counter is restored during a RET instruction.
The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from
location 0x00 and up.
12
5.1.1 Program Memory Organization
after reset Address
14-bit PC 0x0000 Program execution begins here after a reset
CY7C65013
CY7C65113
0x0002 USB Bus Reset interrupt vector
0x0004 128-µs timer interrupt vector
0x0006 1.024-ms timer interrupt vector
0x0008 USB address A endpoint 0 interrupt vector
0x000A USB address A endpoint 1 interrupt vector
0x000C USB address A endpoint 2 interrupt vector
0x000E USB address B endpoint 0 interrupt vector
0x0010 USB address B endpoint 1 interrupt vector
0x0012 Hub interrupt vector
0x0014 Reserved
0x0016 GPIO interrupt vector
0x0018
0x001A
I2C interrupt vector
Program Memory begins here
0x1FDF
Figure 5-1. Program Memory Space with Interrupt Vector Table
8 KB (-32) PROM ends here (CY7C65013, CY7C65113)
13
CY7C65013
CY7C65113
5.2 8-Bit Accumulator (A)
The accumulator is the general-purpose register for the microcontroller.
5.3 8-Bit Temporary Register (X)
The “X” register i s av ailable t o the firmware f or temp orary storage of intermediate resul ts. The mi crocontroller c an perf orm indexed
operations based on the value in X. Refer to Section 5.6.3 for additional information.
5.4 8-Bit Program Stack Pointer (PSP)
During a reset, the Program Stack Pointer (PSP) is set to 0x00 and “grows” upward from this address. The PSP may be set by
firmware, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and
RETI instructions under firmware control. The PSP is not readable by the firmware.
During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as
two bytes of data memory. The first byte is st ored in the memory addressed b y the PSP, then the PSP is incre mented. The sec ond
byte is stored in memory addressed by the PSP, and the PSP is incremented again. The overall effect is to store the program
counter and flags on the program “stack” and increment the PSP by two.
The Return From Interrupt (RETI) instruction decrements the PSP, then restores the second byte from memory addressed by the
PSP. The PSP is decremented again and the first b yte is restored fro m memory addressed b y the PSP. After the program counter
and flags ha v e been res tored from stac k, the interrupts are e nab led. Th e ov er all eff ec t is to res tore the p rogr am cou nter and flags
from the program stack, decrement the PSP by two, and re-enable interrupts.
The Call Subroutine (CALL) instruction st ores the program counter and flags on the program stack an d increments the PSP by two .
The Return From Subroutine (RET) instruction restores the program counter but not the flags from the program stack and
decrements the PSP by two.
5.4.1 Data Memory Organization
The CY7C65x13 microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program
stack, user v ariab le s, da ta stac k, and U SB endpo int FIFOs . The f ollowi ng is on e e xampl e of wher e the prog ram stac k, data stac k,
and user variables areas could be located.
After reset Address
8-bit DSP 8-bit PSP 0x00
(Move DSP
8-bit DSP
Notes:
1. Refer to Section 5.5 for a description of DSP.
2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Tabl e 17 -1.
[1]
)
user selected
User variables
USB FIFO space for up to two Ad dresses and five endpo ints
0xFF
Program Stack Growth
Data Stack Growth
[2]
14
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