CYPRESS CY7C64713, CY7C64714 User Manual

CY7C64713/14

EZ-USB FX1™ USB Microcontroller

Full-speed USB Peripheral Controller

1.0 Features

• Single-chip integrated USB transceiver, SIE, and
enhanced 8051 microprocessor

• Fit, form and function upgradable to the FX2LP
(CY7C68013A)

—Pin-compatible
—Object-code-compatible
—Functionally-compatible (FX1 functionality is a

Subset of the FX2LP)

• Draws no more than 65 m A in any mode making the FX1
suitable for bus powered applications

• Software: 8051 runs from internal RAM, which is:

—Downloaded via USB
—Loaded from EEPROM
—External memory device (12 8-pin configuration only)

• 16 KBytes of on-chip Code/Data RAM

• Four programmable BULK/INTERRUPT/ISOCH­RONOUS endpoint s

—Buffering options: double, triple, and quad

• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint

• 8- or 16-bit external data interface

• Smart Media Standard ECC generation

•GPIF

—Allows direct connect ion to most parallel interfaces;

8- and 16-bit

—Programmable waveform descriptors and configu-

ration registers to define waveforms

24 MHz
Ext. XTAL

High-performance micro
using standard tools
with lower-power options

—Supports multiple Ready (RDY) inputs and Control

(CTL) outputs

• Integrated, industry standard 8051 with enhanced
features

—Up to 48-MHz clock rate
—Four clocks per instruction cycle
—Two USARTS
—Three counter/timers
—Expanded interrupt system
—Two data pointers

• 3.3V operation with 5V tolerant inputs

•Smart SIE

• Vectored USB interrupts

• Separate dat a buffers for the Setup and DATA portio ns
of a CONTROL transfer

• Integrated I

2

C controller, runs at 100 or 400 KHz

• 48-MHz, 24-MHz, or 12-MHz 8051 operation

• Four integrated FIFOs

—Brings glue and FIFOs inside for lower system cost
—Automatic conversion to and from 16-bit buses
—Master or slave operation
—FIFOs can use externally supplied clock or

asynchronous strobes

—Easy interface to ASIC and DSP ICs

• Vectored for FIFO and GPIF interrupts

• Up to 40 general purpose I/Os

• Three package options—128-pin TQFP, 100-pin TQFP,

and 56-pin QFN Lead-free

FX1

Address (16)

D+

D–

Integrated
full-speed XCVR

x20

VCC

PLL

1.5k
connected for

enumeration

USB

XCVR

Enhanced USB core
Simplifies 8051 code

/0.5
/1.0
/2.0

CY

Smart

USB

Engine

8051 Core

12/24/48 MHz,

four clocks/cycle

16 KB

RAM

“Soft Configuration”

Easy firmware changes

Figure 1-1. Block Diagram

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-08039 Rev. *B Revised February 14, 2005

Data (8)

Additional I/Os (24)

GPIF

ECC

Address (16) / Data Bus (8)

FIFO

FIFO and endpoint memory
(master or slave operation)

Master

4 kB

2

I

C

Abundant I/O

including two USARTS

ADDR (9)

RDY (6)
CTL (6)

8/16

General
programmable I/F
to ASIC/DSP or bus

standards such as

ATAPI, EPP, etc.

Up to 96 MBytes/s

burst rate

CY7C64713/14

2.0 Functional Description

EZ-USB FX1 (CY7C64713/4) is a full-speed highly
integrated, USB microc ontroller. By integrating the USB trans­ceiver , serial interface engine (SIE), enhanc ed 8051 microcon­troller, and a programmable peripheral interface in a single
chip, Cypress has created a ve ry cost-effecti ve solution tha t
provides superior time-to-market advantages.

Because it incorporat es the USB transcei ver , the EZ-USB FX1
is more economi cal, prov iding a small er footprin t soluti on than
USB SIE or external transceiver implementations. With
EZ-USB FX1, the Cypress Smart SIE handles most of the USB
protocol in hardwa re, freeing the embed ded microcontroll er for
application-specific functions and decreasing development
time to ensure USB compatibility.

The General Programmable Interface (GPIF) and Master/
Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy
and glueless interface to popular interfaces such as
UTOPIA, EPP, PCMCIA, and most DSP/processors.

Three lead-free packages are defined for the family: 56 QFN,
100 TQFP, and 128 TQFP.

ATA,

3.0 Applications

• DSL modems

• ATA interface

• Memory card readers

• Legacy conversion devices

• Home PNA

• Wireless LA N

• MP3 players

• Networking

The “Reference Designs” section of the cypress website
provides additional tools for typical USB applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Please visit
http://www.cypress.com for more information.

4.0 Functional Overview

4.1 USB Signaling Speed

FX1 operates at one of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:

• Full speed, with a signaling bit rate of 12 Mbps.

FX1 does not support the low-speed signaling mode of 1.5
Mbps or the high-speed mode of 480 Mbps.

C1

4.2 8051 Microprocessor

The 8051 microprocessor embedded in the FX1 family has
256 bytes of register RAM, an expanded interrupt system,
three timer/counters, and two USARTs.

4.2.1 8051 Clock Frequency

FX1 has an on-chip oscillator circ uit that use s an external 24­MHz (±100 ppm) crystal with the following characteristics:

• Parallel resonant

• Fundamental mode

• 500-µW drive level

• 12-pF (5% tolerance) load capacitors.

An on-chip PLL multiplies the 24-MHz oscillator up to 480
MHz, as required by the transceiver/PHY, and internal
counters divide it down for use as the 8051 clock. Th e de fau lt
8051 clock frequency is 12 MHz. The clock frequency of the
8051 can be changed by the 8051 through the CPUCS
register, dynamically.

The CLKOUT pin, which can be three-stated and inverted
using internal control bits, outputs the 50% duty cycle 8051
clock, at the selected 8051 clock frequency—48, 24, or 12
MHz.

4.2.2 USARTS

FX1 contains two standard 8051 USARTs, addressed via
Special Function Register (SFR) bits. The USART interface
pins are available on separate I/O pins, and are not multi­plexed with port pins.

UART0 and UAR T1 can operate using an intern al clock at 23 0
KBaud with no more than 1% baud rate error. 230-KBaud
operation is achieved by an in ternally derived clock source that
generates overflow pulses at the appropriate time. The
internal clock adjus ts for the 8051 cloc k ra te (4 8, 2 4, 1 2 M Hz)
such that it always presents the correct frequency for 230­KBaud operation.

4.2.3 Special Function Registers

Certain 8051 SFR addresses are populated to provide fast
access to critical FX1 functions. These SFR additions are
shown in Table 4-1. Bold type indicates non-standard,
enhanced 8051 registers . The two SFR ro ws that end wit h “0”
and “8” contain bit-addressable registers. The four I/O ports
A–D use the SFR addresses used in the standard 8051 for
ports 0–3, which are not implemented in FX1. Because of the
faster and more efficient SFR addressing, the FX1 I/O ports
are not addressable in extern al R AM space (using the MOVX
instruction).

24 MHz

C2

[1]

12 pf

20 × PLL

Figure 4-1. Crystal Configuration

Note:

1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively.

Document #: 38-08039 Rev. *B Page 2 of 50

12 pf

12-pF capacitor values assumes a trace
capacitance of 3 pF per side on a four-layer FR4 PCA

CY7C64713/14

4.3 I2C Bus

FX1 supports the I2C bus as a master only at 100/400 KHz.
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3V, even if no I

4.4 Buses

All packages: 8- or 16-bit “FIFO” bidirectional data bus, multi­plexed on I/O ports B and D. 128-pin package: adds 16-bit

2

C

output-only 8051 address bus, 8-bit bidirectional data bus.

device is connected.

Table 4-1. Special Function Registers

x8x 9x Ax Bx CxDxExFx

0
1SP EXIF
2DPL0 MPAGE
3DPH0
4 DPL1
5 DPH1
6 DPS

IOA IOB IOC IOD SCON1 PSW ACC B

INT2CLR IOE SBUF1
INT4CLR OEA

OEB
OEC
OED
OEE

7PCON
8 TCON SCON0 IE IP T2CON EICON EIE EIP
9 TMOD SBUF0
ATL0AUTOPTRH1 EP2468STAT EP01STAT RCAP2L

BTL1AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H
CTH0reserved EP68FIFOFLGS TL2
DTH1AUTOPTRH2 GPIFSGLDATH TH2
E CKCON AUTOPTRL2 GPIFSGLDATLX
F reserved AUTOPTRSETUP GPIFSGLDATLNOX

4.5 USB Boot Methods

During the power-up sequence, internal logic checks the I2C
port for the connection of an EEPROM whose first byte is
either 0xC0 or 0x C 2. I f f ou n d, it us es th e V ID/ PI D/ D ID val u es
in the EEPROM in place of the internally stored value s (0xC0),
or it boot-loads the EEPROM contents into internal RAM
(0xC2). If no EEPROM is detected, FX1 enumerates using
internally stored descriptors. The default ID values for FX1 are
VID/PID/DID (0x04B4, 0x6473, 0xAxxx where xxx=Chip
revision).

[2]

Table 4-2. Default ID Values for FX1

Default VID/PID/DID

Vendor ID 0x04B4 Cypress Semiconductor
Product ID 0x6473 EZ-USB FX1
Device

release

0xAnnn Depends chip revision (nnn = chip

revision where first silicon = 001)

4.6 ReNumeration™

Because the FX1’s configuration is soft, one chip can take on
the identities of multiple distinct USB devices.

When first plugged into USB, the FX1 enumerates automati­cally and download s firmwa re and U SB descr iptor t ables over
the USB cable. Next, the FX1 enumerates again, this time as

Note:

2. The I

2

C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.

a device defined by the downloaded information. This
patented two-step process, called ReNumeration, happens
instantly when the device is plugged in, with no hint that the
initial download step has occurred.

Two control bits in the USBCS (USB Control and Status)
register control the ReNumeration process: DISCON and
RENUM. To simulate a USB disconnect, the firmware sets
DISCON to 1. To reconnect, the firmware clears DISCON to 0.

Before reconnecting, the firmware sets or clears the RENUM
bit to indicate wh ether the firm ware or the Default U SB Device
will handle devi ce reques ts ov er end point zer o: if REN UM = 0,
the Default USB Device wil l handle device requ ests; if RENUM
= 1, the firmware will.

4.7 Bus-powered Applications

The FX1 fully supports bus-powered designs by enumerating
with less than 100 mA as required by the USB specification.

4.8 Interrupt System

4.8.1 INT2 Interrupt Request and Enable Registers

FX1 implements an autovector feature for INT2 and INT4.
There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)
vectors. See EZ-USB Technical Reference Manual (TRM) for
more details.

Document #: 38-08039 Rev. *B Page 3 of 50

CY7C64713/14

4.8.2 USB-Interrupt Autovectors

The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that normally would be
required to identify the individual USB interrupt source, the
FX1 provides a second level of interrupt vectoring, called
Autovectoring. When a USB interrupt is asserted, the FX1
pushes the program counter onto its stack then jumps to
address 0x0043, where it expects to find a “jump” instruction
to the USB Interrupt service routine.

The FX1 jump instruction is encoded as shown in Table 4-3.
If Autovectoring is enabled (AV2EN = 1 in the INTSETUP

register), the FX1 substitutes its INT2VEC byte. Therefore, if

Table 4-3. INT2 USB Interrupts

USB INTERRUPT TABLE FOR INT2

Priority INT2VEC Value Source Notes

1 00 SUDAV Setup Data Available
2 04 SOF Start of Frame
3 08 SUTOK Setup Token Received
4 0C SUSPEND USB Suspend request
5 10 USB RESET Bus reset
6 14 reserved
7 18 EP0ACK FX1 ACK’d the CONTROL Handshake
8 1C reserved

9 20 EP0-IN EP0-IN ready to be loaded with data
10 24 EP0-OUT EP0-OUT has USB data
11 28 EP1-IN EP1-IN ready to be loaded with data
12 2C EP1-OUT EP1-OUT has USB data
13 30 EP2 IN: buffer available. OUT: buffer has data
14 34 EP4 IN: buffer available. OUT: buffer has data
15 38 EP6 IN: buffer available. OUT: buffer has data
16 3C EP8 IN: buffer available. OUT: buffer has data
17 40 IBN IN-Bulk-NAK (any IN endpoint)
18 44 reserved
19 48 EP0PING EP0 OUT was Pinged and it NAK’d
20 4C EP1PING EP1 OUT was Pinged and it NAK’d
21 50 EP2PING EP2 OUT was Pinged and it NAK’d
22 54 EP4PING EP4 OUT was Pinged and it NAK’d
23 58 EP6PING EP6 OUT was Pinged and it NAK’d
24 5C EP8PING EP8 OUT was Pinged and it NAK’d
25 60 ERRLIMIT Bus errors exceeded the programmed limit
26 64
27 68 reserved
28 6C reserved
29 70 EP2ISOERR ISO EP2 OUT PID sequence error
30 74 EP4ISOERR ISO EP4 OUT PID sequence error
31 78 EP6ISOERR ISO EP6 OUT PID sequence error
32 7C EP8ISOERR ISO EP8 OUT PID sequence error

the high byte (“page”) of a jump-table address is preloaded at
location 0x0044, the automatically-inserted INT2VEC byte at
0x0045 will direct the jum p to the correct addres s out of the 27
addresses within the page.

4.8.3 FIFO/GPIF Interrupt (INT4)

Just as the USB Inte rrupt is sha red am ong 2 7 ind ividual USB­interrupt sources, the FIFO/GPIF interrupt is shared among 14
individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like
the USB Interrupt, can employ autovectoring. Table 4-4 shows
the priority and INT4VEC values for the 14 FIFO/GPIF
interrupt sources.

Document #: 38-08039 Rev. *B Page 4 of 50

Table 4-4. Individual FIFO/GPIF Interrupt Sources

Priority INT4VEC Value Source Notes

1 80 EP2PF Endpoint 2 Programmable Flag
2 84 EP4PF Endpoint 4 Programmable Flag
3 88 EP6PF Endpoint 6 Programmable Flag
4 8C EP8PF Endpoint 8 Programmable Flag
5 90 EP2EF Endpoint 2 Empty Flag
6 94 EP4EF Endpoint 4 Empty Flag
7 98 EP6EF Endpoint 6 Empty Flag
8 9C EP8EF Endpoint 8 Empty Flag

9 A0 EP2FF Endpoint 2 Full Flag
10 A4 EP4FF Endpoint 4 Full Flag
11 A8 EP6FF Endpoint 6 Full Flag
12 AC EP8FF Endpoint 8 Full Flag
13 B0 GPIFDONE GPIF Operation Complete
14 B4 GPIFWF GPIF Waveform

CY7C64713/14

If Autovectoring is enabled (AV4EN = 1 in the INTSETUP

4.9 Reset and Wakeup

register), the FX1 substitutes its INT4VEC byte. Therefore, if
the high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically-inserted INT4VEC byte at
0x0055 will direct the jump to the c orrect address out of the 14
addresses within the page. When the ISR occurs, the FX1
pushes the program counter onto its stack then jumps to
address 0x0053, where it expects to find a “jump” instruction
to the ISR Interrupt service routine.

4.9.1 Reset Pin

The input pin, RESET#, will res et the FX1 when asserted. This
pin has hysteresis and is active LOW. When a crystal is used
with the CY7C64713/4 the reset period must allow for the
stabilization of the crystal and the PLL. This reset period
should be approximately 5 ms after VCC has reached 3.0
Volts. If the crystal input pin is driven by a clock signal the
internal PLL stabilizes in 200 µs after VCC has reached

[3]

. Figure 4-2 shows a power on reset condition and a

3.0V
reset applied during operation. A power on reset is defined as
the time reset is asserted while power is being applied to the
circuit. A powered reset is defined to be when the FX1 has
previously been powered on and operating and the RESET#
pin is asserted.

Cypress provides an application note which describes and
recommends power on res et implementation and can be found
on the Cypress web site. Wh ile the appl ication no te discus ses
the FX2, the information provid ed app lies a lso to the FX1. F or
more infor mation on reset implem entation for th e FX2 fa mily
of products visit the http://www.cypress.com.

Note:

3. If the external clock is powered at the same time as the CY7C64713/4 and has a stabilization wait period, it must be added to the 200

µs.

Document #: 38-08039 Rev. *B Page 5 of 50

CY7C64713/14

RESET#

V

IL

3.3V

3.0V

VCC

0V

T

RESET

Power on Reset

Figure 4-2. Reset Timing Plots

Table 4-5. Reset Timing Values

Condition T

RESET

Power-On Reset with crystal 5 ms
Power-On Reset with external

200 µs + Clock stability time

clock
Powered Reset 200 µs

4.9.2 Wakeup Pins

The 8051 puts it self and the rest of the chip into a pow er-down
mode by setting PCON.0 = 1. This stops the oscillator and
PLL. When WAKEUP is asserted by external logic, the oscil­lator restarts, after the PLL stabilizes, and then the 8051
receives a wakeup interrupt. This applies whether or not FX1
is connected to the USB.

The FX1 exits the power-down (USB suspend) state using one
of the following methods:

• USB bus activity (if D+/D– lines are left floating, noise on
these lines may indicate activity to the FX1 and initiate a
wakeup).

• External logic asserts the WAKEUP pin

• External logic asserts the PA3/WU2 pin.

The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is by default active low.

4.10 Program/Data RAM

RESET#

V

IL

3.3V

VCC

0V

T

RESET

Powered Reset

access it as both program and data memory. No USB control
registers appear in this space.

Two memory maps are shown in the following diagrams:

Figure 4-3 Internal Code Memory, EA = 0
Figure 4-4 External Code Memory, EA = 1.

4.10.2 Internal Code Memory, EA = 0

This mode implements the internal 16-KByte block of RAM
(starting at 0) as combined code and data memory. When
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside
the chip. This allows the user to connect a 64-KByte memory
without requiring address decodes to keep clear of internal
memory spaces.

Only the internal 16 KBytes an d scratch pad 0. 5 KBytes RAM
spaces have the following access:

• USB download

• USB upload

• Setup data pointer

2

C interface boot load.

• I

4.10.3 External Code Memory, EA = 1

The bottom 16 KBytes of program memory is external, and
therefore the bottom 16 KBytes of internal RAM is accessible
only as data memory.

4.10.1 Size

The FX1 has 16 KBytes of inter nal progr am/ dat a RAM, w here
PSEN#/RD# signals are internally ORed to allow the 8051 to

Document #: 38-08039 Rev. *B Page 6 of 50

Inside FX1 Outside FX1

FFFF

4K FIFO buffers

E200
E1FF

0.5 KBytes RAM

Data (RD#,WR#)*

E000

3FFF

7.5 KBytes
USB regs and

(RD#,WR#)

(OK to populate
data memory
here—RD#/WR#
strobes are not
active)

40 KBytes
External
Data
Memory
(RD#,WR#)

48 KBytes
External
Code
Memory
(PSEN#)

CY7C64713/14

16 KBytes RAM
Code and Data
(PSEN#,RD#,WR#)*

0000

(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)

Data Code

(OK to populate
program
memory here—
PSEN# strobe
is not active)

*SUDPTR, USB upload/download, I2C interface boot access

Figure 4-3. Internal Code Memory, EA = 0

Inside FX1 Outside FX1

FFFF

4K FIFO buffers

E200
E1FF

0.5 KBytes RAM

Data (RD#,WR#)*

E000

3FFF

7.5 KBytes
USB regs and

(RD#,WR#)

(OK to populate
data memory
here—RD#/WR#
strobes are not
active)

40 KBytes
External
Data
Memory
(RD#,WR#)

64 KBytes
External
Code
Memory
(PSEN#)

(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)

Data Code

0000

16 KBytes
RAM
Data
(RD#,WR#)*

*SUDPTR, USB upload/download, I2C interface boot access

Figure 4-4. External Code Memory, EA = 1

Document #: 38-08039 Rev. *B Page 7 of 50

4.11 Register Addresses

CY7C64713/14

FFFF

F000
EFFF

E800
E7FF
E7C0

E7BF
E780
E77F

E740

E73F

E700
E6FF

E500
E4FF
E480
E47F

E400

E3FF
E200

E1FF

E000

4 KBytes EP2-EP8

(8 x 512)

Not all Space is available

for all transfer types

2 KBytes RESERVED

64 Bytes EP1IN

64 Bytes EP1OUT

64 Bytes EP0 IN/OUT

64 Bytes RESERVED

8051 Addressable Registers

Reserved (128)

128 bytes GPIF Waveforms

Reserved (512)

512 bytes

8051 xdata RAM

buffers

(512)

4.12 Endpoint RAM

4.12.1 Size

• 3 × 64 bytes (Endpoints 0 and 1)

• 8 × 512 bytes (Endpoints 2, 4, 6, 8)

4.12.2 Organization

• EP0—Bidirectional endpoint zero, 64- byte buffer

• EP1IN, EP1OUT—64-byte buffers, bulk or interrupt

• EP2,4,6,8—Eight 512-byte bu ffers, bulk, inter rupt, or isoch-

ronous, of which only the transfer size is available.
EP4 and EP8 can be double buf fered, while EP2 an d 6 can

be either double, triple , or quad buffered. Regard less of the
physical size of the buffer, each endpo int buffer accomm o­dates only one full-speed packet. For bulk endpoints the
maximum number o f bytes it can accommoda te is 64, ev en
though the physical buffer size is 512 or 1024. For an
ISOCHRONOUS endpoint the maximum number of bytes
it can accommodate is 1023. For endpoint configuration
options, see Figure 4-5.

4.12.3 Setup Data Buffer

A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup
data from a CONTROL transfer.

Document #: 38-08039 Rev. *B Page 8 of 50

4.12.4 Endpoint Configurations

EP0 IN&OUT

EP1 IN

EP1 OUT

64
64
64

CY7C64713/14

64

64

64

64

64

64

64

64
64
64

64

64

64

64

64

64
64
64

64
64
64

64
64
64

64

64

64

64

64

64

64

64

64

EP2

EP2

64

64

EP4

64
64

EP6

64
64

EP8

64

64

1

64
64

EP4

64
64

EP6

64
64

64
64

2

EP2

64
64

EP4

64
64

EP6

1023

1023

3

EP2

64
64

64
64

EP6

64

64

EP8

64
64

4

EP2

64
64

64
64

EP6

64
64

64

64

5

Figure 4-5. Endpoint Configuration

Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT. The endpoint buffers can be
configured in any 1 of the 12 configurations shown in the
vertical columns. In ful l-s pe ed, BU LK m od e use s onl y the firs t
64 bytes of ea ch buffer, even though mem ory exists for t he
allocation of the isochronous transfers in BULK mode the
unused endpoint buf fer sp ace is not av ailab le for other ope ra­tions. An example endpoint configuration would be:

EP2—1023 double buffere d; EP6—64 quad buffered (column

8).

4.12.5 Default Alternate Settings

Table 4-6. Default Alternate Settings

[4, 5]

Alternate

Setting 0 1 2 3

ep0 64 64 64 64
ep1out 0 64 bulk 64 int 64 int
ep1in 0 64 bulk 64 int 64 int
ep2 0 64 bulk out (2×)64 int out (2×) 64 iso out (2×)
ep4 0 64 bulk out (2×)64 bulk out (2×) 64 bulk out (2×)
ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×)
ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)

EP2

64
64

64
64

EP6

1023

1023

6

EP2

1023

1023

EP6

64
64

EP8

64
64

7

EP2

1023

1023

EP6

64
64

64
64

8

EP2

1023

1023

EP6

1023

1023

9

EP2

64
64

64

EP6

64

64

64

EP8

64
64

10

EP2

1023

1023

1023
1023

EP8

64
64

11

EP2

1023

1023

1023

1023

12

are controlled by F IFO control signa ls (such as IFCLK, SL CS#,
SLRD, SL WR, SLOE, PKTEND, and flag s). The usable size of
these buffers depend on the USB transfer mode as describe d
in Section 4.12.2.

In operation , so me of th e eig ht RAM bl ocks fill or em pty from
the SIE, while the others are connected to the I/O transfer
logic. The trans fer logic takes two forms, the G PIF for internally
generated control signals, or the slave FIFO interface for
externally controlled transfers.

4.13.2 Master/Slave Control Signals

The FX1 endpoint FIFOS are im plemente d as eight physica lly
distinct 256x16 RAM blocks. The 8051/SIE can switch any of
the RAM blocks between tw o domains, th e USB (SIE) domain
and the 8051-I/O Un it do ma in. This switching is don e virtually
instantaneously, giving essentially zero transfer time between
“USB FIFOS” and “Slave FIFOS.” Since they are phy sically the
same memory, no bytes are actually transferred between
buffers.

4.13 External FIFO Interface

4.13.1 Architecture

The FX1 slave FIF O arc hitecture has eight 5 12- byte blocks in
the endpoint RA M tha t d ire ct l y s er v e a s FIF O m em or i e s, a nd

Notes:

4. “0” means “not implemented.”

5. “2×” means “double buf fered.”

Document #: 38-08039 Rev. *B Page 9 of 50

CY7C64713/14

At any given time, some RAM blocks are filling/emptying with
USB data under SIE control, while other RAM blocks are
available to the 8051 and/or the I/O control unit. The RAM
blocks operate as single-port in the USB domain, and dual­port in the 8051-I/O domai n. Th e bl oc ks can be c onf igu r ed a s
single, double, triple, or quad buffered as previously shown.

The I/O control unit implements either an internal-master (M
for master) or external-master (S for Slave) interface.

In Master (M) mode, the GPIF internally controls
FIFOADR[1..0] to select a FIFO. The RDY pi ns (two in the 56­pin package, six in the 10 0-pin and 128-pin p ack ages) ca n be
used as flag inputs from an external FIFO or other logic if
desired. The GPIF can be r un from ei ther an internal ly derive d
clock or externally supplied clock (IFCLK), at a rate that
transfers data up to 96 Megabytes/s (48-MHz IFCLK with 16­bit interface).

In Slave (S) mode, the FX1 accept s either an interna lly derived
clock or externally supplied clock (IFCLK, max. frequency 48
MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals
from external logic. When using an external IFCLK, the
external clock mus t be present b efore switch ing to the ext ernal
clock with the I FCLKSRC bit . Each endpoint can individ ually
be selected for byte or word operation by an internal configu­ration bit, and a Slave FIFO Output Enable signal SLOE
enables data of the sel ec ted width. External logic mu st in su re
that the output enable sign al is inac tive when writing data to a
slave FIFO. The slave interface can also operate asynchro­nously, where the SLRD and SLWR signals act directly as
strobes, rather than a cloc k qual ifier as in synchr onous m ode.
The signals SLRD, SLWR, SLOE and PKTEND are gated by
the signal SLCS#.

4.13.3 GPIF and FIFO Clock Rates

An 8051 register bit selects one of two frequencies for the
internally suppl ied i nterfac e cloc k: 30 MHz a nd 48 MHz. Alt er­natively, an externally supplied clock of 5 MHz–48 MHz
feeding the IFCLK pin can be used as the interface clock.
IFCLK can be configured to function as an output clock when
the GPIF and FIFOs are internally clocked. An output enable
bit in the IFCONFIG register turns this clock output off, if
desired. Another bit within the IFCONFIG register will invert
the IFCLK signal whether internally or externally sourced.

4.14 GPIF

The GPIF is a flexible 8- or 16-bit parallel interface driven by a
user-programmable finite state machine. It allows the
CY7C64713/4 to perform local bus mastering, and can
implement a wide variety of protocols such as ATA interface,
printer parallel port, and Utopia.

The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general-purpose ready
inputs (RDY). The data bus width can be 8 or 16 bits. Each
GPIF vector defines the s tate of the control outputs, and deter­mines what stat e a ready input (or multi ple inputs) must be
before proceeding. The GPIF vector can be programmed to
advance a FIFO to the next data value, advance an address,
etc. A sequence of the GPIF vectors make up a single
waveform that will be executed to perform the desired data
move between the FX1 and the external device.

Document #: 38-08039 Rev. *B Page 10 of 50

4.14.1 Six Control OUT Signals

The 100- and 128-pin packages bring out all six Control Output
pins (CTL0-CTL5). The 8051 prog rams the GPIF unit to define
the CTL waveforms. The 56-pin package brings out three of
these signals, CTL0–CTL2. CTLx waveform edges can be
programmed to make transitions as fast as once per clock
(20.8 ns using a 48-MHz clock).

4.14.2 Six Ready IN Signals

The 100- and 128-pin packages bring out all six Ready in puts
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56-pin package brings out
two of these signals, RDY0–1.

4.14.3 Nine GPIF Address OUT Signals

Nine GPIF address line s are avai lable in th e 100 - and 128-pi n
packages, GPIFADR[8..0]. The GPIF address lines allow
indexing through up to a 512-byte block of RAM. If more
address lines are needed, I/O port pins can be used.

4.14.4 Long Transfer Mode

In master mode, t he 8051 app ropriately sets G PIF transac tion
count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended trans fers of up to 2
The GPIF automatical ly thro ttles d ata flow to preven t under or
overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers
to represent the current status of the transaction.

32

transactions.

4.15 ECC Generation

The EZ-USB FX1 can calculate ECCs (Error-Correcting
Codes) on da ta that passes acros s its GPIF or Slave F IFO
interfaces. There are two ECC configurations: Two ECCs,
each calculated o ver 256 bytes (Sm artMedia™ S tandard); and
one ECC calculated over 512 bytes.

The ECC can correct any one-bit error or detect any two-bit
error.

Note: To use the ECC logic, the GPIF or Slav e FIFO inte rface
must be configured for byte-wide operation.

4.15.1 ECC Implementation

The two ECC configurations are selected by the ECCM bit:

4.15.1.1 ECCM = 0

Two 3-byte ECCs, each calculated over a 256-byte block of
data. This configuration conforms to the SmartMedia
Standard.

Write any value to ECCRESET, then pass data across the
GPIF or Slave FIFO interface. The ECC for the first 256 bytes
of data will be c alculated and s tored in ECC1. T he ECC for the
next 256 bytes will be stored in ECC2. After the second ECC
is calculated, the va lues in the ECCx reg isters will not ch ang e
until ECCRESET is written again, even if more data is subse­quently passed across the interface.

4.15.1.2 ECCM=1

One 3-byte ECC calculated over a 512-byte block of data.
Write any value to ECCRESET then pass data across the

GPIF or Slave FIFO interface. The ECC for the first 512 bytes
of data will be calculated and stored in ECC1; EC C2 is unused.
After the ECC is calcu lated, the v alue in ECC 1 will not ch ange

CY7C64713/14

until ECCRESET is written again, even if more data is subse­quently passed across the interface

4.18.2 I

At power-on reset the I

2

C Interface Boot Load Access

2

C interface boot loader will load the

VID/PID/DID configuration bytes and up to 16 KBytes of

4.16 USB Uploads and Downloads

The core has the abilit y to dire ctly edi t the data content s of the
internal 16 KByte RAM and of the internal 512-byte scratch
pad RAM via a vendor-specific command. This capability is
normally used when “soft” downloading user code and is
available only to and from internal RAM, only when the 8051
is held in reset. The avai lable RAM spac es are 16 KBytes from
0x0000–0x3FFF (code/data) and 512 bytes from
0xE000–0xE1FF (scratch pad data RAM).

[6]

4.17 Autopointer Access

FX1 provides two identical autopointers. They are similar to
the internal 8051 dat a poi nter s, bu t with an ad dit ion al fe ature:
they can optional ly increment after ev ery memory access. This
capability is available to and from both internal and external
RAM. The autopointers are av ailable in external FX1 regist ers,
under control of a mode bit (AUTOPTRSETUP.0). Using the
external FX1 autopoint er access (at 0xE67B – 0xE67C) allows
the autopointer t o acces s al l RAM, int ernal and exte rnal to the

program/data. The availa ble RA M sp aces are 16 KByte s from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The
8051 will be in reset. I

2

C interface boot loads only occur after

power-on reset.

2

4.18.3 I

The 8051 can control peripherals connected to the I
using the I2CTL an d I2DA T regis ters. FX1 provid es I
control only, it is never an I

C Interface General Purpose Access

2

C slave.

2

4.19 Compatible with Previous Generation
EZ-USB FX2

The EZ-USB FX1 is fit/form/function-upgradable to the EZ­USB FX2LP. This makes for a easy transition for designers
wanting to upgrade their systems from full-speed to the high­speed designs. The pinout and package selection are
identical, and all of the firmware developed for the FX1 will
function in the FX2LP with proper addition of High Speed
descriptors and speed switching code.

part. Also, the autopointers can point to any FX1 register or
endpoint buff er space. When au topointer ac cess to exte rnal
memory is enabled, location 0xE67B and 0xE67C in XDATA
and code space cannot be used.

5.0 Pin Assignments

Figure 5-1 identifies all signals for the three package types.
The following pages illustrate the indiv idual pin diagrams , plus

4.18 I2C Controller

FX1 has one I2C port that is driv en by two internal controllers,
one that automatically operates at boot time to load
VID/PID/DID and configuration information, and another that
the 8051, once running, uses to control external I

2

C port operates in master mode only.

The I

4.18.1 I

The I

2

C Port Pins

2

C- pins SCL and SDA must have external 2.2-kΩ pull­up resistors even if no EEPROM is connected to the FX1.
External EEPROM device address pins must be configured
properly. See Table 4-7 for configuring the device address
pins.

Table 4-7. Strap Boot EEPROM Address Lines to These
Values

Bytes Example EEPROM A2 A1 A0

16 24LC00

[7]

N/A N/A N/A
128 24LC01 0 0 0
256 24LC02 0 0 0
4K 24LC32 0 0 1
8K 24LC64 0 0 1
16K 24LC128 0 0 1

2

C devices.

a combination diagra m showin g which of the full set of signal s
are available in the 128-, 100-, and 56-pin packages.

The signals on t he lef t edge of t he 56-pin packa ge in Figure 5-
1 are common to all versions in the FX1 family. Three modes
are availabl e in al l packa ge ve rsion s: Por t, GP IF mast er, and
Slave FIFO. These modes defi ne the signals on the right edge
of the diagram. The 8051 select s the in terface m ode usin g the
IFCONFIG[1:0] register bits. Port mod e is the power-on de fault
configuration.

The 100-pin pa ckage adds func tional ity to the 56 -pin p ack age
by adding these pins:

• PORTC or alternate GPIFADR[7:0] address signals

• PORTE or alternate GPIFADR[8] address signal and seve n

additional 8051 signals

• Three GPIF Control s i gnals

• Four GPIF Ready signals

• Nine 8051 signals (two USARTs, three timer inputs,

INT4,and INT5#)

• BKPT, RD#, WR#.

The 128-pin package adds the 8051 address and data buses
plus control sign als. Note th at two of the required s ignals, RD #
and WR#, are present in the 100-pin version. In the 100-pin
and 128-pin versions, an 8051 control bit can be set to pulse
the RD# and WR# pins when the 8051 reads from/writes to
PORTC.

Notes:

6. After the data has been downloaded from the host, a “loader” can execute from internal RAM in order to transfer downloaded data to external memory.

7. This EEPROM does not have address pins.

2

C bus

C master

Document #: 38-08039 Rev. *B P age 11 of 50

Port GPIF Master Slave FIFO

XTALIN
XTALOUT
RESET#
WAKEUP#

SCL
SDA

T0OUT
T1OUT

IFCLK
CLKOUT

DPLUS
DMINUS

56

100

BKPT
PORTC7/GPIFADR7

PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0

PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT

D7
D6
D5
D4
D3
D2
D1
D0

128

EA

PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0

INT0#/PA0
INT1#/PA1

PA2

WU2/PA3

PA4
PA5
PA6
PA7

RxD0

TxD0

RxD1

TxD1

INT4

INT5#

T2
T1
T0

RD#

WR#

CS#
OE#

PSEN#

A15
A14
A13
A12
A11
A10

A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]

RDY0
RDY1

CTL0
CTL1
CTL2

INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7

CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5

CY7C64713/14

FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]

SLRD
SLWR

FLAGA
FLAGB
FLAGC

INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#

Figure 5-1. Signals

Document #: 38-08039 Rev. *B Page 12 of 50

CY7C64713/14

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

PD1/FD9

PD2/FD10

PD3/FD11

INT5#

VCC

PE0/T0OUT

PE1/T1OUT

PE2/T2OUT

PE3/RXD0OUT

PE4/RXD1OUT

PE5/INT6

PE6/T2EX

PE7/GPIFADR8

GND

A4

A5

A6

A7

PD4/FD12

PD5/FD13

PD6/FD14

PD7/FD15

GND

A8

A9

A10

1

CLKOUT

2

VCC

3

GND

4

RDY0/*SLRD

5

RDY1/*SLWR

6

RDY2

7

RDY3

8

RDY4

9

RDY5

10

AVCC

11

XTALOUT

12

XTALIN

13

AGND

14

NC

15

NC

16

NC

17

AVCC

18

DPLUS

19

DMINUS

20

AGND

21

A11

22

A12

23

A13

24

A14

25

A15

26

VCC

27

GND

28

INT4

29

T0

30

T1

31

T2

32

*IFCLK

33

RESERVED

34

BKPT

35

EA

36

SCL

37

SDA

38

OE#

A3
A2
A1
A0

D7
D6
D5

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

PD0/FD8

*WAKEUP

VCC

RESET#

CTL5

GND

PA7/*FLAGD/SLCS#

PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0

CY7C64713/4
128-pin TQFP

PA3/*WU2

PA2/*SLOE

PA1/INT1#
PA0/INT0#

VCC

GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0

CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA

VCC
CTL4
CTL3

PSEN#

WR#

RD#

PB0/FD0

RXD0

TXD0

GND

VCC

CS#

VCC

RXD1

TXD1

PB4/FD4

PB7/FD7

PB6/FD6

PB5/FD5

GND

D0

D1

D2

D3

VCC

D4

PB3/FD3

PB2/FD2

PB1/FD1

GND

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

Figure 5-2. CY7C64713/4 128-pin TQFP Pin Assignment

* denotes pro grammable polarity

Document #: 38-08039 Rev. *B Page 13 of 50

100

CLKOUT

99

PD7/FD15

GND

CY7C64713/14

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

PD1/FD9

PD2/FD10

PD3/FD11

INT5#

VCC

PE0/T0OUT

PE1/T1OUT

PE2/T2OUT

PE3/RXD0OUT

PE4/RXD1OUT

PE5/INT6

PE6/T2EX

PE7/GPIFADR8

GND

PD4/FD12

PD5/FD13

PD6/FD14

1

VCC

2

GND

3

RDY0/*SLRD

4

RDY1/*SLWR

5

RDY2

6

RDY3

7

RDY4

8

RDY5

9

AVCC

10

XTALOUT

11

XTALIN

12

AGND

13

NC

14

NC

15

NC

16

AVCC

17

DPLUS

18

DMINUS

19

AGND

20

VCC

21

GND

22

INT4

23

T0

24

T1

25

T2

26

*IFCLK

27

RESERVED

28

BKPT

29

SCL

30

SDA

CY7C64713/4
100-pin TQFP

PD0/FD8

*WAKEUP

VCC

RESET#

CTL5

GND

PA7/*FLAGD/SLCS#

PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0

PA3/*WU2

PA2/*SLOE

PA1/INT1#
PA0/INT0#

VCC

GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0

CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA

VCC
CTL4
CTL3

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

PB3/FD3

PB2/FD2

PB1/FD1

RD#

31

PB0/FD0

RXD0

TXD0

WR#

VCC

36

35

34

33

32

GND

VCC

41

40

39

38

37

RXD1

TXD1

43

42

PB4/FD4

44

PB7/FD7

PB6/FD6

PB5/FD5

GND

GND

VCC

50

49

48

47

46

45

Figure 5-3. CY7C64713/4 100-pin TQFP Pin Assignment

* denotes programmable polarity

Document #: 38-08039 Rev. *B Page 14 of 50

CLKOUT/**PE1/T1OUT

CY7C64713/14

RDY0/*SLRD

RDY1/*SLWR

AVCC

XTALOUT

XTALIN

AGND

AVCC

DPLUS

DMINUS

AGND

VCC

GND

10
11
12

PD7/FD15

54

GND

53

50

51

52

CY7C64713/4

49

48

GND

VCC

55

56

1
2
3
4
5
6
7

47

PD1/FD9

46

PD2/FD10

PD3/FD11

PD4/FD12

PD5/FD13

PD6/FD14

56-pin QFN

8
9

PD0/FD8

45

*WAKEUP

44

VCC

43

RESET#

42

GND

41

PA7/*FLAGD/SLCS#

40

PA6/*PKTEND

39

PA5/FIFOADR1

38

PA4/FIFOADR0

37

PA3/*WU2

36

PA2/*SLOE

35

PA1/INT1#

34

PA0/INT0#

33

VCC

32

CTL2/*FLAGC

31

*IFCLK/**PE0/T0OUT

RESERVED

Document #: 38-08039 Rev. *B Page 15 of 50

13
14

16

15

SDA

SCL

Figure 5-4. CY7C64713/4 56-pin QFN Pin Assignment

18

17

PB0/FD0

VCC

* denotes programmable polarity

19

PB1/FD1

20

PB2/FD2

21

PB3/FD3

22

PB4/FD4

23

PB5/FD5

24

PB6/FD6

25

PB7/FD7

26

GND

27

VCC

28

GND

CTL1/*FLAGB

30
29

CTL0/*FLAGA