Cypress CY7C60413, CY7C60445, CY7C64355, CY7C60455, CY7C64356 Technical Reference Manual

...

enCoRe™ V CY7C643xx,

enCoRe™ V LV CY7C604xx

Technical Reference Manual (TRM)

Document No. 001-32519 Rev *H

November 19, 2018

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

www.cypress.com

Copyrights

© Cypress Semiconductor Corporation, 2007-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, FRAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document Number: 001-32519 Rev. *H 2

Section A: Overview 9

1. Pin Information 15

1.1 Pinouts....................................................................................................................................15

1.1.1 CY7C60413 enCoRe V LV 16-Pin Part Pinout ....................................................15

1.1.2 CY7C60445 enCoRe V LV 32-Pin Part Pinout16

1.1.3 CY7C64345, CY7C64343, enCoRe V 32-Pin Part Pinout .....................................17

1.1.4 CY8C20646A/AS/LCY8C20666A/AS/L CY7C64355, CY7C64356 enCoRe V 48-Pin Part Pinout18

1.1.5 CY7C60455, CY7C60456 enCoRe V LV 48-Pin Part Pinout.................................19

1.1.6 CY8C20066A, CY8CTMG200-00LTXI, CY8CTMG200A-00LTXI PSoC, CY7C64300 enCoRe V and CY7C60400 enCoRe V LV OCD 48-Pin Part Pinout20

1.1.7 32-Pin QFN (with USB) .........................................................................................21

1.1.8 48-Pin SSOP .........................................................................................................22

Section B: enCoRe V Core 23

2. CPU Core (M8C) 26

2.1 Overview.................................................................................................................................26

2.2 Internal Registers....................................................................................................................26

2.3 Address Spaces......................................................................................................................26

2.4 Instruction Set Summary ........................................................................................................27

2.5 Instruction Formats .................................................................................................................29

2.5.1 One-Byte Instructions ............................................................................................29

2.5.2 Two-Byte Instructions.............................................................................................29

2.5.3 Three-Byte Instructions..........................................................................................30

2.6 Register Definitions.................................................................................................................31

2.6.1 CPU_F Register ....................................................................................................31

2.6.2 Related Registers ..................................................................................................31

3. Supervisory ROM (SROM) 32

3.1 Architectural Description.........................................................................................................32

3.1.1 Additional SROM Feature ......................................................................................33

3.1.2 SROM Function Descriptions.................................................................................33

3.2 Register Definitions.................................................................................................................37

4. RAM Paging 38

4.1 Architectural Description.........................................................................................................38

4.1.1 Basic Paging ..........................................................................................................38

4.1.2 Stack Operations....................................................................................................38

4.1.3 Interrupts................................................................................................................39

4.1.4 MVI Instructions .....................................................................................................39

4.1.5 Current Page Pointer .............................................................................................39

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 3

Contents

4.1.6 Index Memory Page Pointer ..................................................................................40

4.2 Register Definitions.................................................................................................................41

4.2.1 TMP_DRx Registers .............................................................................................41

4.2.2 CUR_PP Register .................................................................................................41

4.2.3 STK_PP Register ..................................................................................................42

4.2.4 IDX_PP Register ...................................................................................................42

4.2.5 MVR_PP Register .................................................................................................42

4.2.6 MVW_PP Register ................................................................................................43

4.2.7 Related Registers ..................................................................................................43

5. Interrupt Controller 44

5.1 Architectural Description.........................................................................................................44

5.1.1 Posted versus Pending Interrupts..........................................................................45

5.2 Application Overview ..............................................................................................................45

5.3 Register Definitions.................................................................................................................46

5.3.1 INT_CLR0 Register ...............................................................................................46

5.3.2 INT_CLR1 Register................................................................................................47

5.3.3 INT_CLR2 Register ...............................................................................................48

5.3.4 INT_MSK0 Register ...............................................................................................49

5.3.5 INT_MSK1 Register ...............................................................................................49

5.3.6 INT_MSK2 Register ...............................................................................................50

5.3.7 INT_SW_EN Register ...........................................................................................50

5.3.8 INT_VC Register ...................................................................................................51

5.3.9 Related Registers ..................................................................................................51

6. General-Purpose I/O (GPIO) 52

6.1 Architectural Description.........................................................................................................52

6.1.1 General Description ...............................................................................................53

6.1.2 Digital I/O ...............................................................................................................53

6.1.3 Analog and Digital Inputs .......................................................................................53

6.1.4 Port 1 Distinctions ..................................................................................................53

6.1.5 Port 0 Distinctions ..................................................................................................53

6.1.6 GPIO Block Interrupts ............................................................................................54

6.1.7 Data Bypass...........................................................................................................55

6.2 Register Definitions.................................................................................................................56

6.2.1 PRTxDR Registers ................................................................................................56

6.2.2 PRTxIE Registers .................................................................................................56

6.2.3 PRTxDMx Registers .............................................................................................57

6.2.4 IO_CFG1 Register .................................................................................................58

6.2.5 IO_CFG2 Register .................................................................................................58

7. Analog-to-Digital Converter (ADC) 59

7.1 Architectural Description.........................................................................................................59

7.2 Brief Overview of ADC Components and Registers ...............................................................60

7.2.1 Interface Command/Status Block...........................................................................60

7.2.2 ADC .......................................................................................................................60

7.3 ADC Register Definitions - Application Interface ....................................................................64

7.3.1 ADC Data Register ................................................................................................64

7.3.2 ADC Status Register..............................................................................................64

7.4 Application Overview ..............................................................................................................65

7.4.1 Use of Application Interface ...................................................................................65

7.4.2 Status Codes..........................................................................................................65

7.4.3 ADC Usage Guidelines ..........................................................................................65

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 4

Contents

7.4.4 Typical ADC Operation Procedure.........................................................................66

8. Internal Main Oscillator (IMO) 67

8.1 Architectural Description.........................................................................................................67

8.2 Application Overview ..............................................................................................................67

8.2.1 Trimming the IMO ..................................................................................................67

8.2.2 Engaging Slow IMO ...............................................................................................67

8.3 Register Definitions.................................................................................................................68

8.3.1 IMO_TR Register ...................................................................................................68

8.3.2 IMO_TR1 Register ................................................................................................68

8.3.3 CPU_SCR1 Register .............................................................................................69

8.3.4 OSC_CR2 Register................................................................................................69

8.3.5 Related Registers ..................................................................................................69

8.4 Timing Diagrams.....................................................................................................................69

8.5 Clocking Strategy....................................................................................................................70

8.6 Usage Guidelines ...................................................................................................................70

8.6.1 Power Down Guidelines.........................................................................................70

8.7 Block Size/Area ......................................................................................................................70

8.8 Gate Count .............................................................................................................................70

8.9 Block Pin List ..........................................................................................................................70

8.10 Block Level Interfaces.............................................................................................................70

8.11 Initialization .............................................................................................................................70

8.12 Wounding................................................................................................................................70

8.13 On-Chip Debugger Modes......................................................................................................70

8.14 Test Modes .............................................................................................................................70

8.15 Power Modes..........................................................................................................................70

8.16 Design Flow ............................................................................................................................70

8.17 Operating Condition Requirements .......................................................................................71

8.18 DC Specifications ..................................................................................................................71

8.19 AC Specifications....................................................................................................................71

9. Internal Low-speed Oscillator (ILO) 72

9.1 Architectural Description.........................................................................................................72

9.2 Register Definitions.................................................................................................................73

9.2.1 ILO_TR Register ...................................................................................................73

10. External Crystal Oscillator (ECO) 74

10.1 Architectural Description.........................................................................................................74

10.2 Application Overview ..............................................................................................................75

10.3 Register Definitions.................................................................................................................76

10.3.1 ECO_ENBUS Register .........................................................................................76

10.3.2 ECO_TRIM Register .............................................................................................76

10.3.3 ECO_CFG Register ..............................................................................................76

10.3.4 Related Registers ..................................................................................................77

10.4 Usage Modes and Guidelines.................................................................................................77

11. Sleep and Watchdog 78

11.1 Architectural Description.........................................................................................................78

11.1.1 Sleep Control Implementation Logic ......................................................................79

11.1.2 Sleep Timer............................................................................................................81

11.2 Application Overview ..............................................................................................................81

11.3 Register Definitions.................................................................................................................82

11.3.1 RES_WDT Register ..............................................................................................82

11.3.2 SLP_CFG Register ...............................................................................................82

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Contents

11.3.3 SLP_CFG2 Register .............................................................................................83

11.3.4 SLP_CFG3 Register .............................................................................................83

11.3.5 Related Registers ..................................................................................................83

11.4 Timing Diagrams.....................................................................................................................84

11.4.1 Sleep Sequence.....................................................................................................84

11.4.2 Wakeup Sequence.................................................................................................85

11.4.3 Bandgap Refresh ...................................................................................................85

11.4.4 Watchdog Timer.....................................................................................................86

11.5 ................................................................................................................................................86

12. Regulated I/O 87

12.1 Architectural Description.........................................................................................................87

12.1.1 Bias Generator.......................................................................................................88

12.1.2 Charge Pump.........................................................................................................88

12.1.3 Comparator ............................................................................................................88

12.1.4 Replica Structure....................................................................................................88

12.1.5 Pass Transistors ....................................................................................................88

12.2 Application Overview ..............................................................................................................88

12.3 Register Definitions.................................................................................................................89

12.3.1 IO_CFG1 Register .................................................................................................89

12.3.2 IO_CFG2 Register .................................................................................................89

13. I/O Analog Multiplexer 90

13.1 Architectural Description.........................................................................................................90

13.2 Register Definitions.................................................................................................................91

13.2.1 MUX_CRx Registers..............................................................................................91

Section C: System Resources 92

14. Digital Clocks 96

14.1 Architectural Description.........................................................................................................96

14.1.1 Internal Main Oscillator ..........................................................................................96

14.1.2 Internal Low-speed Oscillator ................................................................................96

14.1.3 External Clock........................................................................................................97

14.2 Register Definitions.................................................................................................................99

14.2.1 USB_MISC_CR Register ......................................................................................99

14.2.2 OUT_P1 Register ..................................................................................................99

14.2.3 OSC_CR0 Register .............................................................................................101

14.2.4 OSC_CR2 Register .............................................................................................102

15. I2C Slave 103

15.1 Architectural Description.......................................................................................................103

15.1.1 Basic I

15.2 Application Overview ............................................................................................................105

15.2.1 Slave Operation ...................................................................................................105

15.3 Register Definitions...............................................................................................................106

15.3.1 I2C_XCFG Register .............................................................................................106

15.3.2 I2C_ADDR Register.............................................................................................106

15.3.3 I2C_CFG Register ..............................................................................................107

15.3.4 I2C_SCR Register ..............................................................................................109

15.3.5 I2C_DR Register ................................................................................................. 110

15.4 Timing Diagrams...................................................................................................................111

15.4.1 Clock Generation ................................................................................................. 111

15.4.2 Basic I/O Timing................................................................................................... 111

C Data Transfer .......................................................................................104

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Contents

15.4.3 Status Timing .......................................................................................................112

15.4.4 Slave Stall Timing.................................................................................................113

16. System Resets 114

16.1 Architectural Description.......................................................................................................114

16.2 Pin Behavior During Reset ...................................................................................................114

16.2.1 GPIO Behavior on Power Up ...............................................................................114

16.2.2 Powerup External Reset Behavior .......................................................................115

16.2.3 GPIO Behavior on External Reset .......................................................................115

16.3 Register Definitions...............................................................................................................116

16.3.1 CPU_SCR1 Register ........................................................................................... 116

16.3.2 CPU_SCR0 Register ........................................................................................... 117

16.4 Timing Diagrams...................................................................................................................118

16.4.1 Power-On-Reset ..................................................................................................118

16.4.2 External Reset ..................................................................................................... 118

16.4.3 Watchdog Timer Reset ........................................................................................118

16.4.4 Reset Details........................................................................................................120

16.5 Power Modes........................................................................................................................120

17. POR and LVD 121

17.1 Architectural Description.......................................................................................................121

17.2 Register Definitions...............................................................................................................122

17.2.1 VLT_CR Register .................................................................................................122

17.2.2 VLT_CMP Register ..............................................................................................122

18. SPI 123

18.1 Architectural Description.......................................................................................................123

18.1.1 SPI Protocol Function ..........................................................................................123

18.1.2 SPI Master Function ............................................................................................124

18.1.3 SPI Slave Function ..............................................................................................124

18.1.4 Input Synchronization ..........................................................................................125

18.2 Register Definitions...............................................................................................................125

18.2.1 SPI_TXR Register................................................................................................125

18.2.2 SPI_RXR Register ...............................................................................................126

18.2.3 SPI_CR Register..................................................................................................127

18.2.4 SPI_CFG Register ...............................................................................................128

18.2.5 Related Registers ................................................................................................128

18.3 Timing Diagrams...................................................................................................................129

18.3.1 SPI Mode Timing .................................................................................................129

18.3.2 SPIM Timing ........................................................................................................130

18.3.3 SPIS Timing .........................................................................................................134

19. Programmable Timer 137

19.1 Architectural Description.......................................................................................................137

19.1.1 Operation .............................................................................................................137

19.2 Register Definitions...............................................................................................................139

19.2.1 PT0_CFG Register ..............................................................................................139

19.2.2 PT1_CFG Register ..............................................................................................139

19.2.3 PT2_CFG Register ..............................................................................................140

19.2.4 PTx_DATA0 Register ...........................................................................................140

19.2.5 PTx_DATA1 Register ...........................................................................................140

20. Full-Speed USB 141

20.1 Architectural Description.......................................................................................................141

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Contents

20.2 Application Description .........................................................................................................141

20.2.1 USB SIE...............................................................................................................141

20.2.2 USB SRAM ..........................................................................................................142

20.2.3 Oscillator Lock .....................................................................................................144

20.2.4 Transceiver ..........................................................................................................144

20.2.5 USB Suspend ......................................................................................................145

20.2.6 Regulator .............................................................................................................145

20.3 Register Definitions...............................................................................................................147

20.3.1 USB_SOF0 Register............................................................................................147

20.3.2 USB_CR0 Register ..............................................................................................147

20.3.3 USBIO_CR0 Register ..........................................................................................148

20.3.4 USBIO_CR1 Register ..........................................................................................148

20.3.5 EP0_CR Register.................................................................................................149

20.3.6 EP0_CNT Register ..............................................................................................150

20.3.7 EP0_DRx Register...............................................................................................150

20.3.8 EPx_CNT1 Register.............................................................................................151

20.3.9 EPx_CNT0 Register.............................................................................................152

20.3.10 EPx_CR0 Register...............................................................................................153

20.3.11 PMAx_WA Register .............................................................................................154

20.3.12 PMAx_DR Register..............................................................................................155

20.3.13 PMAx_RA Register ..............................................................................................156

20.3.14 USB_CR1 Register ..............................................................................................157

20.3.15 USB_MISC_CR Register ....................................................................................157

20.3.16 IMO_TR1 Register ...............................................................................................158

Section D: Registers 159

21. Register Reference 163

21.1 Maneuvering Around the Registers ......................................................................................163

21.2 Register Conventions ...........................................................................................................163

21.3 Bank 0 Registers ..................................................................................................................164

21.4 Bank 1 Registers ..................................................................................................................212

Section E: Glossary 239

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 8

Section A: Overview

The enCoRe™ V family consists of many On-Chip Controller devices. The CY8C20x46A/46AS/96A/46L/96LCY7C643xx and CY7C604xx enCoRe V devices have fixed analog and digital resources in addition to a fast CPU, flash program memory, and SRAM data memory to support various algorithms.

For the most up-to-date ordering, pinout, packaging, or electrical specification information, refer to the enCoRe V device’s datasheet. For the most current technical reference manual information and newest product documentation, go to the Cypress web site at http://www.cypress.com >> Documentation.

This section contains:

■ Pin Information on page 15.

Document Organization

This manual is organized into sections and chapters, according to enCoRe V functionality. Each section contains a top-level architectural diagram and a register summary (if applicable). Most chapters within the sections have an introduction, an architectural/application description, register definitions, and timing diagrams. The sections are as follows:

■ Overview – Presents the top-level architecture, helpful information to get started, and document history and

conventions. The enCoRe V device pinouts are detailed in Pin Information, on page 15.

■ enCoRe V Core – Describes the heart of the enCoRe V device in various chapters, beginning with an architectural over-

view and a summary list of registers pertaining to the enCoRe V core.

■ System Resources – Presents additional enCoRe V system resources, beginning with an overview and a summary list of

registers pertaining to system resources.

■ Registers – Lists all enCoRe V device registers in register mapping tables, and presents bit-level detail of each register in

its own Register Reference chapter. Where applicable, detailed register descriptions are also located in each chapter.

■ Glossary – Defines the specialized terminology used in this manual. Glossary terms are presented in bold, italic font

throughout this manual.

■ Index – Lists the location of key topics and elements that constitute and empower the enCoRe V devices.

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 9

Top-Level Architecture

The enCoRe V block diagram on the next page illustrates the top-level architecture of the CY8C20X46A/46AS/96A/46L/96LCY7C643xx and CY7C604xx devices. Each major grouping in the diagram is covered in this manual in its own section: enCoRe V Core and System Resources. Banding these two main areas together is the communica-

tion network of the system bus.

enCoRe V Core

The enCoRe V Core is a powerful engine that supports a rich instruction set. It includes the SRAM for data storage, an inter- rupt controller for easy program execution to new addresses, sleep and watchdog timers, a regulated 3.0-V output option for Port 1 I/Os, and multiple clock sources that include the IMO (internal main oscillator) and ILO (internal low-speed oscillator)

for precision, programmable clocking.

The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. Within the CPU core are the SROM and Flash memory components that provide flexible pro-

gramming.

enCoRe V GPIOs provide connection to the CPU and external resources of the device. Each pin’s drive mode is selectable from four options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on low level and change from last read.

System Resources

The System Resources provide additional enCoRe V capability. These system resources include:

■ Digital clocks to increase flexibility.

■ I2C functionality with “no bus stalling.”

■ Various system resets supported by the M8C.

■ Power-on-reset (POR) circuit protection.

■ SPI master and slave functionality.

■ A programmable timer to provide periodic interrupts.

■ Clock boost network providing a stronger signal to switches.

■ Full-speed USB interface for USB 2.0 communication with 512 bytes of dedicated buffer memory and an internal 3-V reg-

ulator.

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 10

enCoRe V Core Top-Level Block Diagram

CAPSENSE

SYSTEM

1K/2K

SRAM

Inte rrupt

Controller

Sleep and

Watchdog

M ultip le Clo ck Sou rce s

Inte rna l Lo w Sp ee d O sc illator (IL O )

6/1 2/24 M H z In terna l M ain O sc illato r

(IM O)

PSoC CORE

CPU Core (M8C)

Supervisory ROM (SROM )

8K/16K/32K Flash

Nonvolatile M emory

SYSTEM RESOURCES

SYSTEM BUS

Analog

Reference

SYSTEM BUS

Port 3 Port 2 Port 1 P or t 0

CapSense

Module

Global Analog Interconnect

1.8/2.5/3V LDO

Analog

Mux

Two

Com parators

I2C

Slave

SPI

Master/

Slave

POR

and

LVD

USB

System

Resets

Internal Voltage

References

Three 16-Bit

Program mable

Tim ers

PWRSYS (Regulator)

Port 4

Digital

Clocks

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 11

Getting Started

The quickest path to understanding enCoRe V is by reading the enCoRe V device’s datasheet and using PSoC Designer™ Integrated Development Environment (IDE). This manual is useful for understanding the details of the enCoRe V integrated

circuit.

Important Note

For the most up-to-date Ordering, Packaging, or Electrical Specification information, refer to the individual

enCoRe V device’s datasheet or go to http://www.cypress.com.

Support

Free support for enCoRe V products is available online at http://www.cypress.com. Resources include Training Seminars, Discussion Forums, Application Notes, TightLink Technical Support Email/Knowledge Base, and Application Support Technicians.

Technical Support can be reached at http://www.cypress.com/support.

Product Upgrades

Cypress provides scheduled upgrades and version enhancements for PSoC Designer free of charge. You can order the upgrades from your distributor on CD-ROM or download them directly from http://www.cypress.com under Software. Also pro- vided are critical updates to system documentation under http://www.cypress.com >> Documentation.

Development Kits

Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store

contains development kits, C compilers, and all accessories for enCoRe V development. Go to the Cypress Online Store at

http://www.cypress.com under Order >> USB Kits.

Document History

This section serves as a chronicle of the CY8C20XX6A/AS/LenCoRe™ V and enCoRe™ V LV CY7C643xx and CY7C604xx Technical Reference Manual.

Technical Reference Manual History

Versio n/

Release Date

** September 2007 HMT First release of the enCoRe™ V and enCoRe™ V LV CY7C643xx and CY7C604xx Technical Reference Manual.

*A June 2008 HMT Second release of the enCoRe™ V and enCoRe™ V LV CY7C643xx and CY7C604xx Technical Reference Manual.

*B June 2009 FSU Third release of the enCoRe™ V and enCoRe™ V LV CY7C643xx and CY7C604xx Technical Reference Manual.

*C September 2009 FSU Fourth release of the enCoRe™ V and enCoRe™ V LV CY7C643xx and CY7C604xx Technical Reference Manual.

*D November 2009 FSU Multiple fixes, primarily to the sleep and I2C chapters.

*E December 2009 FSU Multiple fixes, primarily to the External Crystal Oscillator chapter.

*F September 2012 ANTG Updated external clock source description

*G October 2015 ASRI

*H November 2018 RAJV Updated the template

Originator Description of Change

Removed all instances of IMODIS related information and provided information for "no glitch protection in the device for an external clock".

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 12

Documentation Conventions

There are only four distinguishing font types used in this manual, besides those found in the headings.

■ The first is the use of italics when referencing a docu-

ment title or file name.

■ The second is the use of bold italics when referencing a

term described in the Glossary of this manual.

■ The third is the use of Times New Roman font, distinguish-

ing equation examples.

■ The fourth is the use of Courier New font, distinguish-

ing code examples.

The following table lists the register conventions that are specific to this manual. A more detailed set of register conventions is located in the Register Reference chapter on

page 163.

Convention Example Description

‘x’ in a register name

R R : 00 Read register or bit(s)

W W : 00 Write register or bit(s)

O RO : 00 Only a read/write register or bit(s).

L RL : 00 Logical register or bit(s)

C RC : 00 Clearable register or bit(s)

00 RW : 00 Reset value is 0x00 or 00h

XX RW : XX Register is not reset

0, 0,04h Register is in bank 0

1, 1,23h Register is in bank 1

x, x,F7h

Empty, grayedout table cell

PRTxIE

Multiple instances/address ranges of the same register

Reserved bit or group of bits, unless otherwise stated

Numeric Naming

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example,

‘14h’ or ‘3Ah’) and hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary

numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an

‘h’ or ‘b’ are decimal.

Units of Measure

This table lists the units of measure used in this manual.

Units of Measure

Symbol Unit of Measure

°C degrees Celsius

dB decibels

fF femtofarads

Hz hertz

k kilo, 1000

KB 1024 bytes

Kbit 1024 bits

kHz kilohertz (32.000)

k kilohms

MHz megahertz

M megaohms

A microamperes

F microfarads

s microseconds

V microvolts

Vrms microvolts root-mean-square

mA milliamperes

ms milliseconds

mV millivolts

nA nanoampheres

ns nanoseconds

nV nanovolts

 ohms

pF picofarads

pp peak-to-peak

ppm parts per million

sps samples per second

 sigma: one standard deviation

V volts

210, 1024

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 13

Acronyms

This table lists the acronyms that are used in this manual.

Acronyms

Acronym Description

ABUS analog output bus

AC alternating current

ADC analog-to-digital converter

API Application Programming Interface

BR bit rate

BRA bus request acknowledge

BRQ bus request

CI carry in

CMP compare

CO carry out

CPU central processing unit

CRC cyclic redundancy check

DAC digital-to-analog converter

DC direct current

DI digital or data input

DMA direct memory access

DO digital or data output

ECO external crystal oscillator

FB feedback

GIE global interrupt enable

GPIO general-purpose I/O

ICE in-circuit emulator

IDE integrated development environment

ILO internal low-speed oscillator

IMO internal main oscillator

I/O input/output

IOR I/O read

IOW I/O write

IPOR imprecise power-on-reset

IRQ interrupt request

ISR interrupt service routine

ISSP in system serial programming

IVR interrupt vector read

LRb last received bit

LRB last received byte

LSb least significant bit

LSB least significant byte

MISO master-in-slave-out

MOSI master-out-slave-in

MSb most significant bit

MSB most significant byte

PC program counter

PCH program counter high

PCL program counter low

PD power down

PMA PSoC® memory arbiter

POR power-on-reset

Acronyms (continued)

Acronym Description

PPOR precision power-on-reset

PRS pseudo random sequence

PSSDC power system sleep duty cycle

RAM random access memory

RETI return from interrupt

RO relaxation oscillator

ROM read-only memory

RW read/write

SIE serial interface engine

SE0 single-ended zero

SOF start of frame

SP stack pointer

SPI serial peripheral interconnect

SPIM serial peripheral interconnect master

SPIS serial peripheral interconnect slave

SRAM static random access memory

SROM supervisory read-only memory

SSADC single slope ADC

SSC supervisory system call

TC terminal count

USB universal serial bus

WDT watchdog timer

WDR watchdog reset

XRES external reset

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 14

1. Pin Information

P2[5]

P1[7] P1[5]

P1[3]

P0[3]

P0[7]

Vdd

P0[4]

P1[1]

P1[0]

P1[2]

P2[3]

P1[4]

XRES

P0[1]

Vss

QFN

(Top View)

1 2

3 4

12 11 10 9

161514

567

This chapter lists, describes, and illustrates all pins and pinout configurations for the CY8C20X46A/46AS/96A/46L/ 96LCY7C643xx and CY7C604xx enCoRe V devices. For up-to-date ordering, pinout, and packaging information, refer to the individual enCoRe V device’s datasheet or go to http://www.cypress.com.

1.1 Pinouts

TheCY8C20X46A/46AS/96A/46L/96LCY7C643xx and CY7C604xx enCoRe V devices are available in a variety of packages.

Every port pin (labeled with a “P”), except for Vss, Vdd, and XRES in the following tables and illustrations, is capable of Dig-

ital I/O.

1.1.1 CY7C60413 enCoRe V LV 16-Pin Part Pinout

Table 1-1. 16-Pin QFN/COL Part Pinout

Pin No.

1 IO I P2[5] XTAL Out

2 IO I P2[3] XTAL In

3 IOHR I P1[7] I2C SCL, SPI SS

4 IOHR I P1[5] I2C SDA, SPI MISO

5 IOHR I P1[3] SPI CLK

6 IOHR I P1[1]

7 Power Vss Ground pin

8 IOHR I P1[0]

9 IOHR I P1[2]

10 IOHR I P1[4] EXTCLK

11 Input XRES Active high external reset with internal pull down

12 IOH I P0[4]

13 Power Vdd Power pin

14 IOH I P0[7]

15 IOH I P0[3]

16 IOH I P0[1]

Legend A = Analog, I = Input, O = Output, H = 5-mA High Output Drive, R = Regulated Output Option.

Typ e

Digital Analog

These are the ISSP pins, which are not High-Z at POR.

Name Description

TC CLK

, I2C SCL, SPI MOSI

TC DATA

, I2C SDA, SPI CLK

Devices

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 15

1.1.2

P0[1] P2[7] P2[5] P2[3] P2[1] P3[3]

QFN

(Top View)

101112

131415

1 2 3 4 5 6 7 8

24 23 22 21 20 19 18 17

32313029282726

Vss

P0[3]

P0[7]

Vdd

P0[6]

P0[4]

P0[2]

P3[1] P1[7]

P0[0] P2[6]

P3[0] XRES

P1[5]

P1[3]

P1[1]

Vss

P1[0]

P1[2]

P1[4]

P1[6]

P2[4] P2[2] P2[0] P3[2]

P0[5]

Pin Information

CY7C60445 enCoRe V LV 32-Pin Part Pinout

Table 1-2. 32-Pin QFN Part Pinout

Pin No.

Digital

1 IOH I P0[1] Integrating input

2 IO I P2[7]

3 IO I P2[5] XTAL Out

4 IO I P2[3] XTAL In

5 IO I P2[1]

6 IO I P3[3]

7 IO I P3[1]

8 IOHR I P1[7] I2C SCL, SPI SS

9 IOHR I P1[5] I2C SDA, SPI MISO

10 IOHR I P1[3] SPI CLK

11 IOHR I P1[1]

12 Power Vss Ground pin

13 IOHR I P1[0]

14 IOHR I P1[2]

15 IOHR I P1[4] EXTCLK

16 IOHR I P1[6]

17 Input XRES Active high external reset with internal pull down

18 IO I P3[0]

19 IO I P3[2]

20 IO I P2[0]

21 IO I P2[2]

22 IO I P2[4]

23 IO I P2[6]

24 IOH I P0[0]

25 IOH I P0[2]

26 IOH I P0[4]

27 IOH I P0[6]

28 Power Vdd Power pin

29 IOH I P0[7]

30 IOH I P0[5]

31 IOH I P0[3]

32 Power Vss Ground pin

Legend A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.

Name Description

Analog

TC CLK

TC DATA

These are the ISSP pins, which are not High-Z at POR.

The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal.

, I2C SCL, SPI MOSI

, I2C SDA, SPI CLK

CY7C60445 enCoRe V LV Devices

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 16

1.1.3 CY7C64345, CY7C64343, enCoRe V 32-Pin Part Pinout

P0[1] P2[5] P2[3] P2[1] P1[7] P1[5]

QFN

(Top View)

101112

131415

1 2 3 4 5 6 7 8

24 23 22 21 20 19 18 17

32313029282726

Vss

P0[3]

P0[7]

Vdd

P0[6]

P0[4]

P0[2]

P1[3]

P1[1]

P0[0] P2[6]

P3[0]

XRES

Vss

D+

D-

Vdd

P1[0]

P1[2]

P1[4]

P1[6]

P2[4] P2[2]

P2[0] P3[2]

P0[5]

Pin Information

Table 1-3. 32-Pin QFN Part Pinout

Pin No.

Digital

1 IOH I P0[1]

2 IO I P2[5] XTAL Out

3 IO IP2[3]XTAL In

4 IO I P2[1]

5 IOHR I P1[7] I2C SCL, SPI SS

6 IOHR I P1[5] I2C SDA, SPI MISO

7 IOHR I P1[3] SPI CLK

8 IOHR I P1[1]

9 Power Vss Ground pin

10 IO D+ USB PHY

11 IO D- USB PHY

12 Power Vdd Power pin

13 IOHR I P1[0]

14 IOHR I P1[2]

15 IOHR I P1[4] EXTCLK

16 IOHR I P1[6]

17 Input XRES Active high external reset with internal

18 IO IP3[0]

19 IO IP3[2]

20 IO IP2[0]

21 IO I P2[2]

22 IO I P2[4]

23 IO I P2[6]

24 IOH I P0[0]

25 IOH I P0[2]

26 IOH I P0[4]

27 IOH I P0[6]

28 Power Vdd Power pin

29 IOH I P0[7]

30 IOH I P0[5]

31 IOH I P0[3]

32 Power Vss Ground pin

LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.

Name Description

Analog

TC CLK

TC DATA

pull down

These are the ISSP pins, which are not High Z at POR (Power On Reset).

, I2C SCL, SPI MOSI

, I2C SDA, SPI CLK

CY7C64345, CY7C64343 enCoRe V Devices

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 17

1.1.4 CY8C20646A/AS/LCY8C20666A/AS/L

QFN

(Top View)

P0[1]

Vss

P0[3]

P0[5]

P0[7]NCNC

Vdd

P0[6]

P0[4]

P0[2]

P0[0]

10 11

P2[7]

P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1]

P1[7]

35 34 33 32 31 30 29

28 27 26

4847464544

43424140393837

P2[4]

P2[2] P2[0] P4[2] P4[0]

P3[6] P3[4]

P3[2] P3[0]

XRES P1[6]

P2[6]

1 2 3 4 5 6 7 8 9

131415161718192021

P1[5]

P1[3]

P1[1]

Vss

D+

D-

Vdd

P1[0]

P1[2]

P1[4]

CY7C64355, CY7C64356 enCoRe V 48-Pin Part Pinout

Pin Information

TC CLK

TC DATA

, I2C SCL, SPI MOSI

, I2C SDA, SPI CLK

CY7C64355, CY7C64356 enCoRe VDevices

Pin No.

Digital

Name Description31 IO I P4[0]

Analog

Table 1-4. 48-Pin Part Pinout

Pin No.

Digital

1 NC No connection

2 IO I P2[7]

3 IO I P2[5] XTAL Out

4 IO I P2[3] XTAL In

5 IO I P2[1]

6 IO I P4[3]

7 IO IP4[1]

8 IO I P3[7]

9 IO I P3[5]

10 IO I P3[3]

11 IO I P3[1]

12 IOHR I P1[7] I2C SCL, SPI SS

13 IOHR I P1[5] I2C SDA, SPI MISO

14 NC No connection

15 NC No connection

16 IOHR I P1[3] SPI CLK

17 IOHR I P1[1]

18 Power Vss Ground pin

19 IO D + USB PHY

20 IO D - USB PHY

21 Power Vdd Power pin

22 IOHR I P1[0]

23 IOHR I P1[2]

24 IOHR I P1[4] EXTCLK

25 IOHR I P1[6]

26 Input XRES Active high external reset with internal pull down

27 IO I P3[0]

28 IO IP3[2]

29 IO IP3[4]

30 IO IP3[6]

32 IO I P4[2]

33 IO I P2[0] 41 Power Vdd Power pin

34 IO I P2[2] 42 NC No connection

35 IO I P2[4] 43 NC No connection

36 IO I P2[6] 44 IOH I P0[7]

37 IOH I P0[0] 45 IOH I P0[5]

38 IOH I P0[2] 46 IOH I P0[3]

39 IOH I P0[4] 47 Power Vss Ground pin

40 IOH I P0[6] 48 IOH I P0[1]

Legend A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.

Name Description

Analog

These are the ISSP pins, which are not High-Z at POR.

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 18

1.1.5 CY7C60455, CY7C60456 enCoRe V LV 48-Pin Part Pinout

QFN

(Top View)

P0[1]

Vss

P0[3]

P0[5]

P0[7]NCNC

Vdd

P0[6]

P0[4]

P0[2]

P0[0]

10 11

P2[7]

P2[5] P2[3] P2[1] P4[3] P4[1]

P3[7] P3[5] P3[3] P3[1] P1[7]

35 34 33 32 31 30 29

28 27 26

4847464544

43424140393837

P2[4]

P2[2] P2[0] P4[2] P4[0]

P3[6] P3[4]

P3[2] P3[0]

XRES P1[6]

P2[6]

1 2 3 4 5 6 7 8 9

131415161718192021

P1[5]

P1[3]

P1[1]

Vss

Vdd

P1[0]

P1[2]

P1[4]

Pin Information

Table 1-5. 48-Pin Part Pinout

Pin No.

Digital

1 NC No connection

2 IO I P2[7]

3 IO I P2[5] XTAL Out

4 IO I P2[3] XTAL In

5 IO I P2[1]

6 IO I P4[3]

7 IO IP4[1]

8 IO I P3[7]

9 IO I P3[5]

10 IO I P3[3]

11 IO I P3[1]

12 IOHR I P1[7] I2C SCL, SPI SS

13 IOHR I P1[5] I2C SDA, SPI MISO

14 NC No connection

15 NC No connection

16 IOHR I P1[3] SPI CLK

17 IOHR I P1[1]

18 Power Vss Ground pin

19 NC No connection

20 NC No connection

21 Power Vdd Power pin

22 IOHR I P1[0]

23 IOHR I P1[2]

24 IOHR I P1[4] EXTCLK

25 IOHR I P1[6]

26 Input XRES Active high external reset with

27 IO I P3[0]

28 IO IP3[2]

29 IO IP3[4]

30 IO IP3[6]

31 IO I P4[0]

32 IO I P4[2]

33 IO I P2[0] 41 Power Vdd Power pin

34 IO I P2[2] 42 NC No connection

35 IO I P2[4] 43 NC No connection

36 IO I P2[6] 44 IOH I P0[7]

37 IOH I P0[0] 45 IOH I P0[5]

38 IOH I P0[2] 46 IOH I P0[3]

39 IOH I P0[4] 47 Power Vss Ground pin

40 IOH I P0[6] 48 IOH I P0[1]

LEGEND

A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 19

CY7C60455, CY7C60456 enCoRe V LV Devices

Name Description

Analog

TC CLK

, I2C SCL, SPI MOSI

TC DATA

internal pull down

These are the ISSP pins, which are not High Z at POR (Power On Reset).

, I2C SDA, SPI CLK

Pin No.

Digital

Name Description

Analog

Pin Information

QFN

(Top View)

P0[1]

Vss

P0[3]

P0[5]

P0[7]

OCDE

OCDO

Vdd

P0[6]

P0[4]

P0[2]

P0[0]

10 11

P2[7]

OCDOE

P2[5] P2[3] P2[1] P4[3] P4[1]

P3[7] P3[5] P3[3] P3[1]

P1[7]

35 34

33 32 31 30 29

28 27 26

4847464544

43424140393837

P2[4]

P2[2] P2[0]

P4[2] P4[0]

P3[6] P3[4]

P3[2] P3[0]

XRES P1[6]

P2[6]

1 2 3 4 5 6 7 8 9

131415161718192021

P1[5]

CCLK

HCLK

P1[3]

P1[1]

Vss

D +

D -

Vdd

P1[0]

P1[2]

P1[4]

1.1.6 CY8C20066A, CY8CTMG200-00LTXI, CY8CTMG200A-00LTXI PSoC, CY7C64300 enCoRe V and CY7C60400 enCoRe V LV OCD 48-Pin Part Pinout

The 48-pin QFN part is for on-chip debugging (OCD). Note that this part is only used for in-circuit debugging. It is NOT avail- able for production.

Table 1-6. 48-Pin OCD Part Pinout

Pin No.

Digital

1 OCDOE OCD directional pin

2 IO I P2[7]

3 IO I P2[5] XTAL Out

4 IO I P2[3] XTAL In

5 IO I P2[1]

6 IO I P4[3]

7 IO IP4[1]

8 IO I P3[7]

9 IO I P3[5]

10 IO I P3[3]

11 IO I P3[1]

12 IOHR I P1[7] I2C SCL, SPI SS

13 IOHR I P1[5] I2C SDA, SPI MISO

14 CCLK OCD CPU CLK OUTPUT

15 HCLK OCD HIGH SPEED CLK

16 IOHR I P1[3] SPI CLK

17 IOHR I P1[1]

18 Power Vss Ground pin

19 IO D+ USB PHY

20 IO D– USB PHY

21 Power Vdd Power pin

22 IOHR I P1[0]

23 IOHR I P1[2]

24 IOHR I P1[4] EXTCLK

25 IOHR I P1[6]

26 Input XRES Active high external reset with

27 IO I P3[0]

28 IO IP3[2]

29 IO IP3[4]

30 IO IP3[6]

31 IO I P4[0]

32 IO I P4[2]

33 IO I P2[0] 41 Power Vdd Power pin

34 IO I P2[2] 42 OCDO OCD even data I/O

35 IO I P2[4] 43 OCDE OCD odd data output

36 IO I P2[6] 44 IOH I P0[7]

37 IOH I P0[0] 45 IOH I P0[5]

38 IOH I P0[2] 46 IOH I P0[3]

39 IOH I P0[4] 47 Power Vss Ground pin

40 IOH I P0[6] 48 IOH I P0[1]

Legend

A = Analog, I = Input, O = Output, NC = No Connection, H = 5-mA High Output Drive, R = Regulated Output Option.

Name Description

Analog

TC CLK

TC DATA

internal pull down

ISSP pin which is not High-Z at POR.

The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal.

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 20

, I2C SCL, SPI MOSI

, I2C SDA, SPI CLK

CY8C20066A, CY8CTMG200-00LTXI, CY8CTMG200A-00LTXI,

CY7C64300, CY7C60400 enCoRe V OCD Devices

NOT FOR PRODUCTION – OCD Part

Pin No.

Digital

Name Description

Analog

1.1.7 32-Pin QFN (with USB)

P0[1] P2[5] P2[3] P2[1] P1[7] P1[5]

QFN

(Top View)

101112

131415

1 2

3 4 5 6 7 8

24 23 22 21 20 19 18 17

32313029282726

Vss

P0[3]

P0[7]

Vdd

P0[6]

P0[4]

P0[2]

P1[3] P1[1]

P0[0] P2[6]

P3[0]

XRES

Vss

USB PHY, D+

USB D–

Vdd

P1[0]

P1[2]

P1[4]

P1[6]

P2[4] P2[2] P2[0] P3[2]

P0[5]

Pin Information

Table 1-7. Pin Definitions – CY8C20496A/L PSoC Device

Pin No.

Typ e

Digital Analog

Name Description

1 IOH I P0[1] Integrating Input

2 I/O I P2[5] XTAL Out

3 I/O I P2[3] XTAL In

4 I/O I P2[1]

5 IOHR I P1[7]

6 IOHR I P1[5]

C SCL, SPI SS

C SDA, SPI MISO

7 IOHR I P1[3] SPI CLK

8 IOHR I P1[1]

9 Power V

ISSP CLK

Ground Pin

, I2C SCL, SPI MOSI

10 I D+ USB D+

12 Power V

13 IOHR I P1[0]

D– USB D–

Power pin

ISSP DATA

, I2C SDA, SPI CLKI

14 IOHR I P1[2]

15 IOHR I P1[4] Optional external clock input (EXTCLK)

16 IOHR I P1[6]

17 Input XRES Active high external reset with internal pull-down

18 I/O I P3[0]

19 I/O I P3[2]

20 I/O I P2[0]

21 I/O I P2[2]

22 I/O I P2[4]

23 I/O I P2[6]

24 IOH I P0[0]

25 IOH I P0[2]

26 IOH I P0[4]

27 IOH I P0[6]

28 Power V

Power Pin

29 IOH I P0[7]

30 IOH I P0[5]

31 IOH I P0[3] Integrating Input

32 Power V

A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Legend

On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The

SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high-impedance state. On reset, after XRES deasserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high-impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.

The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not con-

nected to ground, it must be electrically floated and not connected to any other signal.

Alternate SPI clock.

Ground Pin

CY8C20496A/L PSoC Device

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 21

1.1.8 48-Pin SSOP

P0[7]

Vdd

P0[5]

P0[6]

P0[3]

P0[4]

0[1] P0[2]

P2[7]

P0[0]

P2[5]

P2[6]

P2[3]

P2[4]

P2[1]

P2[2]

P2[0]

P3[6]

P4[3]

P3[4]

P4[1]

P3[2]

P3[0]

P3[7]

XRES

P3[5]

P3[3]

P3[1] NC

P1[7]

P1[5 ]

P1[6]

P1[3]

P1[4]

P1[1] P1[2]

Vss P1[0]

SSOP

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21

23 24

48 47 46 45

44 42 40

41 39

38 37 36 35

32 31 30

29 28 27 26 25

Table 1-8. Pin Definitions – CY8C20536A, CY8C20546A, and CY8C20566A PSoC Device

CY8C20536A, CY8C20546A, and CY8C20566A

PSoC Device

Digital

Pin No.

1 IOH I P0[7] 2 IOH I P0[5] 3 IOH I P0[3] Integrating Input 4 IOH I P0[1] Integrating Input 5 I/O I P2[7] 6 I/O I P2[5] XTAL Out 7 I/O IP2[3]XTAL In 8 I/O I P2[1] 9 NC No connection 10 NC No connection 11 I/O I P4[3] 12 I/O I P4[1] 13 NC No connection 14 I/O I P3[7] 15 I/O I P3[5] 16 I/O I P3[3] 17 I/O I P3[1] 18 NC No connection 19 NC No connection 20 IOHR I P1[7]

21 IOHR I P1[5]

22 IOHR I P1[3] SPI CLK 23 IOHR I P1[1]

24 V

25 IOHR I P1[0]

26 IOHR I P1[2] 27 IOHR I P1[4]

28 IOHR IP1[6] 29 NC No connection 30 NC No connection 31 NC No connection 32 NC No connection

Name

Analog

C SCL, SPI SS

C SDA, SPI MISO

ISSP CLK Ground Pin

ISSP DATA

, I2C SCL, SPI MOSI

Description

, I2C SDA, SPI CLK

Optional external clock input (

EXT CLK)

Pin Information

33 NC No connection 41 I/O I P2[2] 34 NC No connection 42 I/O I P2[4] 35 XRES Active high external reset with internal

36 I/O I P3[0] 44 IOH I P0[0] 37 I/O I P3[2] 45 IOH I P0[2] 38 I/O I P3[4] 46 IOH I P0[4] 39 I/O I P3[6] 47 IOH I P0[6] 40 I/O I P2[0] 48 Power V

Legend A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 22

Analog

Name

Description

Power Pin

Digital

Pin No.

pull-down

On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The

Alternate SPI clock.

43 I/O I P2[6]

Section B: enCoRe V Core

1K, 2K

SRAM

Interrupt

Controller

Sleep and Watchdog

Multiple Clock Sources

Internal Low Speed Oscillator (ILO)

6/12/24 MHz Internal Main Oscillator (IMO)

CORE

CPU Core (M8C)

Supervisory ROM (SROM)

8K, 16K, 32K Flash

Nonvolatile Memory

SYSTEM BUS

Port 3 Port 2 Port 1 Port 0

1.8/2.5/3V LDO

PWRSYS

(Regulator)

Port 4

The enCoRe V Core section discusses the core components of an enCoRe V device with a base part number of CY7C643xx and CY7C604xx and the registers associated with those components. The core section covers the heart of the enCoRe V

device, which includes the M8C microcontroller; SROM, interrupt controller, GPIO, and SRAM paging; multiple clock

sources such as IMO and ILO; and sleep and watchdog functionality. This section includes these chapters:

■ CPU Core (M8C) on page 26.

■ Supervisory ROM (SROM) on page 32.

■ RAM Paging on page 38.

■ Interrupt Controller on page 44.

■ General-Purpose I/O (GPIO) on page 52.

Top-Level Core Architecture

This figure displays the top-level architecture of the enCoRe V core. Each component of the figure is discussed at length in this section.

enCoRe V Core Block Diagram

■ Internal Main Oscillator (IMO) on page 67.

■ Internal Low-speed Oscillator (ILO) on page 72.

■ External Crystal Oscillator (ECO), on page 74

■ Sleep and Watchdog on page 78.

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 23

Core Register Summary

This table lists all the enCoRe V registers for the CPU core in address order within their system resource configuration. The

grayed out bits are reserved bits. If you write these bits, always write them with a value of ‘0’. For the core registers, the first

‘x’ in some register addresses represents either bank 0 or bank 1. These registers are listed throughout this manual in bank

0, even though they are also available in bank 1.

Summary Table of the Core Registers

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access

M8C REGISTER

x,F7h CPU_F

x,6Ch TMP_DR0

x,6Dh TMP_DR1

x,6Eh TMP_DR2

x,6Fh TMP_DR3

0,D0h CUR_PP

0,D1h STK_PP

0,D3h IDX_PP

0,D4h MVR_PP

0,D5h MVW_PP

0,DAh INT_CLR0

0,DBh INT_CLR1

0,DCh INT_CLR2

0,DEh INT_MSK2

0,DFh INT_MSK1

0,E0h INT_MSK0

0,E1h INT_SW_EN

0,E2h INT_VC Pending Interrupt[7:0] RC : 00

0,00h PRT0DR Data[7:0] RW : 00

0,01h PRT0IE Interrupt Enables[7:0] RW : 00

0,04h PRT1DR Data[7:0] RW : 00

0,05h PRT1IE Interrupt Enables[7:0] RW : 00

0,08h PRT2DR Data[7:0] RW : 00

0,09h PRT2IE Interrupt Enables[7:0] RW : 00

0,0Ch PRT3DR Data[7:0] RW : 00

0,0Dh PRT3IE Interrupt Enables[7:0] RW : 00

1,00h PRT0DM0 Drive Mode 0[7:0] RW : 00

1,01h PRT0DM1 Drive Mode 1[7:0] RW : FF

1,04h PRT1DM0 Drive Mode 0[7:0] RW : 00

1,05h PRT1DM1 Drive Mode 1[7:0] RW : FF

1,08h PRT2DM0 Drive Mode 0[7:0] RW : 00

1,09h PRT2DM1 Drive Mode 1[7:0] RW : FF

1,0Ch PRT3DM0 Drive Mode 0[7:0] RW : 00

1,0Dh PRT3DM1 Drive Mode 1[7:0] RW : FF

0,10h PRTxDR Data[7:0] RW : 00

0,11h PRTxIE Interrupt Enables[7:0] RW : 00

1,10h PRTxDM0 Drive Mode 0[7:0] RW : 00

1,11h PRTxDM1 Drive Mode 0[7:0] RW : 00

PgMode[1:0] XIO_1 XIO Carry Zero GIE RL : 02

RAM PAGING (SRAM) REGISTERS (page 38)

INTERRUPT CONTROLLER REGISTERS (page 44)

I2C Sleep SPI GPIO Timer0 Reserved Reserved V Monitor RW : 00

Endpoint3 Endpoint2 Endpoint1 Endpoint0 USB SOF USB Bus Rst Timer2 Timer1 RW : 00

USB_WAKE Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4 RW : 00

USB Wakeu p

Endpoint3 Endpoint2 Endpoint1 Endpoint0 USB SOF

I2C Sleep SPI GPIO Timer0 Reserved Reserved V Monitor RW : 00

GENERAL-PURPOSE I/O (GPIO) REGISTERS (page 56)

(page 26)

Data[7:0] RW : 00

Page Bits[2:0] RW : 0

Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4 RW : 00

USB Bus Reset

Timer2 Ti mer1 RW : 00

ENSWINT RW : 0

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 24

Summary Table of the Core Registers (continued)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access

1,DCh IO_CFG1 StrongP Range[1:0]

INTERNAL MAIN OSCILLATOR (IMO) REGISTER (page 68)

1,E8h IMO_TR Trim[7:0] W: 00

1,FAh IMO_TR1

x,FEh CPU_SCR1

1,E2h OSC_CR2

1,E9h ILO_TR

1,D2h ECO_ENBUS

1,D3h ECO_TRIM

1,E1h ECO_CFG

0,E3h RES_WDT WDSL_Clear[7:0] W : 00

1,EBh SLP_CFG

1,ECh SLP_CFG2

1,EDh SLP_CFG3

Legend

L The and f, expr; or f, expr; and xor f, expr instructions can be used to modify this register. x An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used. C Clearable register or bit(s). R Read register or bit(s). W Write register or bit(s).

IRESS SLIM[1:O] IRAMDIS # : 00

CLK48MEN EXTCLKEN RSVD RW : 00

INTERNAL LOW-SPEED OSCILLATOR (ILO) REGISTER (page 73)

PD_MODE ILOFREQ SATBIASB Freq Trim[3:0] RW : 18

EXTERNAL CRYSTAL OSCILLATOR (ECO) REGISTERS (page 74)

SLEEP AND WATCHDOG REGISTERS (page 82)

PSSDC[1:0] RW : 0

DBL_TAPS T2TAP [1:0] T1TAP [1:0] T0TAP [1:0] RW : 0x7F

P1_LOW_

THRS

ECO_XGM[2:0] ECO_LP[1:0] RW : 00

SPICLK_ON

_P10

ECO_LPM ECO_EXW ECO_EX RW : 00

ALT_Buzz [1:0] I2C_ON LSO_OFF RW : 00

REG_EN IOINT RW : 00

Fine Trim[2:0] RW : 00

ECO_ENBUS[2:0] RW : 07

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 25

2. CPU Core (M8C)

This chapter explains the CPU Core, called the M8C, and its associated register. It covers the internal M8C registers, address

spaces, instruction set and formats. For additional information concerning the M8C instruction set, refer to the PSoC Designer Assembly Language User Guide available at http://www.cypress.com. For a quick reference of all enCoRe V regis-

ters in address order, refer to the Register Reference chapter on page 163.

2.1 Overview

The M8C is a four MIPS 8-bit Harvard architecture micropro-

cessor. Selectable processor clock speeds up to 24 MHz enable you to tune the M8C to a particular application’s performance and power requirements. The M8C supports a rich instruction set that allows for efficient low-level language support.

2.2 Internal Registers

The M8C has five internal registers that are used in program execution. Here is a list of these registers.

■ Accumulator (A)

■ Index (X)

■ Program Counter (PC)

■ Stack Pointer (SP)

■ Flags (F)

All the internal M8C registers are 8 bits in width, except for

the PC, which is 16 bits wide. Upon reset, A, X, PC, and SP

are reset to 00h. The Flag register (F) is reset to 02h, indi-

cating that the Z flag is set. With each stack operation, the SP is automatically incre-

mented or decremented so that it always points to the next

stack byte in RAM. If the last byte in the stack is at address

, the stack pointer wraps to RAM address 00h. It is the

FFh

firmware developer’s responsibility to ensure that the stack

does not overlap with user-defined variables in RAM.

The F register is read by using address F7h in either register bank.

2.3 Address Spaces

The M8C has three address spaces: ROM, RAM, and regis-

ters. The ROM address space includes the Supervisory ROM (SROM) and the flash. The ROM address space is

accessed through its own address and data bus.

The ROM address space is composed of the SROM and the on-chip flash program store. Flash is organized into 128byte blocks. Program store page boundaries are not an issue because the M8C automatically increments the 16-bit PC on every instruction. This makes the block boundaries invisible to user code. Instructions occurring on a 128-byte flash page boundary (with the exception of JMP instructions) incur an extra M8C clock cycle, because the upper byte of the PC is incremented.

The register address space is used to configure the enCoRe Vmicrocontroller’s programmable blocks. It consists of two banks of 256 bytes each. To switch between banks, the XIO bit in the Flag register is set or cleared (set for Bank1, cleared for Bank0). The common convention is to leave the bank set to Bank0 (XIO cleared), switch to Bank1 as needed (set XIO), then switch back to Bank0.

With the exception of the F register, the M8C internal registers are not accessible via an explicit register address. The internal M8C registers are accessed using these instructions:

■ MOV A, expr

■ MOV X, expr

■ SWAP A, SP

■ OR F, expr

■ JMP LABEL

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 26

CPU Core (M8C)

2.4 Instruction Set Summary

The instruction set is summarized in both Ta bl e 2-1 and Table 2-2 (in numeric and mnemonic order, respectively), and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (visit http://www.cypress.com).

Table 2-1. Instruction Set Summary Sorted Numerically by Opcode

Instruction Format Flags

Bytes

Cycles

Opcode Hex

00 15 1 SSC 2D 8 2 OR [X+expr], A Z 5A 5 2 MOV [expr], X

01 4 2 ADD A, expr C, Z 2E 9 3 OR [expr], expr Z 5B 4 1 MOV A, X Z

02 6 2 ADD A, [expr] C, Z 2F 10 3 OR [X+expr], expr Z 5C 4 1 MOV X, A

03 7 2 ADD A, [X+expr] C, Z 30 9 1 HALT 5D 6 2 MOV A, reg[expr] Z

04 7 2 ADD [expr], A C, Z 31 4 2 XOR A, expr Z 5E 7 2 MOV A, reg[X+expr] Z

05 8 2 ADD [X+expr], A C, Z 32 6 2 XOR A, [expr] Z 5F 10 3 MOV [expr], [expr]

06 9 3 ADD [expr], expr C, Z 33 7 2 XOR A, [X+expr] Z 60 5 2 MOV reg[expr], A

07 10 3 ADD [X+expr], expr C, Z 34 7 2 XOR [expr], A Z 61 6 2 MOV reg[X+expr], A

08 4 1 PUSH A 35 8 2 XOR [X+expr], A Z 62 8 3 MOV reg[expr], expr

09 4 2 ADC A, expr C, Z 36 9 3 XOR [expr], expr Z 63 9 3 MOV reg[X+expr], expr

0A 6 2 ADC A, [expr] C, Z 37 10 3 XOR [X+expr], expr Z 64 4 1 ASL A C, Z

0B 7 2 ADC A, [X+expr] C, Z 38 5 2 ADD SP, expr 65 7 2 ASL [expr] C, Z

0C 7 2 ADC [expr], A C, Z 39 5 2 CMP A, expr

0D 8 2 ADC [X+expr], A C, Z 3A 7 2 CMP A, [expr] 67 4 1 ASR A C, Z

0E 9 3 ADC [expr], expr C, Z 3B 8 2 CMP A, [X+expr] 68 7 2 ASR [expr] C, Z

0F 10 3 ADC [X+expr], expr C, Z 3C 8 3 CMP [expr], expr 69 8 2 ASR [X+expr] C, Z

10 4 1 PUSH X 3D 9 3 CMP [X+expr], expr 6A 4 1 RLC A C, Z

11 4 2 SUB A, expr C, Z 3E 10 2 MVI A, [ [expr]++ ] Z 6B 7 2 RLC [expr] C, Z

12 6 2 SUB A, [expr] C, Z 3F 10 2 MVI [ [expr]++ ], A 6C 8 2 RLC [X+expr] C, Z

13 7 2 SUB A, [X+expr] C, Z 40 4 1 NOP 6D 4 1 RRC A C, Z

14 7 2 SUB [expr], A C, Z 41 9 3 AND reg[expr], expr Z 6E 7 2 RRC [expr] C, Z

15 8 2 SUB [X+expr], A C, Z 42 10 3 AND reg[X+expr], expr Z 6F 8 2 RRC [X+expr] C, Z

16 9 3 SUB [expr], expr C, Z 43 9 3 OR reg[expr], expr Z 70 4 2 AND F, expr C, Z

17 10 3 SUB [X+expr], expr C, Z 44 10 3 OR reg[X+expr], expr Z 71 4 2 OR F, expr C, Z

18 5 1 POP A Z 45 9 3 XOR reg[expr], expr Z 72 4 2 XOR F, expr C, Z

19 4 2 SBB A, expr C, Z 46 10 3 XOR reg[X+expr], expr Z 73 4 1 CPL A Z

1A 6 2 SBB A, [expr] C, Z 47 8 3 TST [expr], expr Z 74 4 1 INC A C, Z

1B 7 2 SBB A, [X+expr] C, Z 48 9 3 TST [X+expr], expr Z 75 4 1 INC X C, Z

1C 7 2 SBB [expr], A C, Z 49 9 3 TST reg[expr], expr Z 76 7 2 INC [expr] C, Z

1D 8 2 SBB [X+expr], A C, Z 4A 10 3 TST reg[X+expr], expr Z 77 8 2 INC [X+expr] C, Z

1E 9 3 SBB [expr], expr C, Z 4B 5 1 SWAP A, X Z 78 4 1 DEC A C, Z

1F 10 3 SBB [X+expr], expr C, Z 4C 7 2 SWAP A, [expr] Z 79 4 1 DEC X C, Z

20 5 1 POP X 4D 7 2 SWAP X, [expr] 7A 7 2 DEC [expr] C, Z

21 4 2 AND A, expr Z 4E 5 1 SWAP A, SP Z 7B 8 2 DEC [X+expr] C, Z

22 6 2 AND A, [expr] Z 4F 4 1 MOV X, SP 7C 13 3 LCALL

23 7 2 AND A, [X+expr] Z 50 4 2 MOV A, expr Z 7D 7 3 LJMP

24 7 2 AND [expr], A Z 51 5 2 MOV A, [expr] Z 7E 10 1 RETI C, Z

25 8 2 AND [X+expr], A Z 52 6 2 MOV A, [X+expr] Z 7F 8 1 RET

26 9 3 AND [expr], expr Z 53 5 2 MOV [expr], A 8x 5 2 JMP

27 10 3 AND [X+expr], expr Z 54 6 2 MOV [X+expr], A 9x 11 2 CALL

28 11 1 ROMX Z 55 8 3 MOV [expr], expr Ax 5 2 JZ

29 4 2 OR A, expr Z 56 9 3 MOV [X+expr], expr Bx 5 2 JNZ

2A 6 2 OR A, [expr] Z 57 4 2 MOV X, expr Cx 5 2 JC

2B 7 2 OR A, [X+expr] Z 58 6 2 MOV X, [expr] Dx 5 2 JNC

2C 7 2 OR [expr], A Z 59 7 2 MOV X, [X+expr] Ex 7 2 JACC

Note 1 Interrupt acknowledge to Interrupt Vector table = 13 cycles. Fx 13 2 INDEX Z

Note 2 The number of cycles required by an instruction is increased by one for instructions that span

128 byte page boundaries in the flash memory space.

Opcode Hex

Instruction Format Flags

Bytes

Cycles

if (A=B) Z=1

if (A<B) C=1

Instruction Format Flags

Bytes

Cycles

Opcode Hex

66 8 2 ASL [X+expr] C, Z

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 27

Table 2-2. Instruction Set Summary Sorted Alphabetically by Mnemonic

CPU Core (M8C)

Instruction Format Flags

Bytes

Cycles

Opcode Hex

09 4 2 ADC A, expr C, Z 76 7 2 INC [expr] C, Z 20 5 1 POP X

0A 6 2 ADC A, [expr] C, Z 77 8 2 INC [X+expr] C, Z 18 5 1 POP A Z

0B 7 2 ADC A, [X+expr] C, Z Fx 13 2 INDEX Z 10 4 1 PUSH X

0C 7 2 ADC [expr], A C, Z Ex 7 2 JACC 08 4 1 PUSH A

0D 8 2 ADC [X+expr], A C, Z Cx 5 2 JC 7E 10 1 RETI C, Z

0E 9 3 ADC [expr], expr C, Z 8x 5 2 JMP 7F 8 1 RET

0F 10 3 ADC [X+expr], expr C, Z Dx 5 2 JNC 6A 4 1 RLC A C, Z

01 4 2 ADD A, expr C, Z Bx 5 2 JNZ 6B 7 2 RLC [expr] C, Z

02 6 2 ADD A, [expr] C, Z Ax 5 2 JZ 6C 8 2 RLC [X+expr] C, Z

03 7 2 ADD A, [X+expr] C, Z 7C 13 3 LCALL 28 11 1 ROMX Z

04 7 2 ADD [expr], A C, Z 7D 7 3 LJMP 6D 4 1 RRC A C, Z

05 8 2 ADD [X+expr], A C, Z 4F 4 1 MOV X, SP 6E 7 2 RRC [expr] C, Z

06 9 3 ADD [expr], expr C, Z 50 4 2 MOV A, expr Z 6F 8 2 RRC [X+expr] C, Z

07 10 3 ADD [X+expr], expr C, Z 51 5 2 MOV A, [expr] Z 19 4 2 SBB A, expr C, Z

38 5 2 ADD SP, expr 52 6 2 MOV A, [X+expr] Z 1A 6 2 SBB A, [expr] C, Z

21 4 2 AND A, expr Z 53 5 2 MOV [expr], A 1B 7 2 SBB A, [X+expr] C, Z

22 6 2 AND A, [expr] Z 54 6 2 MOV [X+expr], A 1C 7 2 SBB [expr], A C, Z

23 7 2 AND A, [X+expr] Z 55 8 3 MOV [expr], expr 1D 8 2 SBB [X+expr], A C, Z

24 7 2 AND [expr], A Z 56 9 3 MOV [X+expr], expr 1E 9 3 SBB [expr], expr C, Z

25 8 2 AND [X+expr], A Z 57 4 2 MOV X, expr 1F 10 3 SBB [X+expr], expr C, Z

26 9 3 AND [expr], expr Z 58 6 2 MOV X, [expr] 00 15 1 SSC

27 10 3 AND [X+expr], expr Z 59 7 2 MOV X, [X+expr] 11 4 2 SUB A, expr C, Z

70 4 2 AND F, expr C, Z 5A 5 2 MOV [expr], X 12 6 2 SUB A, [expr] C, Z

41 9 3 AND reg[expr], expr Z 5B 4 1 MOV A, X Z 13 7 2 SUB A, [X+expr] C, Z

42 10 3 AND reg[X+expr], expr Z 5C 4 1 MOV X, A 14 7 2 SUB [expr], A C, Z

64 4 1 ASL A C, Z 5D 6 2 MOV A, reg[expr] Z 15 8 2 SUB [X+expr], A C, Z

65 7 2 ASL [expr] C, Z 5E 7 2 MOV A, reg[X+expr] Z 16 9 3 SUB [expr], expr C, Z

66 8 2 ASL [X+expr] C, Z 5F 10 3 MOV [expr], [expr] 17 10 3 SUB [X+expr], expr C, Z

67 4 1 ASR A C, Z 60 5 2 MOV reg[expr], A 4B 5 1 SWAP A, X Z

68 7 2 ASR [expr] C, Z 61 6 2 MOV reg[X+expr], A 4C 7 2 SWAP A, [expr] Z

69 8 2 ASR [X+expr] C, Z 62 8 3 MOV reg[expr], expr 4D 7 2 SWAP X, [expr]

9x 11 2 CALL 63 9 3 MOV reg[X+expr], expr 4E 5 1 SWAP A, SP Z

39 5 2 CMP A, expr

3A 7 2 CMP A, [expr] 3F 10 2 MVI [ [expr]++ ], A 48 9 3 TST [X+expr], expr Z

3B 8 2 CMP A, [X+expr] 40 4 1 NOP 49 9 3 TST reg[expr], expr Z

3C 8 3 CMP [expr], expr 29 4 2 OR A, expr Z 4A 10 3 TST reg[X+expr], expr Z

3D 9 3 CMP [X+expr], expr 2A 6 2 OR A, [expr] Z 72 4 2 XOR F, expr C, Z

73 4 1 CPL A Z 2B 7 2 OR A, [X+expr] Z 31 4 2 XOR A, expr Z

78 4 1 DEC A C, Z 2C 7 2 OR [expr], A Z 32 6 2 XOR A, [expr] Z

79 4 1 DEC X C, Z 2D 8 2 OR [X+expr], A Z 33 7 2 XOR A, [X+expr] Z

7A 7 2 DEC [expr] C, Z 2E 9 3 OR [expr], expr Z 34 7 2 XOR [expr], A Z

7B 8 2 DEC [X+expr] C, Z 2F 10 3 OR [X+expr], expr Z 35 8 2 XOR [X+expr], A Z

30 9 1 HALT 43 9 3 OR reg[expr], expr Z 36 9 3 XOR [expr], expr Z

74 4 1 INC A C, Z 44 10 3 OR reg[X+expr], expr Z 37 10 3 XOR [X+expr], expr Z

75 4 1 INC X C, Z 71 4 2 OR F, expr C, Z 45 9 3 XOR reg[expr], expr Z

Note 1 Interrupt acknowledge to Interrupt Vector table = 13 cycles. 46 10 3 XOR reg[X+expr], expr Z

Note 2 The number of cycles required by an instruction is increased by one for instructions that span

128 byte page boundaries in the flash memory space.

if (A=B) Z=1

if (A<B) C=1

Opcode Hex

3E 10 2 MVI A, [ [expr]++ ] Z 47 8 3 TST [expr], expr Z

Instruction Format Flags

Bytes

Cycles

Opcode Hex

Instruction Format Flags

Bytes

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 28

CPU Core (M8C)

2.5 Instruction Formats

The M8C has a total of seven instruction formats that use instruction lengths of one, two, and three bytes. All instruction bytes are taken from the program memory (flash), using an address and data bus that are independent from the address and data buses used for register and RAM access.

While examples of instructions are given in this section,

refer to the PSoC Designer Assembly Language User Guide

for detailed information on individual instructions.

2.5.1 One-Byte Instructions

Many instructions, such as some of the MOV instructions, have single-byte forms because they do not use an address or data as an operand. As shown in Table 2-3, one-byte instructions use an 8-bit opcode. The set of one-byte instructions are divided into four categories, according to where their results are stored.

Table 2-3. One-Byte Instruction Format

Byte 0

8-Bit Opcode

The first category of one-byte instructions are those that do not update any register or RAM. Only the one-byte NOP and

SSC instructions fit this category. While the program coun- ter is incremented as these instructions execute, they do not

cause any other internal M8C registers to update, nor do these instructions directly affect the register space or the RAM address space. The SSC instruction causes SROM code to run, which modifies RAM and the M8C internal registers.

The second category contains the two PUSH instructions. The PUSH instructions are unique because they are the only one-byte instructions that modify a RAM address. These instructions automatically increment the SP.

The third category contains the HALT instruction. The instruction is unique because it is the only one-byte instruction that modifies a user register. The HALT instruction modifies user register space address FFh (CPU_SCR0 register).

The final category for one-byte instructions are those that update the internal M8C registers. This category holds the largest number of instructions:

ASL, ASR, CPL, DEC, INC,

MOV, POP, RET, RETI , RLC, ROMX, RRC, SWAP. These

instructions cause the A, X, and SP registers or SRAM to update.

HALT

2.5.2 Two-Byte Instructions

The majority of M8C instructions are two bytes in length. While these instructions are divided into categories identical to the one-byte instructions, this does not provide a useful distinction between the three two-byte instruction formats that the M8C uses.

Table 2-4. Two-Byte Instruction Formats

Byte 0 Byte 1

4-Bit Opcode 12-Bit Relative Address

8-Bit Opcode 8-Bit Data

8-Bit Opcode 8-Bit Address

The first two-byte instruction format, shown in the first row of

Table 2-4, is used by short jumps and calls:

JACC, INDEX, JC, JNC, JNZ, JZ. This instruction format

uses only four bits for the instruction opcode, leaving 12 bits to store the relative destination address in a two’s-complement form. These instructions can change program execution to an address relative to the current address by –2048 or +2047.

The second two-byte instruction format, shown in the second row of Table 2-4, is used by instructions that employ the

Source Immediate addressing mode (see the PSoC Designer Assembly Language User Guide). The destination

for these instructions is an internal M8C register, while the source is a constant value. An example of this type of instruction is

The third two-byte instruction format, shown in the third row of Ta b le 2 -4, is used by a wide range of instructions and addressing modes. The following is a list of the addressing modes that use this third two-byte instruction format:

■ Source Direct (ADD A, [7])

■ Source Indexed (ADD A, [X+7])

■ Destination Direct (ADD [7], A)

■ Destination Indexed (ADD [X+7], A)

■ Source Indirect Post Increment (MVI A, [7])

■ Destination Indirect Post Increment (MVI [7], A)

For more information on addressing modes see the PSoC Designer Assembly Language User Guide.

ADD A, 7.

CALL, JMP,

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 29

CPU Core (M8C)

2.5.3 Three-Byte Instructions

The three-byte instruction formats are the second most prevalent instruction formats. These instructions need three bytes because they either move data between two addresses in the user accessible address space (registers and RAM) or they hold 16-bit absolute addresses as the destination of a long jump or long call.

Table 2-5. Three-Byte Instruction Formats

Byte 0 Byte 1 Byte 2

8-Bit Opcode 16-Bit Address (MSB, LSB)

8-Bit Opcode 8-Bit Address 8-Bit Data

8-Bit Opcode 8-Bit Address 8-Bit Address

The first instruction format, shown in the first row of

Table 2-5, is used by the LJMP and LCALL instructions.

These instructions change program execution unconditionally to an absolute address. The instructions use an 8-bit opcode, leaving room for a 16-bit destination address.

The second three-byte instruction format, shown in the second row of Tab l e 2- 5, is used by the following two addressing modes:

■ Destination Direct Source Immediate (ADD [7], 5)

■ Destination Indexed Source Immediate

(ADD [X+7], 5)

The third three-byte instruction format, shown in the third row of Ta bl e 2-5, is for the Destination Direct Source Direct addressing mode, which is used by only one instruction. This instruction format uses an 8-bit opcode followed by two 8-bit addresses. The first address is the destination address in RAM, while the second address is the source address in RAM. The following is an example of this instruction:

MOV [7], [5]

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 30

+ 227 hidden pages

Cypress CY7C60413, CY7C60445, CY7C64355, CY7C60455, CY7C64356 Technical Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Section A: Overview

Document Organization

Top-Level Architecture

Getting Started

Document History

Documentation Conventions

1. Pin Information

1.1 Pinouts

1.1.1 CY7C60413 enCoRe V LV 16-Pin Part Pinout

CY7C60445 enCoRe V LV 32-Pin Part Pinout

1.1.3 CY7C64345, CY7C64343, enCoRe V 32-Pin Part Pinout

1.1.5 CY7C60455, CY7C60456 enCoRe V LV 48-Pin Part Pinout

1.1.6 CY8C20066A, CY8CTMG200-00LTXI, CY8CTMG200A-00LTXI PSoC, CY7C64300 enCoRe V and CY7C60400 enCoRe V LV OCD 48-Pin Part Pinout

1.1.7 32-Pin QFN (with USB)

1.1.8 48-Pin SSOP

Section B: enCoRe V Core

Top-Level Core Architecture

Core Register Summary

2. CPU Core (M8C)

2.1 Overview

2.2 Internal Registers

2.3 Address Spaces

2.4 Instruction Set Summary

2.5 Instruction Formats

2.5.1 One-Byte Instructions

2.5.2 Two-Byte Instructions

2.5.3 Three-Byte Instructions